xref: /utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maldives/hvd_ex/halHVD_EX.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
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93*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
94*53ee8cc1Swenshuai.xi 
95*53ee8cc1Swenshuai.xi #ifndef _HAL_HVD_H_
96*53ee8cc1Swenshuai.xi #define _HAL_HVD_H_
97*53ee8cc1Swenshuai.xi #if !defined(MSOS_TYPE_NUTTX) || defined(SUPPORT_X_MODEL_FEATURE)
98*53ee8cc1Swenshuai.xi 
99*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
100*53ee8cc1Swenshuai.xi //  Macro and Define
101*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
102*53ee8cc1Swenshuai.xi // Feature
103*53ee8cc1Swenshuai.xi #define HAL_HVD_ENABLE_MUTEX_PROTECT    HVD_ENABLE_MUTEX_PROTECT
104*53ee8cc1Swenshuai.xi #define HAL_HVD_ENABLE_MIU_PROTECT      HVD_ENABLE_MIU_RST_PROTECT
105*53ee8cc1Swenshuai.xi #define HAL_HVD_ENABLE_VPU_CMD    1
106*53ee8cc1Swenshuai.xi 
107*53ee8cc1Swenshuai.xi // MBox type of FW cmd
108*53ee8cc1Swenshuai.xi #if (HAL_HVD_ENABLE_VPU_CMD)
109*53ee8cc1Swenshuai.xi     #define HAL_HVD_CMD_MBOX            E_HVD_VPU_HI_0
110*53ee8cc1Swenshuai.xi     #define HAL_HVD_CMD_ARG_MBOX        E_HVD_VPU_HI_1
111*53ee8cc1Swenshuai.xi #else
112*53ee8cc1Swenshuai.xi     #define HAL_HVD_CMD_MBOX            E_HVD_HI_0
113*53ee8cc1Swenshuai.xi     #define HAL_HVD_CMD_ARG_MBOX        E_HVD_HI_1
114*53ee8cc1Swenshuai.xi #endif
115*53ee8cc1Swenshuai.xi // MBox other usages
116*53ee8cc1Swenshuai.xi #define HAL_HVD_REG_ISR_VPU     E_HVD_VPU_RISC_1
117*53ee8cc1Swenshuai.xi #define HAL_HVD_REG_FW_STATE    E_HVD_RISC_0
118*53ee8cc1Swenshuai.xi #define HAL_HVD_REG_ISR_HVD     E_HVD_RISC_1
119*53ee8cc1Swenshuai.xi #define HAL_HVD_REG_DISP_INFO_COPYED    E_HVD_RISC_1
120*53ee8cc1Swenshuai.xi #define HAL_HVD_REG_DISP_INFO_CHANGE    E_HVD_RISC_1
121*53ee8cc1Swenshuai.xi #define HAL_HVD_REG_DISP_CTL    E_HVD_HI_0
122*53ee8cc1Swenshuai.xi 
123*53ee8cc1Swenshuai.xi #define PRESET_ONE_PENDING_BUFFER       (1 << 0)  /// For AVC, one pending buffer mode, reduce from two to one
124*53ee8cc1Swenshuai.xi #define PRESET_FRAMERATE_HANDLING       (1 << 1)  /// For AVC, Handle frame rate by input frame rate when sequence did not have frame rate info.
125*53ee8cc1Swenshuai.xi #define PRESET_TSP_IN_BBU_MODE          (1 << 2)  /// For AVS/AVS+ only. Raw data comes from TSP while HVD HW engine triggers decode according to BBU table
126*53ee8cc1Swenshuai.xi 
127*53ee8cc1Swenshuai.xi #if defined(CHIP_T3)
128*53ee8cc1Swenshuai.xi // patch for HW bug
129*53ee8cc1Swenshuai.xi #define HVD_MIU1_BASE_ADDRESS   0x08000000UL//0x10000000UL
130*53ee8cc1Swenshuai.xi #else // CHIP_U3
131*53ee8cc1Swenshuai.xi #define HVD_MIU1_BASE_ADDRESS   0x08000000UL
132*53ee8cc1Swenshuai.xi #endif
133*53ee8cc1Swenshuai.xi 
134*53ee8cc1Swenshuai.xi #define HVD_RV_BROKENBYUS_BIT    29
135*53ee8cc1Swenshuai.xi 
136*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
137*53ee8cc1Swenshuai.xi //  Type and Structure
138*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
139*53ee8cc1Swenshuai.xi 
140*53ee8cc1Swenshuai.xi typedef enum
141*53ee8cc1Swenshuai.xi {
142*53ee8cc1Swenshuai.xi     E_HVD_HI_0,
143*53ee8cc1Swenshuai.xi     E_HVD_HI_1,
144*53ee8cc1Swenshuai.xi     E_HVD_RISC_0,
145*53ee8cc1Swenshuai.xi     E_HVD_RISC_1,
146*53ee8cc1Swenshuai.xi     E_HVD_VPU_HI_0,
147*53ee8cc1Swenshuai.xi     E_HVD_VPU_HI_1,
148*53ee8cc1Swenshuai.xi     E_HVD_VPU_RISC_0,
149*53ee8cc1Swenshuai.xi     E_HVD_VPU_RISC_1,
150*53ee8cc1Swenshuai.xi } HVD_MBOX_TYPE;
151*53ee8cc1Swenshuai.xi 
152*53ee8cc1Swenshuai.xi typedef enum
153*53ee8cc1Swenshuai.xi {
154*53ee8cc1Swenshuai.xi     //Support TSP/TS/File mode
155*53ee8cc1Swenshuai.xi     E_HAL_HVD_MAIN_STREAM,
156*53ee8cc1Swenshuai.xi 
157*53ee8cc1Swenshuai.xi     //Only support file mode
158*53ee8cc1Swenshuai.xi     E_HAL_HVD_SUB_STREAM,
159*53ee8cc1Swenshuai.xi 
160*53ee8cc1Swenshuai.xi     //Only support MVC mode
161*53ee8cc1Swenshuai.xi     E_HAL_HVD_MVC_STREAM,
162*53ee8cc1Swenshuai.xi } HAL_HVD_StreamType;
163*53ee8cc1Swenshuai.xi 
164*53ee8cc1Swenshuai.xi typedef struct
165*53ee8cc1Swenshuai.xi {
166*53ee8cc1Swenshuai.xi     HAL_HVD_StreamId eStreamId;
167*53ee8cc1Swenshuai.xi     MS_BOOL bUsed;
168*53ee8cc1Swenshuai.xi     MS_BOOL bDispOutSide;
169*53ee8cc1Swenshuai.xi     MS_U32 u32PTSPreWptr;
170*53ee8cc1Swenshuai.xi     MS_U32 u32PTSByteCnt;
171*53ee8cc1Swenshuai.xi     MS_U32 u32BBUWptr;
172*53ee8cc1Swenshuai.xi     MS_U32 u32BBUEntryNum;
173*53ee8cc1Swenshuai.xi     MS_U32 u32BBUEntryNumTH;
174*53ee8cc1Swenshuai.xi     MS_U32 u32DispQIndex;
175*53ee8cc1Swenshuai.xi     MS_U32 u32PrivateData;
176*53ee8cc1Swenshuai.xi     MS_U32 u32FreeData;
177*53ee8cc1Swenshuai.xi     MS_U32 u32RegBase;
178*53ee8cc1Swenshuai.xi } HVD_EX_Stream;
179*53ee8cc1Swenshuai.xi 
180*53ee8cc1Swenshuai.xi typedef struct
181*53ee8cc1Swenshuai.xi {
182*53ee8cc1Swenshuai.xi     MS_BOOL bColocateBBUMode;
183*53ee8cc1Swenshuai.xi 
184*53ee8cc1Swenshuai.xi }HVD_EX_PreSet;
185*53ee8cc1Swenshuai.xi 
186*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
187*53ee8cc1Swenshuai.xi //  Function and Variable
188*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
189*53ee8cc1Swenshuai.xi MS_BOOL     HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType);
190*53ee8cc1Swenshuai.xi MS_BOOL     HAL_HVD_EX_DeinitHW(void);
191*53ee8cc1Swenshuai.xi void        HAL_HVD_EX_FlushMemory(void);
192*53ee8cc1Swenshuai.xi void        HAL_HVD_EX_ReadMemory(void);
193*53ee8cc1Swenshuai.xi void        HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl *pHVDCtrlsBase);
194*53ee8cc1Swenshuai.xi void        HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange);
195*53ee8cc1Swenshuai.xi MS_U32      HAL_HVD_EX_GetHWVersionID(void);
196*53ee8cc1Swenshuai.xi HAL_HVD_StreamId HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType);
197*53ee8cc1Swenshuai.xi void        HAL_HVD_EX_PowerCtrl(MS_BOOL bEnable);
198*53ee8cc1Swenshuai.xi void        HAL_HVD_EX_InitRegBase(MS_U32 u32RegBase);
199*53ee8cc1Swenshuai.xi HVD_Return  HAL_HVD_EX_InitVariables(MS_U32 u32Id);
200*53ee8cc1Swenshuai.xi HVD_Return  HAL_HVD_EX_InitShareMem(MS_U32 u32Id);
201*53ee8cc1Swenshuai.xi HVD_Return  HAL_HVD_EX_InitRegCPU(MS_U32 u32Id);
202*53ee8cc1Swenshuai.xi HVD_Return  HAL_HVD_EX_SetData(MS_U32 u32Id, HVD_SetData u32type, MS_U32 u32Data);
203*53ee8cc1Swenshuai.xi MS_U32      HAL_HVD_EX_GetData(MS_U32 u32Id, HVD_GetData eType);
204*53ee8cc1Swenshuai.xi MS_S64      HAL_HVD_EX_GetData_EX(MS_U32 u32Id, HVD_GetData eType);
205*53ee8cc1Swenshuai.xi MS_U32      HAL_HVD_EX_GetShmAddr(MS_U32 u32Id);
206*53ee8cc1Swenshuai.xi MS_BOOL     HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id, MS_U16 u16HSize, MS_U16 u16VSize, MS_U32 u32FrmRate);
207*53ee8cc1Swenshuai.xi HVD_Return  HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg);
208*53ee8cc1Swenshuai.xi HVD_Return  HAL_HVD_EX_DeInit(MS_U32 u32Id);
209*53ee8cc1Swenshuai.xi HVD_Return  HAL_HVD_EX_PushPacket(MS_U32 u32Id, HVD_BBU_Info *pInfo);
210*53ee8cc1Swenshuai.xi void        HAL_HVD_EX_EnableISR(MS_U32 u32Id, MS_BOOL bEnable);
211*53ee8cc1Swenshuai.xi void        HAL_HVD_EX_SetForceISR(MS_U32 u32Id, MS_BOOL bEnable);
212*53ee8cc1Swenshuai.xi void        HAL_HVD_EX_SetClearISR(MS_U32 u32Id);
213*53ee8cc1Swenshuai.xi MS_BOOL     HAL_HVD_EX_IsISROccured(MS_U32 u32Id);
214*53ee8cc1Swenshuai.xi MS_BOOL     HAL_HVD_EX_IsEnableISR(MS_U32 u32Id);
215*53ee8cc1Swenshuai.xi MS_BOOL     HAL_HVD_EX_IsAlive(MS_U32 u32Id);
216*53ee8cc1Swenshuai.xi MS_BOOL     HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id);
217*53ee8cc1Swenshuai.xi MS_BOOL     HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id);
218*53ee8cc1Swenshuai.xi void        HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable);
219*53ee8cc1Swenshuai.xi MS_U32      HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr);
220*53ee8cc1Swenshuai.xi void        HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr, MS_U32 u32Data);
221*53ee8cc1Swenshuai.xi MS_U16      HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock);
222*53ee8cc1Swenshuai.xi void        HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id);
223*53ee8cc1Swenshuai.xi void        HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable);
224*53ee8cc1Swenshuai.xi void        HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id);
225*53ee8cc1Swenshuai.xi void        HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num);
226*53ee8cc1Swenshuai.xi void        HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl *pDrvCtrl, HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl);
227*53ee8cc1Swenshuai.xi void	    HVD_EX_SetRstFlag(MS_BOOL bRst);
228*53ee8cc1Swenshuai.xi MS_BOOL     HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id);
229*53ee8cc1Swenshuai.xi #if HVD_ENABLE_MVC
230*53ee8cc1Swenshuai.xi MS_BOOL     HAL_HVD_EX_CheckMVCID(MS_U32 u32Id);
231*53ee8cc1Swenshuai.xi VDEC_EX_View  HAL_HVD_EX_GetView(MS_U32 u32Id);
232*53ee8cc1Swenshuai.xi #endif ///HVD_ENABLE_MVC
233*53ee8cc1Swenshuai.xi MS_BOOL HAL_HVD_EX_Init_Share_Mem(void);
234*53ee8cc1Swenshuai.xi void        HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id);
235*53ee8cc1Swenshuai.xi MS_U32      HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id);
236*53ee8cc1Swenshuai.xi HVD_Return HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id, MS_BOOL bEnable);
237*53ee8cc1Swenshuai.xi void        HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id, MS_U32 u32ModeFlag);
238*53ee8cc1Swenshuai.xi MS_BOOL HAL_HVD_EX_GetSupport2ndMVOPInterface(void);
239*53ee8cc1Swenshuai.xi void        HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id);
240*53ee8cc1Swenshuai.xi void        HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_U32 drvprectrl);
241*53ee8cc1Swenshuai.xi MS_BOOL 	HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id);
242*53ee8cc1Swenshuai.xi void HAL_HVD_MVDMiuClientSel(MS_U8 u8MiuSel);
243*53ee8cc1Swenshuai.xi 
244*53ee8cc1Swenshuai.xi #endif
245*53ee8cc1Swenshuai.xi typedef enum
246*53ee8cc1Swenshuai.xi {
247*53ee8cc1Swenshuai.xi 	E_BBU_FSM_START  = 0,
248*53ee8cc1Swenshuai.xi     E_BBU_FSM_0,
249*53ee8cc1Swenshuai.xi     E_BBU_FSM_00,
250*53ee8cc1Swenshuai.xi     E_BBU_FSM_001,
251*53ee8cc1Swenshuai.xi } VDEC_EX_BBU_FSM_STATE;
252*53ee8cc1Swenshuai.xi 
253*53ee8cc1Swenshuai.xi MS_BOOL _HVD_EX_IS_BBU_TSP_MODE(MS_U32 u32Id);
254*53ee8cc1Swenshuai.xi MS_BOOL _HVD_EX_BBU_Get_TaskRunning(MS_U32 u32Id);
255*53ee8cc1Swenshuai.xi void _HVD_EX_BBU_Set_TaskRunning(MS_U32 u32Id,MS_BOOL val);
256*53ee8cc1Swenshuai.xi MS_U32 _HVD_EX_GetESOffsetIncrease(MS_U32 u32Id, MS_U32 inc, MS_U32 offset);
257*53ee8cc1Swenshuai.xi MS_U32 _HVD_EX_GetESOffsetMinus(MS_U32 u32Id, MS_U32 mis, MS_U32 offset);
258*53ee8cc1Swenshuai.xi void _HVD_EX_ES_DBG_PRINT(MS_U32 u32Id, MS_U32 offset, MS_U32 length);
259*53ee8cc1Swenshuai.xi MS_U32 _HVD_EX_ES_Read(MS_U32 u32Id, MS_U32 offset);
260*53ee8cc1Swenshuai.xi 
261*53ee8cc1Swenshuai.xi MS_BOOL _HVD_EX_CheckWaterLevel(MS_U32 u32Id, MS_U32 u32ESRptr, MS_U32 u32ESWptr);
262*53ee8cc1Swenshuai.xi MS_BOOL _HVD_EX_BBU_FindStartCode(MS_U32 u32Id,MS_U32* u32Offset, MS_U32 u32ESRptr, MS_U32 u32ESWptr);
263*53ee8cc1Swenshuai.xi 
264*53ee8cc1Swenshuai.xi void HAL_HVD_EX_BBU_Proc(MS_U32 u32Id);
265*53ee8cc1Swenshuai.xi void HAL_HVD_EX_BBU_StopProc(MS_U32 u32Id);
266*53ee8cc1Swenshuai.xi #endif // _HAL_HVD_H_
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