1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #include <string.h>
101 #include "drvHVD_Common.h"
102
103 // Internal Definition
104 #include "drvHVD_def.h"
105 #include "fwHVD_if.h"
106 #include "halVPU_EX.h"
107 #include "halHVD_EX.h"
108 #include "regHVD_EX.h"
109
110 //-------------------------------------------------------------------------------------------------
111 // Driver Compiler Options
112 //-------------------------------------------------------------------------------------------------
113 #if !defined(MSOS_TYPE_NUTTX) || defined(SUPPORT_X_MODEL_FEATURE)
114
115 //-------------------------------------------------------------------------------------------------
116 // Local Defines
117 //-------------------------------------------------------------------------------------------------
118 #define RV_VLC_TABLE_SIZE 0x20000
119 /* Add for Mobile Platform by Ted Sun */
120 //#define HVD_DISPQ_PREFETCH_COUNT 2
121 #define HVD_FW_MEM_OFFSET 0x100000UL // 1M
122 #define VPU_QMEM_BASE 0x20000000UL
123 #define HVD_HW_MAX_PIXEL (3840*2160*31000ULL) // 4kx2k@30p
124
125 #if 0
126 static HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
127 static MS_U8 g_hvd_nal_fill_pair[2][8] = { {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0, 0, 0} };
128 static MS_U32 u32RV_VLCTableAddr = 0; // offset from Frame buffer start address
129 static MS_U16 _u16DispQPtr = 0;
130 #endif
131
132 //---------------------------------- Mutex settings -----------------------------------------
133 #if HAL_HVD_ENABLE_MUTEX_PROTECT
134 #define _HAL_HVD_MutexCreate() \
135 do \
136 { \
137 if (s32HVDMutexID < 0) \
138 { \
139 s32HVDMutexID = OSAL_HVD_MutexCreate((MS_U8*)(_u8HVD_Mutex)); \
140 } \
141 } while (0)
142
143 #define _HAL_HVD_MutexDelete() \
144 do \
145 { \
146 if (s32HVDMutexID >= 0) \
147 { \
148 OSAL_HVD_MutexDelete(s32HVDMutexID); \
149 s32HVDMutexID = -1; \
150 } \
151 } while (0)
152
153 #define _HAL_HVD_Entry() \
154 do \
155 { \
156 if (s32HVDMutexID >= 0) \
157 { \
158 if (!OSAL_HVD_MutexObtain(s32HVDMutexID, OSAL_HVD_MUTEX_TIMEOUT)) \
159 { \
160 printf("[HAL HVD][%06d] Mutex taking timeout\n", __LINE__); \
161 } \
162 } \
163 } while (0)
164
165 #define _HAL_HVD_Return(_ret_) \
166 do \
167 { \
168 if (s32HVDMutexID >= 0) \
169 { \
170 OSAL_HVD_MutexRelease(s32HVDMutexID); \
171 } \
172 return _ret_; \
173 } while(0)
174
175 #define _HAL_HVD_Release() \
176 do \
177 { \
178 if (s32HVDMutexID >= 0) \
179 { \
180 OSAL_HVD_MutexRelease(s32HVDMutexID); \
181 } \
182 } while (0)
183
184
185 #else // HAL_HVD_ENABLE_MUTEX_PROTECT
186
187 #define _HAL_HVD_MutexCreate()
188 #define _HAL_HVD_MutexDelete()
189 #define _HAL_HVD_Entry()
190 #define _HAL_HVD_Return(_ret) {return _ret;}
191 #define _HAL_HVD_Release()
192
193 #endif // HAL_HVD_ENABLE_MUTEX_PROTECT
194
195 //------------------------------ MIU SETTINGS ----------------------------------
196 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(4))
197 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
198 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(2))
199 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(1))
200
201 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(4))
202 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
203 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(2))
204 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(1))
205
206 #define HVD_MVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4))
207 #define HVD_MVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12))
208 #define HVD_HVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(2)) == BIT(2))
209 #define HVD_HVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
210
211 #if SUPPORT_EVD
212 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(2))
213 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(3))
214 #define _MaskMiu1Req_EVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(2))
215 #define _MaskMiu1Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(3))
216 #define HVD_EVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(2)) == BIT(2))
217 #define HVD_EVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(3)) == BIT(3))
218 #endif
219
220 #define _HVD_MIU_SetReqMask(miu_clients, mask) \
221 do \
222 { \
223 if (HVD_##miu_clients##_ON_MIU1 == 0) \
224 { \
225 _MaskMiuReq_##miu_clients(mask); \
226 } \
227 else \
228 { \
229 _MaskMiu1Req_##miu_clients(mask); \
230 } \
231 } while (0)
232
233 // check RM is supported or not
234 #define HVD_HW_RUBBER3 (HAL_HVD_EX_GetHWVersionID()& BIT(14))
235 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 3
236 //-------------------------------------------------------------------------------------------------
237 // Local Structures
238 //-------------------------------------------------------------------------------------------------
239
240 //-------------------------------------------------------------------------------------------------
241 // Local Functions Prototype
242 //-------------------------------------------------------------------------------------------------
243 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id);
244 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr);
245 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg);
246 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox);
247 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg);
248 //static void _HVD_EX_MBoxClear(MS_U8 u8MBox);
249 static MS_U32 _HVD_EX_GetPC(void);
250 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id);
251 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug);
252 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg);
253 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd);
254 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg);
255 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable);
256 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id);
257 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id);
258 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id);
259 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo);
260 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen);
261 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2);
262 static MS_U32 _HVD_EX_GetVUIDispInfo(MS_U32 u32Id);
263 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id);
264 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id);
265 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id);
266 static MS_U8 _HVD_EX_GetStreamIdx(MS_U32 u32Id);
267 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id);
268 #if SUPPORT_EVD
269 static void HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable);
270 static MS_BOOL HAL_EVD_EX_DeinitHW(void);
271 #endif
272 //-------------------------------------------------------------------------------------------------
273 // Global Variables
274 //-------------------------------------------------------------------------------------------------
275 #if defined (__aeon__)
276 static MS_U32 u32HVDRegOSBase = 0xA0200000;
277 #else
278 static MS_U32 u32HVDRegOSBase = 0xBF200000;
279 #endif
280 #if HAL_HVD_ENABLE_MUTEX_PROTECT
281 MS_S32 s32HVDMutexID = -1;
282 MS_U8 _u8HVD_Mutex[] = { "HVD_Mutex" };
283 #endif
284
285
286 //-------------------------------------------------------------------------------------------------
287 // Local Variables
288 //-------------------------------------------------------------------------------------------------
289 typedef struct
290 {
291
292 HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
293 MS_U8 g_hvd_nal_fill_pair[2][8];
294 MS_U32 u32RV_VLCTableAddr; // offset from Frame buffer start address
295 MS_U16 _u16DispQPtr;
296
297 //HVD_EX_Drv_Ctrl *_pHVDCtrls;
298 MS_U32 u32HVDCmdTimeout;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
299 MS_U32 u32VPUClockType;
300 MS_U32 u32HVDClockType;//160
301 #if SUPPORT_EVD
302 MS_U32 u32EVDClockType;
303 #endif
304 HVD_EX_Stream _stHVDStream[3];
305
306 volatile HVD_Frm_Information *pHvdFrm;//_HVD_EX_GetNextDispFrame()
307 MS_BOOL g_RstFlag;
308 MS_U64 u64pts_real;
309 MS_U32 u32VP8BBUWptr;
310 //pre_set
311 HVD_Pre_Ctrl *pHVDPreCtrl_Hal[2];
312
313 } HVD_Hal_CTX;
314
315 HVD_Hal_CTX* pHVDHalContext = NULL;
316 HVD_Hal_CTX gHVDHalContext;
317 HVD_EX_Drv_Ctrl *_pHVDCtrls = NULL;
318
319 static HVD_EX_PreSet _stHVDPreSet[HAL_HVD_EX_MAX_SUPPORT_STREAM] =
320 {
321 {FALSE},
322 {FALSE},
323 {FALSE},
324 };
325
326 //-------------------------------------------------------------------------------------------------
327 // Debug Functions
328 //-------------------------------------------------------------------------------------------------
HVD_EX_SetRstFlag(MS_BOOL bRst)329 void HVD_EX_SetRstFlag(MS_BOOL bRst)
330 {
331 pHVDHalContext->g_RstFlag = bRst;
332 }
HVD_EX_GetRstFlag(void)333 MS_BOOL HVD_EX_GetRstFlag(void)
334 {
335 return pHVDHalContext->g_RstFlag;
336 }
337
338 //-------------------------------------------------------------------------------------------------
339 // Local Functions
340 //-------------------------------------------------------------------------------------------------
341
_HVD_EX_Context_Init_HAL(void)342 static void _HVD_EX_Context_Init_HAL(void)
343 {
344 pHVDHalContext->u32HVDCmdTimeout = 100;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
345 pHVDHalContext->u32VPUClockType = 240; //it should same as:_VPU_EX_InitAll() eClkSpeed
346 pHVDHalContext->u32HVDClockType = 240;//160;
347 #if SUPPORT_EVD
348 pHVDHalContext->u32EVDClockType = 384;
349 #endif
350 pHVDHalContext->_stHVDStream[0].eStreamId = E_HAL_HVD_MAIN_STREAM0;
351 pHVDHalContext->_stHVDStream[1].eStreamId = E_HAL_HVD_SUB_STREAM0;
352 pHVDHalContext->_stHVDStream[2].eStreamId = E_HAL_HVD_SUB_STREAM1;
353 }
354
_HVD_EX_GetBBUReadptr(MS_U32 u32Id)355 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id)
356 {
357 MS_U16 u16Ret = 0;
358 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
359 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
360 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
361 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
362 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
363
364 #if HVD_ENABLE_MVC
365 if(HAL_HVD_EX_CheckMVCID(u32Id))
366 {
367 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
368 }
369 #endif /// HVD_ENABLE_MVC
370
371 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
372 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
373
374 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
375 {
376 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS4);
377 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS3);
378 }
379 else
380 #ifdef SUPPORT_EVD
381 if ((0 == u8TaskId) || (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
382 #else
383 if (0 == u8TaskId)
384 #endif
385 {
386 //if(pCtrl->InitParams.bColocateBBUMode)
387 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
388 u16Ret = pShm->u32ColocateBBUReadPtr;
389 else
390 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB));
391 }
392 else
393 {
394 //if(pCtrl->InitParams.bColocateBBUMode)
395 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
396 u16Ret = pShm->u32ColocateBBUReadPtr;
397 else
398 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2);
399 }
400
401 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
402 _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2));
403
404 return u16Ret;
405 }
406
_HVD_EX_GetBBUWritedptr(MS_U32 u32Id)407 static MS_U16 _HVD_EX_GetBBUWritedptr(MS_U32 u32Id)
408 {
409 MS_U16 u16Ret = 0;
410 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
411 HVD_EX_Drv_Ctrl *pDrvCtrl = _HVD_EX_GetDrvCtrl(u32Id);
412 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
413 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
414 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
415
416 #if HVD_ENABLE_MVC
417 if (HAL_HVD_EX_CheckMVCID(u32Id))
418 {
419 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
420 }
421 #endif /// HVD_ENABLE_MVC
422 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
423 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
424
425 if ((pDrvCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8) // VP8
426 {
427 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS4);
428 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS3);
429 }
430 else
431 #ifdef SUPPORT_EVD
432 if ((0 == u8TaskId) || (E_HVD_INIT_HW_HEVC == (pDrvCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
433 #else
434 if (0 == u8TaskId)
435 #endif
436 {
437 //if(pDrvCtrl->InitParams.bColocateBBUMode)
438 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
439 u16Ret = pShm->u32ColocateBBUWritePtr;
440 else
441 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB));
442 }
443 else
444 {
445 //if(pDrvCtrl->InitParams.bColocateBBUMode)
446 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
447 u16Ret = pShm->u32ColocateBBUWritePtr;
448 else
449 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2);
450 }
451
452 return u16Ret;
453 }
454
_HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)455 static void _HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)
456 {
457 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
458 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
459
460 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), 0);
461 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
462 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2, 0);
463 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
464 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, 0);
465 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
466 _HVD_Write2Byte(HVD_REG_NAL_RPTR_HI_BS4, 0);
467 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
468 }
469
_HVD_EX_SetBBUWriteptr(MS_U32 u32Id,MS_U16 u16BBUNewWptr)470 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr)
471 {
472 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
473 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
474 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
475 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
476 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
477
478 #if HVD_ENABLE_MVC
479 if (HAL_HVD_EX_CheckMVCID(u32Id))
480 {
481 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
482 }
483 #endif /// HVD_ENABLE_MVC
484
485 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
486 {
487 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, u16BBUNewWptr);
488 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS4, u16BBUNewWptr);
489 }
490 else
491 #ifdef SUPPORT_EVD
492 if ((0 == u8TaskId) || (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
493 #else
494 if (0 == u8TaskId)
495 #endif
496 {
497 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), u16BBUNewWptr);
498 //if(pCtrl->InitParams.bColocateBBUMode)
499 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
500 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
501 }
502 else
503 {
504 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2, u16BBUNewWptr);
505 //if(pCtrl->InitParams.bColocateBBUMode)
506 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
507 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
508 }
509
510 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
511 _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2));
512
513 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
514 }
515
_HVD_EX_MBoxSend(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 u32Msg)516 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg)
517 {
518 MS_BOOL bResult = TRUE;
519 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
520 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
521
522 switch (u8MBox)
523 {
524 case E_HVD_HI_0:
525 {
526 _HVD_Write4Byte(HVD_REG_HI_MBOX0_L(u32RB), u32Msg);
527 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET);
528 break;
529 }
530 case E_HVD_HI_1:
531 {
532 _HVD_Write4Byte(HVD_REG_HI_MBOX1_L(u32RB), u32Msg);
533 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET);
534 break;
535 }
536 case E_HVD_VPU_HI_0:
537 {
538 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX0, u32Msg);
539 break;
540 }
541 case E_HVD_VPU_HI_1:
542 {
543 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX1, u32Msg);
544 break;
545 }
546 default:
547 {
548 bResult = FALSE;
549 break;
550 }
551 }
552
553 return bResult;
554 }
555
_HVD_EX_MBoxReady(MS_U32 u32Id,MS_U8 u8MBox)556 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox)
557 {
558 MS_BOOL bResult = TRUE;
559 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
560 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
561
562 switch (u8MBox)
563 {
564 case E_HVD_HI_0:
565 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
566 break;
567 case E_HVD_HI_1:
568 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
569 break;
570 case E_HVD_RISC_0:
571 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
572 break;
573 case E_HVD_RISC_1:
574 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
575 break;
576 case E_HVD_VPU_HI_0:
577 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX0);
578 break;
579 case E_HVD_VPU_HI_1:
580 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX1);
581 break;
582 case E_HVD_VPU_RISC_0:
583 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0);
584 break;
585 case E_HVD_VPU_RISC_1:
586 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX1);
587 break;
588 default:
589 break;
590 }
591
592 return bResult;
593 }
594
_HVD_EX_MBoxRead(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 * u32Msg)595 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg)
596 {
597 MS_BOOL bResult = TRUE;
598 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
599 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
600
601 switch (u8MBox)
602 {
603 case E_HVD_HI_0:
604 {
605 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX0_L(u32RB));
606 break;
607 }
608 case E_HVD_HI_1:
609 {
610 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX1_L(u32RB));
611 break;
612 }
613 case E_HVD_RISC_0:
614 {
615 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX0_L(u32RB));
616 break;
617 }
618 case E_HVD_RISC_1:
619 {
620 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX1_L(u32RB));
621 break;
622 }
623 case E_HVD_VPU_RISC_0:
624 {
625 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, u32Msg);
626 break;
627 }
628 case E_HVD_VPU_RISC_1:
629 {
630 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX1, u32Msg);
631 break;
632 }
633 default:
634 {
635 bResult = FALSE;
636 break;
637 }
638 }
639
640 return bResult;
641 }
642
643 #if 0
644 static void _HVD_EX_MBoxClear(MS_U8 u8MBox)
645 {
646 switch (u8MBox)
647 {
648 case E_HVD_RISC_0:
649 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR, HVD_REG_RISC_MBOX0_CLR);
650 break;
651 case E_HVD_RISC_1:
652 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR, HVD_REG_RISC_MBOX1_CLR);
653 break;
654 case E_HVD_VPU_RISC_0:
655 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX0);
656 break;
657 case E_HVD_VPU_RISC_1:
658 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX1);
659 break;
660 default:
661 break;
662 }
663 }
664 #endif
665
_HVD_EX_GetPC(void)666 static MS_U32 _HVD_EX_GetPC(void)
667 {
668 MS_U32 u32PC = 0;
669 u32PC = HAL_VPU_EX_GetProgCnt();
670 // HVD_MSG_DBG("<gdbg>pc0 =0x%lx\n",u32PC);
671 return u32PC;
672 }
673
_HVD_EX_GetESWritePtr(MS_U32 u32Id)674 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id)
675 {
676 MS_U32 u32Data = 0;
677 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
678 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
679
680 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
681 {
682 u32Data = pCtrl->LastNal.u32NalAddr + pCtrl->LastNal.u32NalSize;
683
684 if (u32Data > pCtrl->MemMap.u32BitstreamBufSize)
685 {
686 u32Data -= pCtrl->MemMap.u32BitstreamBufSize;
687
688 HVD_EX_MSG_ERR("app should not put this kind of packet\n");
689 }
690 }
691 else
692 {
693 #if HVD_ENABLE_MVC
694 MS_U8 u8ViewIdx = 0;
695 if(HAL_HVD_EX_CheckMVCID(u32Id))
696 {
697 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
698 }
699 if(u8ViewIdx != 0) /// 2nd ES ptr.
700 {
701 u32Data = pShm->u32ES2WritePtr;
702 }
703 else
704 {
705 u32Data = pShm->u32ESWritePtr;
706 }
707 #else
708 u32Data = pShm->u32ESWritePtr;
709 #endif
710 }
711
712 return u32Data;
713 }
714
715 #define NAL_UNIT_LEN_BITS 21
716 #define NAL_UNIT_OFT_BITS 30
717 #define NAL_UNIT_OFT_LOW_BITS (32-NAL_UNIT_LEN_BITS)
718 #define NAL_UNIT_OFT_HIGH_BITS (NAL_UNIT_OFT_BITS-NAL_UNIT_OFT_LOW_BITS)
719 #define NAL_UNIT_OFT_LOW_MASK (((unsigned int)0xFFFFFFFF)>>(32-NAL_UNIT_OFT_LOW_BITS))
720
_HVD_EX_GetESReadPtr(MS_U32 u32Id,MS_BOOL bDbug)721 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug)
722 {
723 MS_U32 u32Data = 0;
724 MS_U8 u8TaskId = 0;
725 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
726 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
727 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
728 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
729 MS_U32 u32VP8_BBU_DRAM_ST_ADDR_BS3 = pShm->u32HVD_BBU_DRAM_ST_ADDR;
730
731 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
732 #if HVD_ENABLE_MVC
733 if(HAL_HVD_EX_CheckMVCID(u32Id))
734 {
735 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
736 }
737 #endif /// HVD_ENABLE_MVC
738
739 if (((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV) || (TRUE == bDbug))
740 {
741 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8)
742 {
743 // MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
744 MS_U16 u16ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
745 MS_U16 u16WritePtr = _HVD_EX_GetBBUWritedptr(u32Id);
746 MS_U32 *u32Adr;
747 MS_U32 u32Tmp;
748
749 if (u16ReadPtr == u16WritePtr)
750 {
751 u32Data = _HVD_EX_GetESWritePtr(u32Id);
752 }
753 else
754 {
755 if (u16ReadPtr)
756 u16ReadPtr--;
757 else
758 u16ReadPtr = VP8_BBU_DRAM_TBL_ENTRY - 1;
759
760 u32Adr = (MS_U32 *)(MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS3 + (u16ReadPtr << 3)));
761
762 u32Data = (*u32Adr) >> NAL_UNIT_LEN_BITS;
763 u32Tmp = (*(u32Adr+1)) & (0xffffffff>>(32-(NAL_UNIT_OFT_BITS-(32-NAL_UNIT_LEN_BITS))));
764 u32Tmp = u32Tmp << (32-NAL_UNIT_LEN_BITS);
765 u32Data = u32Data | u32Tmp;
766
767 //printf("[VP8] GetESRptr (%x,%x,%x,%x,%d,%d)\n", u32Adr, (*u32Adr), (*(u32Adr+1)) , u32Data, u16ReadPtr, u16WritePtr);
768 //while(1);
769 }
770 goto EXIT;
771 }
772 // set reg_poll_nal_rptr 0
773 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), 0, HVD_REG_ESB_RPTR_POLL);
774 // set reg_poll_nal_rptr 1
775 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL);
776
777 // read reg_nal_rptr_hi
778 #ifdef SUPPORT_EVD
779 if ((0 == u8TaskId) || (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
780 #else
781 if (0 == u8TaskId)
782 #endif
783 {
784 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR(u32RB)) & 0xFFC0;
785 u32Data >>= 6;
786 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H(u32RB)) << 10;
787 }
788 else
789 {
790 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR_L_BS2) & 0xFFC0;
791 u32Data >>= 6;
792 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H_BS2) << 10;
793 }
794
795 u32Data <<= 3; // unit
796
797 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
798 {
799 MS_U32 u32ESWptr = _HVD_EX_GetESWritePtr(u32Id);
800
801 if ((pCtrl->u32LastESRptr < u32ESWptr) && (u32Data > u32ESWptr))
802 {
803 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
804 u32Data = u32ESWptr;
805 }
806 else if ((pCtrl->u32LastESRptr == u32ESWptr) && (u32Data > u32ESWptr))
807 {
808 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
809 u32Data = u32ESWptr;
810 }
811 else if ((_HVD_EX_GetBBUQNumb(u32Id) == 0) && ((u32Data - u32ESWptr) < 32)
812 && ((pShm->u32FwState & E_HVD_FW_STATE_MASK) == E_HVD_FW_PLAY))
813 {
814 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
815 u32Data = u32ESWptr;
816 }
817 else if (((u32Data > u32ESWptr) && (pCtrl->u32LastESRptr > u32Data))
818 && ((u32Data - u32ESWptr) < 32)
819 && (pCtrl->u32FlushRstPtr == 1))
820 {
821 //HVD_MSG_INFO("444HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
822 u32Data = u32ESWptr;
823 }
824 }
825
826 // remove illegal pointer
827 #if 1
828 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
829 {
830 MS_U32 u32PacketStaddr = u32Data + pCtrl->MemMap.u32BitstreamBufAddr;
831
832 if (((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStaddr) &&
833 (u32PacketStaddr <
834 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
835 {
836 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is located in drv process buffer(%lx %lx)\n" , u32Data , pCtrl->u32LastESRptr, pCtrl->MemMap.u32DrvProcessBufAddr , pCtrl->MemMap.u32DrvProcessBufSize );
837 u32Data = pCtrl->u32LastESRptr;
838 }
839 }
840 #endif
841 }
842 else
843 {
844 #if HVD_ENABLE_MVC
845 MS_U8 u8ViewIdx = 0;
846 if(HAL_HVD_EX_CheckMVCID(u32Id))
847 {
848 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
849 }
850 if(u8ViewIdx != 0) /// 2nd ES ptr.
851 {
852 u32Data = pShm->u32ES2ReadPtr;
853 }
854 else
855 {
856 u32Data = pShm->u32ESReadPtr;
857 }
858 #else
859 u32Data = pShm->u32ESReadPtr;
860 #endif
861 }
862
863 EXIT:
864
865 pCtrl->u32LastESRptr = u32Data;
866
867 return u32Data;
868 }
869
_HVD_EX_SetCMDArg(MS_U32 u32Id,MS_U32 u32Arg)870 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg)
871 {
872 MS_U16 u16TimeOut = 0xFFFF;
873 MS_BOOL bResult = FALSE;
874
875 HVD_EX_MSG_DBG("Send ARG 0x%lx to HVD\n", u32Arg);
876
877 while (--u16TimeOut)
878 {
879 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX) && _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX))
880 {
881 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, u32Arg);
882 break;
883 }
884 }
885
886 return bResult;
887 }
888
_HVD_EX_SetCMD(MS_U32 u32Id,MS_U32 u32Cmd)889 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd)
890 {
891 MS_U16 u16TimeOut = 0xFFFF;
892 MS_BOOL bResult = FALSE;
893 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
894
895 HVD_EX_MSG_DBG("Send CMD 0x%lx to HVD \n", u32Cmd);
896
897 #if HVD_ENABLE_MVC
898 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
899 {
900 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
901 }
902 #endif /// HVD_ENABLE_MVC
903
904 while (--u16TimeOut)
905 {
906 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX))
907 {
908 u32Cmd |= (u8TaskId << 24);
909 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmd);
910 break;
911 }
912 }
913 return bResult;
914 }
915
_HVD_EX_SendCmd(MS_U32 u32Id,MS_U32 u32Cmd,MS_U32 u32CmdArg)916 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg)
917 {
918 MS_U32 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
919
920 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
921 {
922 if (HVD_GetSysTime_ms() > u32timeout)
923 {
924 HVD_EX_MSG_ERR("Timeout: cmd=0x%lx arg=0x%lx\n", u32Cmd, u32CmdArg);
925 return E_HVD_RETURN_TIMEOUT;
926 }
927
928 #if 0
929 if (u32Cmd == E_HVD_CMD_STOP)
930 {
931 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
932 #if HVD_ENABLE_MVC
933 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
934 {
935 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
936 }
937 #endif /// HVD_ENABLE_MVC
938 MS_U32 u32Cmdtmp = (u8TaskId << 24) | E_HVD_CMD_STOP;
939
940 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmdtmp);
941 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, 0);
942
943 return E_HVD_RETURN_SUCCESS;
944 }
945 #endif
946
947 if(u32Cmd < E_DUAL_CMD_BASE)
948 {
949 //_HVD_EX_GetPC();
950 HAL_HVD_EX_Dump_FW_Status(u32Id);
951 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
952 }
953 }
954
955 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
956
957 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
958 {
959 if (HVD_GetSysTime_ms() > u32timeout)
960 {
961 HVD_EX_MSG_ERR("cmd timeout: %lx\n", u32Cmd);
962 return E_HVD_RETURN_TIMEOUT;
963 }
964
965 if(u32Cmd < E_DUAL_CMD_BASE)
966 {
967 //_HVD_EX_GetPC();
968 HAL_HVD_EX_Dump_FW_Status(u32Id);
969 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
970 }
971 }
972
973 return E_HVD_RETURN_SUCCESS;
974 }
975
_HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)976 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)
977 {
978 #if HAL_HVD_ENABLE_MIU_PROTECT
979 _HVD_MIU_SetReqMask(MVD_RW, bEnable);
980 _HVD_MIU_SetReqMask(MVD_BBU_R, bEnable);
981 #if SUPPORT_EVD
982 _HVD_MIU_SetReqMask(EVD_RW, bEnable);
983 _HVD_MIU_SetReqMask(EVD_BBU_R, bEnable);
984 #endif
985 _HVD_MIU_SetReqMask(HVD_RW, bEnable);
986 _HVD_MIU_SetReqMask(HVD_BBU_R, bEnable);
987 HAL_VPU_EX_MIU_RW_Protect(bEnable);
988 //HVD_Delay_ms(1);
989 #endif
990 return;
991 }
992
_HVD_EX_SetBufferAddr(MS_U32 u32Id)993 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id)
994 {
995 MS_U16 u16Reg = 0;
996 MS_U32 u32StAddr = 0;
997 MS_BOOL bBitMIU1 = FALSE;
998 MS_BOOL bCodeMIU1 = FALSE;
999 MS_U8 u8TaskId = 0;
1000 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1001 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1002 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1003 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1004
1005 if(pCtrl == NULL) return;
1006
1007 // nal table settngs
1008 if (pCtrl->MemMap.u32CodeBufAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1009 {
1010 bCodeMIU1 = TRUE;
1011 }
1012
1013 if (pCtrl->MemMap.u32BitstreamBufAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1014 {
1015 bBitMIU1 = TRUE;
1016 }
1017
1018 if (bBitMIU1 != bCodeMIU1)
1019 {
1020 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
1021
1022 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1023 {
1024 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1025 }
1026 }
1027 else
1028 {
1029 u32StAddr = pCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU_DRAM_ST_ADDR;
1030
1031 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1032 {
1033 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1034 }
1035 }
1036
1037 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1038 {
1039 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
1040
1041 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS3, (MS_U16)(u32StAddr >> 3));
1042 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS3, (MS_U16)(u32StAddr >> 19));
1043 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS3, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1044
1045 u32StAddr += 0x2000;
1046
1047 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS4, (MS_U16)(u32StAddr >> 3));
1048 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS4, (MS_U16)(u32StAddr >> 19));
1049 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS4, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1050
1051 // ES buffer
1052 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1053
1054 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1055 {
1056 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1057 }
1058
1059 HVD_EX_MSG_DBG("ESB start addr=%lx\n", u32StAddr);
1060
1061 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1062 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1063
1064 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1065 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1066
1067 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1068 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1069 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1070 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1071 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1072 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1073
1074 return;
1075 }
1076
1077 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1078
1079 HVD_EX_MSG_DBG("NAL start addr=%lx\n", u32StAddr);
1080
1081 #ifdef SUPPORT_EVD
1082 if ((0 == u8TaskId) || (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
1083 #else
1084 if (0 == u8TaskId)
1085 #endif
1086 {
1087 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
1088 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
1089 // -1 is for NAL_TAB_LEN counts from zero.
1090 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1091 }
1092 else
1093 {
1094 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2, (MS_U16) (u32StAddr >> 3));
1095 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2, (MS_U16) (u32StAddr >> 19));
1096 // -1 is for NAL_TAB_LEN counts from zero.
1097 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2, (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1098 }
1099
1100 // ES buffer
1101 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1102
1103 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1104 {
1105 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1106 }
1107
1108 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%lx\n", u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1109
1110 #ifdef SUPPORT_EVD
1111 if ((0 == u8TaskId) || (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
1112 #else
1113 if (0 == u8TaskId)
1114 #endif
1115 {
1116 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1117 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1118
1119 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1120 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1121 }
1122 else
1123 {
1124 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2, HVD_LWORD(u32StAddr >> 3));
1125 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2, HVD_HWORD(u32StAddr >> 3));
1126
1127 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1128 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1129 }
1130
1131 // others
1132 #ifdef SUPPORT_EVD
1133 if ((0 == u8TaskId) || (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
1134 #else
1135 if (0 == u8TaskId)
1136 #endif
1137 {
1138 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1139
1140 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1141 {
1142 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1143 }
1144 else
1145 {
1146 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1147 }
1148
1149 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1150
1151 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1152 {
1153 u16Reg |= HVD_REG_BBU_PASER_DISABLE; // force BBU to remove nothing, RM only
1154 }
1155 else // AVS or AVC
1156 {
1157 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1158 {
1159 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
1160 }
1161 else // start code remained
1162 {
1163 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
1164 }
1165 }
1166
1167 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1168
1169 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1170 }
1171 else
1172 {
1173 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2);
1174
1175 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1176 {
1177 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1178 }
1179 else
1180 {
1181 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1182 }
1183
1184 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1185
1186 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1187 {
1188 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1189 }
1190 else // AVS or AVC
1191 {
1192 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1193 {
1194 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1195 }
1196 else // start code remained
1197 {
1198 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1199 }
1200 }
1201
1202 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1203
1204 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2, u16Reg);
1205 }
1206
1207 #if (HVD_ENABLE_MVC)
1208 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
1209 {
1210 /// Used sub stream to record sub view data.
1211 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
1212 //printf("**************** Buffer setting for MVC dual-BBU *************\n");
1213
1214 if (bBitMIU1 != bCodeMIU1)
1215 {
1216 u32StAddr = pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr + pDrvCtrl_Sub->u32BBUTblInBitstreamBufAddr;
1217
1218 if (u32StAddr >= pDrvCtrl_Sub->MemMap.u32MIU1BaseAddr)
1219 {
1220 u32StAddr -= pDrvCtrl_Sub->MemMap.u32MIU1BaseAddr;
1221 }
1222 }
1223 else
1224 {
1225 u32StAddr = pDrvCtrl_Sub->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU2_DRAM_ST_ADDR;
1226
1227 if (u32StAddr >= pDrvCtrl_Sub->MemMap.u32MIU1BaseAddr)
1228 {
1229 u32StAddr -= pDrvCtrl_Sub->MemMap.u32MIU1BaseAddr;
1230 }
1231 }
1232
1233
1234 HVD_EX_MSG_DBG("[MVC] _HAL_HVD_SetBuffer2Addr: nal StAddr:%lx \n", u32StAddr);
1235 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2, (MS_U16)(u32StAddr >> 3));
1236 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2, (MS_U16)(u32StAddr >> 19));
1237 // -1 is for NAL_TAB_LEN counts from zero.
1238 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum - 1));
1239
1240 // ES buffer
1241 u32StAddr = pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr;
1242 if(u32StAddr >= pDrvCtrl_Sub->MemMap.u32MIU1BaseAddr)
1243 {
1244 u32StAddr -= pDrvCtrl_Sub->MemMap.u32MIU1BaseAddr;
1245 }
1246
1247 HVD_EX_MSG_DBG("[MVC] 2nd ES _HAL_HVD_SetBuffer2Addr: ESb StAddr:%lx, len:%lx.\n", u32StAddr, pDrvCtrl_Sub->MemMap.u32BitstreamBufSize);
1248 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2, HVD_LWORD(u32StAddr >> 3));
1249 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2, HVD_HWORD(u32StAddr >> 3));
1250
1251 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2, HVD_LWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1252 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2, HVD_HWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1253
1254 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2);
1255 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1256 {
1257 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1258 HVD_EX_MSG_DBG("[MVC] 2nd ES, TSP mode.\n");
1259 }
1260 else
1261 {
1262 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1263 HVD_EX_MSG_DBG("[MVC] 2nd ES, BBU mode.\n");
1264 }
1265 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1266 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1267 {
1268 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1269 }
1270 else // AVS or AVC
1271 {
1272 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1273 {
1274 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1275 }
1276 else // start code remained
1277 {
1278 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1279 ///HVD_MSG_DBG("[MVC] BBU Paser all.\n");
1280 }
1281 }
1282 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1283 ///HVD_MSG_DBG("[MVC] 2nd MIF BBU 0x%lx.\n",(MS_U32)u16Reg);
1284 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2, u16Reg);
1285 }
1286 #endif
1287
1288
1289 // MIF offset
1290 #if 0
1291 {
1292 MS_U16 offaddr = 0;
1293 u32StAddr = pCtrl->MemMap.u32CodeBufAddr;
1294 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1295 {
1296 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1297 }
1298 HVD_EX_MSG_DBG("MIF offset:%lx \n", u32StAddr);
1299 offaddr = (MS_U16) ((u32StAddr) >> 20);
1300 offaddr &= BMASK(HVD_REG_MIF_OFFSET_L_BITS:0);
1301 //0x1FF; // 9 bits(L + H)
1302 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU);
1303 u16Reg &= ~HVD_REG_MIF_OFFSET_H;
1304 u16Reg &= ~(BMASK(HVD_REG_MIF_OFFSET_L_BITS:0));
1305 if (offaddr & BIT(HVD_REG_MIF_OFFSET_L_BITS))
1306 {
1307 u16Reg |= HVD_REG_MIF_OFFSET_H;
1308 }
1309 _HVD_Write2Byte(HVD_REG_MIF_BBU, (u16Reg | (offaddr & BMASK(HVD_REG_MIF_OFFSET_L_BITS:0))));
1310 }
1311 #endif
1312 }
1313
1314 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
1315 // Note: For VP8 only. MVC ES buffer address will be set when _HVD_EX_SetBufferAddr() is called
1316 static void _HVD_EX_SetESBufferAddr(MS_U32 u32Id)
1317 {
1318 MS_U16 u16Reg = 0;
1319 MS_U32 u32StAddr = 0;
1320 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1321 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1322 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1323
1324 if(pCtrl == NULL) return;
1325
1326 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1327 {
1328 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
1329
1330 // ES buffer
1331 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1332
1333 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1334 {
1335 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1336 }
1337
1338 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1339 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1340
1341 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1342 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1343
1344 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1345 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1346 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1347 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1348 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1349 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1350
1351 return;
1352 }
1353
1354 // ES buffer
1355 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1356
1357 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1358 {
1359 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1360 }
1361
1362 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%lx\n", u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1363
1364 if (0 == HAL_VPU_EX_GetTaskId(u32Id))
1365 {
1366 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1367 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1368
1369 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1370 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1371 }
1372 else
1373 {
1374 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2, HVD_LWORD(u32StAddr >> 3));
1375 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2, HVD_HWORD(u32StAddr >> 3));
1376
1377 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1378 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1379 }
1380 }
1381 #endif
1382
_HVD_EX_GetESLevel(MS_U32 u32Id)1383 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id)
1384 {
1385 MS_U32 u32Wptr = 0;
1386 MS_U32 u32Rptr = 0;
1387 MS_U32 u32CurMBX = 0;
1388 MS_U32 u32ESsize = 0;
1389 MS_U32 u32Ret = E_HVD_ESB_LEVEL_NORMAL;
1390 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1391
1392 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
1393 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
1394 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
1395
1396 if (u32Rptr >= u32Wptr)
1397 {
1398 u32CurMBX = u32Rptr - u32Wptr;
1399 }
1400 else
1401 {
1402 u32CurMBX = u32ESsize - (u32Wptr - u32Rptr);
1403 }
1404
1405 if (u32CurMBX == 0)
1406 {
1407 u32Ret = E_HVD_ESB_LEVEL_UNDER;
1408 }
1409 else if (u32CurMBX < HVD_FW_AVC_ES_OVER_THRESHOLD)
1410 {
1411 u32Ret = E_HVD_ESB_LEVEL_OVER;
1412 }
1413 else
1414 {
1415 u32CurMBX = u32ESsize - u32CurMBX;
1416 if (u32CurMBX < HVD_FW_AVC_ES_UNDER_THRESHOLD)
1417 {
1418 u32Ret = E_HVD_ESB_LEVEL_UNDER;
1419 }
1420 }
1421
1422 return u32Ret;
1423 }
1424
_HVD_EX_GetESQuantity(MS_U32 u32Id)1425 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id)
1426 {
1427 MS_U32 u32Wptr = 0;
1428 MS_U32 u32Rptr = 0;
1429 MS_U32 u32ESsize = 0;
1430 MS_U32 u32Ret = 0;
1431 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1432
1433 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
1434 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
1435 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
1436
1437
1438 if(u32Wptr >= u32Rptr)
1439 {
1440 u32Ret = u32Wptr - u32Rptr;
1441 }
1442 else
1443 {
1444 u32Ret = u32ESsize - u32Rptr + u32Wptr;
1445 }
1446 //printf("ES Quantity <0x%lx> W:0x%lx, R:0x%lx, Q:0x%lx.\n",u32Id,u32Wptr,u32Rptr,u32Ret);
1447 return u32Ret;
1448 }
1449
_HVD_EX_SetRegCPU(MS_U32 u32Id)1450 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id)
1451 {
1452 MS_U32 u32FirmVer = 0;
1453 MS_U32 u32Timeout = 20000;
1454 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1455
1456 HVD_EX_MSG_DBG("HVD HW ver id: 0x%04lx\n", HAL_HVD_EX_GetHWVersionID());
1457
1458 #if HVD_ENABLE_TIME_MEASURE
1459 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
1460 #endif
1461
1462 HAL_VPU_EX_SetFWReload(!pCtrl->bTurboFWMode);
1463
1464 VPU_EX_FWCodeCfg fwCfg;
1465 VPU_EX_TaskInfo taskInfo;
1466 VPU_EX_VLCTblCfg vlcCfg;
1467 VPU_EX_NDecInitPara nDecInitPara;
1468
1469 memset(&fwCfg, 0, sizeof(VPU_EX_FWCodeCfg));
1470 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
1471 memset(&vlcCfg, 0, sizeof(VPU_EX_VLCTblCfg));
1472 memset(&nDecInitPara, 0, sizeof(VPU_EX_NDecInitPara));
1473
1474 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
1475 {
1476 vlcCfg.u32DstAddr = MsOS_PA2KSEG1(pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr);
1477 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
1478 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
1479 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr;
1480 vlcCfg.u32VLCTableOffset = pHVDHalContext->u32RV_VLCTableAddr;
1481 nDecInitPara.pVLCCfg = &vlcCfg;
1482 }
1483
1484 nDecInitPara.pFWCodeCfg = &fwCfg;
1485 nDecInitPara.pTaskInfo = &taskInfo;
1486
1487 fwCfg.u8SrcType = pCtrl->MemMap.eFWSourceType;
1488 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
1489 fwCfg.u32DstSize = pCtrl->MemMap.u32CodeBufSize;
1490 fwCfg.u32BinAddr = pCtrl->MemMap.u32FWBinaryVAddr;
1491 fwCfg.u32BinSize = pCtrl->MemMap.u32FWBinarySize;
1492
1493 taskInfo.u32Id = u32Id;
1494
1495 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
1496 {
1497 taskInfo.eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
1498 }
1499 else
1500 {
1501 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
1502 }
1503
1504 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
1505
1506 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
1507 {
1508 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
1509 }
1510 else
1511 {
1512 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
1513 }
1514 taskInfo.u32HeapSize = HVD_DRAM_SIZE;
1515
1516 #ifdef SUPPORT_EVD
1517 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC)
1518 taskInfo.u32HeapSize = EVD_DRAM_SIZE;
1519 #endif
1520
1521 if(TRUE == HVD_EX_GetRstFlag())
1522 {
1523 //Delete task for Rst
1524 if(!HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
1525 {
1526 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
1527 }
1528 HVD_EX_SetRstFlag(FALSE);
1529 }
1530
1531 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara))
1532 {
1533 HVD_EX_MSG_ERR("Task create fail!\n");
1534
1535 return FALSE;
1536 }
1537
1538 while (u32Timeout)
1539 {
1540 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_INIT_DONE);
1541
1542 if (u32FirmVer != 0)
1543 {
1544 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID);
1545 break;
1546 }
1547 u32Timeout--;
1548 HVD_Delay_ms(1);
1549 }
1550
1551 if (u32Timeout > 0)
1552 {
1553 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1554
1555 pHVDHalContext->_stHVDStream[u8Idx].bUsed = TRUE;
1556
1557 HVD_EX_MSG_INF("FW version binary=0x%lx, if=0x%lx\n", u32FirmVer, (MS_U32) HVD_FW_VERSION);
1558 }
1559 else
1560 {
1561 HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET),
1562 HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID));
1563
1564 if (TRUE != HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
1565 {
1566 HVD_EX_MSG_ERR("Task delete fail!\n");
1567 }
1568
1569 return FALSE;
1570 }
1571
1572 #if HVD_ENABLE_TIME_MEASURE
1573 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
1574 #endif
1575
1576 return TRUE;
1577 }
1578
_HVD_EX_GetPTSTableRptr(MS_U32 u32Id)1579 static MS_U32 _HVD_EX_GetPTSTableRptr(MS_U32 u32Id)
1580 {
1581 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1582 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1583 if (pShm->u32PTStableRptrAddr & VPU_QMEM_BASE)
1584 {
1585 return HAL_VPU_EX_MemRead(pShm->u32PTStableRptrAddr);
1586 }
1587 else
1588 {
1589 return *((MS_U32 *) MsOS_PA2KSEG1(pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
1590 }
1591 }
1592
_HVD_EX_GetPTSTableWptr(MS_U32 u32Id)1593 static MS_U32 _HVD_EX_GetPTSTableWptr(MS_U32 u32Id)
1594 {
1595 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1596 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1597
1598 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
1599 {
1600 return HAL_VPU_EX_MemRead(pShm->u32PTStableWptrAddr);
1601 }
1602 else
1603 {
1604 return *((MS_U32 *) MsOS_PA2KSEG1(pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
1605 }
1606 }
1607
_HVD_EX_SetPTSTableWptr(MS_U32 u32Id,MS_U32 u32Value)1608 static void _HVD_EX_SetPTSTableWptr(MS_U32 u32Id, MS_U32 u32Value)
1609 {
1610 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1611 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1612
1613 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
1614 {
1615 if (!HAL_VPU_EX_MemWrite(pShm->u32PTStableWptrAddr, u32Value))
1616 {
1617 HVD_EX_MSG_ERR("PTS table SRAM write failed\n");
1618 }
1619 }
1620 else
1621 {
1622 *((MS_U32 *) MsOS_PA2KSEG1(pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
1623 }
1624 }
1625
_HVD_EX_UpdatePTSTable(MS_U32 u32Id,HVD_BBU_Info * pInfo)1626 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo)
1627 {
1628 MS_U32 u32PTSWptr = HVD_U32_MAX;
1629 MS_U32 u32PTSRptr = HVD_U32_MAX;
1630 MS_U32 u32DestAddr = 0;
1631 HVD_PTS_Entry PTSEntry;
1632 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1633 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1634 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1635
1636 // update R & W ptr
1637 u32PTSRptr = _HVD_EX_GetPTSTableRptr(u32Id);
1638
1639 HVD_EX_MSG_DBG("PTS table rptr:0x%lx, wptr=0x%lx\n", u32PTSRptr, _HVD_EX_GetPTSTableWptr(u32Id));
1640
1641 if (u32PTSRptr >= MAX_PTS_TABLE_SIZE)
1642 {
1643 HVD_EX_MSG_ERR("PTS table Read Ptr(%lx) > max table size(%lx) \n", u32PTSRptr,
1644 (MS_U32) MAX_PTS_TABLE_SIZE);
1645 return E_HVD_RETURN_FAIL;
1646 }
1647
1648 // check queue is full or not
1649 u32PTSWptr = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr + 1;
1650 u32PTSWptr %= MAX_PTS_TABLE_SIZE;
1651
1652 if (u32PTSWptr == u32PTSRptr)
1653 {
1654 HVD_EX_MSG_ERR("PTS table full. Read Ptr(%lx) == new Write ptr(%lx) ,Pre Wptr(%lx) \n", u32PTSRptr,
1655 u32PTSWptr, pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
1656 return E_HVD_RETURN_FAIL;
1657 }
1658
1659 // add one PTS entry
1660 PTSEntry.u32ByteCnt = pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt & HVD_BYTE_COUNT_MASK;
1661 PTSEntry.u32ID_L = pInfo->u32ID_L;
1662 PTSEntry.u32ID_H = pInfo->u32ID_H;
1663 PTSEntry.u32PTS = pInfo->u32TimeStamp;
1664
1665 u32DestAddr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_PTS_TABLE_ST_OFFSET + (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr * sizeof(HVD_PTS_Entry)));
1666
1667 HVD_EX_MSG_DBG("PTS entry dst addr=0x%lx\n", MsOS_VA2PA(u32DestAddr));
1668
1669 HVD_memcpy((void *) u32DestAddr, &PTSEntry, sizeof(HVD_PTS_Entry));
1670
1671 HAL_HVD_EX_FlushMemory();
1672
1673 // update Write ptr
1674 _HVD_EX_SetPTSTableWptr(u32Id, u32PTSWptr);
1675
1676 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = u32PTSWptr;
1677
1678 return E_HVD_RETURN_SUCCESS;
1679 }
1680
_HVD_EX_UpdateESWptr(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen)1681 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen)
1682 {
1683 //---------------------------------------------------
1684 // item format in nal table:
1685 // reserved |borken| u32NalOffset | u32NalLen
1686 // 13 bits |1bit | 29 bits | 21 bits (total 8 bytes)
1687 //---------------------------------------------------
1688 MS_U32 u32Adr = 0;
1689 MS_U32 u32BBUNewWptr = 0;
1690 MS_U8 item[8];
1691 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1692 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1693 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1694 MS_U32 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR;
1695
1696 #if HVD_ENABLE_MVC
1697 if(HAL_HVD_EX_CheckMVCID(u32Id))
1698 {
1699 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
1700 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
1701 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
1702 {
1703 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
1704 }
1705 }
1706 #endif /// HVD_ENABLE_MVC
1707
1708 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1709 {
1710 u32BBUNewWptr = pHVDHalContext->u32VP8BBUWptr;
1711 }
1712 else
1713 {
1714 u32BBUNewWptr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
1715 }
1716 u32BBUNewWptr++;
1717 u32BBUNewWptr %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
1718
1719 // prepare nal entry
1720
1721 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1722 {
1723 // NAL len 22 bits , HEVC level5 constrain
1724 item[0] = u32NalLen & 0xff;
1725 item[1] = (u32NalLen >> 8) & 0xff;
1726 item[2] = ((u32NalLen >> 16) & 0x3f) | ((u32NalOffset << 6) & 0xc0);
1727 item[3] = (u32NalOffset >> 2) & 0xff;
1728 item[4] = (u32NalOffset >> 10) & 0xff;
1729 item[5] = (u32NalOffset >> 18) & 0xff;
1730 item[6] = (u32NalOffset >> 26) & 0x0f; //including broken bit
1731 item[7] = 0;
1732 }
1733 else
1734 {
1735 item[0] = u32NalLen & 0xff;
1736 item[1] = (u32NalLen >> 8) & 0xff;
1737 item[2] = ((u32NalLen >> 16) & 0x1f) | ((u32NalOffset << 5) & 0xe0);
1738 item[3] = (u32NalOffset >> 3) & 0xff;
1739 item[4] = (u32NalOffset >> 11) & 0xff;
1740 item[5] = (u32NalOffset >> 19) & 0xff;
1741 item[6] = (u32NalOffset >> 27) & 0x07; //including broken bit
1742 item[7] = 0;
1743 }
1744
1745 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1746 {
1747 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->u32VP8BBUWptr << 3));
1748 }
1749 else
1750 {
1751 // add nal entry
1752 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
1753 }
1754
1755 HVD_memcpy((void *) u32Adr, (void *) item, 8);
1756
1757 HAL_HVD_EX_FlushMemory();
1758
1759 HVD_EX_MSG_DBG("addr=0x%lx, bbu wptr=0x%lx\n", MsOS_VA2PA(u32Adr), pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
1760
1761 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1762 {
1763 pHVDHalContext->u32VP8BBUWptr = u32BBUNewWptr;
1764 }
1765 else
1766 {
1767 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = u32BBUNewWptr;
1768 }
1769
1770 return E_HVD_RETURN_SUCCESS;
1771 }
1772
_HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen,MS_U32 u32NalOffset2,MS_U32 u32NalLen2)1773 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2)
1774 {
1775 MS_U8 item[8];
1776 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1777 MS_U32 u32Adr = 0;
1778 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1779 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1780 MS_U32 u32VP8_BBU_DRAM_ST_ADDR_BS4 = pShm->u32HVD_BBU2_DRAM_ST_ADDR;
1781
1782 /*
1783 printf("nal2 offset=0x%x, len=0x%x\n",
1784 u32NalOffset2, u32NalLen2);
1785 */
1786
1787 item[0] = u32NalLen2 & 0xff;
1788 item[1] = (u32NalLen2 >> 8) & 0xff;
1789 item[2] = ((u32NalLen2 >> 16) & 0x1f) | ((u32NalOffset2 << 5) & 0xe0);
1790 item[3] = (u32NalOffset2 >> 3) & 0xff;
1791 item[4] = (u32NalOffset2 >> 11) & 0xff;
1792 item[5] = (u32NalOffset2 >> 19) & 0xff;
1793 item[6] = (u32NalOffset2 >> 27) & 0x07;
1794 item[7] = 0;
1795
1796 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1797 {
1798 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->u32VP8BBUWptr << 3));
1799 }
1800 else
1801 {
1802 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
1803 }
1804
1805 HVD_memcpy((void *) u32Adr, (void *) item, 8);
1806
1807 HAL_HVD_EX_FlushMemory();
1808
1809 return _HVD_EX_UpdateESWptr(u32Id, u32NalOffset, u32NalLen);
1810 }
1811
_HVD_EX_GetVUIDispInfo(MS_U32 u32Id)1812 static MS_U32 _HVD_EX_GetVUIDispInfo(MS_U32 u32Id)
1813 {
1814 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1815 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1816
1817 if( ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC) ||
1818 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC) )
1819 {
1820 MS_U16 i;
1821 MS_U32 u32VUIAddr;
1822 MS_U32 *pData = (MS_U32 *) &(pHVDHalContext->g_hvd_VUIINFO);
1823
1824 HAL_HVD_EX_ReadMemory();
1825 u32VUIAddr = pShm->u32AVC_VUIDispInfo_Addr;
1826
1827 for (i = 0; i < sizeof(HVD_AVC_VUI_DISP_INFO); i += 4)
1828 {
1829 if (pShm->u32AVC_VUIDispInfo_Addr & VPU_QMEM_BASE)
1830 {
1831 *pData = HAL_VPU_EX_MemRead(u32VUIAddr + i);
1832 }
1833 else
1834 {
1835 *pData = *((MS_U32 *) MsOS_PA2KSEG1(u32VUIAddr + i + pCtrl->MemMap.u32CodeBufAddr));
1836 }
1837 pData++;
1838 }
1839 }
1840 else
1841 {
1842 memset(&(pHVDHalContext->g_hvd_VUIINFO), 0, sizeof(HVD_AVC_VUI_DISP_INFO));
1843 }
1844
1845 return (MS_U32) &(pHVDHalContext->g_hvd_VUIINFO);
1846 }
1847
_HVD_EX_GetBBUQNumb(MS_U32 u32Id)1848 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id)
1849 {
1850 MS_U32 u32ReadPtr = 0;
1851 MS_U32 eRet = 0;
1852 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1853 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1854
1855 u32ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
1856 MS_U32 u32WritePtr = 0;
1857
1858 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1859 {
1860 u32WritePtr = pHVDHalContext->u32VP8BBUWptr;
1861 }
1862 else
1863 {
1864 u32WritePtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
1865 }
1866
1867 HVD_EX_MSG_DBG("idx=%x, bbu rptr=%lx, bbu wptr=%lx\n", u8Idx, u32ReadPtr, u32WritePtr);
1868
1869 if (u32WritePtr >= u32ReadPtr)
1870 {
1871 eRet = u32WritePtr - u32ReadPtr;
1872 }
1873 else
1874 {
1875 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - u32WritePtr);
1876 }
1877
1878 #if 0
1879 if (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr >= u32ReadPtr)
1880 {
1881 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr - u32ReadPtr;
1882 }
1883 else
1884 {
1885 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
1886 }
1887
1888 #endif
1889 return eRet;
1890 }
1891
_HVD_EX_GetPTSQNumb(MS_U32 u32Id)1892 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id)
1893 {
1894 MS_U32 u32ReadPtr = 0;
1895 MS_U32 eRet = 0;
1896 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1897
1898 u32ReadPtr = _HVD_EX_GetPTSTableRptr(u32Id);
1899
1900 if (u32ReadPtr >= MAX_PTS_TABLE_SIZE)
1901 {
1902 HVD_EX_MSG_ERR("PTS table Read Ptr(%lx) > max table size(%lx) \n", u32ReadPtr,
1903 (MS_U32) MAX_PTS_TABLE_SIZE);
1904 return 0;
1905 }
1906
1907 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1908
1909 if (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr >= u32ReadPtr)
1910 {
1911 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr - u32ReadPtr;
1912 }
1913 else
1914 {
1915 eRet = MAX_PTS_TABLE_SIZE - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
1916 }
1917
1918 return eRet;
1919 }
1920
_HVD_EX_GetNextDispFrame(MS_U32 u32Id)1921 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id)
1922 {
1923 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1924 MS_U16 u16QNum = pShm->u16DispQNumb;
1925 MS_U16 u16QPtr = pShm->u16DispQPtr;
1926 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1927
1928 //static volatile HVD_Frm_Information *pHvdFrm = NULL;
1929 #if (HVD_ENABLE_MVC)
1930 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
1931
1932 if(bMVC)
1933 {
1934 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
1935 {
1936 MS_U16 u16RealQPtr = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex;
1937 MS_U16 u16UsedFrm = 0;
1938
1939 if (u16RealQPtr != u16QPtr)
1940 {
1941 if (u16RealQPtr > u16QPtr)
1942 {
1943 u16UsedFrm = u16RealQPtr - u16QPtr;
1944 }
1945 else
1946 {
1947 u16UsedFrm = pShm->u16DispQSize - (u16QPtr - u16RealQPtr);
1948 }
1949 }
1950
1951 if (u16QNum > u16UsedFrm)
1952 {
1953 volatile HVD_Frm_Information *pHvdFrm;
1954
1955 u16QNum -= u16UsedFrm;
1956 u16QPtr = u16RealQPtr;
1957 pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
1958
1959 if ((u16QPtr%2) == 0) //For MVC mode, we must check the pair of display entry is ready or not
1960 {
1961 volatile HVD_Frm_Information *pHvdFrmNext = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr+1];
1962
1963 if (pHvdFrmNext->u32Status != E_HVD_DISPQ_STATUS_INIT)
1964 {
1965 return NULL;
1966 }
1967 }
1968
1969 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
1970 {
1971 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
1972
1973 if ((u16QPtr%2) == 0)
1974 {
1975 //ALOGE("G1: %x", pHvdFrm->u32PrivateData);
1976 pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData = pHvdFrm->u32PrivateData;
1977 }
1978 else
1979 {
1980 //ALOGE("G2: %x", (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
1981 //pShm->UpdateQueue[pShm->u16UpdateQWtPtr] = (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData;
1982 //pShm->u16UpdateQWtPtr = (pShm->u16UpdateQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
1983 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
1984 }
1985
1986 u16QPtr++;
1987 if (u16QPtr == pShm->u16DispQSize) u16QPtr = 0;
1988 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = u16QPtr;
1989
1990 return (HVD_Frm_Information*)(MS_U32)pHvdFrm;
1991 }
1992 }
1993
1994 return NULL;
1995 }
1996
1997 /* Add for Mobile Platform by Ted Sun */
1998 #if 0
1999 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT*3)
2000 {
2001 u16QNum = HVD_DISPQ_PREFETCH_COUNT*3;
2002 }
2003 #endif
2004
2005 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
2006 //search the next frame to display
2007 while (u16QNum > 0)
2008 {
2009 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
2010 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
2011 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2012
2013 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2014 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2015 {
2016 /// For MVC. Output views after the pair of (base and depend) views were decoded.
2017 /// Check the depned view was initial when Output the base view.
2018 if((u16QPtr%2) == 0)
2019 {
2020 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
2021 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
2022 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
2023 {
2024 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
2025 ///printf("Return NULL.\n");
2026 return NULL;
2027 }
2028 }
2029
2030 //printf("V:%d.\n",u16QPtr);
2031 pHVDHalContext->_u16DispQPtr = u16QPtr;
2032 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2033 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%ld\n", u16QPtr,
2034 (MS_U32) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2035 HVD_EX_MSG_INF("<<< halHVD pts,idH = %lu, %lu [%x]\n", pHVDHalContext->pHvdFrm->u32TimeStamp, pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2036 return (HVD_Frm_Information *)(MS_U32) pHVDHalContext->pHvdFrm;
2037 }
2038
2039 u16QNum--;
2040 //go to next frame in the dispQ
2041 u16QPtr++;
2042
2043 if (u16QPtr >= pShm->u16DispQSize)
2044 {
2045 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
2046 }
2047 }
2048 }
2049 else
2050 #endif ///HVD_ENABLE_MVC
2051 {
2052 volatile HVD_Frm_Information *pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2053
2054 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2055 {
2056
2057 while (u16QNum != 0)
2058 {
2059 pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2060
2061 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2062 {
2063 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2064 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
2065
2066 return (HVD_Frm_Information*)(MS_U32)pHvdFrm;
2067
2068 }
2069 u16QNum--;
2070 //go to next frame in the dispQ
2071 u16QPtr++;
2072
2073 if (u16QPtr == pShm->u16DispQSize)
2074 {
2075 u16QPtr = 0; //wrap to the begin
2076 }
2077
2078 }
2079
2080
2081
2082 return NULL;
2083 }
2084 /* Add for Mobile Platform by Ted Sun */
2085 #if 0
2086 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT)
2087 {
2088 u16QNum = HVD_DISPQ_PREFETCH_COUNT;
2089 }
2090 #endif
2091 //printf("Q: %d %d\n", u16QNum, u16QPtr);
2092 //search the next frame to display
2093 while (u16QNum != 0)
2094 {
2095 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2096
2097 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2098 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2099 {
2100 pHVDHalContext->_u16DispQPtr = u16QPtr;
2101 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2102 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%ld\n", u16QPtr,
2103 (MS_U32) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2104 HVD_EX_MSG_INF("<<< halHVD pts,idH = %lu, %lu [%x]\n", pHVDHalContext->pHvdFrm->u32TimeStamp, pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2105 return (HVD_Frm_Information *)(MS_U32) pHVDHalContext->pHvdFrm;
2106 }
2107
2108 u16QNum--;
2109 //go to next frame in the dispQ
2110 u16QPtr++;
2111
2112 if (u16QPtr == pShm->u16DispQSize)
2113 {
2114 u16QPtr = 0; //wrap to the begin
2115 }
2116 }
2117 }
2118
2119 return NULL;
2120 }
2121 MS_BOOL
HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)2122 HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)
2123 {
2124 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2125 MS_U16 u16QNum = pShm->u16DispQNumb;
2126 MS_U16 u16QPtr = pShm->u16DispQPtr;
2127 static volatile HVD_Frm_Information *pHvdFrm = NULL;
2128
2129 #if (HVD_ENABLE_MVC)
2130 if (HAL_HVD_EX_CheckMVCID(u32Id))
2131 {
2132 if (u16QNum == 1) return TRUE;
2133 }
2134 #endif
2135
2136 while (u16QNum != 0)
2137 {
2138 pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2139 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2140 {
2141 return FALSE;
2142 }
2143 u16QNum--;
2144 u16QPtr++;
2145 if (u16QPtr == pShm->u16DispQSize)
2146 {
2147 u16QPtr = 0; //wrap to the begin
2148 }
2149 }
2150
2151 return TRUE;
2152 }
_HVD_EX_GetDrvCtrl(MS_U32 u32Id)2153 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id)
2154 {
2155 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
2156
2157 return &(_pHVDCtrls[u8DrvId]);
2158 }
2159
_HVD_EX_GetStreamIdx(MS_U32 u32Id)2160 static MS_U8 _HVD_EX_GetStreamIdx(MS_U32 u32Id)
2161 {
2162 MS_U8 u8OffsetIdx = 0;
2163 MS_U8 u8SidBaseMask = 0xF0;
2164 HAL_HVD_StreamId eSidBase = (HAL_HVD_StreamId) (u32Id >> 8 & u8SidBaseMask);
2165
2166 switch (eSidBase)
2167 {
2168 case E_HAL_HVD_MAIN_STREAM_BASE:
2169 {
2170 u8OffsetIdx = 0;
2171 break;
2172 }
2173 case E_HAL_VPU_SUB_STREAM_BASE:
2174 {
2175 u8OffsetIdx = 1;
2176 break;
2177 }
2178 case E_HAL_VPU_MVC_STREAM_BASE:
2179 {
2180 u8OffsetIdx = 0;
2181 break;
2182 }
2183 default:
2184 {
2185 u8OffsetIdx = 0;
2186 break;
2187 }
2188 }
2189
2190 return u8OffsetIdx;
2191 }
2192 /*
2193 static MS_BOOL _HAL_HVD_EX_HVDInUsed(void)
2194 {
2195 MS_U32 i = 0;
2196 for(i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
2197 {
2198 if(TRUE == pHVDHalContext->_stHVDStream[i].bUsed)
2199 {
2200 return TRUE;
2201 }
2202 }
2203 return FALSE;
2204 }
2205 */
2206
HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)2207 MS_U32 HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)
2208 {
2209 MS_U32 u32PhyAddr = 0x0;
2210 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2211
2212 if (pCtrl->MemMap.u32CodeBufAddr == 0)
2213 {
2214 return 0;
2215 }
2216
2217 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
2218
2219 if (u32PhyAddr == 0xFFFFFFFF)
2220 {
2221 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
2222 }
2223 else
2224 {
2225 #if defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
2226 //u32PhyAddr += 0; // if define HVD_OLD_LAYOUT_SHARE_MEM_BIAS under SUPPORT_NEW_MEM_LAYOUT, then we could refine the codes here
2227 #else
2228 u32PhyAddr += HVD_OLD_LAYOUT_SHARE_MEM_BIAS;
2229 #endif
2230 }
2231
2232 return MsOS_PA2KSEG1(u32PhyAddr);
2233 }
2234
2235
HAL_HVD_MVDMiuClientSel(MS_U8 u8MiuSel)2236 void HAL_HVD_MVDMiuClientSel(MS_U8 u8MiuSel)
2237 {
2238
2239 if (u8MiuSel == 0)
2240 {
2241 _HVD_WriteWordMask(MIU_CLIENT_SELECT_GP2, 0, MIU_CLIENT_SELECT_GP2_MVD);
2242 }
2243 else
2244 {
2245 _HVD_WriteWordMask(MIU_CLIENT_SELECT_GP2, MIU_CLIENT_SELECT_GP2_MVD, MIU_CLIENT_SELECT_GP2_MVD);
2246 }
2247
2248 }
2249
2250
2251
2252
HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)2253 MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)
2254 {
2255 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
2256 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2257
2258 // power on / reset HVD; set nal, es rw, bbu parser, release HVD engine
2259 // re-setup clock.
2260
2261 if (!HAL_VPU_EX_HVDInUsed())
2262 {
2263 printf("HVD power on\n");
2264 HAL_HVD_EX_PowerCtrl(TRUE);
2265 }
2266
2267 #if SUPPORT_EVD
2268 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2269 {
2270 printf("EVD power on\n");
2271 HAL_EVD_EX_PowerCtrl(TRUE);
2272 }
2273 #endif
2274
2275 if ((!HAL_VPU_EX_HVDInUsed()) && (DecoderType != E_VPU_EX_DECODER_MVD))
2276 {
2277 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
2278 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
2279 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
2280 _HVD_EX_ResetMainSubBBUWptr(u32Id);
2281
2282 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
2283
2284 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_MC_MIU_256 , HVD_REG_MC_MIU_256);
2285
2286
2287 if((pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable) &&
2288 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
2289 {
2290 if(pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufAddr >= HAL_MIU1_BASE)
2291 {
2292 _HAL_HVD_Entry();
2293 HAL_HVD_MVDMiuClientSel(1);
2294 _HAL_HVD_Release();
2295 }
2296 else
2297 {
2298 _HAL_HVD_Entry();
2299 HAL_HVD_MVDMiuClientSel(0);
2300 _HAL_HVD_Release();
2301 }
2302 }
2303 }
2304
2305 #if SUPPORT_EVD
2306 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2307 {
2308 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
2309 }
2310 #endif
2311
2312 if(pCtrl == NULL)
2313 {
2314 HVD_EX_MSG_ERR("HAL_HVD_EX_InitHW Ctrl is NULL.\n");
2315 //return FALSE;
2316 goto RESET;
2317 }
2318
2319 #if SUPPORT_EVD
2320 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2321 {
2322 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_HEVC_MODE, EVD_REG_RESET_HK_HEVC_MODE);
2323
2324 if ((E_HVD_INIT_MAIN_LIVE_STREAM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK))
2325 ||(E_HVD_INIT_MAIN_FILE_TS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK)))
2326 {
2327 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_TSP2EVD_EN, EVD_REG_RESET_HK_TSP2EVD_EN);
2328 }
2329 goto RESET;
2330 }
2331 #endif
2332
2333 // HVD4, from JANUS and later chip
2334 switch ((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK)
2335 {
2336 case E_HVD_INIT_HW_AVS:
2337 {
2338 if (0 == u8TaskId)
2339 {
2340 _HVD_WriteWordMask(HVD_REG_RESET, 0,
2341 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
2342 }
2343 else
2344 {
2345 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
2346 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
2347 }
2348
2349 break;
2350 }
2351 case E_HVD_INIT_HW_RM:
2352 {
2353 if (0 == u8TaskId)
2354 {
2355 _HVD_WriteWordMask(HVD_REG_RESET, 0,
2356 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
2357
2358 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
2359 {
2360 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
2361 }
2362 else // RV 8
2363 {
2364 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
2365 }
2366 }
2367 else
2368 {
2369 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
2370 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
2371
2372 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
2373 {
2374 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
2375 }
2376 else // RV 8
2377 {
2378 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
2379 }
2380
2381 }
2382
2383 break;
2384 }
2385 default:
2386 {
2387 if (0 == u8TaskId)
2388 {
2389 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
2390 }
2391 else
2392 {
2393 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
2394 }
2395 break;
2396 }
2397 }
2398
2399 RESET:
2400 //T9: use miu128bit
2401 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
2402
2403 if (!HAL_VPU_EX_HVDInUsed())
2404 {
2405 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128));
2406 }
2407
2408 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
2409
2410 #if SUPPORT_EVD
2411 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2412 {
2413 printf("EVD miu 256 bits\n");
2414 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) | EVD_REG_RESET_MIU_256));
2415 }
2416 #endif
2417 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
2418 // Only ES buffer addrress needs to be set for VP8
2419 _HVD_EX_SetESBufferAddr(u32Id);
2420 #else
2421 if(DecoderType != E_VPU_EX_DECODER_MVD)
2422 {
2423 _HVD_EX_SetBufferAddr(u32Id);
2424 }
2425 #endif
2426 if (!HAL_VPU_EX_HVDInUsed())
2427 {
2428 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST);
2429 }
2430
2431 #if SUPPORT_EVD
2432 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2433 {
2434 _HVD_WriteWordMask(EVD_REG_RESET, 0, EVD_REG_RESET_SWRST);
2435 }
2436 #endif
2437
2438 return TRUE;
2439 }
2440
HAL_HVD_EX_DeinitHW(void)2441 MS_BOOL HAL_HVD_EX_DeinitHW(void)
2442 {
2443 MS_U16 u16Timeout = 1000;
2444
2445 _HVD_EX_SetMIUProtectMask(TRUE);
2446
2447 #if SUPPORT_EVD //EVD using HVD DIU, it should be turn off EVD first
2448 //We assume HEVC belong to HVD, so we can disable EVD_REG_RESET_HK_TSP2EVD_EN in DeinitHW.
2449 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_HK_TSP2EVD_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser
2450 HAL_EVD_EX_DeinitHW();
2451 #endif
2452
2453 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
2454
2455 while (u16Timeout)
2456 {
2457 if ((_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) == (HVD_REG_RESET_SWRST_FIN))
2458 {
2459 break;
2460 }
2461 u16Timeout--;
2462 }
2463
2464 HAL_HVD_EX_PowerCtrl(FALSE);
2465
2466 _HVD_EX_SetMIUProtectMask(FALSE);
2467
2468 return TRUE;
2469 }
2470
HAL_HVD_EX_FlushMemory(void)2471 void HAL_HVD_EX_FlushMemory(void)
2472 {
2473 MsOS_FlushMemory();
2474 }
2475
HAL_HVD_EX_ReadMemory(void)2476 void HAL_HVD_EX_ReadMemory(void)
2477 {
2478 MsOS_ReadMemory();
2479 }
2480
HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl * pHVDCtrlsBase)2481 void HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl *pHVDCtrlsBase)
2482 {
2483 _pHVDCtrls = pHVDCtrlsBase;
2484 }
2485
HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)2486 void HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)
2487 {
2488 return;
2489 }
2490
HAL_HVD_EX_GetHWVersionID(void)2491 MS_U32 HAL_HVD_EX_GetHWVersionID(void)
2492 {
2493 return _HVD_Read2Byte(HVD_REG_REV_ID);
2494 }
2495
2496
HAL_HVD_EX_Init_Share_Mem(void)2497 MS_BOOL HAL_HVD_EX_Init_Share_Mem(void)
2498 {
2499 #if (defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS))
2500 #if !defined(SUPPORT_X_MODEL_FEATURE)
2501 MS_U32 u32ShmId;
2502 MS_U32 u32Addr;
2503 MS_U32 u32BufSize;
2504
2505
2506 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HVD HAL",
2507 sizeof(HVD_Hal_CTX),
2508 &u32ShmId,
2509 &u32Addr,
2510 &u32BufSize,
2511 MSOS_SHM_QUERY))
2512 {
2513 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HVD HAL",
2514 sizeof(HVD_Hal_CTX),
2515 &u32ShmId,
2516 &u32Addr,
2517 &u32BufSize,
2518 MSOS_SHM_CREATE))
2519 {
2520 HVD_EX_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
2521 if(pHVDHalContext == NULL)
2522 {
2523 pHVDHalContext = &gHVDHalContext;
2524 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
2525 _HVD_EX_Context_Init_HAL();
2526 HVD_PRINT("[%s]Global structure init Success!!!\n",__FUNCTION__);
2527 }
2528 else
2529 {
2530 HVD_PRINT("[%s]Global structure exists!!!\n",__FUNCTION__);
2531 }
2532 //return FALSE;
2533 }
2534 else
2535 {
2536 memset((MS_U8*)u32Addr,0,sizeof(HVD_Hal_CTX));
2537 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for one process
2538 _HVD_EX_Context_Init_HAL();
2539 }
2540 }
2541 else
2542 {
2543 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for another process
2544 }
2545 #else
2546 if(pHVDHalContext == NULL)
2547 {
2548 pHVDHalContext = &gHVDHalContext;
2549 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
2550 _HVD_EX_Context_Init_HAL();
2551 }
2552 #endif
2553 _HAL_HVD_MutexCreate();
2554 #else
2555 if(pHVDHalContext == NULL)
2556 {
2557 pHVDHalContext = &gHVDHalContext;
2558 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
2559 _HVD_EX_Context_Init_HAL();
2560 }
2561 #endif
2562
2563 return TRUE;
2564 }
2565
2566
HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)2567 HAL_HVD_StreamId HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)
2568 {
2569 MS_U32 i = 0;
2570
2571 if (eStreamType == E_HAL_HVD_MVC_STREAM)
2572 {
2573 if ((FALSE == pHVDHalContext->_stHVDStream[0].bUsed) && (FALSE == pHVDHalContext->_stHVDStream[1].bUsed))
2574 return pHVDHalContext->_stHVDStream[0].eStreamId;
2575 }
2576 else if (eStreamType == E_HAL_HVD_MAIN_STREAM)
2577 {
2578 for (i = 0;
2579 i <
2580 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
2581 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
2582 {
2583 if ((E_HAL_HVD_MAIN_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
2584 {
2585 return pHVDHalContext->_stHVDStream[i].eStreamId;
2586 }
2587 }
2588 }
2589 else if (eStreamType == E_HAL_HVD_SUB_STREAM)
2590 {
2591 for (i = 0;
2592 i <
2593 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
2594 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
2595 {
2596 if ((E_HAL_HVD_SUB_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
2597 {
2598 return pHVDHalContext->_stHVDStream[i].eStreamId;
2599 }
2600 }
2601 }
2602
2603 return E_HAL_HVD_STREAM_NONE;
2604 }
2605
HAL_HVD_EX_PowerCtrl(MS_BOOL bEnable)2606 void HAL_HVD_EX_PowerCtrl(MS_BOOL bEnable)
2607 {
2608 if (bEnable)
2609 {
2610 _HVD_WriteByteMask(REG_TOP_HVD, ~TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
2611 }
2612 else
2613 {
2614 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
2615 }
2616
2617 // fix to not inverse
2618 _HVD_WriteByteMask(REG_TOP_HVD, ~TOP_CKG_HVD_INV, TOP_CKG_HVD_INV);
2619
2620 switch (pHVDHalContext->u32HVDClockType)
2621 {
2622 case 240:
2623 {
2624 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_240MHZ, TOP_CKG_HVD_CLK_MASK);
2625
2626 break;
2627 }
2628 case 216:
2629 {
2630 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_216MHZ, TOP_CKG_HVD_CLK_MASK);
2631
2632 break;
2633 }
2634 case 172:
2635 {
2636 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_172MHZ, TOP_CKG_HVD_CLK_MASK);
2637
2638 break;
2639 }
2640 case 160:
2641 {
2642 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_160MHZ, TOP_CKG_HVD_CLK_MASK);
2643
2644 break;
2645 }
2646 default:
2647 {
2648 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_240MHZ, TOP_CKG_HVD_CLK_MASK); // TODO://if(hvd_clk > miu_clk) set to TOP_CKG_HVD_IDB_CLK_HVD_MIU = 0
2649 // TODO://else set to TOP_CKG_HVD_IDB_CLK_HVD_MIU = 1
2650 break;
2651 }
2652 }
2653
2654 return;
2655 }
2656
HAL_HVD_EX_InitRegBase(MS_U32 u32RegBase)2657 void HAL_HVD_EX_InitRegBase(MS_U32 u32RegBase)
2658 {
2659 u32HVDRegOSBase = u32RegBase;
2660 HAL_VPU_EX_InitRegBase(u32RegBase);
2661 }
2662
HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_U32 drvprectrl)2663 void HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_U32 drvprectrl)
2664 {
2665 HVD_Pre_Ctrl *pHVDPreCtrl_in = (HVD_Pre_Ctrl*)drvprectrl;
2666 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2667 pHVDHalContext->pHVDPreCtrl_Hal[u8Idx] = pHVDPreCtrl_in;
2668 }
2669
HAL_HVD_EX_InitVariables(MS_U32 u32Id)2670 HVD_Return HAL_HVD_EX_InitVariables(MS_U32 u32Id)
2671 {
2672 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2673 HVD_ShareMem *pShm = NULL;
2674 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2675 #if HVD_ENABLE_MVC
2676 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
2677 #endif ///HVD_ENABLE_MVC
2678
2679 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = 0;
2680 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = 0;
2681 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = 0;
2682 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
2683 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
2684 #if HVD_ENABLE_MVC
2685 if(bMVC)
2686 {
2687 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSPreWptr = 0;
2688 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSByteCnt = 0;
2689 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUWptr = 0;
2690 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = 0;
2691 }
2692 #endif ///HVD_ENABLE_MVC
2693
2694 // set a local copy of FW code address; assuming there is only one copy of FW,
2695 // no matter how many task will be created.
2696
2697 pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2698
2699 memset((void *) (pHVDHalContext->g_hvd_nal_fill_pair), 0, 16);
2700
2701 // global variables
2702 pHVDHalContext->u32HVDCmdTimeout = pCtrl->u32CmdTimeout;
2703
2704
2705 // pHVDHalContext->u32VPUClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
2706 // pHVDHalContext->u32HVDClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
2707 // Create mutex
2708 //_HAL_HVD_MutexCreate();
2709
2710 // fill HVD init variables
2711 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2712 {
2713 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = VP8_BBU_DRAM_TBL_ENTRY;
2714 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = VP8_BBU_DRAM_TBL_ENTRY_TH;
2715 }
2716 else
2717 #if HVD_ENABLE_RV_FEATURE
2718 if (((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
2719 {
2720 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = RVD_BBU_DRAM_TBL_ENTRY;
2721 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = RVD_BBU_DRAM_TBL_ENTRY_TH;
2722
2723 if (pCtrl->MemMap.u32FrameBufSize > RV_VLC_TABLE_SIZE)
2724 {
2725 pHVDHalContext->u32RV_VLCTableAddr = pCtrl->MemMap.u32FrameBufSize - RV_VLC_TABLE_SIZE;
2726 pCtrl->MemMap.u32FrameBufSize -= RV_VLC_TABLE_SIZE;
2727 }
2728 else
2729 {
2730 HVD_EX_MSG_ERR("HAL_HVD_EX_InitVariables failed: frame buffer size too small. FB:%lx min:%lx\n",
2731 (MS_U32) pCtrl->MemMap.u32FrameBufSize, (MS_U32) RV_VLC_TABLE_SIZE);
2732 return E_HVD_RETURN_INVALID_PARAMETER;
2733 }
2734 }
2735 else
2736 #endif
2737 {
2738 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = HVD_BBU_DRAM_TBL_ENTRY;
2739 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = HVD_BBU_DRAM_TBL_ENTRY_TH;
2740 #if HVD_ENABLE_MVC
2741 if(bMVC)
2742 {
2743 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = MVC_BBU_DRAM_TBL_ENTRY;
2744 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNumTH = MVC_BBU_DRAM_TBL_ENTRY_TH;
2745 }
2746 #endif /// HVD_ENABLE_MVC
2747 pHVDHalContext->u32RV_VLCTableAddr = 0;
2748 }
2749
2750 if ((HAL_VPU_EX_GetShareInfoAddr(u32Id) != 0xFFFFFFFF)
2751 || ((pCtrl->MemMap.u32CodeBufVAddr <= (MS_U32) pShm) && ((MS_U32) pShm <= (pCtrl->MemMap.u32CodeBufVAddr + pCtrl->MemMap.u32CodeBufSize)))
2752 || ((pCtrl->MemMap.u32BitstreamBufVAddr <= (MS_U32) pShm) && ((MS_U32) pShm <= (pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->MemMap.u32BitstreamBufSize)))
2753 || ((pCtrl->MemMap.u32FrameBufVAddr <= (MS_U32) pShm) && ((MS_U32) pShm <= (pCtrl->MemMap.u32FrameBufVAddr + pCtrl->MemMap.u32FrameBufSize))))
2754 {
2755 HVD_EX_MSG_DBG("input memory: Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miubase=0x%lx\n",
2756 pCtrl->MemMap.u32CodeBufAddr,
2757 pCtrl->MemMap.u32FrameBufAddr,
2758 pCtrl->MemMap.u32BitstreamBufAddr,
2759 pCtrl->MemMap.u32MIU1BaseAddr);
2760 #if HVD_ENABLE_MVC
2761 if(bMVC)
2762 {
2763 HVD_EX_Drv_Ctrl *pHVDCtrl_in_sub = _HVD_EX_GetDrvCtrl(u32Id+0x00011000);
2764 if (( (pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr)<= (MS_U32)pShm)&& ( (MS_U32)pShm <= ((pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr )+ pHVDCtrl_in_sub->MemMap.u32BitstreamBufSize)))
2765 {
2766 HVD_EX_MSG_DBG("[MVC] Bitstream2: 0x%lx.\n", pCtrl->MemMap.u32BitstreamBufAddr);
2767 }
2768 }
2769 #endif /// HVD_ENABLE_MVC
2770
2771 return E_HVD_RETURN_SUCCESS;
2772 }
2773 else
2774 {
2775 HVD_EX_MSG_ERR("failed: Shm addr=0x%lx, Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miubase=0x%lx\n",
2776 MS_PA2KSEG1((MS_U32) pShm),
2777 pCtrl->MemMap.u32CodeBufAddr,
2778 pCtrl->MemMap.u32FrameBufAddr,
2779 pCtrl->MemMap.u32BitstreamBufAddr,
2780 pCtrl->MemMap.u32MIU1BaseAddr);
2781 return E_HVD_RETURN_INVALID_PARAMETER;
2782 }
2783 }
2784
HAL_HVD_EX_InitShareMem(MS_U32 u32Id)2785 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id)
2786 {
2787 MS_U32 u32Addr = 0;
2788 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2789 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2790 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2791
2792 memset(pShm, 0, sizeof(HVD_ShareMem));
2793
2794 u32Addr = pCtrl->MemMap.u32FrameBufAddr;
2795
2796 if (u32Addr >= pCtrl->MemMap.u32MIU1BaseAddr)
2797 {
2798 u32Addr -= pCtrl->MemMap.u32MIU1BaseAddr;
2799 }
2800
2801 pShm->u32FrameRate = pCtrl->InitParams.u32FrameRate;
2802 pShm->u32FrameRateBase = pCtrl->InitParams.u32FrameRateBase;
2803 pShm->u32FrameBufAddr = u32Addr;
2804 pShm->u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
2805 pShm->DispInfo.u16DispWidth = 1;
2806 pShm->DispInfo.u16DispHeight = 1;
2807 pShm->u32CodecType = pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK;
2808 pShm->u32CPUClock = pHVDHalContext->u32VPUClockType;
2809 pShm->u32UserCCIdxWrtPtr = 0xFFFFFFFF;
2810 pShm->DispFrmInfo.u32TimeStamp = 0xFFFFFFFF;
2811 //Chip info
2812 pShm->u16ChipID = E_MSTAR_CHIP_MUNICH;
2813 pShm->u16ChipECONum = pCtrl->InitParams.u16ChipECONum;
2814 // PreSetControl
2815 if (pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->bOnePendingBuffer)
2816 {
2817 pShm->u32PreSetControl |= PRESET_ONE_PENDING_BUFFER;
2818 }
2819
2820
2821 if ((pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable) &&
2822 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
2823 {
2824 pShm->u32PreSetControl |= PRESET_IAP_GN_SHARE_BW_MODE;
2825
2826 if(pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufAddr >= HAL_MIU1_BASE)
2827 {
2828 pShm->u32IapGnBufAddr = pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufAddr - HAL_MIU1_BASE;
2829 pShm->u32IapGnBufSize = pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufSize;
2830 }
2831 else
2832 {
2833 pShm->u32IapGnBufAddr = pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufAddr;
2834 pShm->u32IapGnBufSize = pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufSize;
2835 }
2836 }
2837
2838
2839 //pShm->bColocateBBUMode = pCtrl->InitParams.bColocateBBUMode;//johnny.ko
2840 //pShm->bColocateBBUMode = _stHVDPreSet[u8Idx].bColocateBBUMode;//johnny.ko
2841 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
2842 pShm->u8BBUMode = E_HVD_FW_AUTO_BBU_MODE;
2843 else
2844 pShm->u8BBUMode = E_HVD_DRV_AUTO_BBU_MODE;
2845 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_RAW)
2846 {
2847 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
2848 {
2849 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE_DUAL_ES;
2850 }
2851 else
2852 {
2853 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE;
2854 }
2855 }
2856 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_TS)
2857 {
2858 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
2859 {
2860 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE_DUAL_ES;
2861 }
2862 else
2863 {
2864 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE;
2865 }
2866 }
2867 else
2868 {
2869 pShm->u8SrcMode = E_HVD_SRC_MODE_DTV;
2870 }
2871
2872 #if 1//From T4 and the later chips, QDMA can support the address more than MIU1 base.
2873 if(pCtrl->MemMap.u32CodeBufAddr >= HAL_MIU1_BASE)
2874 {
2875 pShm->u32FWBaseAddr = (pCtrl->MemMap.u32CodeBufAddr-HAL_MIU1_BASE) | 0x40000000; //Bit30 sel miu0/1
2876 }
2877 else
2878 {
2879 pShm->u32FWBaseAddr = pCtrl->MemMap.u32CodeBufAddr;
2880 }
2881 //printf("<DBG>QDMA Addr = %lx <<<<<<<<<<<<<<<<<<<<<<<<\n",pShm->u32FWBaseAddr);
2882 #else
2883 u32Addr = pCtrl->MemMap.u32CodeBufAddr;
2884 if (u32Addr >= pCtrl->MemMap.u32MIU1BaseAddr)
2885 {
2886 u32Addr -= pCtrl->MemMap.u32MIU1BaseAddr;
2887 }
2888 pShm->u32FWBaseAddr = u32Addr;
2889 #endif
2890
2891 // RM only
2892 #if HVD_ENABLE_RV_FEATURE
2893 if ((((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
2894 && (pCtrl->InitParams.pRVFileInfo != NULL))
2895 {
2896 MS_U32 i = 0;
2897
2898 for (i = 0; i < HVD_RM_INIT_PICTURE_SIZE_NUMBER; i++)
2899 {
2900 pShm->pRM_PictureSize[i].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[i];
2901 pShm->pRM_PictureSize[i].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[i];
2902 }
2903
2904 pShm->u8RM_Version = (MS_U8) pCtrl->InitParams.pRVFileInfo->RV_Version;
2905 pShm->u8RM_NumSizes = (MS_U8) pCtrl->InitParams.pRVFileInfo->ulNumSizes;
2906 u32Addr = pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr;
2907
2908 if (u32Addr >= pCtrl->MemMap.u32MIU1BaseAddr)
2909 {
2910 u32Addr -= pCtrl->MemMap.u32MIU1BaseAddr;
2911 }
2912
2913 pShm->u32RM_VLCTableAddr = u32Addr;
2914 }
2915 #endif
2916
2917 if ((E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2918 && (pCtrl->InitParams.pRVFileInfo != NULL))
2919 {
2920 pShm->pRM_PictureSize[0].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[0];
2921 pShm->pRM_PictureSize[0].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[0];
2922 }
2923
2924 //if(pCtrl->InitParams.bColocateBBUMode)
2925 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
2926 {
2927 pShm->u32ColocateBBUWritePtr = pShm->u32ColocateBBUReadPtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
2928 }
2929
2930 HAL_HVD_EX_FlushMemory();
2931
2932 return E_HVD_RETURN_SUCCESS;
2933 }
2934
HAL_HVD_EX_InitRegCPU(MS_U32 u32Id)2935 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id)
2936 {
2937 MS_BOOL bInitRet = FALSE;
2938
2939 #if 0
2940 // check MVD power on
2941 if (_HVD_Read2Byte(REG_TOP_MVD) & (TOP_CKG_MHVD_DIS))
2942 {
2943 HVD_EX_MSG_INF("HVD warning: MVD is not power on before HVD init.\n");
2944 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
2945 HVD_Delay_ms(1);
2946 }
2947 // Check VPU power on
2948 if (_HVD_Read2Byte(REG_TOP_VPU) & (TOP_CKG_VPU_DIS))
2949 {
2950 HVD_EX_MSG_INF("HVD warning: VPU is not power on before HVD init.\n");
2951 _HVD_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
2952 HVD_Delay_ms(1);
2953 }
2954 // check HVD power on
2955 if (_HVD_Read2Byte(REG_TOP_HVD) & (TOP_CKG_HVD_DIS))
2956 {
2957 HVD_EX_MSG_INF("HVD warning: HVD is not power on before HVD init.\n");
2958 HAL_HVD_EX_PowerCtrl(TRUE);
2959 HVD_Delay_ms(1);
2960 }
2961 #endif
2962
2963 bInitRet = _HVD_EX_SetRegCPU(u32Id);
2964
2965 if (!bInitRet)
2966 {
2967 return E_HVD_RETURN_FAIL;
2968 }
2969
2970 bInitRet = HAL_HVD_EX_RstPTSCtrlVariable(u32Id);
2971
2972 if (!bInitRet)
2973 {
2974 return E_HVD_RETURN_FAIL;
2975 }
2976
2977 return E_HVD_RETURN_SUCCESS;
2978 }
2979
HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id,MS_BOOL bEnable)2980 HVD_Return HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id, MS_BOOL bEnable)
2981 {
2982 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2983
2984 _stHVDPreSet[u8Idx].bColocateBBUMode = bEnable;
2985
2986 return E_HVD_RETURN_SUCCESS;
2987 }
2988
HAL_HVD_EX_SetData(MS_U32 u32Id,HVD_SetData u32type,MS_U32 u32Data)2989 HVD_Return HAL_HVD_EX_SetData(MS_U32 u32Id, HVD_SetData u32type, MS_U32 u32Data)
2990 {
2991 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
2992 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2993 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2994 MS_BOOL bMVC = FALSE;
2995 #if HVD_ENABLE_MVC
2996 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
2997 #endif
2998
2999 switch (u32type)
3000 {
3001 // share memory
3002 // switch
3003 case E_HVD_SDATA_FRAMEBUF_ADDR:
3004 {
3005 pShm->u32FrameBufAddr = u32Data;
3006 break;
3007 }
3008 case E_HVD_SDATA_FRAMEBUF_SIZE:
3009 {
3010 pShm->u32FrameBufSize = u32Data;
3011 break;
3012 }
3013 case E_HVD_SDATA_RM_PICTURE_SIZES:
3014 {
3015 HVD_memcpy((volatile void *) pShm->pRM_PictureSize, (void *) ((HVD_PictureSize *) u32Data),
3016 HVD_RM_INIT_PICTURE_SIZE_NUMBER * sizeof(HVD_PictureSize));
3017 break;
3018 }
3019 case E_HVD_SDATA_ERROR_CODE:
3020 {
3021 pShm->u16ErrCode = (MS_U16) u32Data;
3022 break;
3023 }
3024 case E_HVD_SDATA_DISP_INFO_TH:
3025 {
3026 HVD_memcpy((volatile void *) &(pShm->DispThreshold), (void *) ((HVD_DISP_THRESHOLD *) u32Data),
3027 sizeof(HVD_DISP_THRESHOLD));
3028 break;
3029 }
3030 case E_HVD_SDATA_FW_FLUSH_STATUS:
3031 {
3032 pShm->u8FlushStatus = (MS_U8)u32Data;
3033 break;
3034 }
3035 case E_HVD_SDATA_DMX_FRAMERATE:
3036 {
3037 pShm->u32DmxFrameRate = u32Data;
3038 break;
3039 }
3040 case E_HVD_SDATA_DMX_FRAMERATEBASE:
3041 {
3042 pShm->u32DmxFrameRateBase = u32Data;
3043 break;
3044 }
3045 // SRAM
3046
3047 // Mailbox
3048 case E_HVD_SDATA_TRIGGER_DISP: // HVD HI mbox 0
3049 {
3050 if (u32Data != 0)
3051 {
3052 pShm->bEnableDispCtrl = TRUE;
3053 pShm->bIsTrigDisp = TRUE;
3054 }
3055 else
3056 {
3057 pShm->bEnableDispCtrl = FALSE;
3058 }
3059
3060 break;
3061 }
3062 case E_HVD_SDATA_GET_DISP_INFO_START:
3063 {
3064 pShm->bSpsChange = FALSE;
3065 break;
3066 }
3067 case E_HVD_SDATA_VIRTUAL_BOX_WIDTH:
3068 {
3069 pShm->u32VirtualBoxWidth = u32Data;
3070 break;
3071 }
3072 case E_HVD_SDATA_VIRTUAL_BOX_HEIGHT:
3073 {
3074 pShm->u32VirtualBoxHeight = u32Data;
3075 break;
3076 }
3077 case E_HVD_SDATA_DISPQ_STATUS_VIEW:
3078 {
3079 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_INIT)
3080 {
3081 //printf("DispFrame DqPtr: %d\n", u32Data);
3082 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_VIEW;
3083 }
3084 break;
3085 }
3086 case E_HVD_SDATA_DISPQ_STATUS_DISP:
3087 {
3088 if(!(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide))
3089 {
3090 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
3091 {
3092 //printf("DispFrame DqPtr: %ld\n", u32Data);
3093 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_DISP;
3094 }
3095 }
3096 break;
3097 }
3098 case E_HVD_SDATA_DISPQ_STATUS_FREE:
3099 {
3100 if(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
3101 {
3102 if (bMVC)
3103 {
3104 if (pHVDHalContext->_stHVDStream[u8Idx].u32FreeData == 0xFFFF)
3105 {
3106 //ALOGE("R1: %x", u32Data);
3107 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = u32Data;
3108 }
3109 else
3110 {
3111 //ALOGE("R2: %x", (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
3112 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
3113 //pShm->FreeQueue[pShm->u16FreeQWtPtr] = (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData;
3114 //pShm->u16FreeQWtPtr = (pShm->u16FreeQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
3115 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
3116 }
3117 }
3118 else
3119 {
3120 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, u32Data);
3121 }
3122 }
3123 else
3124 {
3125 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
3126 {
3127 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_FREE;
3128 }
3129 }
3130 break;
3131 }
3132 default:
3133 break;
3134 }
3135
3136 HAL_HVD_EX_FlushMemory();
3137
3138 return eRet;
3139 }
3140
HAL_HVD_EX_GetData_EX(MS_U32 u32Id,HVD_GetData eType)3141 MS_S64 HAL_HVD_EX_GetData_EX(MS_U32 u32Id, HVD_GetData eType)
3142 {
3143 MS_S64 s64Ret = 0;
3144 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3145
3146 HAL_HVD_EX_ReadMemory();
3147
3148 switch (eType)
3149 {
3150 case E_HVD_GDATA_PTS_STC_DIFF:
3151 s64Ret = pShm->s64PtsStcDiff;
3152 break;
3153 default:
3154 break;
3155 }
3156
3157 return s64Ret;
3158 }
3159
HAL_HVD_EX_GetData(MS_U32 u32Id,HVD_GetData eType)3160 MS_U32 HAL_HVD_EX_GetData(MS_U32 u32Id, HVD_GetData eType)
3161 {
3162 MS_U32 u32Ret = 0;
3163 //static MS_U64 u64pts_real = 0;
3164 MS_U64 u64pts_low = 0;
3165 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3166 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3167
3168 HAL_HVD_EX_ReadMemory();
3169
3170 if(pShm == NULL)
3171 {
3172 printf("########## VDEC patch for Debug ###########\n");
3173 return 0x0;
3174 }
3175
3176 switch (eType)
3177 {
3178 // share memory
3179 // switch
3180 case E_HVD_GDATA_DISP_INFO_ADDR:
3181 {
3182 u32Ret = (MS_U32) (&pShm->DispInfo);
3183 break;
3184 }
3185 // report
3186 case E_HVD_GDATA_PTS:
3187 {
3188 u32Ret = pShm->DispFrmInfo.u32TimeStamp;
3189 break;
3190 }
3191 case E_HVD_GDATA_U64PTS:
3192 {
3193 u64pts_low = (MS_U64)(pShm->DispFrmInfo.u32TimeStamp);
3194 pHVDHalContext->u64pts_real = (MS_U64)(pShm->DispFrmInfo.u32ID_H);
3195 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
3196 u32Ret = (MS_U32)(&(pHVDHalContext->u64pts_real));
3197 break;
3198 }
3199 case E_HVD_GDATA_DECODE_CNT:
3200 {
3201 u32Ret = pShm->u32DecodeCnt;
3202 break;
3203 }
3204 case E_HVD_GDATA_DATA_ERROR_CNT:
3205 {
3206 u32Ret = pShm->u32DataErrCnt;
3207 break;
3208 }
3209 case E_HVD_GDATA_DEC_ERROR_CNT:
3210 {
3211 u32Ret = pShm->u32DecErrCnt;
3212 break;
3213 }
3214 case E_HVD_GDATA_ERROR_CODE:
3215 {
3216 u32Ret = (MS_U32) (pShm->u16ErrCode);
3217 break;
3218 }
3219 case E_HVD_GDATA_VPU_IDLE_CNT:
3220 {
3221 u32Ret = pShm->u32VPUIdleCnt;
3222 break;
3223 }
3224 case E_HVD_GDATA_DISP_FRM_INFO:
3225 {
3226 u32Ret = (MS_U32) (&pShm->DispFrmInfo);
3227 break;
3228 }
3229 case E_HVD_GDATA_DEC_FRM_INFO:
3230 {
3231 u32Ret = (MS_U32) (&pShm->DecoFrmInfo);
3232 break;
3233 }
3234 case E_HVD_GDATA_ES_LEVEL:
3235 {
3236 u32Ret = (MS_U32) (_HVD_EX_GetESLevel(u32Id));
3237 break;
3238 }
3239 #if HVD_ENABLE_MVC
3240 case E_HVD_GDATA_DISP_FRM_INFO_SUB:
3241 {
3242 u32Ret= (MS_U32) (&(pShm->DispFrmInfo_Sub));
3243 break;
3244 }
3245 case E_HVD_GDATA_DEC_FRM_INFO_SUB:
3246 {
3247 u32Ret= (MS_U32) (&(pShm->DecoFrmInfo_Sub));
3248 break;
3249 }
3250 #endif
3251
3252 // user data
3253 case E_HVD_GDATA_USERDATA_WPTR:
3254 {
3255 u32Ret = (MS_U32) (pShm->u32UserCCIdxWrtPtr);
3256 break;
3257 }
3258 case E_HVD_GDATA_USERDATA_IDX_TBL_ADDR:
3259 {
3260 u32Ret = (MS_U32) (pShm->u8UserCCIdx);
3261 break;
3262 }
3263 case E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR:
3264 {
3265 u32Ret = (MS_U32) (pShm->u32UserCCBase);
3266 break;
3267 }
3268 case E_HVD_GDATA_USERDATA_PACKET_SIZE:
3269 {
3270 u32Ret = (MS_U32) (sizeof(DTV_BUF_type));
3271 break;
3272 }
3273 case E_HVD_GDATA_USERDATA_IDX_TBL_SIZE:
3274 {
3275 u32Ret = (MS_U32) (USER_CC_IDX_SIZE);
3276 break;
3277 }
3278 case E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE:
3279 {
3280 u32Ret = (MS_U32) (USER_CC_DATA_SIZE);
3281 break;
3282 }
3283 // report - modes
3284 case E_HVD_GDATA_IS_SHOW_ERR_FRM:
3285 {
3286 u32Ret = pShm->ModeStatus.bIsShowErrFrm;
3287 break;
3288 }
3289 case E_HVD_GDATA_IS_REPEAT_LAST_FIELD:
3290 {
3291 u32Ret = pShm->ModeStatus.bIsRepeatLastField;
3292 break;
3293 }
3294 case E_HVD_GDATA_IS_ERR_CONCEAL:
3295 {
3296 u32Ret = pShm->ModeStatus.bIsErrConceal;
3297 break;
3298 }
3299 case E_HVD_GDATA_IS_SYNC_ON:
3300 {
3301 u32Ret = pShm->ModeStatus.bIsSyncOn;
3302 break;
3303 }
3304 case E_HVD_GDATA_IS_PLAYBACK_FINISH:
3305 {
3306 u32Ret = pShm->ModeStatus.bIsPlaybackFinish;
3307 break;
3308 }
3309 case E_HVD_GDATA_SYNC_MODE:
3310 {
3311 u32Ret = pShm->ModeStatus.u8SyncType;
3312 break;
3313 }
3314 case E_HVD_GDATA_SKIP_MODE:
3315 {
3316 u32Ret = pShm->ModeStatus.u8SkipMode;
3317 break;
3318 }
3319 case E_HVD_GDATA_DROP_MODE:
3320 {
3321 u32Ret = pShm->ModeStatus.u8DropMode;
3322 break;
3323 }
3324 case E_HVD_GDATA_DISPLAY_DURATION:
3325 {
3326 u32Ret = pShm->ModeStatus.s8DisplaySpeed;
3327 break;
3328 }
3329 case E_HVD_GDATA_FRC_MODE:
3330 {
3331 u32Ret = pShm->ModeStatus.u8FrcMode;
3332 break;
3333 }
3334 case E_HVD_GDATA_NEXT_PTS:
3335 {
3336 u32Ret = pShm->u32NextPTS;
3337 break;
3338 }
3339 case E_HVD_GDATA_DISP_Q_SIZE:
3340 {
3341 u32Ret = pShm->u16DispQSize;
3342 break;
3343 }
3344 case E_HVD_GDATA_DISP_Q_PTR:
3345 {
3346 u32Ret = (MS_U32) pHVDHalContext->_u16DispQPtr;
3347 break;
3348 }
3349 case E_HVD_GDATA_NEXT_DISP_FRM_INFO:
3350 {
3351 u32Ret = (MS_U32) _HVD_EX_GetNextDispFrame(u32Id);
3352 break;
3353 }
3354 case E_HVD_GDATA_REAL_FRAMERATE:
3355 {
3356 // return VPS/VUI timing info framerate, and 0 if timing info not exist
3357 u32Ret = pShm->u32RealFrameRate;
3358 break;
3359 }
3360 case E_HVD_GDATA_IS_ORI_INTERLACE_MODE:
3361 u32Ret=(MS_U32)pShm->DispInfo.u8IsOriginInterlace;
3362 break;
3363 case E_HVD_GDATA_FRM_PACKING_SEI_DATA:
3364 u32Ret=((MS_U32)(pShm->u32Frm_packing_arr_data_addr));
3365 break;
3366 case E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG:
3367 u32Ret=((MS_U32)(pShm->u8FrameMbsOnlyFlag));
3368 break;
3369
3370 // internal control
3371 case E_HVD_GDATA_IS_1ST_FRM_RDY:
3372 {
3373 u32Ret = pShm->bIs1stFrameRdy;
3374 break;
3375 }
3376 case E_HVD_GDATA_IS_I_FRM_FOUND:
3377 {
3378 u32Ret = pShm->bIsIFrmFound;
3379 break;
3380 }
3381 case E_HVD_GDATA_IS_SYNC_START:
3382 {
3383 u32Ret = pShm->bIsSyncStart;
3384 break;
3385 }
3386 case E_HVD_GDATA_IS_SYNC_REACH:
3387 {
3388 u32Ret = pShm->bIsSyncReach;
3389 break;
3390 }
3391 case E_HVD_GDATA_FW_VERSION_ID:
3392 {
3393 u32Ret = pShm->u32FWVersionID;
3394 break;
3395 }
3396 case E_HVD_GDATA_FW_IF_VERSION_ID:
3397 {
3398 u32Ret = pShm->u32FWIfVersionID;
3399 break;
3400 }
3401 case E_HVD_GDATA_BBU_Q_NUMB:
3402 {
3403 u32Ret = _HVD_EX_GetBBUQNumb(u32Id);
3404 break;
3405 }
3406 case E_HVD_GDATA_DEC_Q_NUMB:
3407 {
3408 u32Ret = pShm->u16DecQNumb;
3409 break;
3410 }
3411 case E_HVD_GDATA_DISP_Q_NUMB:
3412 {
3413 u32Ret = pShm->u16DispQNumb;
3414 break;
3415 }
3416 case E_HVD_GDATA_PTS_Q_NUMB:
3417 {
3418 u32Ret = _HVD_EX_GetPTSQNumb(u32Id);
3419 break;
3420 }
3421 case E_HVD_GDATA_FW_INIT_DONE:
3422 {
3423 u32Ret = pShm->bInitDone;
3424 break;
3425 }
3426 // debug
3427 case E_HVD_GDATA_SKIP_CNT:
3428 {
3429 u32Ret = pShm->u32SkipCnt;
3430 break;
3431 }
3432 case E_HVD_GDATA_GOP_CNT:
3433 {
3434 u32Ret = pShm->u32DropCnt;
3435 break;
3436 }
3437 case E_HVD_GDATA_DISP_CNT:
3438 {
3439 u32Ret = pShm->u32DispCnt;
3440 break;
3441 }
3442 case E_HVD_GDATA_DROP_CNT:
3443 {
3444 u32Ret = pShm->u32DropCnt;
3445 break;
3446 }
3447 case E_HVD_GDATA_DISP_STC:
3448 {
3449 u32Ret = pShm->u32DispSTC;
3450 break;
3451 }
3452 case E_HVD_GDATA_VSYNC_CNT:
3453 {
3454 u32Ret = pShm->u32VsyncCnt;
3455 break;
3456 }
3457 case E_HVD_GDATA_MAIN_LOOP_CNT:
3458 {
3459 u32Ret = pShm->u32MainLoopCnt;
3460 break;
3461 }
3462
3463 // AVC
3464 case E_HVD_GDATA_AVC_LEVEL_IDC:
3465 {
3466 u32Ret = pShm->u16AVC_SPS_LevelIDC;
3467 break;
3468 }
3469 case E_HVD_GDATA_AVC_LOW_DELAY:
3470 {
3471 u32Ret = pShm->u8AVC_SPS_LowDelayHrdFlag;
3472 break;
3473 }
3474 case E_HVD_GDATA_AVC_VUI_DISP_INFO:
3475 {
3476 u32Ret = _HVD_EX_GetVUIDispInfo(u32Id);
3477 break;
3478 }
3479 case E_HVD_GDATA_FW_FLUSH_STATUS:
3480 {
3481 u32Ret = (MS_U32) (pShm->u8FlushStatus);
3482 break;
3483 }
3484 case E_HVD_GDATA_FW_CODEC_TYPE:
3485 {
3486 u32Ret = pShm->u32CodecType;
3487 break;
3488 }
3489 case E_HVD_GDATA_FW_ES_BUF_STATUS:
3490 {
3491
3492 u32Ret = (MS_U32)pShm->u8ESBufStatus;
3493 break;
3494 }
3495
3496 // SRAM
3497
3498 // Mailbox
3499 case E_HVD_GDATA_FW_STATE: // HVD RISC MBOX 0 (esp. FW init done)
3500 {
3501 u32Ret = pShm->u32FwState;
3502 break;
3503 }
3504 case E_HVD_GDATA_IS_DISP_INFO_UNCOPYED:
3505 {
3506 u32Ret = pShm->bSpsChange;
3507 break;
3508 }
3509 case E_HVD_GDATA_IS_DISP_INFO_CHANGE: // HVD RISC MBOX 1 (rdy only)
3510 {
3511 u32Ret = pShm->bSpsChange;
3512 break;
3513 }
3514 case E_HVD_GDATA_HVD_ISR_STATUS: // HVD RISC MBOX 1 (value only)
3515 {
3516 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3517
3518 if ((pCtrl->HVDISRCtrl.u32IntCount != pShm->u32IntCount) && pShm->u32FwInfo) // fetch ISR status
3519 {
3520 u32Ret = pShm->u32FwInfo;
3521 pCtrl->HVDISRCtrl.u32IntCount = pShm->u32IntCount;
3522 }
3523 break;
3524 }
3525 case E_HVD_GDATA_IS_FRAME_SHOWED: // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable )
3526 {
3527 if (pShm->bIsTrigDisp) // not clear yet
3528 {
3529 u32Ret = FALSE;
3530 }
3531 else
3532 {
3533 u32Ret = TRUE;
3534 }
3535 break;
3536 }
3537 case E_HVD_GDATA_ES_READ_PTR:
3538 {
3539 u32Ret = _HVD_EX_GetESReadPtr(u32Id, FALSE);
3540 break;
3541 }
3542 case E_HVD_GDATA_ES_WRITE_PTR:
3543 {
3544 u32Ret = _HVD_EX_GetESWritePtr(u32Id);
3545 break;
3546 }
3547 case E_HVD_GDATA_BBU_READ_PTR:
3548 {
3549 u32Ret = _HVD_EX_GetBBUReadptr(u32Id);
3550 break;
3551 }
3552 case E_HVD_GDATA_BBU_WRITE_PTR:
3553 {
3554 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3555 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3556 {
3557 u32Ret = pHVDHalContext->u32VP8BBUWptr;
3558 }
3559 else
3560 {
3561 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
3562 }
3563 break;
3564 }
3565 case E_HVD_GDATA_BBU_WRITE_PTR_FIRED:
3566 {
3567 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3568
3569 u32Ret = pCtrl->u32BBUWptr_Fired;
3570
3571 break;
3572 }
3573 case E_HVD_GDATA_VPU_PC_CNT:
3574 {
3575 u32Ret = _HVD_EX_GetPC();
3576 break;
3577 }
3578 case E_HVD_GDATA_ES_QUANTITY:
3579 {
3580 u32Ret=_HVD_EX_GetESQuantity(u32Id);
3581 break;
3582 }
3583
3584
3585 // FW def
3586 case E_HVD_GDATA_FW_MAX_DUMMY_FIFO: // AVC: 256Bytes AVS: 2kB RM:???
3587 u32Ret = HVD_MAX3(HVD_FW_AVC_DUMMY_FIFO, HVD_FW_AVS_DUMMY_FIFO, HVD_FW_RM_DUMMY_FIFO);
3588 break;
3589
3590 case E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY:
3591 u32Ret = HVD_FW_AVC_MAX_VIDEO_DELAY;
3592 break;
3593 case E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY:
3594 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH;
3595 break;
3596 case E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB:
3597 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
3598 break;
3599 case E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB:
3600 u32Ret = MAX_PTS_TABLE_SIZE;
3601 break;
3602 case E_HVD_GDATA_FW_DUMMY_WRITE_ADDR:
3603 u32Ret = pShm->u32HVD_DUMMY_WRITE_ADDR;
3604 break;
3605 case E_HVD_GDATA_FW_DS_BUF_ADDR:
3606 u32Ret = pShm->u32HVD_DYNAMIC_SCALING_ADDR;
3607 break;
3608 case E_HVD_GDATA_FW_DS_BUF_SIZE:
3609 //u32Ret = HVD_DYNAMIC_SCALING_SIZE;
3610 // ----------------------- yi-chun.pan: for Dynamic Scaling 3k/6k issue ----------20111213---
3611 // ----------------------- modify DRV and AP(SN/MM) first, and then update fw --------------
3612 u32Ret = (1024 * 3);
3613 break;
3614 case E_HVD_GDATA_FW_DS_VECTOR_DEPTH:
3615 u32Ret = HVD_DYNAMIC_SCALING_DEPTH;
3616 break;
3617 case E_HVD_GDATA_FW_DS_INFO_ADDR:
3618 u32Ret = pShm->u32HVD_SCALER_INFO_ADDR;
3619 break;
3620 case E_HVD_GDATA_FW_DS_IS_ENABLED:
3621 {
3622 if (pShm->bDSIsRunning)
3623 {
3624 u32Ret = TRUE;
3625 }
3626 else
3627 {
3628 u32Ret = FALSE;
3629 }
3630 break;
3631 }
3632 case E_HVD_GDATA_TYPE_IS_LEAST_DISPQ_SIZE:
3633 u32Ret = ((MS_U32)(pShm->bIsLeastDispQSize));
3634 break;
3635 case E_HVD_GDATA_FIELD_PIC_FLAG:
3636 u32Ret = ((MS_U32)(pShm->u8FieldPicFlag));
3637 break;
3638 case E_HVD_GDATA_FW_VSYNC_BRIDGE_ADDR:
3639 u32Ret = pShm->u32VSYNC_BRIGE_SHM_ADDR;
3640 break;
3641 case E_HVD_GDATA_TS_SEAMLESS_STATUS:
3642 u32Ret = pShm->u32SeamlessTSStatus;
3643 break;
3644 case E_HVD_GDATA_HVD_HW_MAX_PIXEL:
3645 u32Ret = (MS_U32)(((MS_U64)HVD_HW_MAX_PIXEL)/1000);
3646 break;
3647 default:
3648 break;
3649 }
3650 return u32Ret;
3651 }
3652
HAL_HVD_EX_SetCmd(MS_U32 u32Id,HVD_User_Cmd eUsrCmd,MS_U32 u32CmdArg)3653 HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg)
3654 {
3655 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
3656 MS_U32 u32Cmd = (MS_U32) eUsrCmd;
3657 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3658
3659 _HAL_HVD_Entry();
3660
3661 // check if old SVD cmds
3662 if (u32Cmd < E_HVD_CMD_SVD_BASE)
3663 {
3664 HVD_EX_MSG_ERR("Old SVD FW cmd(%lx %lx) used in HVD.\n", u32Cmd, u32CmdArg);
3665
3666 _HAL_HVD_Return(E_HVD_RETURN_INVALID_PARAMETER);
3667 }
3668
3669 if(u32Cmd == E_HVD_CMD_ENABLE_DISP_OUTSIDE)
3670 {
3671 pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide = (MS_BOOL)u32CmdArg;
3672 }
3673
3674 #if HVD_ENABLE_MVC
3675 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
3676 {
3677 if (HAL_HVD_EX_CheckMVCID(u32Id) && u32Cmd == E_HVD_CMD_FLUSH)
3678 {
3679 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
3680 }
3681 }
3682 #endif
3683
3684 HVD_EX_MSG_DBG("cmd=0x%lx, arg=0x%lx\n", u32Cmd, u32CmdArg);
3685
3686 eRet = _HVD_EX_SendCmd(u32Id, u32Cmd, u32CmdArg);
3687
3688 _HAL_HVD_Return(eRet);
3689 }
3690
HAL_HVD_EX_DeInit(MS_U32 u32Id)3691 HVD_Return HAL_HVD_EX_DeInit(MS_U32 u32Id)
3692 {
3693 HVD_Return eRet = E_HVD_RETURN_FAIL;
3694 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3695 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3696 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
3697
3698 #if HVD_ENABLE_TIME_MEASURE
3699 MS_U32 ExitTimeCnt = 0;
3700 ExitTimeCnt = HVD_GetSysTime_ms();
3701 #endif
3702
3703 pCtrl->MemMap.u32CodeBufVAddr = MS_PA2KSEG1((MS_U32)pCtrl->MemMap.u32CodeBufAddr);
3704
3705 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_PAUSE, 0);
3706
3707 if (E_HVD_RETURN_SUCCESS != eRet)
3708 {
3709 HVD_EX_MSG_ERR("HVD fail to PAUSE %d\n", eRet);
3710 }
3711
3712 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_STOP, 0);
3713
3714 if (E_HVD_RETURN_SUCCESS != eRet)
3715 {
3716 HVD_EX_MSG_ERR("HVD fail to STOP %d\n", eRet);
3717 }
3718
3719 // check FW state to make sure it's STOP DONE
3720 while (E_HVD_FW_STOP_DONE != (HVD_FW_State) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_STATE))
3721 {
3722 if (HVD_GetSysTime_ms() > u32Timeout)
3723 {
3724 HVD_EX_MSG_ERR("FW stop timeout, pc = 0x%lx\n", HAL_VPU_EX_GetProgCnt());
3725
3726 //return E_HVD_RETURN_TIMEOUT;
3727 eRet = E_HVD_RETURN_TIMEOUT;
3728 break;
3729 }
3730 }
3731
3732 VPU_EX_FWCodeCfg fwCfg;
3733 VPU_EX_TaskInfo taskInfo;
3734 VPU_EX_NDecInitPara nDecInitPara;
3735
3736 nDecInitPara.pFWCodeCfg = &fwCfg;
3737 nDecInitPara.pTaskInfo = &taskInfo;
3738
3739 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
3740 fwCfg.u8SrcType = E_HVD_FW_INPUT_SOURCE_NONE;
3741
3742 taskInfo.u32Id = u32Id;
3743 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
3744 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
3745
3746 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
3747 {
3748 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
3749 }
3750 else
3751 {
3752 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
3753 }
3754
3755 if(HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara) != TRUE)
3756 {
3757 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
3758 }
3759
3760 /* clear es buffer */
3761 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
3762 {
3763 //printf("Clear ES buffer\n");
3764
3765 memset((void *) pCtrl->MemMap.u32BitstreamBufVAddr, 0, MIN(128, pCtrl->MemMap.u32BitstreamBufSize));
3766 }
3767
3768 //_HAL_HVD_MutexDelete();
3769
3770 #if HVD_ENABLE_TIME_MEASURE
3771 HVD_EX_MSG_DBG("HVD Stop Time(Wait FW):%d\n", HVD_GetSysTime_ms() - ExitTimeCnt);
3772 #endif
3773
3774 pHVDHalContext->_stHVDStream[u8Idx].bUsed = FALSE;
3775
3776 // reset bbu wptr
3777 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
3778 {
3779 if(TRUE == HAL_VPU_EX_HVDInUsed())
3780 {
3781 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))//apple
3782 {
3783 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
3784 pHVDHalContext->u32VP8BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
3785 }
3786 else
3787 {
3788 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
3789 {
3790 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
3791 }
3792 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
3793 }
3794 }
3795 else
3796 {
3797 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
3798 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
3799 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
3800 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3801 {
3802 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
3803 {
3804 _HVD_EX_ResetMainSubBBUWptr(u32Id);
3805 }
3806 }
3807 else
3808 {
3809 _HVD_EX_ResetMainSubBBUWptr(u32Id);
3810 }
3811 }
3812 }
3813
3814 _stHVDPreSet[u8Idx].bColocateBBUMode = FALSE;
3815
3816 if(pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable)
3817 {
3818 if(pCtrl->MemMap.u32FrameBufAddr >= HAL_MIU1_BASE)
3819 {
3820 _HAL_HVD_Entry();
3821 HAL_HVD_MVDMiuClientSel(1);
3822 _HAL_HVD_Release();
3823 }
3824 else
3825 {
3826 _HAL_HVD_Entry();
3827 HAL_HVD_MVDMiuClientSel(0);
3828 _HAL_HVD_Release();
3829 }
3830 }
3831
3832 HVD_EX_MSG_DBG("success\n");
3833
3834 return eRet;
3835 }
3836
HAL_HVD_EX_PushPacket(MS_U32 u32Id,HVD_BBU_Info * pInfo)3837 HVD_Return HAL_HVD_EX_PushPacket(MS_U32 u32Id, HVD_BBU_Info *pInfo)
3838 {
3839 HVD_Return eRet = E_HVD_RETURN_UNSUPPORTED;
3840 MS_U32 u32Addr = 0;
3841 HVD_EX_Drv_Ctrl *pCtrl = NULL;
3842 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3843
3844 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3845
3846 //if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8 PTS table is not ready yet
3847 {
3848 eRet = _HVD_EX_UpdatePTSTable(u32Id, pInfo);
3849
3850 if (E_HVD_RETURN_SUCCESS != eRet)
3851 {
3852 return eRet;
3853 }
3854 }
3855
3856 //printf(">>> halHVD pts,idH = %lu, %lu\n", pInfo->u32TimeStamp, pInfo->u32ID_H); //STS input
3857
3858 //T9: for 128 bit memory. BBU need to get 2 entry at a time.
3859 if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3860 {
3861 eRet = _HVD_EX_UpdateESWptr(u32Id, 0, 0);
3862
3863 if (E_HVD_RETURN_SUCCESS != eRet)
3864 {
3865 return eRet;
3866 }
3867 }
3868
3869 u32Addr = pInfo->u32Staddr;
3870
3871 if (pInfo->bRVBrokenPacket)
3872 {
3873 u32Addr = pInfo->u32Staddr | BIT(HVD_RV_BROKENBYUS_BIT);
3874 }
3875
3876 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
3877 {
3878 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, pInfo->u32Length, pInfo->u32Staddr2, pInfo->u32Length2);
3879 }
3880 else
3881 {
3882 eRet = _HVD_EX_UpdateESWptr(u32Id, u32Addr, pInfo->u32Length);
3883 }
3884
3885 if (E_HVD_RETURN_SUCCESS != eRet)
3886 {
3887 return eRet;
3888 }
3889
3890 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3891 {
3892 //eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, 0, 0, 0, 0);
3893 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, 0, pInfo->u32Staddr2, 0);
3894
3895 if (E_HVD_RETURN_SUCCESS != eRet)
3896 {
3897 return eRet;
3898 }
3899 }
3900
3901 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt += pInfo->u32Length;
3902
3903 // do not add local pointer
3904 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
3905 {
3906 MS_U32 u32PacketStAddr = pInfo->u32Staddr + pCtrl->MemMap.u32BitstreamBufAddr;
3907
3908 if (!((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStAddr) &&
3909 (u32PacketStAddr <
3910 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
3911 {
3912 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
3913 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
3914 }
3915 else
3916 {
3917 //null packet
3918 pCtrl->LastNal.u32NalAddr = pInfo->u32OriPktAddr;
3919 pCtrl->LastNal.u32NalSize = 0;
3920 }
3921 }
3922 else
3923 {
3924 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
3925 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
3926 }
3927
3928 pCtrl->LastNal.bRVBrokenPacket = pInfo->bRVBrokenPacket;
3929 pCtrl->u32BBUPacketCnt++;
3930
3931 return eRet;
3932 }
3933
HAL_HVD_EX_EnableISR(MS_U32 u32Id,MS_BOOL bEnable)3934 void HAL_HVD_EX_EnableISR(MS_U32 u32Id, MS_BOOL bEnable)
3935 {
3936 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3937 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
3938
3939 if (bEnable)
3940 {
3941 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK);
3942 }
3943 else
3944 {
3945 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK);
3946 }
3947 }
3948
HAL_HVD_EX_SetForceISR(MS_U32 u32Id,MS_BOOL bEnable)3949 void HAL_HVD_EX_SetForceISR(MS_U32 u32Id, MS_BOOL bEnable)
3950 {
3951 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3952 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
3953
3954 if (bEnable)
3955 {
3956 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_FORCE, HVD_REG_RISC_ISR_FORCE);
3957 }
3958 else
3959 {
3960 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_FORCE);
3961 }
3962 }
3963
HAL_HVD_EX_SetClearISR(MS_U32 u32Id)3964 void HAL_HVD_EX_SetClearISR(MS_U32 u32Id)
3965 {
3966 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3967 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
3968
3969 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_CLR, HVD_REG_RISC_ISR_CLR);
3970 }
3971
HAL_HVD_EX_IsISROccured(MS_U32 u32Id)3972 MS_BOOL HAL_HVD_EX_IsISROccured(MS_U32 u32Id)
3973 {
3974 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3975 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
3976
3977 return (MS_BOOL) (_HVD_Read2Byte(HVD_REG_RISC_MBOX_RDY(u32RB)) & HVD_REG_RISC_ISR_VALID);
3978 }
3979
HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)3980 MS_BOOL HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)
3981 {
3982 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3983 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
3984
3985 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK)
3986 {
3987 return FALSE;
3988 }
3989 else
3990 {
3991 return TRUE;
3992 }
3993 }
3994
HAL_HVD_EX_IsAlive(MS_U32 u32Id)3995 MS_BOOL HAL_HVD_EX_IsAlive(MS_U32 u32Id)
3996 {
3997 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3998
3999 if (pCtrl)
4000 {
4001 if ((pCtrl->LivingStatus.u32DecCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DECODE_CNT)) &&
4002 (pCtrl->LivingStatus.u32SkipCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_SKIP_CNT)) &&
4003 (pCtrl->LivingStatus.u32IdleCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_VPU_IDLE_CNT)) &&
4004 (pCtrl->LivingStatus.u32MainLoopCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_MAIN_LOOP_CNT)))
4005 {
4006 return FALSE;
4007 }
4008 else
4009 {
4010 return TRUE;
4011 }
4012 }
4013 else
4014 {
4015 return FALSE;
4016 }
4017 }
4018
HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)4019 MS_BOOL HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)
4020 {
4021 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4022 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4023 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4024
4025 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
4026 {
4027 HAL_HVD_EX_ReadMemory();
4028
4029 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = pShm->u32PTStableByteCnt;
4030 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = _HVD_EX_GetPTSTableWptr(u32Id);
4031
4032 HVD_EX_MSG_DBG("PTS table: WptrAddr:%lx RptrAddr:%lx ByteCnt:%lx PreWptr:%lx\n",
4033 pShm->u32PTStableWptrAddr, pShm->u32PTStableRptrAddr, pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt, pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
4034 }
4035
4036 return TRUE;
4037 }
4038
HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)4039 MS_BOOL HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)
4040 {
4041 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4042 HVD_EX_Drv_Ctrl *pCtrl = NULL;
4043 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4044 MS_U32 u32Data;
4045 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4046
4047 memset(&pShm->DecoFrmInfo, 0, sizeof(HVD_Frm_Information));
4048
4049 HAL_HVD_EX_FlushMemory();
4050 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
4051 {
4052 u32Data = _HVD_EX_GetESReadPtr(u32Id, FALSE);
4053 pCtrl->LastNal.u32NalAddr = u32Data;
4054 pCtrl->LastNal.u32NalSize = 0;
4055 }
4056 return TRUE;
4057 }
4058
HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)4059 void HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)
4060 {
4061 if (bEnable)
4062 {
4063 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_VD_MHEG5, REG_TOP_UART_SEL_0_MASK);
4064 }
4065 else
4066 {
4067 #if defined (__aeon__)
4068 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
4069 #else // defined (__mips__)
4070 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_PIU_0, REG_TOP_UART_SEL_0_MASK);
4071 #endif
4072 }
4073 }
4074
HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)4075 MS_U32 HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)
4076 {
4077 return 0;
4078 }
4079
HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr,MS_U32 u32Data)4080 void HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr, MS_U32 u32Data)
4081 {
4082 return;
4083 }
4084
HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)4085 MS_U16 HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)
4086 {
4087 //if( u16Clock == 0 )
4088 return pHVDHalContext->u32HVDClockType; //140;
4089 //if( )
4090 }
4091
HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)4092 void HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)
4093 {
4094 MS_BOOL bBitMIU1 = FALSE;
4095 MS_BOOL bCodeMIU1 = FALSE;
4096 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4097 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4098 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4099 MS_U32 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR;
4100
4101 #if HVD_ENABLE_MVC
4102 if(HAL_HVD_EX_CheckMVCID(u32Id))
4103 {
4104 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
4105 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
4106 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
4107 {
4108 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
4109 }
4110 }
4111 #endif /// HVD_ENABLE_MVC
4112
4113
4114 if (pCtrl->MemMap.u32CodeBufAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
4115 {
4116 bCodeMIU1 = TRUE;
4117 }
4118
4119 if (pCtrl->MemMap.u32BitstreamBufAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
4120 {
4121 bBitMIU1 = TRUE;
4122 }
4123
4124 if (bBitMIU1 != bCodeMIU1)
4125 {
4126 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
4127 BDMA_Result bdmaRlt;
4128 MS_U32 u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
4129
4130 u32DstAdd = pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
4131 u32SrcAdd = pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR;
4132 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
4133
4134 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
4135
4136 if (E_BDMA_OK != bdmaRlt)
4137 {
4138 HVD_EX_MSG_ERR("MDrv_BDMA_MemCopy fail ret=%x!\n", bdmaRlt);
4139 }
4140 #else
4141 MS_U32 u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
4142
4143 u32DstAdd = pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
4144 u32SrcAdd = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR);
4145 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
4146
4147 HVD_memcpy(u32DstAdd, u32SrcAdd, u32tabsize);
4148 #endif
4149 }
4150
4151 //HVD_EX_MSG_DBG("%lu st:%lx size:%lx BBU: %lu\n", pCtrl->u32BBUPacketCnt, pCtrl->LastNal.u32NalAddr, pCtrl->LastNal.u32NalSize, _stHVDStream[u8Idx].u32BBUWptr);
4152
4153 HAL_HVD_EX_FlushMemory();
4154
4155 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4156 {
4157 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->u32VP8BBUWptr));
4158 pCtrl->u32BBUWptr_Fired = pHVDHalContext->u32VP8BBUWptr;
4159 }
4160 else
4161 {
4162 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr));
4163
4164 pCtrl->u32BBUWptr_Fired = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
4165 }
4166 }
4167
HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)4168 void HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)
4169 {
4170 if (bEnable)
4171 {
4172 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
4173 _HVD_WriteWordMask(REG_TOP_MVD2, 0, TOP_CKG_MHVD2_DIS);
4174 }
4175 else
4176 {
4177 _HVD_WriteWordMask(REG_TOP_MVD, TOP_CKG_MHVD_DIS, TOP_CKG_MHVD_DIS);
4178 _HVD_WriteWordMask(REG_TOP_MVD2, TOP_CKG_MHVD2_DIS, TOP_CKG_MHVD2_DIS);
4179 }
4180 }
4181
HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)4182 void HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)
4183 {
4184 MS_U32 tmp1 = 0;
4185 MS_U32 tmp2 = 0;
4186 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4187
4188 HAL_HVD_EX_ReadMemory();
4189
4190 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_MBOX, &tmp1);
4191 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_ARG_MBOX, &tmp2);
4192
4193 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
4194 {
4195 MS_U32 u32Tmp = u32UartCtrl;
4196
4197 HVD_EX_MSG_DBG("\n");
4198 u32UartCtrl = 0; // turn off debug message to prevent other function prints
4199 printf("\tSystime=%lu, FWVersionID=0x%lx, FwState=0x%lx, ErrCode=0x%lx, ProgCnt=0x%lx\n",
4200 HVD_GetSysTime_ms(), pShm->u32FWVersionID, pShm->u32FwState, (MS_U32) pShm->u16ErrCode, HAL_VPU_EX_GetProgCnt());
4201
4202 printf("\tTime: DispSTC=%lu, DispT=%lu, DecT=%lu, CurrentPts=%lu, Last Cmd=0x%lx, Arg=0x%lx, Rdy1=0x%lx, Rdy2=0x%lx\n",
4203 pShm->u32DispSTC, pShm->DispFrmInfo.u32TimeStamp,
4204 pShm->DecoFrmInfo.u32TimeStamp, pShm->u32CurrentPts, tmp1, tmp2,
4205 (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX), (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX));
4206
4207 printf("\tFlag: InitDone=%d, SpsChange=%d, IsIFrmFound=%d, 1stFrmRdy=%d, SyncStart=%d, SyncReach=%d\n",
4208 pShm->bInitDone, pShm->bSpsChange, pShm->bIsIFrmFound,
4209 pShm->bIs1stFrameRdy, pShm->bIsSyncStart, pShm->bIsSyncReach);
4210
4211 printf("\tQueue: BBUQNumb=%lu, DecQNumb=%d, DispQNumb=%d, ESR=%lu, ESRfromFW=%lu, ESW=%lu, ESLevel=%lu\n",
4212 _HVD_EX_GetBBUQNumb(u32Id), pShm->u16DecQNumb, pShm->u16DispQNumb,
4213 _HVD_EX_GetESReadPtr(u32Id, TRUE), pShm->u32ESReadPtr, _HVD_EX_GetESWritePtr(u32Id),
4214 _HVD_EX_GetESLevel(u32Id));
4215
4216 printf("\tCounter: DecodeCnt=%lu, DispCnt=%lu, DataErrCnt=%lu, DecErrCnt=%lu, SkipCnt=%lu, DropCnt=%lu, idle=%lu, MainLoopCnt=%lu, VsyncCnt=%lu\n",
4217 pShm->u32DecodeCnt, pShm->u32DispCnt, pShm->u32DataErrCnt,
4218 pShm->u32DecErrCnt, pShm->u32SkipCnt, pShm->u32DropCnt,
4219 pShm->u32VPUIdleCnt, pShm->u32MainLoopCnt, pShm->u32VsyncCnt);
4220 printf
4221 ("\tMode: ShowErr=%d, RepLastField=%d, SyncOn=%d, FileEnd=%d, Skip=%d, Drop=%d, DispSpeed=%d, FRC=%d, BlueScreen=%d, FreezeImg=%d, 1Field=%d\n",
4222 pShm->ModeStatus.bIsShowErrFrm, pShm->ModeStatus.bIsRepeatLastField,
4223 pShm->ModeStatus.bIsSyncOn, pShm->ModeStatus.bIsPlaybackFinish,
4224 pShm->ModeStatus.u8SkipMode, pShm->ModeStatus.u8DropMode,
4225 pShm->ModeStatus.s8DisplaySpeed, pShm->ModeStatus.u8FrcMode,
4226 pShm->ModeStatus.bIsBlueScreen, pShm->ModeStatus.bIsFreezeImg,
4227 pShm->ModeStatus.bShowOneField);
4228
4229 u32UartCtrl = u32Tmp; // recover debug level
4230 }
4231 }
4232
HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32Idx,MS_U32 * u32NalOffset,MS_U32 * u32NalSize)4233 void HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32Idx, MS_U32 *u32NalOffset, MS_U32 *u32NalSize)
4234 {
4235 MS_U8 *u32Addr = NULL;
4236 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4237 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4238
4239 if (u32Idx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
4240 {
4241 return;
4242 }
4243
4244 u32Addr = (MS_U8 *)(MsOS_PA2KSEG1(pDrvCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU_DRAM_ST_ADDR + (u32Idx << 3)));
4245
4246 *u32NalSize = *(u32Addr + 2) & 0x1f;
4247 *u32NalSize <<= 8;
4248 *u32NalSize |= *(u32Addr + 1) & 0xff;
4249 *u32NalSize <<= 8;
4250 *u32NalSize |= *(u32Addr) & 0xff;
4251
4252 *u32NalOffset = ((MS_U32) (*(u32Addr + 2) & 0xe0)) >> 5;
4253 *u32NalOffset |= ((MS_U32) (*(u32Addr + 3) & 0xff)) << 3;
4254 *u32NalOffset |= ((MS_U32) (*(u32Addr + 4) & 0xff)) << 11;
4255 *u32NalOffset |= ((MS_U32) (*(u32Addr + 5) & 0xff)) << 19;
4256 }
4257
HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32StartIdx,MS_U32 u32EndIdx,MS_BOOL bShowEmptyEntry)4258 void HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32StartIdx, MS_U32 u32EndIdx, MS_BOOL bShowEmptyEntry)
4259 {
4260 MS_U32 u32CurIdx = 0;
4261 MS_BOOL bFinished = FALSE;
4262 MS_U32 u32NalOffset = 0;
4263 MS_U32 u32NalSize = 0;
4264 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4265
4266 if ((u32StartIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum) || (u32EndIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum))
4267 {
4268 return;
4269 }
4270
4271 u32CurIdx = u32StartIdx;
4272
4273 do
4274 {
4275 if (u32CurIdx == u32EndIdx)
4276 {
4277 bFinished = TRUE;
4278 }
4279
4280 HAL_HVD_EX_GetBBUEntry(u32Id, pDrvCtrl, u32CurIdx, &u32NalOffset, &u32NalSize);
4281
4282 if ((bShowEmptyEntry == FALSE) || (bShowEmptyEntry && (u32NalOffset == 0) && (u32NalSize == 0)))
4283 {
4284 HVD_EX_MSG_DBG("HVD BBU Entry: Idx:%lu Offset:%lx Size:%lx\n", u32CurIdx, u32NalOffset, u32NalSize);
4285 }
4286
4287 u32CurIdx++;
4288
4289 if (u32CurIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
4290 {
4291 u32CurIdx %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
4292 }
4293 } while (bFinished == TRUE);
4294 }
4295
HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)4296 void HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)
4297 {
4298 MS_U32 i = 0;
4299 MS_U32 value = 0;
4300
4301 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
4302 {
4303 HVD_EX_MSG_DBG("\n");
4304
4305 for (i = 0; i <= u32Num; i++)
4306 {
4307 _HVD_Write2Byte(HVD_REG_DEBUG_SEL, i);
4308 value = _HVD_Read2Byte(HVD_REG_DEBUG_DAT_L);
4309 value |= ((MS_U32) _HVD_Read2Byte(HVD_REG_DEBUG_DAT_H)) << 16;
4310
4311 if (value == 0)
4312 {
4313 break;
4314 }
4315
4316 printf(" %08lx", value);
4317
4318 if (((i % 8) + 1) == 8)
4319 {
4320 printf(" |%lu\n", i + 1);
4321 }
4322 }
4323
4324 printf("\nHVD Dump HW status End: total number:%lu\n", i);
4325 }
4326 }
4327
HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl * pDrvCtrl,HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)4328 void HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl *pDrvCtrl, HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)
4329 {
4330 if (pDrvCtrl)
4331 {
4332 pDrvCtrl->Settings.u32MiuBurstLevel = (MS_U32) eMiuBurstCntCtrl;
4333 }
4334 }
4335
4336 #if HVD_ENABLE_MVC
HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)4337 MS_BOOL HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)
4338 {
4339 return ( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id) );
4340 }
4341
HAL_HVD_EX_GetView(MS_U32 u32Id)4342 VDEC_EX_View HAL_HVD_EX_GetView(MS_U32 u32Id)
4343 {
4344 if( (0xFF & (u32Id >> 8)) == 0x10)
4345 return E_VDEC_EX_MAIN_VIEW;
4346 else
4347 return E_VDEC_EX_SUB_VIEW;
4348 }
4349 #endif ///HVD_ENABLE_MVC
4350
HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id)4351 void HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id) //// For MVC
4352 {
4353 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_QUART_PIXEL, TRUE);
4354 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_DBF, TRUE);
4355 return;
4356 }
4357
4358
HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id,MS_U16 u16HSize,MS_U16 u16VSize,MS_U32 u32FrmRate)4359 MS_BOOL HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id, MS_U16 u16HSize, MS_U16 u16VSize, MS_U32 u32FrmRate)
4360 {
4361 HVD_EX_MSG_DBG("%s w:%d, h:%d, fr:%ld, MAX:%lld\n", __FUNCTION__,
4362 u16HSize, u16VSize, u32FrmRate, HVD_HW_MAX_PIXEL);
4363 return (((MS_U64)u16HSize*(MS_U64)u16VSize*(MS_U64)u32FrmRate) <= HVD_HW_MAX_PIXEL);
4364 }
4365
HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)4366 MS_U32 HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)
4367 {
4368 #if 1
4369 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4370 MS_U16 u16QNum = pShm->u16DispQNumb;
4371 MS_U16 u16QPtr = pShm->u16DispQPtr;
4372 // MS_U16 u16QSize = pShm->u16DispQSize;
4373 //static volatile HVD_Frm_Information *pHvdFrm = NULL;
4374 MS_U32 u32DispQNum = 0;
4375 #if HVD_ENABLE_MVC
4376 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4377
4378 if(bMVC)
4379 {
4380 #if 0
4381 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT*3)
4382 {
4383 u16QNum = HVD_DISPQ_PREFETCH_COUNT*3;
4384 }
4385 #endif
4386
4387 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
4388 //search the next frame to display
4389 while (u16QNum > 0)
4390 {
4391 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
4392 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
4393 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
4394
4395 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
4396 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
4397 {
4398 /// For MVC. Output views after the pair of (base and depend) views were decoded.
4399 /// Check the depned view was initial when Output the base view.
4400 if((u16QPtr%2) == 0)
4401 {
4402 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
4403 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
4404 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
4405 {
4406 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
4407 ///printf("Return NULL.\n");
4408 break;
4409 }
4410 }
4411 u32DispQNum++;
4412 }
4413
4414 u16QNum--;
4415 //go to next frame in the dispQ
4416 u16QPtr++;
4417
4418 if (u16QPtr >= pShm->u16DispQSize)
4419 {
4420 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
4421 }
4422 }
4423 }
4424 else
4425 #endif ///HVD_ENABLE_MVC
4426 {
4427 #if 0
4428 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT)
4429 {
4430 u16QNum = HVD_DISPQ_PREFETCH_COUNT;
4431 }
4432 #endif
4433 // printf("Q: %d %d %d\n", u16QNum, u16QPtr, u16QSize);
4434 //search the next frame to display
4435 while (u16QNum != 0)
4436 {
4437 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
4438
4439 // printf("Q2[%d]: %ld\n", u16QPtr, pShm->DispQueue[u16QPtr].u32Status);
4440 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
4441 {
4442 u32DispQNum++;
4443 }
4444
4445 u16QNum--;
4446 //go to next frame in the dispQ
4447 u16QPtr++;
4448
4449 if (u16QPtr == pShm->u16DispQSize)
4450 {
4451 u16QPtr = 0; //wrap to the begin
4452 }
4453 }
4454 }
4455
4456 //printf("dispQnum = %ld, pShm->u16DispQNumb = %d\n", u32DispQNum, pShm->u16DispQNumb);
4457 return u32DispQNum;
4458 #else
4459 HVD_ShareMem *pShm = (HVD_ShareMem *) _HVD_EX_GetShmAddr(u32Id);
4460 return pShm->u16DispQNumb;
4461 #endif
4462 }
4463
HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id,MS_U32 u32ModeFlag)4464 void HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id, MS_U32 u32ModeFlag)
4465 {
4466 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4467 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase =
4468 ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC) ? REG_EVD_BASE : REG_HVD_BASE;
4469 }
4470
4471 #if SUPPORT_EVD
HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable)4472 void HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable)
4473 {
4474 if (bEnable)
4475 {
4476 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, ~TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
4477 _HVD_WriteWordMask(REG_TOP_CKG_EVD, ~TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
4478 }
4479 else
4480 {
4481 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
4482 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
4483 }
4484
4485 switch (pHVDHalContext->u32EVDClockType)
4486 {
4487 case 384:
4488 {
4489 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_480MHZ, TOP_CKG_EVD_PPU_MASK);
4490 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_384MHZ, TOP_CKG_EVD_MASK);
4491 break;
4492 }
4493 case 320:
4494 {
4495 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_384MHZ, TOP_CKG_EVD_PPU_MASK);
4496 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_320MHZ, TOP_CKG_EVD_MASK);
4497 break;
4498 }
4499 case 288:
4500 {
4501 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_288MHZ, TOP_CKG_EVD_PPU_MASK);
4502 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_288MHZ, TOP_CKG_EVD_MASK);
4503 break;
4504 }
4505 case 240:
4506 {
4507 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_240MHZ, TOP_CKG_EVD_PPU_MASK);
4508 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_240MHZ, TOP_CKG_EVD_MASK);
4509 break;
4510 }
4511 case 218:
4512 {
4513 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_218MHZ, TOP_CKG_EVD_PPU_MASK);
4514 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_218MHZ, TOP_CKG_EVD_MASK);
4515 break;
4516 }
4517 case 192:
4518 {
4519 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_192MHZ, TOP_CKG_EVD_PPU_MASK);
4520 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_192MHZ, TOP_CKG_EVD_MASK);
4521 break;
4522 }
4523 case 160:
4524 {
4525 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_160MHZ, TOP_CKG_EVD_PPU_MASK);
4526 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_160MHZ, TOP_CKG_EVD_MASK);
4527 break;
4528 }
4529 default:
4530 {
4531 _HVD_WriteByteMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_480MHZ, TOP_CKG_EVD_PPU_MASK);
4532 _HVD_WriteByteMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_384MHZ, TOP_CKG_EVD_MASK);
4533 break;
4534 }
4535 }
4536
4537 return;
4538 }
4539
HAL_EVD_EX_DeinitHW(void)4540 static MS_BOOL HAL_EVD_EX_DeinitHW(void)
4541 {
4542 MS_U16 u16Timeout = 1000;
4543
4544 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
4545
4546 while (u16Timeout)
4547 {
4548 if ((_HVD_Read2Byte(EVD_REG_RESET) & (EVD_REG_RESET_SWRST_FIN)) == (EVD_REG_RESET_SWRST_FIN))
4549 {
4550 break;
4551 }
4552 u16Timeout--;
4553 }
4554
4555 HAL_EVD_EX_PowerCtrl(FALSE);
4556
4557 return TRUE;
4558 }
4559 #endif
HAL_HVD_EX_GetSupport2ndMVOPInterface(void)4560 MS_BOOL HAL_HVD_EX_GetSupport2ndMVOPInterface(void)
4561 {
4562 return TRUE;
4563 }
HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id)4564 void HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id)
4565 {
4566 _HVD_EX_SetBufferAddr(u32Id);
4567 }
4568
4569
HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)4570 MS_BOOL HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)
4571 {
4572 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4573
4574 if(pCtrl->InitParams.u16ChipECONum == 0)
4575 return FALSE;
4576 else
4577 return TRUE;
4578
4579 }
4580
HAL_HVD_EX_BBU_Proc(MS_U32 u32Id)4581 void HAL_HVD_EX_BBU_Proc(MS_U32 u32Id)
4582 {
4583
4584 }
4585
4586
HAL_HVD_EX_BBU_StopProc(MS_U32 u32Id)4587 void HAL_HVD_EX_BBU_StopProc(MS_U32 u32Id)
4588 {
4589
4590 }
4591
4592 #endif
4593
4594
4595