1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #include <string.h>
101 #include "drvHVD_Common.h"
102
103 // Internal Definition
104 #include "drvHVD_def.h"
105 #include "fwHVD_if.h"
106 #include "halVPU_EX.h"
107 #include "halHVD_EX.h"
108 #include "regHVD_EX.h"
109
110 //-------------------------------------------------------------------------------------------------
111 // Driver Compiler Options
112 //-------------------------------------------------------------------------------------------------
113 #if !defined(MSOS_TYPE_NUTTX) || defined(SUPPORT_X_MODEL_FEATURE)
114
115 //-------------------------------------------------------------------------------------------------
116 // Local Defines
117 //-------------------------------------------------------------------------------------------------
118 #define RV_VLC_TABLE_SIZE 0x20000
119 /* Add for Mobile Platform by Ted Sun */
120 //#define HVD_DISPQ_PREFETCH_COUNT 2
121 #define HVD_FW_MEM_OFFSET 0x100000UL // 1M
122 #define VPU_QMEM_BASE 0x20000000UL
123 #define HVD_HW_MAX_PIXEL (3840*2160*31000ULL) // 4kx2k@30p
124
125 #if 0
126 static HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
127 static MS_U8 g_hvd_nal_fill_pair[2][8] = { {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0, 0, 0} };
128 static MS_U32 u32RV_VLCTableAddr = 0; // offset from Frame buffer start address
129 static MS_U16 _u16DispQPtr = 0;
130 #endif
131
132 //---------------------------------- Mutex settings -----------------------------------------
133 #if HAL_HVD_ENABLE_MUTEX_PROTECT
134 #define _HAL_HVD_MutexCreate() \
135 do \
136 { \
137 if (s32HVDMutexID < 0) \
138 { \
139 s32HVDMutexID = OSAL_HVD_MutexCreate((MS_U8*)(_u8HVD_Mutex)); \
140 } \
141 } while (0)
142
143 #define _HAL_HVD_MutexDelete() \
144 do \
145 { \
146 if (s32HVDMutexID >= 0) \
147 { \
148 OSAL_HVD_MutexDelete(s32HVDMutexID); \
149 s32HVDMutexID = -1; \
150 } \
151 } while (0)
152
153 #define _HAL_HVD_Entry() \
154 do \
155 { \
156 if (s32HVDMutexID >= 0) \
157 { \
158 if (!OSAL_HVD_MutexObtain(s32HVDMutexID, OSAL_HVD_MUTEX_TIMEOUT)) \
159 { \
160 printf("[HAL HVD][%06d] Mutex taking timeout\n", __LINE__); \
161 } \
162 } \
163 } while (0)
164
165 #define _HAL_HVD_Return(_ret_) \
166 do \
167 { \
168 if (s32HVDMutexID >= 0) \
169 { \
170 OSAL_HVD_MutexRelease(s32HVDMutexID); \
171 } \
172 return _ret_; \
173 } while(0)
174
175 #define _HAL_HVD_Release() \
176 do \
177 { \
178 if (s32HVDMutexID >= 0) \
179 { \
180 OSAL_HVD_MutexRelease(s32HVDMutexID); \
181 } \
182 } while (0)
183
184
185 #else // HAL_HVD_ENABLE_MUTEX_PROTECT
186
187 #define _HAL_HVD_MutexCreate()
188 #define _HAL_HVD_MutexDelete()
189 #define _HAL_HVD_Entry()
190 #define _HAL_HVD_Return(_ret) {return _ret;}
191 #define _HAL_HVD_Release()
192
193 #endif // HAL_HVD_ENABLE_MUTEX_PROTECT
194
195 //------------------------------ MIU SETTINGS ----------------------------------
196 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
197 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
198 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(2))
199 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(1))
200
201 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
202 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
203 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(2))
204 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(1))
205
206 #define HVD_MVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(4)) == BIT(4))
207 #define HVD_MVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12))
208 #define HVD_HVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(2)) == BIT(2))
209 #define HVD_HVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(1)) == BIT(1))
210
211 #if SUPPORT_EVD
212 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK+1, m, BIT(5))
213 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK+1, m, BIT(4))
214 #define _MaskMiu1Req_EVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK+1, m, BIT(5))
215 #define _MaskMiu1Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK+1, m, BIT(4))
216 #define HVD_EVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(13)) == BIT(13))
217 #define HVD_EVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(12)) == BIT(12))
218 #endif
219
220 #define _HVD_MIU_SetReqMask(miu_clients, mask) \
221 do \
222 { \
223 if (HVD_##miu_clients##_ON_MIU1 == 0) \
224 { \
225 _MaskMiuReq_##miu_clients(mask); \
226 } \
227 else \
228 { \
229 _MaskMiu1Req_##miu_clients(mask); \
230 } \
231 } while (0)
232
233 // check RM is supported or not
234 #define HVD_HW_RUBBER3 (HAL_HVD_EX_GetHWVersionID()& BIT(14))
235 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 3
236 //-------------------------------------------------------------------------------------------------
237 // Local Structures
238 //-------------------------------------------------------------------------------------------------
239
240 //-------------------------------------------------------------------------------------------------
241 // Local Functions Prototype
242 //-------------------------------------------------------------------------------------------------
243 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id);
244 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr);
245 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg);
246 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox);
247 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg);
248 //static void _HVD_EX_MBoxClear(MS_U8 u8MBox);
249 static MS_U32 _HVD_EX_GetPC(void);
250 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id);
251 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug);
252 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg);
253 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd);
254 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg);
255 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable);
256 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id);
257 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id);
258 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id);
259 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo);
260 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen);
261 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2);
262 static MS_U32 _HVD_EX_GetVUIDispInfo(MS_U32 u32Id);
263 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id);
264 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id);
265 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id);
266 static MS_U8 _HVD_EX_GetStreamIdx(MS_U32 u32Id);
267 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id);
268 #if SUPPORT_EVD
269 static void HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable);
270 static MS_BOOL HAL_EVD_EX_DeinitHW(void);
271 #endif
272 //-------------------------------------------------------------------------------------------------
273 // Global Variables
274 //-------------------------------------------------------------------------------------------------
275 #if defined (__aeon__)
276 static MS_U32 u32HVDRegOSBase = 0xA0200000;
277 #else
278 static MS_U32 u32HVDRegOSBase = 0xBF200000;
279 #endif
280 #if HAL_HVD_ENABLE_MUTEX_PROTECT
281 MS_S32 s32HVDMutexID = -1;
282 MS_U8 _u8HVD_Mutex[] = { "HVD_Mutex" };
283 #endif
284
285
286 //-------------------------------------------------------------------------------------------------
287 // Local Variables
288 //-------------------------------------------------------------------------------------------------
289 typedef struct
290 {
291
292 HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
293 MS_U8 g_hvd_nal_fill_pair[2][8];
294 MS_U32 u32RV_VLCTableAddr; // offset from Frame buffer start address
295 MS_U16 _u16DispQPtr;
296
297 //HVD_EX_Drv_Ctrl *_pHVDCtrls;
298 MS_U32 u32HVDCmdTimeout;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
299 MS_U32 u32VPUClockType;
300 MS_U32 u32HVDClockType;//160
301 #if SUPPORT_EVD
302 MS_U32 u32EVDClockType;
303 #endif
304 HVD_EX_Stream _stHVDStream[3];
305
306 volatile HVD_Frm_Information *pHvdFrm;//_HVD_EX_GetNextDispFrame()
307 MS_BOOL g_RstFlag;
308 MS_U64 u64pts_real;
309 MS_U32 u32VP8BBUWptr;
310 //pre_set
311 HVD_Pre_Ctrl *pHVDPreCtrl_Hal[2];
312
313 } HVD_Hal_CTX;
314
315 HVD_Hal_CTX* pHVDHalContext = NULL;
316 HVD_Hal_CTX gHVDHalContext;
317 HVD_EX_Drv_Ctrl *_pHVDCtrls = NULL;
318
319 static HVD_EX_PreSet _stHVDPreSet[HAL_HVD_EX_MAX_SUPPORT_STREAM] =
320 {
321 {FALSE},
322 {FALSE},
323 {FALSE},
324 };
325
326 //-------------------------------------------------------------------------------------------------
327 // Debug Functions
328 //-------------------------------------------------------------------------------------------------
329 #ifdef SUPPORT_X_MODEL_FEATURE //We using the common compile option to handle X model
330 //static MS_BOOL g_RstFlag = FALSE;
HVD_EX_SetRstFlag(MS_BOOL bRst)331 void HVD_EX_SetRstFlag(MS_BOOL bRst)
332 {
333 pHVDHalContext->g_RstFlag = bRst;
334 }
HVD_EX_GetRstFlag(void)335 MS_BOOL HVD_EX_GetRstFlag(void)
336 {
337 return pHVDHalContext->g_RstFlag;
338 }
339 #endif
340 //-------------------------------------------------------------------------------------------------
341 // Local Functions
342 //-------------------------------------------------------------------------------------------------
343
_HVD_EX_Context_Init_HAL(void)344 static void _HVD_EX_Context_Init_HAL(void)
345 {
346 pHVDHalContext->u32HVDCmdTimeout = 100;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
347 pHVDHalContext->u32VPUClockType = 320; //it should same as:_VPU_EX_InitAll() eClkSpeed
348 pHVDHalContext->u32HVDClockType = 345;//160;
349 #if SUPPORT_EVD
350 pHVDHalContext->u32EVDClockType = 345;
351 #endif
352 pHVDHalContext->_stHVDStream[0].eStreamId = E_HAL_HVD_MAIN_STREAM0;
353 pHVDHalContext->_stHVDStream[1].eStreamId = E_HAL_HVD_SUB_STREAM0;
354 pHVDHalContext->_stHVDStream[2].eStreamId = E_HAL_HVD_SUB_STREAM1;
355 }
356
_HVD_EX_GetBBUReadptr(MS_U32 u32Id)357 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id)
358 {
359 MS_U16 u16Ret = 0;
360 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
361 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
362 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
363 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
364 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
365
366 #if HVD_ENABLE_MVC
367 if(HAL_HVD_EX_CheckMVCID(u32Id))
368 {
369 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
370 }
371 #endif /// HVD_ENABLE_MVC
372
373 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
374 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
375
376 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
377 {
378 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS4);
379 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS3);
380 }
381 else
382 #ifdef SUPPORT_EVD
383 if ((0 == u8TaskId) || (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
384 #else
385 if (0 == u8TaskId)
386 #endif
387 {
388 //if(pCtrl->InitParams.bColocateBBUMode)
389 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
390 u16Ret = pShm->u32ColocateBBUReadPtr;
391 else
392 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB));
393 }
394 else
395 {
396 //if(pCtrl->InitParams.bColocateBBUMode)
397 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
398 u16Ret = pShm->u32ColocateBBUReadPtr;
399 else
400 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2);
401 }
402
403 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
404 _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2));
405
406 return u16Ret;
407 }
408
_HVD_EX_GetBBUWritedptr(MS_U32 u32Id)409 static MS_U16 _HVD_EX_GetBBUWritedptr(MS_U32 u32Id)
410 {
411 MS_U16 u16Ret = 0;
412 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
413 HVD_EX_Drv_Ctrl *pDrvCtrl = _HVD_EX_GetDrvCtrl(u32Id);
414 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
415 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
416 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
417
418 #if HVD_ENABLE_MVC
419 if (HAL_HVD_EX_CheckMVCID(u32Id))
420 {
421 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
422 }
423 #endif /// HVD_ENABLE_MVC
424 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
425 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
426
427 if ((pDrvCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8) // VP8
428 {
429 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS4);
430 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS3);
431 }
432 else
433 #ifdef SUPPORT_EVD
434 if ((0 == u8TaskId) || (E_HVD_INIT_HW_HEVC == (pDrvCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
435 #else
436 if (0 == u8TaskId)
437 #endif
438 {
439 //if(pDrvCtrl->InitParams.bColocateBBUMode)
440 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
441 u16Ret = pShm->u32ColocateBBUWritePtr;
442 else
443 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB));
444 }
445 else
446 {
447 //if(pDrvCtrl->InitParams.bColocateBBUMode)
448 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
449 u16Ret = pShm->u32ColocateBBUWritePtr;
450 else
451 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2);
452 }
453
454 return u16Ret;
455 }
456
_HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)457 static void _HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)
458 {
459 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
460 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
461
462 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), 0);
463 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
464 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2, 0);
465 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
466 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, 0);
467 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
468 _HVD_Write2Byte(HVD_REG_NAL_RPTR_HI_BS4, 0);
469 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
470 }
471
_HVD_EX_SetBBUWriteptr(MS_U32 u32Id,MS_U16 u16BBUNewWptr)472 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr)
473 {
474 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
475 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
476 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
477 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
478 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
479
480 #if HVD_ENABLE_MVC
481 if (HAL_HVD_EX_CheckMVCID(u32Id))
482 {
483 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
484 }
485 #endif /// HVD_ENABLE_MVC
486
487 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
488 {
489 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, u16BBUNewWptr);
490 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS4, u16BBUNewWptr);
491 }
492 else
493 #ifdef SUPPORT_EVD
494 if ((0 == u8TaskId) || (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
495 #else
496 if (0 == u8TaskId)
497 #endif
498 {
499 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), u16BBUNewWptr);
500 //if(pCtrl->InitParams.bColocateBBUMode)
501 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
502 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
503 }
504 else
505 {
506 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2, u16BBUNewWptr);
507 //if(pCtrl->InitParams.bColocateBBUMode)
508 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
509 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
510 }
511
512 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
513 _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2));
514
515 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
516 }
517
_HVD_EX_MBoxSend(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 u32Msg)518 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg)
519 {
520 MS_BOOL bResult = TRUE;
521 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
522 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
523
524 switch (u8MBox)
525 {
526 case E_HVD_HI_0:
527 {
528 _HVD_Write4Byte(HVD_REG_HI_MBOX0_L(u32RB), u32Msg);
529 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET);
530 break;
531 }
532 case E_HVD_HI_1:
533 {
534 _HVD_Write4Byte(HVD_REG_HI_MBOX1_L(u32RB), u32Msg);
535 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET);
536 break;
537 }
538 case E_HVD_VPU_HI_0:
539 {
540 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX0, u32Msg);
541 break;
542 }
543 case E_HVD_VPU_HI_1:
544 {
545 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX1, u32Msg);
546 break;
547 }
548 default:
549 {
550 bResult = FALSE;
551 break;
552 }
553 }
554
555 return bResult;
556 }
557
_HVD_EX_MBoxReady(MS_U32 u32Id,MS_U8 u8MBox)558 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox)
559 {
560 MS_BOOL bResult = TRUE;
561 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
562 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
563
564 switch (u8MBox)
565 {
566 case E_HVD_HI_0:
567 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
568 break;
569 case E_HVD_HI_1:
570 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
571 break;
572 case E_HVD_RISC_0:
573 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
574 break;
575 case E_HVD_RISC_1:
576 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
577 break;
578 case E_HVD_VPU_HI_0:
579 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX0);
580 break;
581 case E_HVD_VPU_HI_1:
582 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX1);
583 break;
584 case E_HVD_VPU_RISC_0:
585 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0);
586 break;
587 case E_HVD_VPU_RISC_1:
588 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX1);
589 break;
590 default:
591 break;
592 }
593
594 return bResult;
595 }
596
_HVD_EX_MBoxRead(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 * u32Msg)597 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg)
598 {
599 MS_BOOL bResult = TRUE;
600 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
601 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
602
603 switch (u8MBox)
604 {
605 case E_HVD_HI_0:
606 {
607 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX0_L(u32RB));
608 break;
609 }
610 case E_HVD_HI_1:
611 {
612 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX1_L(u32RB));
613 break;
614 }
615 case E_HVD_RISC_0:
616 {
617 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX0_L(u32RB));
618 break;
619 }
620 case E_HVD_RISC_1:
621 {
622 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX1_L(u32RB));
623 break;
624 }
625 case E_HVD_VPU_RISC_0:
626 {
627 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, u32Msg);
628 break;
629 }
630 case E_HVD_VPU_RISC_1:
631 {
632 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX1, u32Msg);
633 break;
634 }
635 default:
636 {
637 bResult = FALSE;
638 break;
639 }
640 }
641
642 return bResult;
643 }
644
645 #if 0
646 static void _HVD_EX_MBoxClear(MS_U8 u8MBox)
647 {
648 switch (u8MBox)
649 {
650 case E_HVD_RISC_0:
651 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR, HVD_REG_RISC_MBOX0_CLR);
652 break;
653 case E_HVD_RISC_1:
654 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR, HVD_REG_RISC_MBOX1_CLR);
655 break;
656 case E_HVD_VPU_RISC_0:
657 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX0);
658 break;
659 case E_HVD_VPU_RISC_1:
660 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX1);
661 break;
662 default:
663 break;
664 }
665 }
666 #endif
667
_HVD_EX_GetPC(void)668 static MS_U32 _HVD_EX_GetPC(void)
669 {
670 MS_U32 u32PC = 0;
671 u32PC = HAL_VPU_EX_GetProgCnt();
672 // HVD_MSG_DBG("<gdbg>pc0 =0x%lx\n",u32PC);
673 return u32PC;
674 }
675
_HVD_EX_GetESWritePtr(MS_U32 u32Id)676 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id)
677 {
678 MS_U32 u32Data = 0;
679 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
680 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
681
682 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
683 {
684 u32Data = pCtrl->LastNal.u32NalAddr + pCtrl->LastNal.u32NalSize;
685
686 if (u32Data > pCtrl->MemMap.u32BitstreamBufSize)
687 {
688 u32Data -= pCtrl->MemMap.u32BitstreamBufSize;
689
690 HVD_EX_MSG_ERR("app should not put this kind of packet\n");
691 }
692 }
693 else
694 {
695 #if HVD_ENABLE_MVC
696 MS_U8 u8ViewIdx = 0;
697 if(HAL_HVD_EX_CheckMVCID(u32Id))
698 {
699 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
700 }
701 if(u8ViewIdx != 0) /// 2nd ES ptr.
702 {
703 u32Data = pShm->u32ES2WritePtr;
704 }
705 else
706 {
707 u32Data = pShm->u32ESWritePtr;
708 }
709 #else
710 u32Data = pShm->u32ESWritePtr;
711 #endif
712 }
713
714 return u32Data;
715 }
716
717 #define NAL_UNIT_LEN_BITS 21
718 #define NAL_UNIT_OFT_BITS 30
719 #define NAL_UNIT_OFT_LOW_BITS (32-NAL_UNIT_LEN_BITS)
720 #define NAL_UNIT_OFT_HIGH_BITS (NAL_UNIT_OFT_BITS-NAL_UNIT_OFT_LOW_BITS)
721 #define NAL_UNIT_OFT_LOW_MASK (((unsigned int)0xFFFFFFFF)>>(32-NAL_UNIT_OFT_LOW_BITS))
722
_HVD_EX_GetESReadPtr(MS_U32 u32Id,MS_BOOL bDbug)723 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug)
724 {
725 MS_U32 u32Data = 0;
726 MS_U8 u8TaskId = 0;
727 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
728 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
729 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
730 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
731 MS_U32 u32VP8_BBU_DRAM_ST_ADDR_BS3 = pShm->u32HVD_BBU_DRAM_ST_ADDR;
732
733 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
734 #if HVD_ENABLE_MVC
735 if(HAL_HVD_EX_CheckMVCID(u32Id))
736 {
737 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
738 }
739 #endif /// HVD_ENABLE_MVC
740
741 if (((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV) || (TRUE == bDbug))
742 {
743 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8)
744 {
745 // MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
746 MS_U16 u16ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
747 MS_U16 u16WritePtr = _HVD_EX_GetBBUWritedptr(u32Id);
748 MS_U32 *u32Adr;
749 MS_U32 u32Tmp;
750
751 if (u16ReadPtr == u16WritePtr)
752 {
753 u32Data = _HVD_EX_GetESWritePtr(u32Id);
754 }
755 else
756 {
757 if (u16ReadPtr)
758 u16ReadPtr--;
759 else
760 u16ReadPtr = VP8_BBU_DRAM_TBL_ENTRY - 1;
761
762 u32Adr = (MS_U32 *)(MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS3 + (u16ReadPtr << 3)));
763
764 u32Data = (*u32Adr) >> NAL_UNIT_LEN_BITS;
765 u32Tmp = (*(u32Adr+1)) & (0xffffffff>>(32-(NAL_UNIT_OFT_BITS-(32-NAL_UNIT_LEN_BITS))));
766 u32Tmp = u32Tmp << (32-NAL_UNIT_LEN_BITS);
767 u32Data = u32Data | u32Tmp;
768
769 //printf("[VP8] GetESRptr (%x,%x,%x,%x,%d,%d)\n", u32Adr, (*u32Adr), (*(u32Adr+1)) , u32Data, u16ReadPtr, u16WritePtr);
770 //while(1);
771 }
772 goto EXIT;
773 }
774 // set reg_poll_nal_rptr 0
775 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), 0, HVD_REG_ESB_RPTR_POLL);
776 // set reg_poll_nal_rptr 1
777 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL);
778
779 // read reg_nal_rptr_hi
780 #ifdef SUPPORT_EVD
781 if ((0 == u8TaskId) || (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
782 #else
783 if (0 == u8TaskId)
784 #endif
785 {
786 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR(u32RB)) & 0xFFC0;
787 u32Data >>= 6;
788 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H(u32RB)) << 10;
789 }
790 else
791 {
792 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR_L_BS2) & 0xFFC0;
793 u32Data >>= 6;
794 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H_BS2) << 10;
795 }
796
797 u32Data <<= 3; // unit
798
799 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
800 {
801 MS_U32 u32ESWptr = _HVD_EX_GetESWritePtr(u32Id);
802
803 if ((pCtrl->u32LastESRptr < u32ESWptr) && (u32Data > u32ESWptr))
804 {
805 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
806 u32Data = u32ESWptr;
807 }
808 else if ((pCtrl->u32LastESRptr == u32ESWptr) && (u32Data > u32ESWptr))
809 {
810 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
811 u32Data = u32ESWptr;
812 }
813 else if ((_HVD_EX_GetBBUQNumb(u32Id) == 0) && ((u32Data - u32ESWptr) < 32)
814 && ((pShm->u32FwState & E_HVD_FW_STATE_MASK) == E_HVD_FW_PLAY))
815 {
816 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
817 u32Data = u32ESWptr;
818 }
819 else if (((u32Data > u32ESWptr) && (pCtrl->u32LastESRptr > u32Data))
820 && ((u32Data - u32ESWptr) < 32)
821 && (pCtrl->u32FlushRstPtr == 1))
822 {
823 //HVD_MSG_INFO("444HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
824 u32Data = u32ESWptr;
825 }
826 }
827
828 // remove illegal pointer
829 #if 1
830 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
831 {
832 MS_U32 u32PacketStaddr = u32Data + pCtrl->MemMap.u32BitstreamBufAddr;
833
834 if (((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStaddr) &&
835 (u32PacketStaddr <
836 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
837 {
838 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is located in drv process buffer(%lx %lx)\n" , u32Data , pCtrl->u32LastESRptr, pCtrl->MemMap.u32DrvProcessBufAddr , pCtrl->MemMap.u32DrvProcessBufSize );
839 u32Data = pCtrl->u32LastESRptr;
840 }
841 }
842 #endif
843 }
844 else
845 {
846 #if HVD_ENABLE_MVC
847 MS_U8 u8ViewIdx = 0;
848 if(HAL_HVD_EX_CheckMVCID(u32Id))
849 {
850 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
851 }
852 if(u8ViewIdx != 0) /// 2nd ES ptr.
853 {
854 u32Data = pShm->u32ES2ReadPtr;
855 }
856 else
857 {
858 u32Data = pShm->u32ESReadPtr;
859 }
860 #else
861 u32Data = pShm->u32ESReadPtr;
862 #endif
863 }
864
865 EXIT:
866
867 pCtrl->u32LastESRptr = u32Data;
868
869 return u32Data;
870 }
871
_HVD_EX_SetCMDArg(MS_U32 u32Id,MS_U32 u32Arg)872 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg)
873 {
874 MS_U16 u16TimeOut = 0xFFFF;
875 MS_BOOL bResult = FALSE;
876
877 HVD_EX_MSG_DBG("Send ARG 0x%lx to HVD\n", u32Arg);
878
879 while (--u16TimeOut)
880 {
881 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX) && _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX))
882 {
883 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, u32Arg);
884 break;
885 }
886 }
887
888 return bResult;
889 }
890
_HVD_EX_SetCMD(MS_U32 u32Id,MS_U32 u32Cmd)891 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd)
892 {
893 MS_U16 u16TimeOut = 0xFFFF;
894 MS_BOOL bResult = FALSE;
895 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
896
897 HVD_EX_MSG_DBG("Send CMD 0x%lx to HVD \n", u32Cmd);
898
899 #if HVD_ENABLE_MVC
900 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
901 {
902 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
903 }
904 #endif /// HVD_ENABLE_MVC
905
906 while (--u16TimeOut)
907 {
908 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX))
909 {
910 u32Cmd |= (u8TaskId << 24);
911 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmd);
912 break;
913 }
914 }
915 return bResult;
916 }
917
_HVD_EX_SendCmd(MS_U32 u32Id,MS_U32 u32Cmd,MS_U32 u32CmdArg)918 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg)
919 {
920 MS_U32 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
921
922 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
923 {
924 if (HVD_GetSysTime_ms() > u32timeout)
925 {
926 HVD_EX_MSG_ERR("Timeout: cmd=0x%lx arg=0x%lx\n", u32Cmd, u32CmdArg);
927 return E_HVD_RETURN_TIMEOUT;
928 }
929
930 #if 0
931 if (u32Cmd == E_HVD_CMD_STOP)
932 {
933 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
934 #if HVD_ENABLE_MVC
935 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
936 {
937 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
938 }
939 #endif /// HVD_ENABLE_MVC
940 MS_U32 u32Cmdtmp = (u8TaskId << 24) | E_HVD_CMD_STOP;
941
942 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmdtmp);
943 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, 0);
944
945 return E_HVD_RETURN_SUCCESS;
946 }
947 #endif
948
949 if(u32Cmd < E_DUAL_CMD_BASE)
950 {
951 //_HVD_EX_GetPC();
952 HAL_HVD_EX_Dump_FW_Status(u32Id);
953 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
954 }
955 }
956
957 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
958
959 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
960 {
961 if (HVD_GetSysTime_ms() > u32timeout)
962 {
963 HVD_EX_MSG_ERR("cmd timeout: %lx\n", u32Cmd);
964 return E_HVD_RETURN_TIMEOUT;
965 }
966
967 if(u32Cmd < E_DUAL_CMD_BASE)
968 {
969 //_HVD_EX_GetPC();
970 HAL_HVD_EX_Dump_FW_Status(u32Id);
971 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
972 }
973 }
974
975 return E_HVD_RETURN_SUCCESS;
976 }
977
_HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)978 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)
979 {
980 #if HAL_HVD_ENABLE_MIU_PROTECT
981 _HVD_MIU_SetReqMask(MVD_RW, bEnable);
982 _HVD_MIU_SetReqMask(MVD_BBU_R, bEnable);
983 #if SUPPORT_EVD
984 _HVD_MIU_SetReqMask(EVD_RW, bEnable);
985 _HVD_MIU_SetReqMask(EVD_BBU_R, bEnable);
986 #endif
987 _HVD_MIU_SetReqMask(HVD_RW, bEnable);
988 _HVD_MIU_SetReqMask(HVD_BBU_R, bEnable);
989 HAL_VPU_EX_MIU_RW_Protect(bEnable);
990 //HVD_Delay_ms(1);
991 #endif
992 return;
993 }
994
_HVD_EX_SetBufferAddr(MS_U32 u32Id)995 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id)
996 {
997 MS_U16 u16Reg = 0;
998 MS_U32 u32StAddr = 0;
999 MS_BOOL bBitMIU1 = FALSE;
1000 MS_BOOL bCodeMIU1 = FALSE;
1001 MS_U8 u8TaskId = 0;
1002 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1003 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1004 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1005 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1006
1007 if(pCtrl == NULL) return;
1008
1009 // nal table settngs
1010 if (pCtrl->MemMap.u32CodeBufAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1011 {
1012 bCodeMIU1 = TRUE;
1013 }
1014
1015 if (pCtrl->MemMap.u32BitstreamBufAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1016 {
1017 bBitMIU1 = TRUE;
1018 }
1019
1020 if (bBitMIU1 != bCodeMIU1)
1021 {
1022 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
1023
1024 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1025 {
1026 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1027 }
1028 }
1029 else
1030 {
1031 u32StAddr = pCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU_DRAM_ST_ADDR;
1032
1033 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1034 {
1035 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1036 }
1037 }
1038
1039 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1040 {
1041 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
1042
1043 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS3, (MS_U16)(u32StAddr >> 3));
1044 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS3, (MS_U16)(u32StAddr >> 19));
1045 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS3, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1046
1047 u32StAddr += 0x2000;
1048
1049 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS4, (MS_U16)(u32StAddr >> 3));
1050 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS4, (MS_U16)(u32StAddr >> 19));
1051 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS4, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1052
1053 // ES buffer
1054 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1055
1056 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1057 {
1058 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1059 }
1060
1061 HVD_EX_MSG_DBG("ESB start addr=%lx\n", u32StAddr);
1062
1063 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1064 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1065
1066 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1067 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1068
1069 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1070 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1071 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1072 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1073 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1074 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1075
1076 return;
1077 }
1078
1079 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1080
1081 HVD_EX_MSG_DBG("NAL start addr=%lx\n", u32StAddr);
1082
1083 #ifdef SUPPORT_EVD
1084 if ((0 == u8TaskId) || (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
1085 #else
1086 if (0 == u8TaskId)
1087 #endif
1088 {
1089 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
1090 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
1091 // -1 is for NAL_TAB_LEN counts from zero.
1092 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1093 }
1094 else
1095 {
1096 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2, (MS_U16) (u32StAddr >> 3));
1097 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2, (MS_U16) (u32StAddr >> 19));
1098 // -1 is for NAL_TAB_LEN counts from zero.
1099 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2, (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1100 }
1101
1102 // ES buffer
1103 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1104
1105 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1106 {
1107 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1108 }
1109
1110 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%lx\n", u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1111
1112 #ifdef SUPPORT_EVD
1113 if ((0 == u8TaskId) || (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
1114 #else
1115 if (0 == u8TaskId)
1116 #endif
1117 {
1118 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1119 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1120
1121 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1122 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1123 }
1124 else
1125 {
1126 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2, HVD_LWORD(u32StAddr >> 3));
1127 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2, HVD_HWORD(u32StAddr >> 3));
1128
1129 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1130 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1131 }
1132
1133 // others
1134 #ifdef SUPPORT_EVD
1135 if ((0 == u8TaskId) || (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
1136 #else
1137 if (0 == u8TaskId)
1138 #endif
1139 {
1140 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1141
1142 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1143 {
1144 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1145 }
1146 else
1147 {
1148 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1149 }
1150
1151 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1152
1153 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1154 {
1155 u16Reg |= HVD_REG_BBU_PASER_DISABLE; // force BBU to remove nothing, RM only
1156 }
1157 else // AVS or AVC
1158 {
1159 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1160 {
1161 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
1162 }
1163 else // start code remained
1164 {
1165 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
1166 }
1167 }
1168
1169 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1170
1171 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1172 }
1173 else
1174 {
1175 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2);
1176
1177 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1178 {
1179 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1180 }
1181 else
1182 {
1183 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1184 }
1185
1186 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1187
1188 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1189 {
1190 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1191 }
1192 else // AVS or AVC
1193 {
1194 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1195 {
1196 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1197 }
1198 else // start code remained
1199 {
1200 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1201 }
1202 }
1203
1204 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1205
1206 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2, u16Reg);
1207 }
1208
1209 #if (HVD_ENABLE_MVC)
1210 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
1211 {
1212 /// Used sub stream to record sub view data.
1213 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
1214 //printf("**************** Buffer setting for MVC dual-BBU *************\n");
1215
1216 if (bBitMIU1 != bCodeMIU1)
1217 {
1218 u32StAddr = pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr + pDrvCtrl_Sub->u32BBUTblInBitstreamBufAddr;
1219
1220 if (u32StAddr >= pDrvCtrl_Sub->MemMap.u32MIU1BaseAddr)
1221 {
1222 u32StAddr -= pDrvCtrl_Sub->MemMap.u32MIU1BaseAddr;
1223 }
1224 }
1225 else
1226 {
1227 u32StAddr = pDrvCtrl_Sub->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU2_DRAM_ST_ADDR;
1228
1229 if (u32StAddr >= pDrvCtrl_Sub->MemMap.u32MIU1BaseAddr)
1230 {
1231 u32StAddr -= pDrvCtrl_Sub->MemMap.u32MIU1BaseAddr;
1232 }
1233 }
1234
1235
1236 HVD_EX_MSG_DBG("[MVC] _HAL_HVD_SetBuffer2Addr: nal StAddr:%lx \n", u32StAddr);
1237 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2, (MS_U16)(u32StAddr >> 3));
1238 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2, (MS_U16)(u32StAddr >> 19));
1239 // -1 is for NAL_TAB_LEN counts from zero.
1240 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum - 1));
1241
1242 // ES buffer
1243 u32StAddr = pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr;
1244 if(u32StAddr >= pDrvCtrl_Sub->MemMap.u32MIU1BaseAddr)
1245 {
1246 u32StAddr -= pDrvCtrl_Sub->MemMap.u32MIU1BaseAddr;
1247 }
1248
1249 HVD_EX_MSG_DBG("[MVC] 2nd ES _HAL_HVD_SetBuffer2Addr: ESb StAddr:%lx, len:%lx.\n", u32StAddr, pDrvCtrl_Sub->MemMap.u32BitstreamBufSize);
1250 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2, HVD_LWORD(u32StAddr >> 3));
1251 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2, HVD_HWORD(u32StAddr >> 3));
1252
1253 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2, HVD_LWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1254 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2, HVD_HWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1255
1256 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2);
1257 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1258 {
1259 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1260 HVD_EX_MSG_DBG("[MVC] 2nd ES, TSP mode.\n");
1261 }
1262 else
1263 {
1264 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1265 HVD_EX_MSG_DBG("[MVC] 2nd ES, BBU mode.\n");
1266 }
1267 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1268 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1269 {
1270 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1271 }
1272 else // AVS or AVC
1273 {
1274 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1275 {
1276 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1277 }
1278 else // start code remained
1279 {
1280 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1281 ///HVD_MSG_DBG("[MVC] BBU Paser all.\n");
1282 }
1283 }
1284 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1285 ///HVD_MSG_DBG("[MVC] 2nd MIF BBU 0x%lx.\n",(MS_U32)u16Reg);
1286 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2, u16Reg);
1287 }
1288 #endif
1289
1290
1291 // MIF offset
1292 #if 0
1293 {
1294 MS_U16 offaddr = 0;
1295 u32StAddr = pCtrl->MemMap.u32CodeBufAddr;
1296 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1297 {
1298 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1299 }
1300 HVD_EX_MSG_DBG("MIF offset:%lx \n", u32StAddr);
1301 offaddr = (MS_U16) ((u32StAddr) >> 20);
1302 offaddr &= BMASK(HVD_REG_MIF_OFFSET_L_BITS:0);
1303 //0x1FF; // 9 bits(L + H)
1304 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU);
1305 u16Reg &= ~HVD_REG_MIF_OFFSET_H;
1306 u16Reg &= ~(BMASK(HVD_REG_MIF_OFFSET_L_BITS:0));
1307 if (offaddr & BIT(HVD_REG_MIF_OFFSET_L_BITS))
1308 {
1309 u16Reg |= HVD_REG_MIF_OFFSET_H;
1310 }
1311 _HVD_Write2Byte(HVD_REG_MIF_BBU, (u16Reg | (offaddr & BMASK(HVD_REG_MIF_OFFSET_L_BITS:0))));
1312 }
1313 #endif
1314 }
1315
1316 #if defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
1317 // Note: For VP8 only. MVC ES buffer address will be set when _HVD_EX_SetBufferAddr() is called
_HVD_EX_SetESBufferAddr(MS_U32 u32Id)1318 static void _HVD_EX_SetESBufferAddr(MS_U32 u32Id)
1319 {
1320 MS_U16 u16Reg = 0;
1321 MS_U32 u32StAddr = 0;
1322 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1323 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1324 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1325
1326 if(pCtrl == NULL) return;
1327
1328 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1329 {
1330 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
1331
1332 // ES buffer
1333 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1334
1335 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1336 {
1337 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1338 }
1339
1340 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1341 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1342
1343 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1344 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1345
1346 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1347 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1348 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1349 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1350 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1351 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1352
1353 return;
1354 }
1355
1356 // ES buffer
1357 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1358
1359 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1360 {
1361 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1362 }
1363
1364 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%lx\n", u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1365
1366 if (0 == HAL_VPU_EX_GetTaskId(u32Id))
1367 {
1368 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1369 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1370
1371 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1372 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1373 }
1374 else
1375 {
1376 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2, HVD_LWORD(u32StAddr >> 3));
1377 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2, HVD_HWORD(u32StAddr >> 3));
1378
1379 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1380 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1381 }
1382 }
1383 #endif
1384
_HVD_EX_GetESLevel(MS_U32 u32Id)1385 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id)
1386 {
1387 MS_U32 u32Wptr = 0;
1388 MS_U32 u32Rptr = 0;
1389 MS_U32 u32CurMBX = 0;
1390 MS_U32 u32ESsize = 0;
1391 MS_U32 u32Ret = E_HVD_ESB_LEVEL_NORMAL;
1392 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1393
1394 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
1395 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
1396 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
1397
1398 if (u32Rptr >= u32Wptr)
1399 {
1400 u32CurMBX = u32Rptr - u32Wptr;
1401 }
1402 else
1403 {
1404 u32CurMBX = u32ESsize - (u32Wptr - u32Rptr);
1405 }
1406
1407 if (u32CurMBX == 0)
1408 {
1409 u32Ret = E_HVD_ESB_LEVEL_UNDER;
1410 }
1411 else if (u32CurMBX < HVD_FW_AVC_ES_OVER_THRESHOLD)
1412 {
1413 u32Ret = E_HVD_ESB_LEVEL_OVER;
1414 }
1415 else
1416 {
1417 u32CurMBX = u32ESsize - u32CurMBX;
1418 if (u32CurMBX < HVD_FW_AVC_ES_UNDER_THRESHOLD)
1419 {
1420 u32Ret = E_HVD_ESB_LEVEL_UNDER;
1421 }
1422 }
1423
1424 return u32Ret;
1425 }
1426
_HVD_EX_GetESQuantity(MS_U32 u32Id)1427 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id)
1428 {
1429 MS_U32 u32Wptr = 0;
1430 MS_U32 u32Rptr = 0;
1431 MS_U32 u32ESsize = 0;
1432 MS_U32 u32Ret = 0;
1433 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1434
1435 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
1436 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
1437 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
1438
1439
1440 if(u32Wptr >= u32Rptr)
1441 {
1442 u32Ret = u32Wptr - u32Rptr;
1443 }
1444 else
1445 {
1446 u32Ret = u32ESsize - u32Rptr + u32Wptr;
1447 }
1448 //printf("ES Quantity <0x%lx> W:0x%lx, R:0x%lx, Q:0x%lx.\n",u32Id,u32Wptr,u32Rptr,u32Ret);
1449 return u32Ret;
1450 }
1451
_HVD_EX_SetRegCPU(MS_U32 u32Id)1452 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id)
1453 {
1454 MS_U32 u32FirmVer = 0;
1455 MS_U32 u32Timeout = 20000;
1456 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1457
1458 HVD_EX_MSG_DBG("HVD HW ver id: 0x%04lx\n", HAL_HVD_EX_GetHWVersionID());
1459
1460 #if HVD_ENABLE_TIME_MEASURE
1461 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
1462 #endif
1463
1464 HAL_VPU_EX_SetFWReload(!pCtrl->bTurboFWMode);
1465
1466 VPU_EX_FWCodeCfg fwCfg;
1467 VPU_EX_TaskInfo taskInfo;
1468 VPU_EX_VLCTblCfg vlcCfg;
1469 VPU_EX_NDecInitPara nDecInitPara;
1470
1471 memset(&fwCfg, 0, sizeof(VPU_EX_FWCodeCfg));
1472 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
1473 memset(&vlcCfg, 0, sizeof(VPU_EX_VLCTblCfg));
1474 memset(&nDecInitPara, 0, sizeof(VPU_EX_NDecInitPara));
1475
1476 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
1477 {
1478 vlcCfg.u32DstAddr = MsOS_PA2KSEG1(pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr);
1479 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
1480 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
1481 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr;
1482 vlcCfg.u32VLCTableOffset = pHVDHalContext->u32RV_VLCTableAddr;
1483 nDecInitPara.pVLCCfg = &vlcCfg;
1484 }
1485
1486 nDecInitPara.pFWCodeCfg = &fwCfg;
1487 nDecInitPara.pTaskInfo = &taskInfo;
1488
1489 fwCfg.u8SrcType = pCtrl->MemMap.eFWSourceType;
1490 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
1491 fwCfg.u32DstSize = pCtrl->MemMap.u32CodeBufSize;
1492 fwCfg.u32BinAddr = pCtrl->MemMap.u32FWBinaryVAddr;
1493 fwCfg.u32BinSize = pCtrl->MemMap.u32FWBinarySize;
1494
1495 taskInfo.u32Id = u32Id;
1496
1497 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
1498 {
1499 taskInfo.eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
1500 }
1501 else
1502 {
1503 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
1504 }
1505
1506 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
1507
1508 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
1509 {
1510 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
1511 }
1512 else
1513 {
1514 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
1515 }
1516 taskInfo.u32HeapSize = HVD_DRAM_SIZE;
1517 #ifdef SUPPORT_EVD
1518 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC)
1519 taskInfo.u32HeapSize = EVD_DRAM_SIZE;
1520 #endif
1521 #ifdef SUPPORT_X_MODEL_FEATURE //We using the common compile option to handle X model
1522 if(TRUE == HVD_EX_GetRstFlag())
1523 {
1524 //Delete task for Rst
1525 if(!HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
1526 {
1527 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
1528 }
1529 HVD_EX_SetRstFlag(FALSE);
1530 }
1531 #endif
1532 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara))
1533 {
1534 HVD_EX_MSG_ERR("Task create fail!\n");
1535
1536 return FALSE;
1537 }
1538
1539 while (u32Timeout)
1540 {
1541 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_INIT_DONE);
1542
1543 if (u32FirmVer != 0)
1544 {
1545 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID);
1546 break;
1547 }
1548 u32Timeout--;
1549 HVD_Delay_ms(1);
1550 }
1551
1552 if (u32Timeout > 0)
1553 {
1554 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1555
1556 pHVDHalContext->_stHVDStream[u8Idx].bUsed = TRUE;
1557
1558 HVD_EX_MSG_INF("FW version binary=0x%lx, if=0x%lx\n", u32FirmVer, (MS_U32) HVD_FW_VERSION);
1559 }
1560 else
1561 {
1562 HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET),
1563 HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID));
1564
1565 if (TRUE != HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
1566 {
1567 HVD_EX_MSG_ERR("Task delete fail!\n");
1568 }
1569
1570 return FALSE;
1571 }
1572
1573 #if HVD_ENABLE_TIME_MEASURE
1574 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
1575 #endif
1576
1577 return TRUE;
1578 }
1579
_HVD_EX_GetPTSTableRptr(MS_U32 u32Id)1580 static MS_U32 _HVD_EX_GetPTSTableRptr(MS_U32 u32Id)
1581 {
1582 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1583 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1584 if (pShm->u32PTStableRptrAddr & VPU_QMEM_BASE)
1585 {
1586 return HAL_VPU_EX_MemRead(pShm->u32PTStableRptrAddr);
1587 }
1588 else
1589 {
1590 return *((MS_U32 *) MsOS_PA2KSEG1(pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
1591 }
1592 }
1593
_HVD_EX_GetPTSTableWptr(MS_U32 u32Id)1594 static MS_U32 _HVD_EX_GetPTSTableWptr(MS_U32 u32Id)
1595 {
1596 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1597 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1598
1599 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
1600 {
1601 return HAL_VPU_EX_MemRead(pShm->u32PTStableWptrAddr);
1602 }
1603 else
1604 {
1605 return *((MS_U32 *) MsOS_PA2KSEG1(pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
1606 }
1607 }
1608
_HVD_EX_SetPTSTableWptr(MS_U32 u32Id,MS_U32 u32Value)1609 static void _HVD_EX_SetPTSTableWptr(MS_U32 u32Id, MS_U32 u32Value)
1610 {
1611 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1612 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1613
1614 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
1615 {
1616 if (!HAL_VPU_EX_MemWrite(pShm->u32PTStableWptrAddr, u32Value))
1617 {
1618 HVD_EX_MSG_ERR("PTS table SRAM write failed\n");
1619 }
1620 }
1621 else
1622 {
1623 *((MS_U32 *) MsOS_PA2KSEG1(pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
1624 }
1625 }
1626
_HVD_EX_UpdatePTSTable(MS_U32 u32Id,HVD_BBU_Info * pInfo)1627 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo)
1628 {
1629 MS_U32 u32PTSWptr = HVD_U32_MAX;
1630 MS_U32 u32PTSRptr = HVD_U32_MAX;
1631 MS_U32 u32DestAddr = 0;
1632 HVD_PTS_Entry PTSEntry;
1633 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1634 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1635 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1636
1637 // update R & W ptr
1638 u32PTSRptr = _HVD_EX_GetPTSTableRptr(u32Id);
1639
1640 HVD_EX_MSG_DBG("PTS table rptr:0x%lx, wptr=0x%lx\n", u32PTSRptr, _HVD_EX_GetPTSTableWptr(u32Id));
1641
1642 if (u32PTSRptr >= MAX_PTS_TABLE_SIZE)
1643 {
1644 HVD_EX_MSG_ERR("PTS table Read Ptr(%lx) > max table size(%lx) \n", u32PTSRptr,
1645 (MS_U32) MAX_PTS_TABLE_SIZE);
1646 return E_HVD_RETURN_FAIL;
1647 }
1648
1649 // check queue is full or not
1650 u32PTSWptr = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr + 1;
1651 u32PTSWptr %= MAX_PTS_TABLE_SIZE;
1652
1653 if (u32PTSWptr == u32PTSRptr)
1654 {
1655 HVD_EX_MSG_ERR("PTS table full. Read Ptr(%lx) == new Write ptr(%lx) ,Pre Wptr(%lx) \n", u32PTSRptr,
1656 u32PTSWptr, pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
1657 return E_HVD_RETURN_FAIL;
1658 }
1659
1660 // add one PTS entry
1661 PTSEntry.u32ByteCnt = pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt & HVD_BYTE_COUNT_MASK;
1662 PTSEntry.u32ID_L = pInfo->u32ID_L;
1663 PTSEntry.u32ID_H = pInfo->u32ID_H;
1664 PTSEntry.u32PTS = pInfo->u32TimeStamp;
1665
1666 u32DestAddr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_PTS_TABLE_ST_OFFSET + (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr * sizeof(HVD_PTS_Entry)));
1667
1668 HVD_EX_MSG_DBG("PTS entry dst addr=0x%lx\n", MsOS_VA2PA(u32DestAddr));
1669
1670 HVD_memcpy((void *) u32DestAddr, &PTSEntry, sizeof(HVD_PTS_Entry));
1671
1672 HAL_HVD_EX_FlushMemory();
1673
1674 // update Write ptr
1675 _HVD_EX_SetPTSTableWptr(u32Id, u32PTSWptr);
1676
1677 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = u32PTSWptr;
1678
1679 return E_HVD_RETURN_SUCCESS;
1680 }
1681
_HVD_EX_UpdateESWptr(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen)1682 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen)
1683 {
1684 //---------------------------------------------------
1685 // item format in nal table:
1686 // reserved |borken| u32NalOffset | u32NalLen
1687 // 13 bits |1bit | 29 bits | 21 bits (total 8 bytes)
1688 //---------------------------------------------------
1689 MS_U32 u32Adr = 0;
1690 MS_U32 u32BBUNewWptr = 0;
1691 MS_U8 item[8];
1692 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1693 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1694 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1695 MS_U32 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR;
1696
1697 #if HVD_ENABLE_MVC
1698 if(HAL_HVD_EX_CheckMVCID(u32Id))
1699 {
1700 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
1701 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
1702 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
1703 {
1704 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
1705 }
1706 }
1707 #endif /// HVD_ENABLE_MVC
1708
1709
1710 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1711 {
1712 u32BBUNewWptr = pHVDHalContext->u32VP8BBUWptr;
1713 }
1714 else
1715 {
1716 u32BBUNewWptr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
1717 }
1718 u32BBUNewWptr++;
1719 u32BBUNewWptr %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
1720
1721 // prepare nal entry
1722 item[0] = u32NalLen & 0xff;
1723 item[1] = (u32NalLen >> 8) & 0xff;
1724 item[2] = ((u32NalLen >> 16) & 0x1f) | ((u32NalOffset << 5) & 0xe0);
1725 item[3] = (u32NalOffset >> 3) & 0xff;
1726 item[4] = (u32NalOffset >> 11) & 0xff;
1727 item[5] = (u32NalOffset >> 19) & 0xff;
1728 item[6] = (u32NalOffset >> 27) & 0x07; //including broken bit
1729 item[7] = 0;
1730
1731 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1732 {
1733 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->u32VP8BBUWptr << 3));
1734 }
1735 else
1736 {
1737 // add nal entry
1738 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
1739 }
1740
1741 HVD_memcpy((void *) u32Adr, (void *) item, 8);
1742
1743 HAL_HVD_EX_FlushMemory();
1744
1745 HVD_EX_MSG_DBG("addr=0x%lx, bbu wptr=0x%lx\n", MsOS_VA2PA(u32Adr), pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
1746
1747 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1748 {
1749 pHVDHalContext->u32VP8BBUWptr = u32BBUNewWptr;
1750 }
1751 else
1752 {
1753 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = u32BBUNewWptr;
1754 }
1755
1756 return E_HVD_RETURN_SUCCESS;
1757 }
1758
_HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen,MS_U32 u32NalOffset2,MS_U32 u32NalLen2)1759 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2)
1760 {
1761 MS_U8 item[8];
1762 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1763 MS_U32 u32Adr = 0;
1764 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1765 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1766 MS_U32 u32VP8_BBU_DRAM_ST_ADDR_BS4 = pShm->u32HVD_BBU2_DRAM_ST_ADDR;
1767 /*
1768 printf("nal2 offset=0x%x, len=0x%x\n",
1769 u32NalOffset2, u32NalLen2);
1770 */
1771
1772 item[0] = u32NalLen2 & 0xff;
1773 item[1] = (u32NalLen2 >> 8) & 0xff;
1774 item[2] = ((u32NalLen2 >> 16) & 0x1f) | ((u32NalOffset2 << 5) & 0xe0);
1775 item[3] = (u32NalOffset2 >> 3) & 0xff;
1776 item[4] = (u32NalOffset2 >> 11) & 0xff;
1777 item[5] = (u32NalOffset2 >> 19) & 0xff;
1778 item[6] = (u32NalOffset2 >> 27) & 0x07;
1779 item[7] = 0;
1780
1781 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1782 {
1783 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->u32VP8BBUWptr << 3));
1784 }
1785 else
1786 {
1787 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
1788 }
1789
1790 HVD_memcpy((void *) u32Adr, (void *) item, 8);
1791
1792 HAL_HVD_EX_FlushMemory();
1793
1794 return _HVD_EX_UpdateESWptr(u32Id, u32NalOffset, u32NalLen);
1795 }
1796
_HVD_EX_GetVUIDispInfo(MS_U32 u32Id)1797 static MS_U32 _HVD_EX_GetVUIDispInfo(MS_U32 u32Id)
1798 {
1799 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1800 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1801
1802 if( ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC) ||
1803 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC) )
1804 {
1805 MS_U16 i;
1806 MS_U32 u32VUIAddr;
1807 MS_U32 *pData = (MS_U32 *) &(pHVDHalContext->g_hvd_VUIINFO);
1808
1809 HAL_HVD_EX_ReadMemory();
1810 u32VUIAddr = pShm->u32AVC_VUIDispInfo_Addr;
1811
1812 for (i = 0; i < sizeof(HVD_AVC_VUI_DISP_INFO); i += 4)
1813 {
1814 if (pShm->u32AVC_VUIDispInfo_Addr & VPU_QMEM_BASE)
1815 {
1816 *pData = HAL_VPU_EX_MemRead(u32VUIAddr + i);
1817 }
1818 else
1819 {
1820 *pData = *((MS_U32 *) MsOS_PA2KSEG1(u32VUIAddr + i + pCtrl->MemMap.u32CodeBufAddr));
1821 }
1822 pData++;
1823 }
1824 }
1825 else
1826 {
1827 memset(&(pHVDHalContext->g_hvd_VUIINFO), 0, sizeof(HVD_AVC_VUI_DISP_INFO));
1828 }
1829
1830 return (MS_U32) &(pHVDHalContext->g_hvd_VUIINFO);
1831 }
1832
_HVD_EX_GetBBUQNumb(MS_U32 u32Id)1833 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id)
1834 {
1835 MS_U32 u32ReadPtr = 0;
1836 MS_U32 eRet = 0;
1837 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1838 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1839
1840 u32ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
1841 MS_U32 u32WritePtr = 0;
1842
1843 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1844 {
1845 u32WritePtr = pHVDHalContext->u32VP8BBUWptr;
1846 }
1847 else
1848 {
1849 u32WritePtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
1850 }
1851
1852 HVD_EX_MSG_DBG("idx=%x, bbu rptr=%lx, bbu wptr=%lx\n", u8Idx, u32ReadPtr, u32WritePtr);
1853
1854 if (u32WritePtr >= u32ReadPtr)
1855 {
1856 eRet = u32WritePtr - u32ReadPtr;
1857 }
1858 else
1859 {
1860 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - u32WritePtr);
1861 }
1862
1863 #if 0
1864 if (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr >= u32ReadPtr)
1865 {
1866 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr - u32ReadPtr;
1867 }
1868 else
1869 {
1870 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
1871 }
1872
1873 #endif
1874 return eRet;
1875 }
1876
_HVD_EX_GetPTSQNumb(MS_U32 u32Id)1877 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id)
1878 {
1879 MS_U32 u32ReadPtr = 0;
1880 MS_U32 eRet = 0;
1881 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1882
1883 u32ReadPtr = _HVD_EX_GetPTSTableRptr(u32Id);
1884
1885 if (u32ReadPtr >= MAX_PTS_TABLE_SIZE)
1886 {
1887 HVD_EX_MSG_ERR("PTS table Read Ptr(%lx) > max table size(%lx) \n", u32ReadPtr,
1888 (MS_U32) MAX_PTS_TABLE_SIZE);
1889 return 0;
1890 }
1891
1892 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1893
1894 if (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr >= u32ReadPtr)
1895 {
1896 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr - u32ReadPtr;
1897 }
1898 else
1899 {
1900 eRet = MAX_PTS_TABLE_SIZE - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
1901 }
1902
1903 return eRet;
1904 }
1905
_HVD_EX_GetNextDispFrame(MS_U32 u32Id)1906 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id)
1907 {
1908 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1909 MS_U16 u16QNum = pShm->u16DispQNumb;
1910 MS_U16 u16QPtr = pShm->u16DispQPtr;
1911 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1912
1913 //static volatile HVD_Frm_Information *pHvdFrm = NULL;
1914 #if (HVD_ENABLE_MVC)
1915 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
1916
1917 if(bMVC)
1918 {
1919 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
1920 {
1921 MS_U16 u16RealQPtr = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex;
1922 MS_U16 u16UsedFrm = 0;
1923
1924 if (u16RealQPtr != u16QPtr)
1925 {
1926 if (u16RealQPtr > u16QPtr)
1927 {
1928 u16UsedFrm = u16RealQPtr - u16QPtr;
1929 }
1930 else
1931 {
1932 u16UsedFrm = pShm->u16DispQSize - (u16QPtr - u16RealQPtr);
1933 }
1934 }
1935
1936 if (u16QNum > u16UsedFrm)
1937 {
1938 volatile HVD_Frm_Information *pHvdFrm;
1939
1940 u16QNum -= u16UsedFrm;
1941 u16QPtr = u16RealQPtr;
1942 pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
1943
1944 if ((u16QPtr%2) == 0) //For MVC mode, we must check the pair of display entry is ready or not
1945 {
1946 volatile HVD_Frm_Information *pHvdFrmNext = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr+1];
1947
1948 if (pHvdFrmNext->u32Status != E_HVD_DISPQ_STATUS_INIT)
1949 {
1950 return NULL;
1951 }
1952 }
1953
1954 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
1955 {
1956 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
1957
1958 if ((u16QPtr%2) == 0)
1959 {
1960 //ALOGE("G1: %x", pHvdFrm->u32PrivateData);
1961 pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData = pHvdFrm->u32PrivateData;
1962 }
1963 else
1964 {
1965 //ALOGE("G2: %x", (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
1966 //pShm->UpdateQueue[pShm->u16UpdateQWtPtr] = (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData;
1967 //pShm->u16UpdateQWtPtr = (pShm->u16UpdateQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
1968 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
1969 }
1970
1971 u16QPtr++;
1972 if (u16QPtr == pShm->u16DispQSize) u16QPtr = 0;
1973 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = u16QPtr;
1974
1975 return (HVD_Frm_Information*)(MS_U32)pHvdFrm;
1976 }
1977 }
1978
1979 return NULL;
1980 }
1981
1982 /* Add for Mobile Platform by Ted Sun */
1983 #if 0
1984 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT*3)
1985 {
1986 u16QNum = HVD_DISPQ_PREFETCH_COUNT*3;
1987 }
1988 #endif
1989
1990 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
1991 //search the next frame to display
1992 while (u16QNum > 0)
1993 {
1994 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
1995 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
1996 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
1997
1998 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
1999 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2000 {
2001 /// For MVC. Output views after the pair of (base and depend) views were decoded.
2002 /// Check the depned view was initial when Output the base view.
2003 if((u16QPtr%2) == 0)
2004 {
2005 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
2006 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
2007 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
2008 {
2009 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
2010 ///printf("Return NULL.\n");
2011 return NULL;
2012 }
2013 }
2014
2015 //printf("V:%d.\n",u16QPtr);
2016 pHVDHalContext->_u16DispQPtr = u16QPtr;
2017 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2018 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%ld\n", u16QPtr,
2019 (MS_U32) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2020 HVD_EX_MSG_INF("<<< halHVD pts,idH = %lu, %lu [%x]\n", pHVDHalContext->pHvdFrm->u32TimeStamp, pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2021 return (HVD_Frm_Information *)(MS_U32) pHVDHalContext->pHvdFrm;
2022 }
2023
2024 u16QNum--;
2025 //go to next frame in the dispQ
2026 u16QPtr++;
2027
2028 if (u16QPtr >= pShm->u16DispQSize)
2029 {
2030 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
2031 }
2032 }
2033 }
2034 else
2035 #endif ///HVD_ENABLE_MVC
2036 {
2037 volatile HVD_Frm_Information *pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2038
2039 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2040 {
2041
2042 while (u16QNum != 0)
2043 {
2044 pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2045
2046 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2047 {
2048 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2049 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
2050
2051 return (HVD_Frm_Information*)(MS_U32)pHvdFrm;
2052
2053 }
2054 u16QNum--;
2055 //go to next frame in the dispQ
2056 u16QPtr++;
2057
2058 if (u16QPtr == pShm->u16DispQSize)
2059 {
2060 u16QPtr = 0; //wrap to the begin
2061 }
2062
2063 }
2064
2065
2066
2067 return NULL;
2068 }
2069 /* Add for Mobile Platform by Ted Sun */
2070 #if 0
2071 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT)
2072 {
2073 u16QNum = HVD_DISPQ_PREFETCH_COUNT;
2074 }
2075 #endif
2076 //printf("Q: %d %d\n", u16QNum, u16QPtr);
2077 //search the next frame to display
2078 while (u16QNum != 0)
2079 {
2080 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2081
2082 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2083 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2084 {
2085 pHVDHalContext->_u16DispQPtr = u16QPtr;
2086 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2087 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%ld\n", u16QPtr,
2088 (MS_U32) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2089 HVD_EX_MSG_INF("<<< halHVD pts,idH = %lu, %lu [%x]\n", pHVDHalContext->pHvdFrm->u32TimeStamp, pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2090 return (HVD_Frm_Information *)(MS_U32) pHVDHalContext->pHvdFrm;
2091 }
2092
2093 u16QNum--;
2094 //go to next frame in the dispQ
2095 u16QPtr++;
2096
2097 if (u16QPtr == pShm->u16DispQSize)
2098 {
2099 u16QPtr = 0; //wrap to the begin
2100 }
2101 }
2102 }
2103
2104 return NULL;
2105 }
2106 MS_BOOL
HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)2107 HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)
2108 {
2109 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2110 MS_U16 u16QNum = pShm->u16DispQNumb;
2111 MS_U16 u16QPtr = pShm->u16DispQPtr;
2112 static volatile HVD_Frm_Information *pHvdFrm = NULL;
2113
2114 #if (HVD_ENABLE_MVC)
2115 if (HAL_HVD_EX_CheckMVCID(u32Id))
2116 {
2117 if (u16QNum == 1) return TRUE;
2118 }
2119 #endif
2120
2121 while (u16QNum != 0)
2122 {
2123 pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2124 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2125 {
2126 return FALSE;
2127 }
2128 u16QNum--;
2129 u16QPtr++;
2130 if (u16QPtr == pShm->u16DispQSize)
2131 {
2132 u16QPtr = 0; //wrap to the begin
2133 }
2134 }
2135
2136 return TRUE;
2137 }
_HVD_EX_GetDrvCtrl(MS_U32 u32Id)2138 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id)
2139 {
2140 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
2141
2142 return &(_pHVDCtrls[u8DrvId]);
2143 }
2144
_HVD_EX_GetStreamIdx(MS_U32 u32Id)2145 static MS_U8 _HVD_EX_GetStreamIdx(MS_U32 u32Id)
2146 {
2147 MS_U8 u8OffsetIdx = 0;
2148 MS_U8 u8SidBaseMask = 0xF0;
2149 HAL_HVD_StreamId eSidBase = (HAL_HVD_StreamId) (u32Id >> 8 & u8SidBaseMask);
2150
2151 switch (eSidBase)
2152 {
2153 case E_HAL_HVD_MAIN_STREAM_BASE:
2154 {
2155 u8OffsetIdx = 0;
2156 break;
2157 }
2158 case E_HAL_VPU_SUB_STREAM_BASE:
2159 {
2160 u8OffsetIdx = 1;
2161 break;
2162 }
2163 case E_HAL_VPU_MVC_STREAM_BASE:
2164 {
2165 u8OffsetIdx = 0;
2166 break;
2167 }
2168 default:
2169 {
2170 u8OffsetIdx = 0;
2171 break;
2172 }
2173 }
2174
2175 return u8OffsetIdx;
2176 }
2177 /*
2178 static MS_BOOL _HAL_HVD_EX_HVDInUsed(void)
2179 {
2180 MS_U32 i = 0;
2181 for(i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
2182 {
2183 if(TRUE == pHVDHalContext->_stHVDStream[i].bUsed)
2184 {
2185 return TRUE;
2186 }
2187 }
2188 return FALSE;
2189 }
2190 */
2191
HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)2192 MS_U32 HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)
2193 {
2194 MS_U32 u32PhyAddr = 0x0;
2195 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2196
2197 if (pCtrl->MemMap.u32CodeBufAddr == 0)
2198 {
2199 return 0;
2200 }
2201
2202 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
2203
2204 if (u32PhyAddr == 0xFFFFFFFF)
2205 {
2206 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
2207 }
2208 else
2209 {
2210 #if defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
2211 //u32PhyAddr += 0; // if define HVD_OLD_LAYOUT_SHARE_MEM_BIAS under SUPPORT_NEW_MEM_LAYOUT, then we could refine the codes here
2212 #else
2213 u32PhyAddr += HVD_OLD_LAYOUT_SHARE_MEM_BIAS;
2214 #endif
2215 }
2216
2217 return MsOS_PA2KSEG1(u32PhyAddr);
2218 }
2219
HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)2220 MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)
2221 {
2222 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
2223 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2224
2225 // power on / reset HVD; set nal, es rw, bbu parser, release HVD engine
2226 // re-setup clock.
2227
2228 if (!HAL_VPU_EX_HVDInUsed())
2229 {
2230 printf("HVD power on\n");
2231 HAL_HVD_EX_PowerCtrl(TRUE);
2232 }
2233
2234 #if SUPPORT_EVD
2235 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2236 {
2237 printf("EVD power on\n");
2238 HAL_EVD_EX_PowerCtrl(TRUE);
2239 }
2240 #endif
2241
2242 if (!HAL_VPU_EX_HVDInUsed())
2243 {
2244 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
2245 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
2246 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
2247 _HVD_EX_ResetMainSubBBUWptr(u32Id);
2248
2249 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
2250 }
2251
2252 #if SUPPORT_EVD
2253 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2254 {
2255 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
2256 }
2257 #endif
2258
2259 if(pCtrl == NULL)
2260 {
2261 HVD_EX_MSG_ERR("HAL_HVD_EX_InitHW Ctrl is NULL.\n");
2262 //return FALSE;
2263 goto RESET;
2264 }
2265
2266 #if SUPPORT_EVD
2267 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2268 {
2269 _HVD_WriteWordMask(EVD_REG_RESET, 1, EVD_REG_RESET_HK_HEVC_MODE);
2270
2271 if (E_HVD_INIT_MAIN_LIVE_STREAM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2272 {
2273 _HVD_WriteWordMask(EVD_REG_RESET, 1, EVD_REG_RESET_HK_TSP2EVD_EN);
2274 }
2275 goto RESET;
2276 }
2277 #endif
2278
2279 // HVD4, from JANUS and later chip
2280 switch ((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK)
2281 {
2282 case E_HVD_INIT_HW_AVS:
2283 {
2284 if (0 == u8TaskId)
2285 {
2286 _HVD_WriteWordMask(HVD_REG_RESET, 0,
2287 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
2288 }
2289 else
2290 {
2291 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
2292 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
2293 }
2294
2295 break;
2296 }
2297 case E_HVD_INIT_HW_RM:
2298 {
2299 if (0 == u8TaskId)
2300 {
2301 _HVD_WriteWordMask(HVD_REG_RESET, 0,
2302 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
2303
2304 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
2305 {
2306 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
2307 }
2308 else // RV 8
2309 {
2310 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
2311 }
2312 }
2313 else
2314 {
2315 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
2316 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
2317
2318 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
2319 {
2320 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
2321 }
2322 else // RV 8
2323 {
2324 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
2325 }
2326
2327 }
2328
2329 break;
2330 }
2331 default:
2332 {
2333 if (0 == u8TaskId)
2334 {
2335 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
2336 }
2337 else
2338 {
2339 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
2340 }
2341 break;
2342 }
2343 }
2344
2345 RESET:
2346 //T9: use miu128bit
2347 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
2348
2349 if (!HAL_VPU_EX_HVDInUsed())
2350 {
2351 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128));
2352 }
2353
2354 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
2355
2356 #if SUPPORT_EVD
2357 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2358 {
2359 printf("EVD miu 256 bits\n");
2360 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) | EVD_REG_RESET_MIU_256));
2361 }
2362 #endif
2363 #if defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
2364 // Only ES buffer addrress needs to be set for VP8
2365 _HVD_EX_SetESBufferAddr(u32Id);
2366 #else
2367 if(DecoderType != E_VPU_EX_DECODER_MVD)
2368 {
2369 _HVD_EX_SetBufferAddr(u32Id);
2370 }
2371 #endif
2372 if (!HAL_VPU_EX_HVDInUsed())
2373 {
2374 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST);
2375 }
2376
2377 #if SUPPORT_EVD
2378 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2379 {
2380 _HVD_WriteWordMask(EVD_REG_RESET, 0, EVD_REG_RESET_SWRST);
2381 }
2382 #endif
2383
2384 return TRUE;
2385 }
2386
HAL_HVD_EX_DeinitHW(void)2387 MS_BOOL HAL_HVD_EX_DeinitHW(void)
2388 {
2389 MS_U16 u16Timeout = 1000;
2390
2391 _HVD_EX_SetMIUProtectMask(TRUE);
2392
2393 #if SUPPORT_EVD //EVD using HVD DIU, it should be turn off EVD first
2394 HAL_EVD_EX_DeinitHW();
2395 #endif
2396
2397 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
2398
2399 while (u16Timeout)
2400 {
2401 if ((_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) == (HVD_REG_RESET_SWRST_FIN))
2402 {
2403 break;
2404 }
2405 u16Timeout--;
2406 }
2407
2408 HAL_HVD_EX_PowerCtrl(FALSE);
2409
2410 _HVD_EX_SetMIUProtectMask(FALSE);
2411
2412 return TRUE;
2413 }
2414
HAL_HVD_EX_FlushMemory(void)2415 void HAL_HVD_EX_FlushMemory(void)
2416 {
2417 MsOS_FlushMemory();
2418 }
2419
HAL_HVD_EX_ReadMemory(void)2420 void HAL_HVD_EX_ReadMemory(void)
2421 {
2422 MsOS_ReadMemory();
2423 }
2424
HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl * pHVDCtrlsBase)2425 void HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl *pHVDCtrlsBase)
2426 {
2427 _pHVDCtrls = pHVDCtrlsBase;
2428 }
2429
HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)2430 void HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)
2431 {
2432 return;
2433 }
2434
HAL_HVD_EX_GetHWVersionID(void)2435 MS_U32 HAL_HVD_EX_GetHWVersionID(void)
2436 {
2437 return _HVD_Read2Byte(HVD_REG_REV_ID);
2438 }
2439
2440
HAL_HVD_EX_Init_Share_Mem(void)2441 MS_BOOL HAL_HVD_EX_Init_Share_Mem(void)
2442 {
2443 #if (defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS))
2444 #if !defined(SUPPORT_X_MODEL_FEATURE)
2445 MS_U32 u32ShmId;
2446 MS_VIRT u32Addr;
2447 MS_U32 u32BufSize;
2448
2449
2450 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HVD HAL",
2451 sizeof(HVD_Hal_CTX),
2452 &u32ShmId,
2453 &u32Addr,
2454 &u32BufSize,
2455 MSOS_SHM_QUERY))
2456 {
2457 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HVD HAL",
2458 sizeof(HVD_Hal_CTX),
2459 &u32ShmId,
2460 &u32Addr,
2461 &u32BufSize,
2462 MSOS_SHM_CREATE))
2463 {
2464 HVD_EX_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
2465 if(pHVDHalContext == NULL)
2466 {
2467 pHVDHalContext = &gHVDHalContext;
2468 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
2469 _HVD_EX_Context_Init_HAL();
2470 HVD_PRINT("[%s]Global structure init Success!!!\n",__FUNCTION__);
2471 }
2472 else
2473 {
2474 HVD_PRINT("[%s]Global structure exists!!!\n",__FUNCTION__);
2475 }
2476 //return FALSE;
2477 }
2478 else
2479 {
2480 memset((MS_U8*)u32Addr,0,sizeof(HVD_Hal_CTX));
2481 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for one process
2482 _HVD_EX_Context_Init_HAL();
2483 }
2484 }
2485 else
2486 {
2487 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for another process
2488 }
2489 #else
2490 if(pHVDHalContext == NULL)
2491 {
2492 pHVDHalContext = &gHVDHalContext;
2493 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
2494 _HVD_EX_Context_Init_HAL();
2495 }
2496 #endif
2497 _HAL_HVD_MutexCreate();
2498 #else
2499 if(pHVDHalContext == NULL)
2500 {
2501 pHVDHalContext = &gHVDHalContext;
2502 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
2503 _HVD_EX_Context_Init_HAL();
2504 }
2505 #endif
2506
2507 return TRUE;
2508 }
2509
2510
HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)2511 HAL_HVD_StreamId HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)
2512 {
2513 MS_U32 i = 0;
2514
2515 if (eStreamType == E_HAL_HVD_MVC_STREAM)
2516 {
2517 if ((FALSE == pHVDHalContext->_stHVDStream[0].bUsed) && (FALSE == pHVDHalContext->_stHVDStream[1].bUsed))
2518 return pHVDHalContext->_stHVDStream[0].eStreamId;
2519 }
2520 else if (eStreamType == E_HAL_HVD_MAIN_STREAM)
2521 {
2522 for (i = 0;
2523 i <
2524 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
2525 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
2526 {
2527 if ((E_HAL_HVD_MAIN_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
2528 {
2529 return pHVDHalContext->_stHVDStream[i].eStreamId;
2530 }
2531 }
2532 }
2533 else if (eStreamType == E_HAL_HVD_SUB_STREAM)
2534 {
2535 for (i = 0;
2536 i <
2537 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
2538 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
2539 {
2540 if ((E_HAL_HVD_SUB_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
2541 {
2542 return pHVDHalContext->_stHVDStream[i].eStreamId;
2543 }
2544 }
2545 }
2546
2547 return E_HAL_HVD_STREAM_NONE;
2548 }
2549
HAL_HVD_EX_PowerCtrl(MS_BOOL bEnable)2550 void HAL_HVD_EX_PowerCtrl(MS_BOOL bEnable)
2551 {
2552 if (bEnable)
2553 {
2554 _HVD_WriteByteMask(REG_TOP_HVD, ~TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
2555 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
2556 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS);
2557 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK);
2558 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK);
2559 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK);
2560 _HVD_WriteWordMask(REG_TOP_HVD_IDB, ~TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
2561 }
2562 else
2563 {
2564 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
2565 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
2566 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS);
2567 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK);
2568 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK);
2569 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK);
2570 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
2571 }
2572
2573 // fix to not inverse
2574 _HVD_WriteByteMask(REG_TOP_HVD, ~TOP_CKG_HVD_INV, TOP_CKG_HVD_INV);
2575
2576 switch (pHVDHalContext->u32HVDClockType)
2577 {
2578 case 345:
2579 {
2580 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_345MHZ, TOP_CKG_HVD_CLK_MASK);
2581 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK);
2582 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_VP6_192MHZ, TOP_CKG_VP6_CLK_MASK);
2583 _HVD_WriteWordMask(REG_TOP_HVD_IDB, ~TOP_CKG_HVD_IDB_CLK_HVD_MIU, TOP_CKG_HVD_IDB_CLK_HVD_MIU); // TODO://FIXME: need to check miu clk,
2584 // TODO://if(hvd_clk > miu_clk) set to TOP_CKG_HVD_IDB_CLK_HVD_MIU = 0
2585 // TODO://else set to TOP_CKG_HVD_IDB_CLK_HVD_MIU = 1
2586 break;
2587 }
2588 case 320:
2589 {
2590 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_320MHZ, TOP_CKG_HVD_CLK_MASK);
2591 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK);
2592 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_VP6_192MHZ, TOP_CKG_VP6_CLK_MASK);
2593 _HVD_WriteWordMask(REG_TOP_HVD_IDB, ~TOP_CKG_HVD_IDB_CLK_HVD_MIU, TOP_CKG_HVD_IDB_CLK_HVD_MIU); // TODO://FIXME: need to check miu clk,
2594 // TODO://if(hvd_clk > miu_clk) set to TOP_CKG_HVD_IDB_CLK_HVD_MIU = 0
2595 // TODO://else set to TOP_CKG_HVD_IDB_CLK_HVD_MIU = 1
2596 break;
2597 }
2598 case 288:
2599 {
2600 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_288MHZ, TOP_CKG_HVD_CLK_MASK);
2601 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK);
2602 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_VP6_192MHZ, TOP_CKG_VP6_CLK_MASK);
2603 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_CLK_HVD_MIU, TOP_CKG_HVD_IDB_CLK_HVD_MIU); // TODO://FIXME: need to check miu clk,
2604 // TODO://if(hvd_clk > miu_clk) set to TOP_CKG_HVD_IDB_CLK_HVD_MIU = 0
2605 // TODO://else set to TOP_CKG_HVD_IDB_CLK_HVD_MIU = 1
2606 break;
2607 }
2608 case 240:
2609 {
2610 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_240MHZ, TOP_CKG_HVD_CLK_MASK);
2611 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK);
2612 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_VP6_192MHZ, TOP_CKG_VP6_CLK_MASK);
2613 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_CLK_HVD_MIU, TOP_CKG_HVD_IDB_CLK_HVD_MIU); // TODO://FIXME: need to check miu clk,
2614 // TODO://if(hvd_clk > miu_clk) set to TOP_CKG_HVD_IDB_CLK_HVD_MIU = 0
2615 // TODO://else set to TOP_CKG_HVD_IDB_CLK_HVD_MIU = 1
2616 break;
2617 }
2618 case 216:
2619 {
2620 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_216MHZ, TOP_CKG_HVD_CLK_MASK);
2621 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_172MHZ, TOP_CKG_VP8_MASK);
2622 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_VP6_172MHZ, TOP_CKG_VP6_CLK_MASK);
2623 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_CLK_HVD_MIU, TOP_CKG_HVD_IDB_CLK_HVD_MIU); // TODO://FIXME: need to check miu clk,
2624 // TODO://if(hvd_clk > miu_clk) set to TOP_CKG_HVD_IDB_CLK_HVD_MIU = 0
2625 // TODO://else set to TOP_CKG_HVD_IDB_CLK_HVD_MIU = 1
2626 break;
2627 }
2628 case 172:
2629 {
2630 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_172MHZ, TOP_CKG_HVD_CLK_MASK);
2631 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_172MHZ, TOP_CKG_VP8_MASK);
2632 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_VP6_172MHZ, TOP_CKG_VP6_CLK_MASK);
2633 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_CLK_HVD_MIU, TOP_CKG_HVD_IDB_CLK_HVD_MIU); // TODO://FIXME: need to check miu clk,
2634 // TODO://if(hvd_clk > miu_clk) set to TOP_CKG_HVD_IDB_CLK_HVD_MIU = 0
2635 // TODO://else set to TOP_CKG_HVD_IDB_CLK_HVD_MIU = 1
2636 break;
2637 }
2638 case 144:
2639 {
2640 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_144MHZ, TOP_CKG_HVD_CLK_MASK);
2641 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_144MHZ, TOP_CKG_VP8_MASK);
2642 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_VP6_144MHZ, TOP_CKG_VP6_CLK_MASK);
2643 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_CLK_HVD_MIU, TOP_CKG_HVD_IDB_CLK_HVD_MIU); // TODO://FIXME: need to check miu clk,
2644 // TODO://if(hvd_clk > miu_clk) set to TOP_CKG_HVD_IDB_CLK_HVD_MIU = 0
2645 // TODO://else set to TOP_CKG_HVD_IDB_CLK_HVD_MIU = 1
2646 break;
2647 }
2648 default:
2649 {
2650 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_345MHZ, TOP_CKG_HVD_CLK_MASK);
2651 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK);
2652 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_VP6_192MHZ, TOP_CKG_VP6_CLK_MASK);
2653 _HVD_WriteWordMask(REG_TOP_HVD_IDB, ~TOP_CKG_HVD_IDB_CLK_HVD_MIU, TOP_CKG_HVD_IDB_CLK_HVD_MIU); // TODO://FIXME: need to check miu clk,
2654 // TODO://if(hvd_clk > miu_clk) set to TOP_CKG_HVD_IDB_CLK_HVD_MIU = 0
2655 // TODO://else set to TOP_CKG_HVD_IDB_CLK_HVD_MIU = 1
2656 break;
2657 }
2658 }
2659
2660 return;
2661 }
2662
HAL_HVD_EX_InitRegBase(MS_U32 u32RegBase)2663 void HAL_HVD_EX_InitRegBase(MS_U32 u32RegBase)
2664 {
2665 u32HVDRegOSBase = u32RegBase;
2666 HAL_VPU_EX_InitRegBase(u32RegBase);
2667 }
2668
HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_U32 drvprectrl)2669 void HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_U32 drvprectrl)
2670 {
2671 HVD_Pre_Ctrl *pHVDPreCtrl_in = (HVD_Pre_Ctrl*)drvprectrl;
2672 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2673 pHVDHalContext->pHVDPreCtrl_Hal[u8Idx] = pHVDPreCtrl_in;
2674 }
2675
HAL_HVD_EX_InitVariables(MS_U32 u32Id)2676 HVD_Return HAL_HVD_EX_InitVariables(MS_U32 u32Id)
2677 {
2678 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2679 HVD_ShareMem *pShm = NULL;
2680 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2681 #if HVD_ENABLE_MVC
2682 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
2683 #endif ///HVD_ENABLE_MVC
2684
2685 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = 0;
2686 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = 0;
2687 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = 0;
2688 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
2689 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
2690 #if HVD_ENABLE_MVC
2691 if(bMVC)
2692 {
2693 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSPreWptr = 0;
2694 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSByteCnt = 0;
2695 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUWptr = 0;
2696 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = 0;
2697 }
2698 #endif ///HVD_ENABLE_MVC
2699
2700 // set a local copy of FW code address; assuming there is only one copy of FW,
2701 // no matter how many task will be created.
2702
2703 pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2704
2705 memset((void *) (pHVDHalContext->g_hvd_nal_fill_pair), 0, 16);
2706
2707 // global variables
2708 pHVDHalContext->u32HVDCmdTimeout = pCtrl->u32CmdTimeout;
2709
2710 if(((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVS)
2711 {
2712 if(pHVDHalContext->u32HVDClockType > 288)
2713 pHVDHalContext->u32HVDClockType = 288;
2714 }
2715 // pHVDHalContext->u32VPUClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
2716 // pHVDHalContext->u32HVDClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
2717 // Create mutex
2718 //_HAL_HVD_MutexCreate();
2719
2720 // fill HVD init variables
2721 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2722 {
2723 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = VP8_BBU_DRAM_TBL_ENTRY;
2724 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = VP8_BBU_DRAM_TBL_ENTRY_TH;
2725 }
2726 else
2727 #if HVD_ENABLE_RV_FEATURE
2728 if (((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
2729 {
2730 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = RVD_BBU_DRAM_TBL_ENTRY;
2731 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = RVD_BBU_DRAM_TBL_ENTRY_TH;
2732
2733 if (pCtrl->MemMap.u32FrameBufSize > RV_VLC_TABLE_SIZE)
2734 {
2735 pHVDHalContext->u32RV_VLCTableAddr = pCtrl->MemMap.u32FrameBufSize - RV_VLC_TABLE_SIZE;
2736 pCtrl->MemMap.u32FrameBufSize -= RV_VLC_TABLE_SIZE;
2737 }
2738 else
2739 {
2740 HVD_EX_MSG_ERR("HAL_HVD_EX_InitVariables failed: frame buffer size too small. FB:%lx min:%lx\n",
2741 (MS_U32) pCtrl->MemMap.u32FrameBufSize, (MS_U32) RV_VLC_TABLE_SIZE);
2742 return E_HVD_RETURN_INVALID_PARAMETER;
2743 }
2744 }
2745 else
2746 #endif
2747 {
2748 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = HVD_BBU_DRAM_TBL_ENTRY;
2749 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = HVD_BBU_DRAM_TBL_ENTRY_TH;
2750 #if HVD_ENABLE_MVC
2751 if(bMVC)
2752 {
2753 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = MVC_BBU_DRAM_TBL_ENTRY;
2754 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNumTH = MVC_BBU_DRAM_TBL_ENTRY_TH;
2755 }
2756 #endif /// HVD_ENABLE_MVC
2757 pHVDHalContext->u32RV_VLCTableAddr = 0;
2758 }
2759
2760 if ((HAL_VPU_EX_GetShareInfoAddr(u32Id) != 0xFFFFFFFF)
2761 || ((pCtrl->MemMap.u32CodeBufVAddr <= (MS_U32) pShm) && ((MS_U32) pShm <= (pCtrl->MemMap.u32CodeBufVAddr + pCtrl->MemMap.u32CodeBufSize)))
2762 || ((pCtrl->MemMap.u32BitstreamBufVAddr <= (MS_U32) pShm) && ((MS_U32) pShm <= (pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->MemMap.u32BitstreamBufSize)))
2763 || ((pCtrl->MemMap.u32FrameBufVAddr <= (MS_U32) pShm) && ((MS_U32) pShm <= (pCtrl->MemMap.u32FrameBufVAddr + pCtrl->MemMap.u32FrameBufSize))))
2764 {
2765 HVD_EX_MSG_DBG("input memory: Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miubase=0x%lx\n",
2766 pCtrl->MemMap.u32CodeBufAddr,
2767 pCtrl->MemMap.u32FrameBufAddr,
2768 pCtrl->MemMap.u32BitstreamBufAddr,
2769 pCtrl->MemMap.u32MIU1BaseAddr);
2770 #if HVD_ENABLE_MVC
2771 if(bMVC)
2772 {
2773 HVD_EX_Drv_Ctrl *pHVDCtrl_in_sub = _HVD_EX_GetDrvCtrl(u32Id+0x00011000);
2774 if (( (pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr)<= (MS_U32)pShm)&& ( (MS_U32)pShm <= ((pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr )+ pHVDCtrl_in_sub->MemMap.u32BitstreamBufSize)))
2775 {
2776 HVD_EX_MSG_DBG("[MVC] Bitstream2: 0x%lx.\n", pCtrl->MemMap.u32BitstreamBufAddr);
2777 }
2778 }
2779 #endif /// HVD_ENABLE_MVC
2780
2781 return E_HVD_RETURN_SUCCESS;
2782 }
2783 else
2784 {
2785 HVD_EX_MSG_ERR("failed: Shm addr=0x%lx, Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miubase=0x%lx\n",
2786 MS_PA2KSEG1((MS_U32) pShm),
2787 pCtrl->MemMap.u32CodeBufAddr,
2788 pCtrl->MemMap.u32FrameBufAddr,
2789 pCtrl->MemMap.u32BitstreamBufAddr,
2790 pCtrl->MemMap.u32MIU1BaseAddr);
2791 return E_HVD_RETURN_INVALID_PARAMETER;
2792 }
2793 }
2794
HAL_HVD_EX_InitShareMem(MS_U32 u32Id)2795 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id)
2796 {
2797 MS_U32 u32Addr = 0;
2798 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2799 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2800 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2801
2802 memset(pShm, 0, sizeof(HVD_ShareMem));
2803
2804 u32Addr = pCtrl->MemMap.u32FrameBufAddr;
2805
2806 if (u32Addr >= pCtrl->MemMap.u32MIU1BaseAddr)
2807 {
2808 u32Addr -= pCtrl->MemMap.u32MIU1BaseAddr;
2809 }
2810
2811 pShm->u32FrameRate = pCtrl->InitParams.u32FrameRate;
2812 pShm->u32FrameRateBase = pCtrl->InitParams.u32FrameRateBase;
2813 pShm->u32FrameBufAddr = u32Addr;
2814 pShm->u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
2815 pShm->DispInfo.u16DispWidth = 1;
2816 pShm->DispInfo.u16DispHeight = 1;
2817 pShm->u32CodecType = pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK;
2818 pShm->u32CPUClock = pHVDHalContext->u32VPUClockType;
2819 pShm->u32UserCCIdxWrtPtr = 0xFFFFFFFF;
2820 pShm->DispFrmInfo.u32TimeStamp = 0xFFFFFFFF;
2821 //Chip info
2822 pShm->u16ChipID = E_MSTAR_CHIP_MUJI;
2823 pShm->u16ChipECONum = pCtrl->InitParams.u16ChipECONum;
2824 // PreSetControl
2825 if (pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->bOnePendingBuffer)
2826 {
2827 pShm->u32PreSetControl |= PRESET_ONE_PENDING_BUFFER;
2828 }
2829
2830
2831 //pShm->bColocateBBUMode = pCtrl->InitParams.bColocateBBUMode;//johnny.ko
2832 //pShm->bColocateBBUMode = _stHVDPreSet[u8Idx].bColocateBBUMode;//johnny.ko
2833 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
2834 pShm->u8BBUMode = E_HVD_FW_AUTO_BBU_MODE;
2835 else
2836 pShm->u8BBUMode = E_HVD_DRV_AUTO_BBU_MODE;
2837 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_RAW)
2838 {
2839 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
2840 {
2841 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE_DUAL_ES;
2842 }
2843 else
2844 {
2845 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE;
2846 }
2847 }
2848 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_TS)
2849 {
2850 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
2851 {
2852 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE_DUAL_ES;
2853 }
2854 else
2855 {
2856 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE;
2857 }
2858 }
2859 else
2860 {
2861 pShm->u8SrcMode = E_HVD_SRC_MODE_DTV;
2862 }
2863
2864 #if 1//From T4 and the later chips, QDMA can support the address more than MIU1 base.
2865 if(pCtrl->MemMap.u32CodeBufAddr >= HAL_MIU1_BASE)
2866 {
2867 pShm->u32FWBaseAddr = (pCtrl->MemMap.u32CodeBufAddr-HAL_MIU1_BASE) | 0x40000000; //Bit30 sel miu0/1
2868 }
2869 else
2870 {
2871 pShm->u32FWBaseAddr = pCtrl->MemMap.u32CodeBufAddr;
2872 }
2873 //printf("<DBG>QDMA Addr = %lx <<<<<<<<<<<<<<<<<<<<<<<<\n",pShm->u32FWBaseAddr);
2874 #else
2875 u32Addr = pCtrl->MemMap.u32CodeBufAddr;
2876 if (u32Addr >= pCtrl->MemMap.u32MIU1BaseAddr)
2877 {
2878 u32Addr -= pCtrl->MemMap.u32MIU1BaseAddr;
2879 }
2880 pShm->u32FWBaseAddr = u32Addr;
2881 #endif
2882
2883 // RM only
2884 #if HVD_ENABLE_RV_FEATURE
2885 if ((((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
2886 && (pCtrl->InitParams.pRVFileInfo != NULL))
2887 {
2888 MS_U32 i = 0;
2889
2890 for (i = 0; i < HVD_RM_INIT_PICTURE_SIZE_NUMBER; i++)
2891 {
2892 pShm->pRM_PictureSize[i].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[i];
2893 pShm->pRM_PictureSize[i].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[i];
2894 }
2895
2896 pShm->u8RM_Version = (MS_U8) pCtrl->InitParams.pRVFileInfo->RV_Version;
2897 pShm->u8RM_NumSizes = (MS_U8) pCtrl->InitParams.pRVFileInfo->ulNumSizes;
2898 u32Addr = pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr;
2899
2900 if (u32Addr >= pCtrl->MemMap.u32MIU1BaseAddr)
2901 {
2902 u32Addr -= pCtrl->MemMap.u32MIU1BaseAddr;
2903 }
2904
2905 pShm->u32RM_VLCTableAddr = u32Addr;
2906 }
2907 #endif
2908
2909 if ((E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2910 && (pCtrl->InitParams.pRVFileInfo != NULL))
2911 {
2912 pShm->pRM_PictureSize[0].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[0];
2913 pShm->pRM_PictureSize[0].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[0];
2914 }
2915
2916 //if(pCtrl->InitParams.bColocateBBUMode)
2917 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
2918 {
2919 pShm->u32ColocateBBUWritePtr = pShm->u32ColocateBBUReadPtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
2920 }
2921
2922 HAL_HVD_EX_FlushMemory();
2923
2924 return E_HVD_RETURN_SUCCESS;
2925 }
2926
HAL_HVD_EX_InitRegCPU(MS_U32 u32Id)2927 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id)
2928 {
2929 MS_BOOL bInitRet = FALSE;
2930
2931 #if 0
2932 // check MVD power on
2933 if (_HVD_Read2Byte(REG_TOP_MVD) & (TOP_CKG_MHVD_DIS))
2934 {
2935 HVD_EX_MSG_INF("HVD warning: MVD is not power on before HVD init.\n");
2936 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
2937 HVD_Delay_ms(1);
2938 }
2939 // Check VPU power on
2940 if (_HVD_Read2Byte(REG_TOP_VPU) & (TOP_CKG_VPU_DIS))
2941 {
2942 HVD_EX_MSG_INF("HVD warning: VPU is not power on before HVD init.\n");
2943 _HVD_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
2944 HVD_Delay_ms(1);
2945 }
2946 // check HVD power on
2947 if (_HVD_Read2Byte(REG_TOP_HVD) & (TOP_CKG_HVD_DIS))
2948 {
2949 HVD_EX_MSG_INF("HVD warning: HVD is not power on before HVD init.\n");
2950 HAL_HVD_EX_PowerCtrl(TRUE);
2951 HVD_Delay_ms(1);
2952 }
2953 #endif
2954
2955 bInitRet = _HVD_EX_SetRegCPU(u32Id);
2956
2957 if (!bInitRet)
2958 {
2959 return E_HVD_RETURN_FAIL;
2960 }
2961
2962 bInitRet = HAL_HVD_EX_RstPTSCtrlVariable(u32Id);
2963
2964 if (!bInitRet)
2965 {
2966 return E_HVD_RETURN_FAIL;
2967 }
2968
2969 return E_HVD_RETURN_SUCCESS;
2970 }
2971
HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id,MS_BOOL bEnable)2972 HVD_Return HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id, MS_BOOL bEnable)
2973 {
2974 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2975
2976 _stHVDPreSet[u8Idx].bColocateBBUMode = bEnable;
2977
2978 return E_HVD_RETURN_SUCCESS;
2979 }
2980
HAL_HVD_EX_SetData(MS_U32 u32Id,HVD_SetData u32type,MS_U32 u32Data)2981 HVD_Return HAL_HVD_EX_SetData(MS_U32 u32Id, HVD_SetData u32type, MS_U32 u32Data)
2982 {
2983 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
2984 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2985 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2986 MS_BOOL bMVC = FALSE;
2987 #if HVD_ENABLE_MVC
2988 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
2989 #endif
2990
2991 switch (u32type)
2992 {
2993 // share memory
2994 // switch
2995 case E_HVD_SDATA_FRAMEBUF_ADDR:
2996 {
2997 pShm->u32FrameBufAddr = u32Data;
2998 break;
2999 }
3000 case E_HVD_SDATA_FRAMEBUF_SIZE:
3001 {
3002 pShm->u32FrameBufSize = u32Data;
3003 break;
3004 }
3005 case E_HVD_SDATA_RM_PICTURE_SIZES:
3006 {
3007 HVD_memcpy((volatile void *) pShm->pRM_PictureSize, (void *) ((HVD_PictureSize *) u32Data),
3008 HVD_RM_INIT_PICTURE_SIZE_NUMBER * sizeof(HVD_PictureSize));
3009 break;
3010 }
3011 case E_HVD_SDATA_ERROR_CODE:
3012 {
3013 pShm->u16ErrCode = (MS_U16) u32Data;
3014 break;
3015 }
3016 case E_HVD_SDATA_DISP_INFO_TH:
3017 {
3018 HVD_memcpy((volatile void *) &(pShm->DispThreshold), (void *) ((HVD_DISP_THRESHOLD *) u32Data),
3019 sizeof(HVD_DISP_THRESHOLD));
3020 break;
3021 }
3022 case E_HVD_SDATA_FW_FLUSH_STATUS:
3023 {
3024 pShm->u8FlushStatus = (MS_U8)u32Data;
3025 break;
3026 }
3027 case E_HVD_SDATA_DMX_FRAMERATE:
3028 {
3029 pShm->u32DmxFrameRate = u32Data;
3030 break;
3031 }
3032 case E_HVD_SDATA_DMX_FRAMERATEBASE:
3033 {
3034 pShm->u32DmxFrameRateBase = u32Data;
3035 break;
3036 }
3037 // SRAM
3038
3039 // Mailbox
3040 case E_HVD_SDATA_TRIGGER_DISP: // HVD HI mbox 0
3041 {
3042 if (u32Data != 0)
3043 {
3044 pShm->bEnableDispCtrl = TRUE;
3045 pShm->bIsTrigDisp = TRUE;
3046 }
3047 else
3048 {
3049 pShm->bEnableDispCtrl = FALSE;
3050 }
3051
3052 break;
3053 }
3054 case E_HVD_SDATA_GET_DISP_INFO_START:
3055 {
3056 pShm->bSpsChange = FALSE;
3057 break;
3058 }
3059 case E_HVD_SDATA_VIRTUAL_BOX_WIDTH:
3060 {
3061 pShm->u32VirtualBoxWidth = u32Data;
3062 break;
3063 }
3064 case E_HVD_SDATA_VIRTUAL_BOX_HEIGHT:
3065 {
3066 pShm->u32VirtualBoxHeight = u32Data;
3067 break;
3068 }
3069 case E_HVD_SDATA_DISPQ_STATUS_VIEW:
3070 {
3071 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_INIT)
3072 {
3073 //printf("DispFrame DqPtr: %d\n", u32Data);
3074 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_VIEW;
3075 }
3076 break;
3077 }
3078 case E_HVD_SDATA_DISPQ_STATUS_DISP:
3079 {
3080 if(!(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide))
3081 {
3082 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
3083 {
3084 //printf("DispFrame DqPtr: %ld\n", u32Data);
3085 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_DISP;
3086 }
3087 }
3088 break;
3089 }
3090 case E_HVD_SDATA_DISPQ_STATUS_FREE:
3091 {
3092 if(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
3093 {
3094 if (bMVC)
3095 {
3096 if (pHVDHalContext->_stHVDStream[u8Idx].u32FreeData == 0xFFFF)
3097 {
3098 //ALOGE("R1: %x", u32Data);
3099 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = u32Data;
3100 }
3101 else
3102 {
3103 //ALOGE("R2: %x", (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
3104 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
3105 //pShm->FreeQueue[pShm->u16FreeQWtPtr] = (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData;
3106 //pShm->u16FreeQWtPtr = (pShm->u16FreeQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
3107 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
3108 }
3109 }
3110 else
3111 {
3112 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, u32Data);
3113 }
3114 }
3115 else
3116 {
3117 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
3118 {
3119 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_FREE;
3120 }
3121 }
3122 break;
3123 }
3124 default:
3125 break;
3126 }
3127
3128 HAL_HVD_EX_FlushMemory();
3129
3130 return eRet;
3131 }
3132
HAL_HVD_EX_GetData_EX(MS_U32 u32Id,HVD_GetData eType)3133 MS_S64 HAL_HVD_EX_GetData_EX(MS_U32 u32Id, HVD_GetData eType)
3134 {
3135 MS_S64 s64Ret = 0;
3136 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3137
3138 HAL_HVD_EX_ReadMemory();
3139
3140 switch (eType)
3141 {
3142 case E_HVD_GDATA_PTS_STC_DIFF:
3143 s64Ret = pShm->s64PtsStcDiff;
3144 break;
3145 default:
3146 break;
3147 }
3148
3149 return s64Ret;
3150 }
3151
HAL_HVD_EX_GetData(MS_U32 u32Id,HVD_GetData eType)3152 MS_U32 HAL_HVD_EX_GetData(MS_U32 u32Id, HVD_GetData eType)
3153 {
3154 MS_U32 u32Ret = 0;
3155 //static MS_U64 u64pts_real = 0;
3156 MS_U64 u64pts_low = 0;
3157 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3158 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3159
3160 HAL_HVD_EX_ReadMemory();
3161
3162 if(pShm == NULL)
3163 {
3164 printf("########## VDEC patch for Debug ###########\n");
3165 return 0x0;
3166 }
3167
3168 switch (eType)
3169 {
3170 // share memory
3171 // switch
3172 case E_HVD_GDATA_DISP_INFO_ADDR:
3173 {
3174 u32Ret = (MS_U32) (&pShm->DispInfo);
3175 break;
3176 }
3177 // report
3178 case E_HVD_GDATA_PTS:
3179 {
3180 u32Ret = pShm->DispFrmInfo.u32TimeStamp;
3181 break;
3182 }
3183 case E_HVD_GDATA_U64PTS:
3184 {
3185 u64pts_low = (MS_U64)(pShm->DispFrmInfo.u32TimeStamp);
3186 pHVDHalContext->u64pts_real = (MS_U64)(pShm->DispFrmInfo.u32ID_H);
3187 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
3188 u32Ret = (MS_U32)(&(pHVDHalContext->u64pts_real));
3189 break;
3190 }
3191 case E_HVD_GDATA_DECODE_CNT:
3192 {
3193 u32Ret = pShm->u32DecodeCnt;
3194 break;
3195 }
3196 case E_HVD_GDATA_DATA_ERROR_CNT:
3197 {
3198 u32Ret = pShm->u32DataErrCnt;
3199 break;
3200 }
3201 case E_HVD_GDATA_DEC_ERROR_CNT:
3202 {
3203 u32Ret = pShm->u32DecErrCnt;
3204 break;
3205 }
3206 case E_HVD_GDATA_ERROR_CODE:
3207 {
3208 u32Ret = (MS_U32) (pShm->u16ErrCode);
3209 break;
3210 }
3211 case E_HVD_GDATA_VPU_IDLE_CNT:
3212 {
3213 u32Ret = pShm->u32VPUIdleCnt;
3214 break;
3215 }
3216 case E_HVD_GDATA_DISP_FRM_INFO:
3217 {
3218 u32Ret = (MS_U32) (&pShm->DispFrmInfo);
3219 break;
3220 }
3221 case E_HVD_GDATA_DEC_FRM_INFO:
3222 {
3223 u32Ret = (MS_U32) (&pShm->DecoFrmInfo);
3224 break;
3225 }
3226 case E_HVD_GDATA_ES_LEVEL:
3227 {
3228 u32Ret = (MS_U32) (_HVD_EX_GetESLevel(u32Id));
3229 break;
3230 }
3231 #if HVD_ENABLE_MVC
3232 case E_HVD_GDATA_DISP_FRM_INFO_SUB:
3233 {
3234 u32Ret= (MS_U32) (&(pShm->DispFrmInfo_Sub));
3235 break;
3236 }
3237 case E_HVD_GDATA_DEC_FRM_INFO_SUB:
3238 {
3239 u32Ret= (MS_U32) (&(pShm->DecoFrmInfo_Sub));
3240 break;
3241 }
3242 #endif
3243
3244 // user data
3245 case E_HVD_GDATA_USERDATA_WPTR:
3246 {
3247 u32Ret = (MS_U32) (pShm->u32UserCCIdxWrtPtr);
3248 break;
3249 }
3250 case E_HVD_GDATA_USERDATA_IDX_TBL_ADDR:
3251 {
3252 u32Ret = (MS_U32) (pShm->u8UserCCIdx);
3253 break;
3254 }
3255 case E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR:
3256 {
3257 u32Ret = (MS_U32) (pShm->u32UserCCBase);
3258 break;
3259 }
3260 case E_HVD_GDATA_USERDATA_PACKET_SIZE:
3261 {
3262 u32Ret = (MS_U32) (sizeof(DTV_BUF_type));
3263 break;
3264 }
3265 case E_HVD_GDATA_USERDATA_IDX_TBL_SIZE:
3266 {
3267 u32Ret = (MS_U32) (USER_CC_IDX_SIZE);
3268 break;
3269 }
3270 case E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE:
3271 {
3272 u32Ret = (MS_U32) (USER_CC_DATA_SIZE);
3273 break;
3274 }
3275 // report - modes
3276 case E_HVD_GDATA_IS_SHOW_ERR_FRM:
3277 {
3278 u32Ret = pShm->ModeStatus.bIsShowErrFrm;
3279 break;
3280 }
3281 case E_HVD_GDATA_IS_REPEAT_LAST_FIELD:
3282 {
3283 u32Ret = pShm->ModeStatus.bIsRepeatLastField;
3284 break;
3285 }
3286 case E_HVD_GDATA_IS_ERR_CONCEAL:
3287 {
3288 u32Ret = pShm->ModeStatus.bIsErrConceal;
3289 break;
3290 }
3291 case E_HVD_GDATA_IS_SYNC_ON:
3292 {
3293 u32Ret = pShm->ModeStatus.bIsSyncOn;
3294 break;
3295 }
3296 case E_HVD_GDATA_IS_PLAYBACK_FINISH:
3297 {
3298 u32Ret = pShm->ModeStatus.bIsPlaybackFinish;
3299 break;
3300 }
3301 case E_HVD_GDATA_SYNC_MODE:
3302 {
3303 u32Ret = pShm->ModeStatus.u8SyncType;
3304 break;
3305 }
3306 case E_HVD_GDATA_SKIP_MODE:
3307 {
3308 u32Ret = pShm->ModeStatus.u8SkipMode;
3309 break;
3310 }
3311 case E_HVD_GDATA_DROP_MODE:
3312 {
3313 u32Ret = pShm->ModeStatus.u8DropMode;
3314 break;
3315 }
3316 case E_HVD_GDATA_DISPLAY_DURATION:
3317 {
3318 u32Ret = pShm->ModeStatus.s8DisplaySpeed;
3319 break;
3320 }
3321 case E_HVD_GDATA_FRC_MODE:
3322 {
3323 u32Ret = pShm->ModeStatus.u8FrcMode;
3324 break;
3325 }
3326 case E_HVD_GDATA_NEXT_PTS:
3327 {
3328 u32Ret = pShm->u32NextPTS;
3329 break;
3330 }
3331 case E_HVD_GDATA_DISP_Q_SIZE:
3332 {
3333 u32Ret = pShm->u16DispQSize;
3334 break;
3335 }
3336 case E_HVD_GDATA_DISP_Q_PTR:
3337 {
3338 u32Ret = (MS_U32) pHVDHalContext->_u16DispQPtr;
3339 break;
3340 }
3341 case E_HVD_GDATA_NEXT_DISP_FRM_INFO:
3342 {
3343 u32Ret = (MS_U32) _HVD_EX_GetNextDispFrame(u32Id);
3344 break;
3345 }
3346 case E_HVD_GDATA_REAL_FRAMERATE:
3347 {
3348 /// TODO:
3349 u32Ret=0; //pShm->u32RealFrameRate;
3350 break;
3351 }
3352 case E_HVD_GDATA_IS_ORI_INTERLACE_MODE:
3353 u32Ret=(MS_U32)pShm->DispInfo.u8IsOriginInterlace;
3354 break;
3355 case E_HVD_GDATA_FRM_PACKING_SEI_DATA:
3356 u32Ret=((MS_U32)(pShm->u32Frm_packing_arr_data_addr));
3357 break;
3358 case E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG:
3359 u32Ret=((MS_U32)(pShm->u8FrameMbsOnlyFlag));
3360 break;
3361 case E_HVD_GDATA_FW_STATUS_FLAG:
3362 u32Ret=((MS_U32)(pShm->u32FWStatusFlag));
3363 break;
3364
3365 // internal control
3366 case E_HVD_GDATA_IS_1ST_FRM_RDY:
3367 {
3368 u32Ret = pShm->bIs1stFrameRdy;
3369 break;
3370 }
3371 case E_HVD_GDATA_IS_I_FRM_FOUND:
3372 {
3373 u32Ret = pShm->bIsIFrmFound;
3374 break;
3375 }
3376 case E_HVD_GDATA_IS_SYNC_START:
3377 {
3378 u32Ret = pShm->bIsSyncStart;
3379 break;
3380 }
3381 case E_HVD_GDATA_IS_SYNC_REACH:
3382 {
3383 u32Ret = pShm->bIsSyncReach;
3384 break;
3385 }
3386 case E_HVD_GDATA_FW_VERSION_ID:
3387 {
3388 u32Ret = pShm->u32FWVersionID;
3389 break;
3390 }
3391 case E_HVD_GDATA_FW_IF_VERSION_ID:
3392 {
3393 u32Ret = pShm->u32FWIfVersionID;
3394 break;
3395 }
3396 case E_HVD_GDATA_BBU_Q_NUMB:
3397 {
3398 u32Ret = _HVD_EX_GetBBUQNumb(u32Id);
3399 break;
3400 }
3401 case E_HVD_GDATA_DEC_Q_NUMB:
3402 {
3403 u32Ret = pShm->u16DecQNumb;
3404 break;
3405 }
3406 case E_HVD_GDATA_DISP_Q_NUMB:
3407 {
3408 u32Ret = pShm->u16DispQNumb;
3409 break;
3410 }
3411 case E_HVD_GDATA_PTS_Q_NUMB:
3412 {
3413 u32Ret = _HVD_EX_GetPTSQNumb(u32Id);
3414 break;
3415 }
3416 case E_HVD_GDATA_FW_INIT_DONE:
3417 {
3418 u32Ret = pShm->bInitDone;
3419 break;
3420 }
3421 // debug
3422 case E_HVD_GDATA_SKIP_CNT:
3423 {
3424 u32Ret = pShm->u32SkipCnt;
3425 break;
3426 }
3427 case E_HVD_GDATA_GOP_CNT:
3428 {
3429 u32Ret = pShm->u32DropCnt;
3430 break;
3431 }
3432 case E_HVD_GDATA_DISP_CNT:
3433 {
3434 u32Ret = pShm->u32DispCnt;
3435 break;
3436 }
3437 case E_HVD_GDATA_DROP_CNT:
3438 {
3439 u32Ret = pShm->u32DropCnt;
3440 break;
3441 }
3442 case E_HVD_GDATA_DISP_STC:
3443 {
3444 u32Ret = pShm->u32DispSTC;
3445 break;
3446 }
3447 case E_HVD_GDATA_VSYNC_CNT:
3448 {
3449 u32Ret = pShm->u32VsyncCnt;
3450 break;
3451 }
3452 case E_HVD_GDATA_MAIN_LOOP_CNT:
3453 {
3454 u32Ret = pShm->u32MainLoopCnt;
3455 break;
3456 }
3457
3458 // AVC
3459 case E_HVD_GDATA_AVC_LEVEL_IDC:
3460 {
3461 u32Ret = pShm->u16AVC_SPS_LevelIDC;
3462 break;
3463 }
3464 case E_HVD_GDATA_AVC_LOW_DELAY:
3465 {
3466 u32Ret = pShm->u8AVC_SPS_LowDelayHrdFlag;
3467 break;
3468 }
3469 case E_HVD_GDATA_AVC_VUI_DISP_INFO:
3470 {
3471 u32Ret = _HVD_EX_GetVUIDispInfo(u32Id);
3472 break;
3473 }
3474 case E_HVD_GDATA_FW_FLUSH_STATUS:
3475 {
3476 u32Ret = (MS_U32) (pShm->u8FlushStatus);
3477 break;
3478 }
3479 case E_HVD_GDATA_FW_CODEC_TYPE:
3480 {
3481 u32Ret = pShm->u32CodecType;
3482 break;
3483 }
3484 case E_HVD_GDATA_FW_ES_BUF_STATUS:
3485 {
3486
3487 u32Ret = (MS_U32)pShm->u8ESBufStatus;
3488 break;
3489 }
3490
3491 // SRAM
3492
3493 // Mailbox
3494 case E_HVD_GDATA_FW_STATE: // HVD RISC MBOX 0 (esp. FW init done)
3495 {
3496 u32Ret = pShm->u32FwState;
3497 break;
3498 }
3499 case E_HVD_GDATA_IS_DISP_INFO_UNCOPYED:
3500 {
3501 u32Ret = pShm->bSpsChange;
3502 break;
3503 }
3504 case E_HVD_GDATA_IS_DISP_INFO_CHANGE: // HVD RISC MBOX 1 (rdy only)
3505 {
3506 u32Ret = pShm->bSpsChange;
3507 break;
3508 }
3509 case E_HVD_GDATA_HVD_ISR_STATUS: // HVD RISC MBOX 1 (value only)
3510 {
3511 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3512
3513 if ((pCtrl->HVDISRCtrl.u32IntCount != pShm->u32IntCount) && pShm->u32FwInfo) // fetch ISR status
3514 {
3515 u32Ret = pShm->u32FwInfo;
3516 pCtrl->HVDISRCtrl.u32IntCount = pShm->u32IntCount;
3517 }
3518 break;
3519 }
3520 case E_HVD_GDATA_IS_FRAME_SHOWED: // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable )
3521 {
3522 if (pShm->bIsTrigDisp) // not clear yet
3523 {
3524 u32Ret = FALSE;
3525 }
3526 else
3527 {
3528 u32Ret = TRUE;
3529 }
3530 break;
3531 }
3532 case E_HVD_GDATA_ES_READ_PTR:
3533 {
3534 u32Ret = _HVD_EX_GetESReadPtr(u32Id, FALSE);
3535 break;
3536 }
3537 case E_HVD_GDATA_ES_WRITE_PTR:
3538 {
3539 u32Ret = _HVD_EX_GetESWritePtr(u32Id);
3540 break;
3541 }
3542 case E_HVD_GDATA_BBU_READ_PTR:
3543 {
3544 u32Ret = _HVD_EX_GetBBUReadptr(u32Id);
3545 break;
3546 }
3547 case E_HVD_GDATA_BBU_WRITE_PTR:
3548 {
3549 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3550 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3551 {
3552 u32Ret = pHVDHalContext->u32VP8BBUWptr;
3553 }
3554 else
3555 {
3556 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
3557 }
3558 break;
3559 }
3560 case E_HVD_GDATA_BBU_WRITE_PTR_FIRED:
3561 {
3562 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3563
3564 u32Ret = pCtrl->u32BBUWptr_Fired;
3565
3566 break;
3567 }
3568 case E_HVD_GDATA_VPU_PC_CNT:
3569 {
3570 u32Ret = _HVD_EX_GetPC();
3571 break;
3572 }
3573 case E_HVD_GDATA_ES_QUANTITY:
3574 {
3575 u32Ret=_HVD_EX_GetESQuantity(u32Id);
3576 break;
3577 }
3578
3579
3580 // FW def
3581 case E_HVD_GDATA_FW_MAX_DUMMY_FIFO: // AVC: 256Bytes AVS: 2kB RM:???
3582 u32Ret = HVD_MAX3(HVD_FW_AVC_DUMMY_FIFO, HVD_FW_AVS_DUMMY_FIFO, HVD_FW_RM_DUMMY_FIFO);
3583 break;
3584
3585 case E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY:
3586 u32Ret = HVD_FW_AVC_MAX_VIDEO_DELAY;
3587 break;
3588 case E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY:
3589 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH;
3590 break;
3591 case E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB:
3592 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
3593 break;
3594 case E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB:
3595 u32Ret = MAX_PTS_TABLE_SIZE;
3596 break;
3597 case E_HVD_GDATA_FW_DUMMY_WRITE_ADDR:
3598 u32Ret = pShm->u32HVD_DUMMY_WRITE_ADDR;
3599 break;
3600 case E_HVD_GDATA_FW_DS_BUF_ADDR:
3601 u32Ret = pShm->u32HVD_DYNAMIC_SCALING_ADDR;
3602 break;
3603 case E_HVD_GDATA_FW_DS_BUF_SIZE:
3604 //u32Ret = HVD_DYNAMIC_SCALING_SIZE;
3605 // ----------------------- yi-chun.pan: for Dynamic Scaling 3k/6k issue ----------20111213---
3606 // ----------------------- modify DRV and AP(SN/MM) first, and then update fw --------------
3607 u32Ret = (1024 * 3);
3608 break;
3609 case E_HVD_GDATA_FW_DS_VECTOR_DEPTH:
3610 u32Ret = HVD_DYNAMIC_SCALING_DEPTH;
3611 break;
3612 case E_HVD_GDATA_FW_DS_INFO_ADDR:
3613 u32Ret = pShm->u32HVD_SCALER_INFO_ADDR;
3614 break;
3615 case E_HVD_GDATA_FW_DS_IS_ENABLED:
3616 {
3617 if (pShm->bDSIsRunning)
3618 {
3619 u32Ret = TRUE;
3620 }
3621 else
3622 {
3623 u32Ret = FALSE;
3624 }
3625 break;
3626 }
3627 case E_HVD_GDATA_TYPE_IS_LEAST_DISPQ_SIZE:
3628 u32Ret = ((MS_U32)(pShm->bIsLeastDispQSize));
3629 break;
3630 case E_HVD_GDATA_FIELD_PIC_FLAG:
3631 u32Ret = ((MS_U32)(pShm->u8FieldPicFlag));
3632 break;
3633 case E_HVD_GDATA_FW_VSYNC_BRIDGE_ADDR:
3634 u32Ret = pShm->u32VSYNC_BRIGE_SHM_ADDR;
3635 break;
3636 case E_HVD_GDATA_TS_SEAMLESS_STATUS:
3637 u32Ret = pShm->u32SeamlessTSStatus;
3638 break;
3639 case E_HVD_GDATA_HVD_HW_MAX_PIXEL:
3640 u32Ret = (MS_U32)(((MS_U64)HVD_HW_MAX_PIXEL)/1000);
3641 break;
3642 default:
3643 break;
3644 }
3645 return u32Ret;
3646 }
3647
HAL_HVD_EX_SetCmd(MS_U32 u32Id,HVD_User_Cmd eUsrCmd,MS_U32 u32CmdArg)3648 HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg)
3649 {
3650 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
3651 MS_U32 u32Cmd = (MS_U32) eUsrCmd;
3652 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3653
3654 _HAL_HVD_Entry();
3655
3656 // check if old SVD cmds
3657 if (u32Cmd < E_HVD_CMD_SVD_BASE)
3658 {
3659 HVD_EX_MSG_ERR("Old SVD FW cmd(%lx %lx) used in HVD.\n", u32Cmd, u32CmdArg);
3660
3661 _HAL_HVD_Return(E_HVD_RETURN_INVALID_PARAMETER);
3662 }
3663
3664 if(u32Cmd == E_HVD_CMD_ENABLE_DISP_OUTSIDE)
3665 {
3666 pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide = (MS_BOOL)u32CmdArg;
3667 }
3668
3669 #if HVD_ENABLE_MVC
3670 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
3671 {
3672 if (HAL_HVD_EX_CheckMVCID(u32Id) && u32Cmd == E_HVD_CMD_FLUSH)
3673 {
3674 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
3675 }
3676 }
3677 #endif
3678
3679 HVD_EX_MSG_DBG("cmd=0x%lx, arg=0x%lx\n", u32Cmd, u32CmdArg);
3680
3681 eRet = _HVD_EX_SendCmd(u32Id, u32Cmd, u32CmdArg);
3682
3683 _HAL_HVD_Return(eRet);
3684 }
3685
HAL_HVD_EX_DeInit(MS_U32 u32Id)3686 HVD_Return HAL_HVD_EX_DeInit(MS_U32 u32Id)
3687 {
3688 HVD_Return eRet = E_HVD_RETURN_FAIL;
3689 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3690 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3691 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
3692
3693 #if HVD_ENABLE_TIME_MEASURE
3694 MS_U32 ExitTimeCnt = 0;
3695 ExitTimeCnt = HVD_GetSysTime_ms();
3696 #endif
3697
3698 pCtrl->MemMap.u32CodeBufVAddr = MS_PA2KSEG1((MS_U32)pCtrl->MemMap.u32CodeBufAddr);
3699
3700 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_PAUSE, 0);
3701
3702 if (E_HVD_RETURN_SUCCESS != eRet)
3703 {
3704 HVD_EX_MSG_ERR("HVD fail to PAUSE %d\n", eRet);
3705 }
3706
3707 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_STOP, 0);
3708
3709 if (E_HVD_RETURN_SUCCESS != eRet)
3710 {
3711 HVD_EX_MSG_ERR("HVD fail to STOP %d\n", eRet);
3712 }
3713
3714 // check FW state to make sure it's STOP DONE
3715 while (E_HVD_FW_STOP_DONE != (HVD_FW_State) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_STATE))
3716 {
3717 if (HVD_GetSysTime_ms() > u32Timeout)
3718 {
3719 HVD_EX_MSG_ERR("FW stop timeout, pc = 0x%lx\n", HAL_VPU_EX_GetProgCnt());
3720
3721 //return E_HVD_RETURN_TIMEOUT;
3722 eRet = E_HVD_RETURN_TIMEOUT;
3723 break;
3724 }
3725 }
3726
3727 VPU_EX_FWCodeCfg fwCfg;
3728 VPU_EX_TaskInfo taskInfo;
3729 VPU_EX_NDecInitPara nDecInitPara;
3730
3731 nDecInitPara.pFWCodeCfg = &fwCfg;
3732 nDecInitPara.pTaskInfo = &taskInfo;
3733
3734 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
3735 fwCfg.u8SrcType = E_HVD_FW_INPUT_SOURCE_NONE;
3736
3737 taskInfo.u32Id = u32Id;
3738 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
3739 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
3740
3741 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
3742 {
3743 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
3744 }
3745 else
3746 {
3747 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
3748 }
3749
3750 if(HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara) != TRUE)
3751 {
3752 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
3753 }
3754
3755 /* clear es buffer */
3756 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
3757 {
3758 //printf("Clear ES buffer\n");
3759
3760 memset((void *) pCtrl->MemMap.u32BitstreamBufVAddr, 0, MIN(128, pCtrl->MemMap.u32BitstreamBufSize));
3761 }
3762
3763 //_HAL_HVD_MutexDelete();
3764
3765 #if HVD_ENABLE_TIME_MEASURE
3766 HVD_EX_MSG_DBG("HVD Stop Time(Wait FW):%d\n", HVD_GetSysTime_ms() - ExitTimeCnt);
3767 #endif
3768
3769 pHVDHalContext->_stHVDStream[u8Idx].bUsed = FALSE;
3770
3771 // reset bbu wptr
3772 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
3773 {
3774 if(TRUE == HAL_VPU_EX_HVDInUsed())
3775 {
3776 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))//apple
3777 {
3778 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
3779 pHVDHalContext->u32VP8BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
3780 }
3781 else
3782 {
3783 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
3784 {
3785 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
3786 }
3787 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
3788 }
3789 }
3790 else
3791 {
3792 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
3793 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
3794 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
3795 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3796 {
3797 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
3798 {
3799 _HVD_EX_ResetMainSubBBUWptr(u32Id);
3800 }
3801 }
3802 else
3803 {
3804 _HVD_EX_ResetMainSubBBUWptr(u32Id);
3805 }
3806 }
3807 }
3808
3809 _stHVDPreSet[u8Idx].bColocateBBUMode = FALSE;
3810
3811 HVD_EX_MSG_DBG("success\n");
3812
3813 return eRet;
3814 }
3815
HAL_HVD_EX_PushPacket(MS_U32 u32Id,HVD_BBU_Info * pInfo)3816 HVD_Return HAL_HVD_EX_PushPacket(MS_U32 u32Id, HVD_BBU_Info *pInfo)
3817 {
3818 HVD_Return eRet = E_HVD_RETURN_UNSUPPORTED;
3819 MS_U32 u32Addr = 0;
3820 HVD_EX_Drv_Ctrl *pCtrl = NULL;
3821 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3822
3823 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3824
3825 //if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8 PTS table is not ready yet
3826 {
3827 eRet = _HVD_EX_UpdatePTSTable(u32Id, pInfo);
3828
3829 if (E_HVD_RETURN_SUCCESS != eRet)
3830 {
3831 return eRet;
3832 }
3833 }
3834
3835 //printf(">>> halHVD pts,idH = %lu, %lu\n", pInfo->u32TimeStamp, pInfo->u32ID_H); //STS input
3836
3837 //T9: for 128 bit memory. BBU need to get 2 entry at a time.
3838 if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3839 {
3840 eRet = _HVD_EX_UpdateESWptr(u32Id, 0, 0);
3841
3842 if (E_HVD_RETURN_SUCCESS != eRet)
3843 {
3844 return eRet;
3845 }
3846 }
3847
3848 u32Addr = pInfo->u32Staddr;
3849
3850 if (pInfo->bRVBrokenPacket)
3851 {
3852 u32Addr = pInfo->u32Staddr | BIT(HVD_RV_BROKENBYUS_BIT);
3853 }
3854
3855 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
3856 {
3857 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, pInfo->u32Length, pInfo->u32Staddr2, pInfo->u32Length2);
3858 }
3859 else
3860 {
3861 eRet = _HVD_EX_UpdateESWptr(u32Id, u32Addr, pInfo->u32Length);
3862 }
3863
3864 if (E_HVD_RETURN_SUCCESS != eRet)
3865 {
3866 return eRet;
3867 }
3868
3869 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3870 {
3871 //eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, 0, 0, 0, 0);
3872 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, 0, pInfo->u32Staddr2, 0);
3873
3874 if (E_HVD_RETURN_SUCCESS != eRet)
3875 {
3876 return eRet;
3877 }
3878 }
3879
3880 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt += pInfo->u32Length;
3881
3882 // do not add local pointer
3883 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
3884 {
3885 MS_U32 u32PacketStAddr = pInfo->u32Staddr + pCtrl->MemMap.u32BitstreamBufAddr;
3886
3887 if (!((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStAddr) &&
3888 (u32PacketStAddr <
3889 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
3890 {
3891 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
3892 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
3893 }
3894 else
3895 {
3896 //null packet
3897 pCtrl->LastNal.u32NalAddr = pInfo->u32OriPktAddr;
3898 pCtrl->LastNal.u32NalSize = 0;
3899 }
3900 }
3901 else
3902 {
3903 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
3904 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
3905 }
3906
3907 pCtrl->LastNal.bRVBrokenPacket = pInfo->bRVBrokenPacket;
3908 pCtrl->u32BBUPacketCnt++;
3909
3910 return eRet;
3911 }
3912
HAL_HVD_EX_EnableISR(MS_U32 u32Id,MS_BOOL bEnable)3913 void HAL_HVD_EX_EnableISR(MS_U32 u32Id, MS_BOOL bEnable)
3914 {
3915 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3916 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
3917
3918 if (bEnable)
3919 {
3920 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK);
3921 }
3922 else
3923 {
3924 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK);
3925 }
3926 }
3927
HAL_HVD_EX_SetForceISR(MS_U32 u32Id,MS_BOOL bEnable)3928 void HAL_HVD_EX_SetForceISR(MS_U32 u32Id, MS_BOOL bEnable)
3929 {
3930 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3931 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
3932
3933 if (bEnable)
3934 {
3935 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_FORCE, HVD_REG_RISC_ISR_FORCE);
3936 }
3937 else
3938 {
3939 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_FORCE);
3940 }
3941 }
3942
HAL_HVD_EX_SetClearISR(MS_U32 u32Id)3943 void HAL_HVD_EX_SetClearISR(MS_U32 u32Id)
3944 {
3945 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3946 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
3947
3948 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_CLR, HVD_REG_RISC_ISR_CLR);
3949 }
3950
HAL_HVD_EX_IsISROccured(MS_U32 u32Id)3951 MS_BOOL HAL_HVD_EX_IsISROccured(MS_U32 u32Id)
3952 {
3953 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3954 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
3955
3956 return (MS_BOOL) (_HVD_Read2Byte(HVD_REG_RISC_MBOX_RDY(u32RB)) & HVD_REG_RISC_ISR_VALID);
3957 }
3958
HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)3959 MS_BOOL HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)
3960 {
3961 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3962 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
3963
3964 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK)
3965 {
3966 return FALSE;
3967 }
3968 else
3969 {
3970 return TRUE;
3971 }
3972 }
3973
HAL_HVD_EX_IsAlive(MS_U32 u32Id)3974 MS_BOOL HAL_HVD_EX_IsAlive(MS_U32 u32Id)
3975 {
3976 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3977
3978 if (pCtrl)
3979 {
3980 if ((pCtrl->LivingStatus.u32DecCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DECODE_CNT)) &&
3981 (pCtrl->LivingStatus.u32SkipCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_SKIP_CNT)) &&
3982 (pCtrl->LivingStatus.u32IdleCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_VPU_IDLE_CNT)) &&
3983 (pCtrl->LivingStatus.u32MainLoopCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_MAIN_LOOP_CNT)))
3984 {
3985 return FALSE;
3986 }
3987 else
3988 {
3989 return TRUE;
3990 }
3991 }
3992 else
3993 {
3994 return FALSE;
3995 }
3996 }
3997
HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)3998 MS_BOOL HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)
3999 {
4000 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4001 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4002 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4003
4004 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
4005 {
4006 HAL_HVD_EX_ReadMemory();
4007
4008 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = pShm->u32PTStableByteCnt;
4009 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = _HVD_EX_GetPTSTableWptr(u32Id);
4010
4011 HVD_EX_MSG_DBG("PTS table: WptrAddr:%lx RptrAddr:%lx ByteCnt:%lx PreWptr:%lx\n",
4012 pShm->u32PTStableWptrAddr, pShm->u32PTStableRptrAddr, pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt, pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
4013 }
4014
4015 return TRUE;
4016 }
4017
HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)4018 MS_BOOL HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)
4019 {
4020 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4021 HVD_EX_Drv_Ctrl *pCtrl = NULL;
4022 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4023 MS_U32 u32Data;
4024 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4025
4026 memset(&pShm->DecoFrmInfo, 0, sizeof(HVD_Frm_Information));
4027
4028 HAL_HVD_EX_FlushMemory();
4029 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
4030 {
4031 u32Data = _HVD_EX_GetESReadPtr(u32Id, FALSE);
4032 pCtrl->LastNal.u32NalAddr = u32Data;
4033 pCtrl->LastNal.u32NalSize = 0;
4034 }
4035 return TRUE;
4036 }
4037
HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)4038 void HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)
4039 {
4040 if (bEnable)
4041 {
4042 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_VD_MHEG5, REG_TOP_UART_SEL_0_MASK);
4043 }
4044 else
4045 {
4046 #if defined (__aeon__)
4047 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
4048 #else // defined (__mips__)
4049 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_PIU_0, REG_TOP_UART_SEL_0_MASK);
4050 #endif
4051 }
4052 }
4053
HAL_HVD_EX_GetData_Dbg(MS_VIRT u32Addr)4054 MS_U32 HAL_HVD_EX_GetData_Dbg(MS_VIRT u32Addr)
4055 {
4056 return 0;
4057 }
4058
HAL_HVD_EX_SetData_Dbg(MS_VIRT u32Addr,MS_U32 u32Data)4059 void HAL_HVD_EX_SetData_Dbg(MS_VIRT u32Addr, MS_U32 u32Data)
4060 {
4061 return;
4062 }
4063
HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)4064 MS_U16 HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)
4065 {
4066 //if( u16Clock == 0 )
4067 return 216; //140;
4068 //if( )
4069 }
4070
HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)4071 void HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)
4072 {
4073 MS_BOOL bBitMIU1 = FALSE;
4074 MS_BOOL bCodeMIU1 = FALSE;
4075 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4076 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4077 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4078 MS_U32 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR;
4079
4080 #if HVD_ENABLE_MVC
4081 if(HAL_HVD_EX_CheckMVCID(u32Id))
4082 {
4083 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
4084 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
4085 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
4086 {
4087 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
4088 }
4089 }
4090 #endif /// HVD_ENABLE_MVC
4091
4092 if (pCtrl->MemMap.u32CodeBufAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
4093 {
4094 bCodeMIU1 = TRUE;
4095 }
4096
4097 if (pCtrl->MemMap.u32BitstreamBufAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
4098 {
4099 bBitMIU1 = TRUE;
4100 }
4101
4102 if (bBitMIU1 != bCodeMIU1)
4103 {
4104 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
4105 BDMA_Result bdmaRlt;
4106 MS_U32 u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
4107
4108 u32DstAdd = pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
4109 u32SrcAdd = pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR;
4110 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
4111
4112 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
4113
4114 if (E_BDMA_OK != bdmaRlt)
4115 {
4116 HVD_EX_MSG_ERR("MDrv_BDMA_MemCopy fail ret=%x!\n", bdmaRlt);
4117 }
4118 #else
4119 MS_U32 u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
4120
4121 u32DstAdd = pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
4122 u32SrcAdd = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR);
4123 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
4124
4125 HVD_memcpy(u32DstAdd, u32SrcAdd, u32tabsize);
4126 #endif
4127 }
4128
4129 //HVD_EX_MSG_DBG("%lu st:%lx size:%lx BBU: %lu\n", pCtrl->u32BBUPacketCnt, pCtrl->LastNal.u32NalAddr, pCtrl->LastNal.u32NalSize, _stHVDStream[u8Idx].u32BBUWptr);
4130
4131 HAL_HVD_EX_FlushMemory();
4132
4133 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4134 {
4135 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->u32VP8BBUWptr));
4136 pCtrl->u32BBUWptr_Fired = pHVDHalContext->u32VP8BBUWptr;
4137 }
4138 else
4139 {
4140 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr));
4141
4142 pCtrl->u32BBUWptr_Fired = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
4143 }
4144 }
4145
HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)4146 void HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)
4147 {
4148 if (bEnable)
4149 {
4150 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
4151 _HVD_WriteWordMask(REG_TOP_MVD2, 0, TOP_CKG_MHVD2_DIS);
4152 }
4153 else
4154 {
4155 _HVD_WriteWordMask(REG_TOP_MVD, TOP_CKG_MHVD_DIS, TOP_CKG_MHVD_DIS);
4156 _HVD_WriteWordMask(REG_TOP_MVD2, TOP_CKG_MHVD2_DIS, TOP_CKG_MHVD2_DIS);
4157 }
4158 }
4159
HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)4160 void HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)
4161 {
4162 MS_U32 tmp1 = 0;
4163 MS_U32 tmp2 = 0;
4164 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4165
4166 HAL_HVD_EX_ReadMemory();
4167
4168 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_MBOX, &tmp1);
4169 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_ARG_MBOX, &tmp2);
4170
4171 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
4172 {
4173 MS_U32 u32Tmp = u32UartCtrl;
4174
4175 HVD_EX_MSG_DBG("\n");
4176 u32UartCtrl = 0; // turn off debug message to prevent other function prints
4177 printf("\tSystime=%lu, FWVersionID=0x%lx, FwState=0x%lx, ErrCode=0x%lx, ProgCnt=0x%lx\n",
4178 HVD_GetSysTime_ms(), pShm->u32FWVersionID, pShm->u32FwState, (MS_U32) pShm->u16ErrCode, HAL_VPU_EX_GetProgCnt());
4179
4180 printf("\tTime: DispSTC=%lu, DispT=%lu, DecT=%lu, CurrentPts=%lu, Last Cmd=0x%lx, Arg=0x%lx, Rdy1=0x%lx, Rdy2=0x%lx\n",
4181 pShm->u32DispSTC, pShm->DispFrmInfo.u32TimeStamp,
4182 pShm->DecoFrmInfo.u32TimeStamp, pShm->u32CurrentPts, tmp1, tmp2,
4183 (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX), (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX));
4184
4185 printf("\tFlag: InitDone=%d, SpsChange=%d, IsIFrmFound=%d, 1stFrmRdy=%d, SyncStart=%d, SyncReach=%d\n",
4186 pShm->bInitDone, pShm->bSpsChange, pShm->bIsIFrmFound,
4187 pShm->bIs1stFrameRdy, pShm->bIsSyncStart, pShm->bIsSyncReach);
4188
4189 printf("\tQueue: BBUQNumb=%lu, DecQNumb=%d, DispQNumb=%d, ESR=%lu, ESRfromFW=%lu, ESW=%lu, ESLevel=%lu\n",
4190 _HVD_EX_GetBBUQNumb(u32Id), pShm->u16DecQNumb, pShm->u16DispQNumb,
4191 _HVD_EX_GetESReadPtr(u32Id, TRUE), pShm->u32ESReadPtr, _HVD_EX_GetESWritePtr(u32Id),
4192 _HVD_EX_GetESLevel(u32Id));
4193
4194 printf("\tCounter: DecodeCnt=%lu, DispCnt=%lu, DataErrCnt=%lu, DecErrCnt=%lu, SkipCnt=%lu, DropCnt=%lu, idle=%lu, MainLoopCnt=%lu, VsyncCnt=%lu\n",
4195 pShm->u32DecodeCnt, pShm->u32DispCnt, pShm->u32DataErrCnt,
4196 pShm->u32DecErrCnt, pShm->u32SkipCnt, pShm->u32DropCnt,
4197 pShm->u32VPUIdleCnt, pShm->u32MainLoopCnt, pShm->u32VsyncCnt);
4198 printf
4199 ("\tMode: ShowErr=%d, RepLastField=%d, SyncOn=%d, FileEnd=%d, Skip=%d, Drop=%d, DispSpeed=%d, FRC=%d, BlueScreen=%d, FreezeImg=%d, 1Field=%d\n",
4200 pShm->ModeStatus.bIsShowErrFrm, pShm->ModeStatus.bIsRepeatLastField,
4201 pShm->ModeStatus.bIsSyncOn, pShm->ModeStatus.bIsPlaybackFinish,
4202 pShm->ModeStatus.u8SkipMode, pShm->ModeStatus.u8DropMode,
4203 pShm->ModeStatus.s8DisplaySpeed, pShm->ModeStatus.u8FrcMode,
4204 pShm->ModeStatus.bIsBlueScreen, pShm->ModeStatus.bIsFreezeImg,
4205 pShm->ModeStatus.bShowOneField);
4206
4207 u32UartCtrl = u32Tmp; // recover debug level
4208 }
4209 }
4210
HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32Idx,MS_U32 * u32NalOffset,MS_U32 * u32NalSize)4211 void HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32Idx, MS_U32 *u32NalOffset, MS_U32 *u32NalSize)
4212 {
4213 MS_U8 *u32Addr = NULL;
4214 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4215 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4216
4217 if (u32Idx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
4218 {
4219 return;
4220 }
4221
4222 u32Addr = (MS_U8 *)(MsOS_PA2KSEG1(pDrvCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU_DRAM_ST_ADDR + (u32Idx << 3)));
4223
4224 *u32NalSize = *(u32Addr + 2) & 0x1f;
4225 *u32NalSize <<= 8;
4226 *u32NalSize |= *(u32Addr + 1) & 0xff;
4227 *u32NalSize <<= 8;
4228 *u32NalSize |= *(u32Addr) & 0xff;
4229
4230 *u32NalOffset = ((MS_U32) (*(u32Addr + 2) & 0xe0)) >> 5;
4231 *u32NalOffset |= ((MS_U32) (*(u32Addr + 3) & 0xff)) << 3;
4232 *u32NalOffset |= ((MS_U32) (*(u32Addr + 4) & 0xff)) << 11;
4233 *u32NalOffset |= ((MS_U32) (*(u32Addr + 5) & 0xff)) << 19;
4234 }
4235
HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32StartIdx,MS_U32 u32EndIdx,MS_BOOL bShowEmptyEntry)4236 void HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32StartIdx, MS_U32 u32EndIdx, MS_BOOL bShowEmptyEntry)
4237 {
4238 MS_U32 u32CurIdx = 0;
4239 MS_BOOL bFinished = FALSE;
4240 MS_U32 u32NalOffset = 0;
4241 MS_U32 u32NalSize = 0;
4242 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4243
4244 if ((u32StartIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum) || (u32EndIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum))
4245 {
4246 return;
4247 }
4248
4249 u32CurIdx = u32StartIdx;
4250
4251 do
4252 {
4253 if (u32CurIdx == u32EndIdx)
4254 {
4255 bFinished = TRUE;
4256 }
4257
4258 HAL_HVD_EX_GetBBUEntry(u32Id, pDrvCtrl, u32CurIdx, &u32NalOffset, &u32NalSize);
4259
4260 if ((bShowEmptyEntry == FALSE) || (bShowEmptyEntry && (u32NalOffset == 0) && (u32NalSize == 0)))
4261 {
4262 HVD_EX_MSG_DBG("HVD BBU Entry: Idx:%lu Offset:%lx Size:%lx\n", u32CurIdx, u32NalOffset, u32NalSize);
4263 }
4264
4265 u32CurIdx++;
4266
4267 if (u32CurIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
4268 {
4269 u32CurIdx %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
4270 }
4271 } while (bFinished == TRUE);
4272 }
4273
HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)4274 void HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)
4275 {
4276 MS_U32 i = 0;
4277 MS_U32 value = 0;
4278
4279 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
4280 {
4281 HVD_EX_MSG_DBG("\n");
4282
4283 for (i = 0; i <= u32Num; i++)
4284 {
4285 _HVD_Write2Byte(HVD_REG_DEBUG_SEL, i);
4286 value = _HVD_Read2Byte(HVD_REG_DEBUG_DAT_L);
4287 value |= ((MS_U32) _HVD_Read2Byte(HVD_REG_DEBUG_DAT_H)) << 16;
4288
4289 if (value == 0)
4290 {
4291 break;
4292 }
4293
4294 printf(" %08lx", value);
4295
4296 if (((i % 8) + 1) == 8)
4297 {
4298 printf(" |%lu\n", i + 1);
4299 }
4300 }
4301
4302 printf("\nHVD Dump HW status End: total number:%lu\n", i);
4303 }
4304 }
4305
HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl * pDrvCtrl,HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)4306 void HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl *pDrvCtrl, HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)
4307 {
4308 if (pDrvCtrl)
4309 {
4310 pDrvCtrl->Settings.u32MiuBurstLevel = (MS_U32) eMiuBurstCntCtrl;
4311 }
4312 }
4313
4314 #if HVD_ENABLE_MVC
HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)4315 MS_BOOL HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)
4316 {
4317 return ( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id) );
4318 }
4319
HAL_HVD_EX_GetView(MS_U32 u32Id)4320 VDEC_EX_View HAL_HVD_EX_GetView(MS_U32 u32Id)
4321 {
4322 if( (0xFF & (u32Id >> 8)) == 0x10)
4323 return E_VDEC_EX_MAIN_VIEW;
4324 else
4325 return E_VDEC_EX_SUB_VIEW;
4326 }
4327 #endif ///HVD_ENABLE_MVC
4328
HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id)4329 void HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id) //// For MVC
4330 {
4331 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_QUART_PIXEL, TRUE);
4332 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_DBF, TRUE);
4333 return;
4334 }
4335
4336
HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id,MS_U16 u16HSize,MS_U16 u16VSize,MS_U32 u32FrmRate)4337 MS_BOOL HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id, MS_U16 u16HSize, MS_U16 u16VSize, MS_U32 u32FrmRate)
4338 {
4339 HVD_EX_MSG_DBG("%s w:%d, h:%d, fr:%ld, MAX:%lld\n", __FUNCTION__,
4340 u16HSize, u16VSize, u32FrmRate, HVD_HW_MAX_PIXEL);
4341 return (((MS_U64)u16HSize*(MS_U64)u16VSize*(MS_U64)u32FrmRate) <= HVD_HW_MAX_PIXEL);
4342 }
4343
HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)4344 MS_U32 HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)
4345 {
4346 #if 1
4347 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4348 MS_U16 u16QNum = pShm->u16DispQNumb;
4349 MS_U16 u16QPtr = pShm->u16DispQPtr;
4350 // MS_U16 u16QSize = pShm->u16DispQSize;
4351 //static volatile HVD_Frm_Information *pHvdFrm = NULL;
4352 MS_U32 u32DispQNum = 0;
4353 #if HVD_ENABLE_MVC
4354 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4355
4356 if(bMVC)
4357 {
4358 #if 0
4359 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT*3)
4360 {
4361 u16QNum = HVD_DISPQ_PREFETCH_COUNT*3;
4362 }
4363 #endif
4364
4365 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
4366 //search the next frame to display
4367 while (u16QNum > 0)
4368 {
4369 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
4370 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
4371 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
4372
4373 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
4374 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
4375 {
4376 /// For MVC. Output views after the pair of (base and depend) views were decoded.
4377 /// Check the depned view was initial when Output the base view.
4378 if((u16QPtr%2) == 0)
4379 {
4380 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
4381 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
4382 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
4383 {
4384 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
4385 ///printf("Return NULL.\n");
4386 continue;
4387 }
4388 }
4389 u32DispQNum++;
4390 }
4391
4392 u16QNum--;
4393 //go to next frame in the dispQ
4394 u16QPtr++;
4395
4396 if (u16QPtr >= pShm->u16DispQSize)
4397 {
4398 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
4399 }
4400 }
4401 }
4402 else
4403 #endif ///HVD_ENABLE_MVC
4404 {
4405 #if 0
4406 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT)
4407 {
4408 u16QNum = HVD_DISPQ_PREFETCH_COUNT;
4409 }
4410 #endif
4411 // printf("Q: %d %d %d\n", u16QNum, u16QPtr, u16QSize);
4412 //search the next frame to display
4413 while (u16QNum != 0)
4414 {
4415 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
4416
4417 // printf("Q2[%d]: %ld\n", u16QPtr, pShm->DispQueue[u16QPtr].u32Status);
4418 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
4419 {
4420 u32DispQNum++;
4421 }
4422
4423 u16QNum--;
4424 //go to next frame in the dispQ
4425 u16QPtr++;
4426
4427 if (u16QPtr == pShm->u16DispQSize)
4428 {
4429 u16QPtr = 0; //wrap to the begin
4430 }
4431 }
4432 }
4433
4434 //printf("dispQnum = %ld, pShm->u16DispQNumb = %d\n", u32DispQNum, pShm->u16DispQNumb);
4435 return u32DispQNum;
4436 #else
4437 HVD_ShareMem *pShm = (HVD_ShareMem *) _HVD_EX_GetShmAddr(u32Id);
4438 return pShm->u16DispQNumb;
4439 #endif
4440 }
4441
HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id,MS_U32 u32ModeFlag)4442 void HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id, MS_U32 u32ModeFlag)
4443 {
4444 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4445 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase =
4446 ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC) ? REG_EVD_BASE : REG_HVD_BASE;
4447 }
4448
4449 #if SUPPORT_EVD
HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable)4450 void HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable)
4451 {
4452 if (bEnable)
4453 {
4454 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, ~TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
4455 _HVD_WriteWordMask(REG_TOP_CKG_EVD, ~TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
4456 }
4457 else
4458 {
4459 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
4460 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
4461 }
4462
4463 switch (pHVDHalContext->u32EVDClockType)
4464 {
4465 case 345:
4466 {
4467 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_345MHZ, TOP_CKG_EVD_PPU_MASK);
4468 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_345MHZ, TOP_CKG_EVD_MASK);
4469 break;
4470 }
4471 case 320:
4472 {
4473 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_320MHZ, TOP_CKG_EVD_PPU_MASK);
4474 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_320MHZ, TOP_CKG_EVD_MASK);
4475 break;
4476 }
4477 case 288:
4478 {
4479 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_288MHZ, TOP_CKG_EVD_PPU_MASK);
4480 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_288MHZ, TOP_CKG_EVD_MASK);
4481 break;
4482 }
4483 case 240:
4484 {
4485 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_240MHZ, TOP_CKG_EVD_PPU_MASK);
4486 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_240MHZ, TOP_CKG_EVD_MASK);
4487 break;
4488 }
4489 case 216:
4490 {
4491 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_216MHZ, TOP_CKG_EVD_PPU_MASK);
4492 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_216MHZ, TOP_CKG_EVD_MASK);
4493 break;
4494 }
4495 case 192:
4496 {
4497 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_192MHZ, TOP_CKG_EVD_PPU_MASK);
4498 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_192MHZ, TOP_CKG_EVD_MASK);
4499 break;
4500 }
4501 case 160:
4502 {
4503 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_160MHZ, TOP_CKG_EVD_PPU_MASK);
4504 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_160MHZ, TOP_CKG_EVD_MASK);
4505 break;
4506 }
4507 default:
4508 {
4509 _HVD_WriteByteMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_345MHZ, TOP_CKG_EVD_PPU_MASK);
4510 _HVD_WriteByteMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_345MHZ, TOP_CKG_EVD_MASK);
4511 break;
4512 }
4513 }
4514
4515 return;
4516 }
4517
HAL_EVD_EX_DeinitHW(void)4518 static MS_BOOL HAL_EVD_EX_DeinitHW(void)
4519 {
4520 MS_U16 u16Timeout = 1000;
4521
4522 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
4523
4524 while (u16Timeout)
4525 {
4526 if ((_HVD_Read2Byte(EVD_REG_RESET) & (EVD_REG_RESET_SWRST_FIN)) == (EVD_REG_RESET_SWRST_FIN))
4527 {
4528 break;
4529 }
4530 u16Timeout--;
4531 }
4532
4533 HAL_EVD_EX_PowerCtrl(FALSE);
4534
4535 return TRUE;
4536 }
4537 #endif
HAL_HVD_EX_GetSupport2ndMVOPInterface(void)4538 MS_BOOL HAL_HVD_EX_GetSupport2ndMVOPInterface(void)
4539 {
4540 return TRUE;
4541 }
HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id)4542 void HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id)
4543 {
4544 _HVD_EX_SetBufferAddr(u32Id);
4545 }
HAL_HVD_EX_BBU_Proc(MS_U32 u32Id)4546 void HAL_HVD_EX_BBU_Proc(MS_U32 u32Id)
4547 {
4548
4549 }
4550
4551
HAL_HVD_EX_BBU_StopProc(MS_U32 u32Id)4552 void HAL_HVD_EX_BBU_StopProc(MS_U32 u32Id)
4553 {
4554
4555 }
4556
4557 #endif
4558
4559