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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _FW_HVD_IF_H_ 96 #define _FW_HVD_IF_H_ 97 98 //------------------------------------------------------------------------------------------------- 99 // Hardware Capability 100 //------------------------------------------------------------------------------------------------- 101 #define HVD_FW_VERSION 0x00001365 102 #define HVD_FW_IF_VERSION 0x00730155 103 104 //------------------------------------------------------------------------------------------------- 105 // Macro and Define 106 //------------------------------------------------------------------------------------------------- 107 // TOP 108 //#if (!(defined( MSOS_TYPE_NOS) ||defined( MSOS_TYPE_ECOS) || defined( MSOS_TYPE_LINUX))) 109 #if (!defined( _MS_TYPES_H_) && (!defined(_DRVHVD_COMMON_H_))) 110 typedef unsigned char MS_BOOL; // 1 byte 111 /// data type unsigned char, data length 1 byte 112 typedef unsigned char MS_U8; // 1 byte 113 /// data type unsigned short, data length 2 byte 114 typedef unsigned short MS_U16; // 2 bytes 115 /// data type unsigned int, data length 4 byte 116 typedef unsigned long MS_U32; // 4 bytes 117 /// data type unsigned int64, data length 8 byte 118 typedef unsigned long long MS_U64; // 8 bytes 119 /// data type signed char, data length 1 byte 120 typedef signed char MS_S8; // 1 byte 121 /// data type signed short, data length 2 byte 122 typedef signed short MS_S16; // 2 bytes 123 /// data type signed int, data length 4 byte 124 typedef signed long MS_S32; // 4 bytes 125 /// data type signed int64, data length 8 byte 126 typedef signed long long MS_S64; // 8 bytes 127 #endif 128 129 // HW settings (Offset base is code buffer address.) 130 #define HVD_SRAM_START 0x20000000UL 131 132 #define HVD_DRAM_SIZE 0x40000 // Default HVD DRAM heap size, 256k 133 #define EVD_DRAM_SIZE 0xD0000 // Default EVD DRAM heap size, 832k 134 135 #define TEE_ONE_TASK_SHM_SIZE 0x20000 // 128K 136 137 #define HVD_SHARE_MEM_ST_SIZE (0x1000) 138 #define HVD_PTS_TABLE_ST_SIZE (0x8000) 139 #define HVD_BBU_DRAM_ST_SIZE (0x2000) 140 #define HVD_BBU2_DRAM_ST_SIZE (0x3000) 141 #define HVD_AVC_DTVINFO_SIZE (0x1000) 142 #define HVD_AVC_INFO608_SIZE (0x1000) 143 #define HVD_AVC_INFO708_SIZE (0x4800) 144 #define HVD_AVC_USERDATA_SIZE (0x2900) 145 146 #define MIN_4K2K_WIDTH 3800 147 #define MIN_4K2K_HEIGHT 2000 148 149 #define EVD_MIUSEL_MASK (0x3) 150 #define EVD_BS_MIUSEL_SHIFT (0) 151 #define EVD_LUMA8_MIUSEL_SHIFT (2) 152 #define EVD_LUMA2_MIUSEL_SHIFT (4) 153 #define EVD_CHROMA_MIUSEL_SHIFT (6) 154 155 #if defined(SUPPORT_NEW_MEM_LAYOUT) 156 157 #define HVD_SHARE_INFO_DEFAULT_OFFSET (0x0) 158 159 #define MAX_PTS_TABLE_SIZE 2048 // max (reserve 0xE0000~0xE8000) //1024 160 #define AVOID_PTS_TABLE_OVERFLOW_THRESHOLD 24 161 #define HVD_BYTE_COUNT_MASK 0x1FFFFFFF // hvd fw reg_byte_pos 29bit 162 163 #define HVD_BBU_DRAM_TBL_ENTRY (0x4000/8) // bbu entry. 64bits(8 bytes) every entry. 164 #define HVD_BBU_DRAM_TBL_ENTRY_TH (HVD_BBU_DRAM_TBL_ENTRY-4) // bbu entry. 64bits(8 bytes) every entry. 165 166 /// HVD_BBU_DRAM_ST_ADDR + 0x2000 for test MVC dual-bbu mode 167 #define HVD_BBU2_DRAM_TBL_ENTRY (0x1000/8) // bbu entry. 64bits(8 bytes) every entry. 168 #define HVD_BBU2_DRAM_TBL_ENTRY_TH (HVD_BBU2_DRAM_TBL_ENTRY-4) // bbu entry. 64bits(8 bytes) every entry. 169 170 #if 1 /// SUPPORT_MVC 171 #define MVC_BBU_DRAM_ST_SIZE (0x2000) 172 #define MVC_BBU_DRAM_TBL_ENTRY (0x1000/8) // bbu entry. 64bits(8 bytes) every entry. 173 #define MVC_BBU_DRAM_TBL_ENTRY_TH (MVC_BBU_DRAM_TBL_ENTRY-4) // bbu entry. 64bits(8 bytes) every entry. 174 175 #define MVC_BBU2_DRAM_TBL_ENTRY (0x1000/8) // bbu entry. 64bits(8 bytes) every entry. 176 #define MVC_BBU2_DRAM_TBL_ENTRY_TH (MVC_BBU2_DRAM_TBL_ENTRY-4) // bbu entry. 64bits(8 bytes) every entry. 177 #endif // SUPPORT_MVC 178 179 #define RVD_BBU_DRAM_TBL_ENTRY (0x4000/8) // bbu entry. 64bits(8 bytes) every entry. 180 #define RVD_BBU_DRAM_TBL_ENTRY_TH (RVD_BBU_DRAM_TBL_ENTRY-4) // bbu entry. 64bits(8 bytes) every entry. 181 182 #define VP8_BBU_DRAM_ST_SIZE (0x2000) 183 #define VP8_BBU_DRAM_TBL_ENTRY (0x1000/8) // bbu entry. 64bits(8 bytes) every entry. 184 #define VP8_BBU_DRAM_TBL_ENTRY_TH (VP8_BBU_DRAM_TBL_ENTRY-4) // bbu entry. 64bits(8 bytes) every entry. 185 186 #if defined(SUPPORT_EVD) && (SUPPORT_EVD==1) 187 #define HVD_SHARE_MEM_ST_OFFSET 0xB0000 188 #define VSYNC_BRIGE_SHM_ADDR 0xCFA00 189 #else 190 #define HVD_SHARE_MEM_ST_OFFSET 0xA0000 191 #define VSYNC_BRIGE_SHM_ADDR 0xBFA00 192 #endif 193 194 #define HVD_DYNAMIC_SCALING_SIZE 0x1F00 195 #define HVD_DYNAMIC_SCALING_SIZE_3K 0xC00 // allocate 6k. actually use: 16 align => 3k 196 #define HVD_DYNAMIC_SCALING_SIZE_6K 0x1800 // allocate 6k. actually use: 32 align => 6k 197 #define HVD_DYNAMIC_SCALING_DEPTH 0x10 198 #define HVD_DYNAMIC_SCALING_3D_DEPTH 0x20 /// 3D Dynamic scaling use 32. 199 #define HVD_SCALER_INFO_SIZE 0x100 200 201 #define HVD_AVC_FRAME_PACKING_SEI_SIZE 0x100 202 #define HVD_AVC_FRAME_PACKING_SEI_NUM 2 203 204 //DBG 205 #define HVD_DBG_DUMP_SIZE 0x06500 206 #define HVD_DUMMY_WRITE_MAX_SIZE 0x200 207 208 #define VSYNC_BRIGE_SHM_MAX_SIZE 0x600 209 #define MAX_VSYNC_BRIDGE_DISPQ_NUM 8 210 211 #define HVD_DISP_QUEUE_MAX_SIZE 42 212 // AVC 213 #define HVD_FW_AVC_DUMMY_FIFO 256 // bytes 214 #define HVD_FW_AVC_MAX_DECODE_TICK 100000 // tick ??? 215 #define HVD_FW_AVC_MAX_VIDEO_DELAY 1000 // ms ; based on ??? 216 #define HVD_FW_AVC_ES_MIN_TSP_DATA_SIZE 0x100 217 #define HVD_FW_AVC_ES_MIN_TSP_DATA_SIZE2 0x1800 218 #define HVD_FW_BROKEN_BY_US_MIN_DATA_SIZE 0x1800 219 220 #define HVD_FW_AVC_ES_UNDER_THRESHOLD 0x800 // 2048 221 #define HVD_FW_AVC_ES_OVER_THRESHOLD 0x40000 // 256*1024 222 223 // User CC 224 #define USER_CC_DATA_SIZE 38 225 #define USER_CC_IDX_SIZE 12 226 227 // AVS 228 #define HVD_FW_AVS_DUMMY_FIFO 2048 //BYTES 229 230 // RM 231 #define HVD_FW_RM_DUMMY_FIFO 256 // ?? 232 #define HVD_RM_INIT_PICTURE_SIZE_NUMBER 8 233 234 #define EXT_CC_INFO_LENGTH 16 235 #define EXT_608_CC_PACKET_LENGTH 16 236 #define EXT_608_CC_DATA_ALIGN EXT_608_CC_PACKET_LENGTH 237 #define EXT_708_CC_PACKET_LENGTH 128 238 #define EXT_708_CC_DATA_ALIGN EXT_708_CC_PACKET_LENGTH 239 240 #else // if not defined (SUPPORT_NEW_MEM_LAYOUT) 241 242 #define HVD_SHARE_INFO_DEFAULT_OFFSET 0xE0000 243 #define HVD_OLD_LAYOUT_SHARE_MEM_BIAS 0xD000 244 245 /* New Memory Layout */ 246 #if 1 247 #define HVD_PTS_TABLE_ST_OFFSET 0xE0000 248 #define MAX_PTS_TABLE_SIZE 2048 // max (reserve 0xE0000~0xE8000) //1024 249 #define AVOID_PTS_TABLE_OVERFLOW_THRESHOLD 24 250 #define HVD_BYTE_COUNT_MASK 0x1FFFFFFF // hvd fw reg_byte_pos 29bit 251 252 #define HVD_BBU_DRAM_ST_ADDR 0xE8000 // bbu table from dram starting address 253 #define HVD_BBU_DRAM_TBL_ENTRY (0x4000/8) // bbu entry. 64bits(8 bytes) every entry. 254 #define HVD_BBU_DRAM_TBL_ENTRY_TH (HVD_BBU_DRAM_TBL_ENTRY-4) // bbu entry. 64bits(8 bytes) every entry. 255 256 /// HVD_BBU_DRAM_ST_ADDR + 0x2000 for test MVC dual-bbu mode 257 #define HVD_BBU2_DRAM_ST_ADDR (HVD_BBU_DRAM_ST_ADDR + 0x2000) //0xEA000 // bbu table from dram starting address 258 #define HVD_BBU2_DRAM_TBL_ENTRY (0x1000/8) // bbu entry. 64bits(8 bytes) every entry. 259 #define HVD_BBU2_DRAM_TBL_ENTRY_TH (HVD_BBU2_DRAM_TBL_ENTRY-4) // bbu entry. 64bits(8 bytes) every entry. 260 261 #if 1 /// SUPPORT_MVC 262 #define MVC_BBU_DRAM_ST_ADDR 0xE8000 // bbu table from dram starting address 263 #define MVC_BBU_DRAM_TBL_ENTRY (0x1000/8) // bbu entry. 64bits(8 bytes) every entry. 264 #define MVC_BBU_DRAM_TBL_ENTRY_TH (MVC_BBU_DRAM_TBL_ENTRY-4) // bbu entry. 64bits(8 bytes) every entry. 265 266 #define MVC_BBU2_DRAM_ST_ADDR (MVC_BBU_DRAM_ST_ADDR + 0x2000) // bbu table from dram starting address 267 #define MVC_BBU2_DRAM_TBL_ENTRY (0x1000/8) // bbu entry. 64bits(8 bytes) every entry. 268 #define MVC_BBU2_DRAM_TBL_ENTRY_TH (MVC_BBU2_DRAM_TBL_ENTRY-4) // bbu entry. 64bits(8 bytes) every entry. 269 #endif // SUPPORT_MVC 270 271 #define RVD_BBU_DRAM_TBL_ENTRY (0x4000/8) // bbu entry. 64bits(8 bytes) every entry. 272 #define RVD_BBU_DRAM_TBL_ENTRY_TH (RVD_BBU_DRAM_TBL_ENTRY-4) // bbu entry. 64bits(8 bytes) every entry. 273 #define VP8_BBU_DRAM_ST_ADDR_BS3 HVD_BBU_DRAM_ST_ADDR // bbu table from dram starting address 274 #define VP8_BBU_DRAM_ST_ADDR_BS4 (HVD_BBU_DRAM_ST_ADDR + 0x2000) // bbu table from dram starting address 275 #define VP8_BBU_DRAM_TBL_ENTRY (0x1000/8) // bbu entry. 64bits(8 bytes) every entry. 276 #define VP8_BBU_DRAM_TBL_ENTRY_TH (VP8_BBU_DRAM_TBL_ENTRY-4) // bbu entry. 64bits(8 bytes) every entry. 277 278 #define HVD_SHARE_MEM_ST_OFFSET 0xED000 279 280 #define HVD_DYNAMIC_SCALING_ADDR 0xEE000 281 #define HVD_DYNAMIC_SCALING_SIZE 0x1F00 282 #define HVD_DYNAMIC_SCALING_SIZE_3K 0xC00 // allocate 6k. actually use: 16 align => 3k 283 #define HVD_DYNAMIC_SCALING_SIZE_6K 0x1800 // allocate 6k. actually use: 32 align => 6k 284 #define HVD_DYNAMIC_SCALING_DEPTH 0x10 285 #define HVD_DYNAMIC_SCALING_3D_DEPTH 0x20 /// 3D Dynamic scaling use 32. 286 #define HVD_SCALER_INFO_ADDR 0xEFF00 287 #define HVD_SCALER_INFO_SIZE 0x100 288 289 #define HVD_AVC_DTVINFO 0xF0000 290 #define HVD_AVC_INFO608 0xF1000 291 #define HVD_AVC_INFO708 0xF2000 292 #define HVD_AVC_USERDATA 0xF6800 293 #define HVD_AVC_FRAME_PACKING_SEI 0xF9100 294 #define HVD_AVC_FRAME_PACKING_SEI_SIZE 0x100 295 #define HVD_AVC_FRAME_PACKING_SEI_NUM 2 296 297 //DBG 298 #define HVD_DBG_DUMP_ADDR 0xF9300 299 #define HVD_DBG_DUMP_SIZE 0x06500 300 301 #define HVD_DUMMY_WRITE_ADDR 0xFF800 302 #define HVD_DUMMY_WRITE_MAX_SIZE 0x200 303 304 #define VSYNC_BRIGE_SHM_ADDR 0xFFA00 305 #define VSYNC_BRIGE_SHM_MAX_SIZE 0x600 306 #define MAX_VSYNC_BRIDGE_DISPQ_NUM 8 307 308 #define HVD_DISP_QUEUE_MAX_SIZE 42 309 // AVC 310 #define HVD_FW_AVC_DUMMY_FIFO 256 // bytes 311 #define HVD_FW_AVC_MAX_DECODE_TICK 100000 // tick ??? 312 #define HVD_FW_AVC_MAX_VIDEO_DELAY 1000 // ms ; based on ??? 313 #define HVD_FW_AVC_ES_MIN_TSP_DATA_SIZE 0x100 314 #define HVD_FW_AVC_ES_MIN_TSP_DATA_SIZE2 0x1800 315 #define HVD_FW_BROKEN_BY_US_MIN_DATA_SIZE 0x1800 316 317 #define HVD_FW_AVC_ES_UNDER_THRESHOLD 0x800 // 2048 318 #define HVD_FW_AVC_ES_OVER_THRESHOLD 0x12C00 // 75*1024 319 320 // User CC 321 #define USER_CC_DATA_SIZE 38 322 #define USER_CC_IDX_SIZE 12 323 324 // AVS 325 #define HVD_FW_AVS_DUMMY_FIFO 2048 //BYTES 326 327 // RM 328 #define HVD_FW_RM_DUMMY_FIFO 256 // ?? 329 #define HVD_RM_INIT_PICTURE_SIZE_NUMBER 8 330 331 332 #define EXT_CC_INFO_LENGTH 16 333 #define EXT_608_CC_PACKET_LENGTH 16 334 #define EXT_608_CC_DATA_ALIGN EXT_608_CC_PACKET_LENGTH 335 #define EXT_708_CC_PACKET_LENGTH 128 336 #define EXT_708_CC_DATA_ALIGN EXT_708_CC_PACKET_LENGTH 337 338 #endif 339 #endif // #if deifned(SUPPORT_NEW_MEM_LAYOUT) 340 341 /* Old Memory Layout */ 342 #if 0 343 #define HVD_PTS_TABLE_ST_OFFSET 0x70000 344 #define MAX_PTS_TABLE_SIZE 2048 // max (reserve 0x70000~0x78000) //1024 345 #define HVD_BYTE_COUNT_MASK 0x1FFFFFFF // hvd fw reg_byte_pos 29bit 346 347 #define HVD_BBU_DRAM_ST_ADDR 0x78000 // bbu table from dram starting address 348 #define HVD_BBU_DRAM_TBL_ENTRY (0x1000/8) // bbu entry. 64bits(8 bytes) every entry. 349 #define HVD_BBU_DRAM_TBL_ENTRY_TH (HVD_BBU_DRAM_TBL_ENTRY-4) // bbu entry. 64bits(8 bytes) every entry. 350 #if 1 /// SUPPORT_MVC 351 /// HVD_BBU_DRAM_ST_ADDR + 0x2000 for test MVC dual-bbu mode 352 #define HVD_BBU2_DRAM_ST_ADDR HVD_BBU_DRAM_ST_ADDR + 0x2000 //0x7A000 // bbu table from dram starting address 353 #define HVD_BBU2_DRAM_TBL_ENTRY (0x1000/8) // bbu entry. 64bits(8 bytes) every entry. 354 #define HVD_BBU2_DRAM_TBL_ENTRY_TH (HVD_BBU2_DRAM_TBL_ENTRY-4) // bbu entry. 64bits(8 bytes) every entry. 355 #endif // SUPPORT_MVC 356 #define RVD_BBU_DRAM_TBL_ENTRY (0x4000/8) // bbu entry. 64bits(8 bytes) every entry. 357 #define RVD_BBU_DRAM_TBL_ENTRY_TH (RVD_BBU_DRAM_TBL_ENTRY-4) // bbu entry. 64bits(8 bytes) every entry. 358 #define VP8_BBU_DRAM_ST_ADDR_BS3 HVD_BBU_DRAM_ST_ADDR // bbu table from dram starting address 359 #define VP8_BBU_DRAM_ST_ADDR_BS4 (HVD_BBU_DRAM_ST_ADDR + 0x2000) // bbu table from dram starting address 360 #define VP8_BBU_DRAM_TBL_ENTRY (0x1000/8) // bbu entry. 64bits(8 bytes) every entry. 361 #define VP8_BBU_DRAM_TBL_ENTRY_TH (HVD_BBU_DRAM_TBL_ENTRY-4) // bbu entry. 64bits(8 bytes) every entry. 362 363 #define HVD_SHARE_MEM_ST_OFFSET 0x7D000 364 365 #define HVD_DYNAMIC_SCALING_ADDR 0x7E000 366 #define HVD_DYNAMIC_SCALING_SIZE 0x1F00 367 #define HVD_DYNAMIC_SCALING_SIZE_3K 0xC00 // allocate 6k. actually use: 16 align => 3k 368 #define HVD_DYNAMIC_SCALING_SIZE_6K 0x1800 // allocate 6k. actually use: 32 align => 6k 369 #define HVD_DYNAMIC_SCALING_DEPTH 0x10 370 #define HVD_SCALER_INFO_ADDR 0x7FF00 371 #define HVD_SCALER_INFO_SIZE 0x100 372 373 #define HVD_AVC_DTVINFO 0x80000 374 #define HVD_AVC_INFO608 0x81000 375 #define HVD_AVC_INFO708 0x82000 376 #define HVD_AVC_USERDATA 0x86800 377 #define HVD_AVC_FRAME_PACKING_SEI 0x88000 378 #define HVD_AVC_FRAME_PACKING_SEI_SIZE 0x100 379 #define HVD_AVC_FRAME_PACKING_SEI_NUM 2 380 381 #define HVD_DUMMY_WRITE_ADDR 0x8FE00 382 #define HVD_DUMMY_WRITE_MAX_SIZE 0x200 383 384 #define HVD_DBG_DUMP_ADDR 0xD0000 385 #define HVD_DBG_DUMP_SIZE 0x20000 386 387 #define HVD_DISP_QUEUE_MAX_SIZE 36 388 // AVC 389 #define HVD_FW_AVC_DUMMY_FIFO 256 // bytes 390 #define HVD_FW_AVC_MAX_DECODE_TICK 100000 // tick ??? 391 #define HVD_FW_AVC_MAX_VIDEO_DELAY 1000 // ms ; based on ??? 392 #define HVD_FW_AVC_ES_MIN_TSP_DATA_SIZE 0x100 393 #define HVD_FW_AVC_ES_UNDER_THRESHOLD 0x800 // 2048 394 #define HVD_FW_AVC_ES_OVER_THRESHOLD 0x12C00 // 75*1024 395 396 // User CC 397 #define USER_CC_DATA_SIZE 24 398 #define USER_CC_IDX_SIZE 12 399 400 // AVS 401 #define HVD_FW_AVS_DUMMY_FIFO 2048 //BYTES 402 403 // RM 404 #define HVD_FW_RM_DUMMY_FIFO 256 // ?? 405 #define HVD_RM_INIT_PICTURE_SIZE_NUMBER 8 406 #endif 407 408 // Debug 409 #define HVD_FW_AVS_OUTPUT_INFO_ADDR 0x20001F00UL 410 #define HVD_FW_AVC_OUTPUT_INFO_ADDR 0x20001F00UL 411 412 #define PRESET_ONE_PENDING_BUFFER (1 << 0) /// For AVC, one pending buffer mode, reduce from two to one 413 #define PRESET_IAP_GN_SHARE_BW_MODE (1 << 1) /// For AVC 4K2K, move IAP GN buffer to another miu to share BW mode //johnny.ko 414 415 typedef enum 416 { 417 E_HVD_IQMEM_INIT_NONE = 0, 418 E_HVD_IQMEM_INIT_LOADING, //HK -> FW 419 E_HVD_IQMEM_INIT_LOADED, //FW -> HK 420 E_HVD_IQMEM_INIT_FINISH //HK -> FW 421 422 }HVD_IQMEM_INIT_STATUS; 423 424 425 426 typedef enum 427 { 428 E_HVD_FLUSH_NONE = 0, 429 E_HVD_FLUSH_RUNNING, //HK -> FW 430 E_HVD_FLUSH_DONE //FW -> HK 431 432 }HVD_FLUSH_STATUS; 433 434 typedef enum 435 { 436 E_HVD_ISR_EVENT_NONE = 0, ///< disable ISR 437 E_HVD_ISR_EVENT_DISP_ONE = BIT(0), ///< HVD display one frame on screen. 438 E_HVD_ISR_EVENT_DISP_REPEAT = BIT(1), ///< The current displayed frame is repeated frame. 439 E_HVD_ISR_EVENT_DISP_WITH_CC = BIT(2), ///< Current displayed frame should be displayed with user data. 440 E_HVD_ISR_EVENT_DISP_FIRST_FRM = BIT(3), ///< HVD display first frame on screen. 441 442 E_HVD_ISR_EVENT_DEC_ONE = BIT(8), ///< HVD decoded one frame done. 443 E_HVD_ISR_EVENT_DEC_I = BIT(9), ///< HVD decoded one I frame done. 444 E_HVD_ISR_EVENT_DEC_HW_ERR = BIT(10), ///< HVD HW found decode error. 445 E_HVD_ISR_EVENT_DEC_CC_FOUND = BIT(11), ///< HVD found one user data with decoded frame(with display order). 446 E_HVD_ISR_EVENT_DEC_DISP_INFO_CHANGE = BIT(12), ///< HVD found display information change. 447 E_HVD_ISR_EVENT_DEC_DATA_ERR = BIT(13), ///< HVD HW found decode error. 448 E_HVD_ISR_EVENT_DEC_FIRST_FRM = BIT(14), ///< HVD decode first frame. 449 E_HVD_ISR_EVENT_DEC_SEQ_HDR_FOUND = BIT(15), ///< HVD found sequence header. 450 } HVD_ISR_Event_Type; 451 452 typedef enum 453 { 454 E_HVD_USER_DATA_MODE_DVB_NORMAL = 0x00, 455 E_HVD_USER_DATA_MODE_DIRECTTV_CC = 0x01, 456 E_HVD_USER_DATA_MODE_FRM_PACKING_ARRANGEMENT = 0x02, 457 E_HVD_USER_DATA_MODE_ATSC_CC_RAW = 0x04, 458 E_HVD_USER_DATA_MODE_CC_UNTIL_START_CODE = 0x08 459 } HVD_USER_DATA_MODE; 460 461 462 typedef enum 463 { 464 E_HVD_DRV_AUTO_BBU_MODE = 0x00, 465 E_HVD_FW_AUTO_BBU_MODE = 0x01, 466 } HVD_BBU_MODE; 467 468 typedef enum 469 { 470 E_HVD_FW_STATUS_NONE = 0, ///< NONE Flag 471 E_HVD_FW_STATUS_SEEK_TO_I = BIT(0), ///< Seek to I slice/frame flag 472 } HVD_FW_STATUS_FLAG; 473 474 /* 475 //interupt flag , value is in VPU RISC MBOX 1 ( for LG GP DTV only) 476 #define HVD_ISR_USER_DATA (1 << 0) 477 #define HVD_ISR_DATA_ERR (1 << 1) 478 #define HVD_ISR_PIC_DEC_ERR (1 << 2) 479 #define HVD_ISR_DEC_OVER (1 << 3) 480 #define HVD_ISR_DEC_UNDER (1 << 4) 481 #define HVD_ISR_DEC_I (1 << 5) 482 #define HVD_ISR_DIS_READY (1 << 6) 483 #define HVD_ISR_SEQ_INFO (1 << 7) 484 #define HVD_ISR_VIDEO_SKIP (1 << 8) 485 #define HVD_ISR_VIDEO_REPEAT (1 << 9) 486 #define HVD_ISR_VIDEO_FREERUN (1 << 10) 487 #define HVD_ISR_INVALID_STREAM (1 << 11) 488 #define HVD_ISR_VIDEO_AVSYNC_DONE (1 << 12) 489 #define HVD_ISR_VIDEO_VSYNC (1 << 31) 490 */ 491 492 //------------------------------------------------------------------------------------------------- 493 // Type and Structure 494 //------------------------------------------------------------------------------------------------- 495 // User CC 496 #define USR_BUF_SIZE (256) 497 498 typedef struct _DTV_BUF_type 499 { 500 MS_U8 type; // 0xCC:continue, 0:P 1:B 2:I 501 MS_U8 len; // size byte of buf 502 MS_U8 active; // 0:free 1:already dma out or not assign 2:assign 503 MS_U8 pic_struct; // pic_struct, Reserved when 0, Top Field when 1, Bottom Field when 2, and Frame picture when 3. 504 MS_U32 pts; 505 MS_U16 u16TempRefCnt; // Temp Ref Count for UserData ,Value that increases by 1 for each frame (like time stamp) 506 MS_U16 u16Res; // Reserved 507 MS_U32 u32Res; // Reserved 508 MS_U8 buf[USR_BUF_SIZE]; //user data 509 } DTV_BUF_type; //size must <= 276, currently only use 272 510 511 #define HVD_FRM_PACKIMG_PAYLOAD_SIZE ((HVD_AVC_FRAME_PACKING_SEI_SIZE/HVD_AVC_FRAME_PACKING_SEI_NUM)-20) /// 20: HVD_Frame_packing_SEI size expect payload data 512 513 typedef struct 514 { 515 MS_BOOL bUsed; 516 MS_BOOL bvaild; 517 MS_U8 u8Frm_packing_arr_cnl_flag; // u(1) 518 MS_U8 u8Frm_packing_arr_type; // u(7) 519 MS_U8 u8content_interpretation_type; // u(6) 520 MS_U8 u1Quincunx_sampling_flag:1; // u(1) 521 MS_U8 u1Spatial_flipping_flag:1; // u(1) 522 MS_U8 u1Frame0_flipping_flag:1; // u(1) 523 MS_U8 u1Field_views_flag:1; // u(1) 524 MS_U8 u1Current_frame_is_frame0_flag:1; // u(1) 525 MS_U8 u1Frame0_self_contained_flag:1; // u(1) 526 MS_U8 u1Frame1_self_contained_flag:1; // u(1) 527 MS_U8 u1Reserved1:1; // u(1) 528 MS_U8 u4Frame0_grid_position_x:4; // u(4) 529 MS_U8 u4Frame0_grid_position_y:4; // u(4) 530 MS_U8 u4Frame1_grid_position_x:4; // u(4) 531 MS_U8 u4Frame1_grid_position_y:4; // u(4) 532 MS_U16 u16CropRight; 533 MS_U16 u16CropLeft; 534 MS_U16 u16CropBottom; 535 MS_U16 u16CropTop; 536 MS_U8 u8payload_len; 537 MS_U8 u8WaitSPS; 538 MS_U8 u8Reserved[2]; 539 MS_U8 u8payload[HVD_FRM_PACKIMG_PAYLOAD_SIZE]; 540 } HVD_Frame_packing_SEI; 541 542 // stuct 543 typedef struct 544 { 545 MS_U16 u16HorSize; 546 MS_U16 u16VerSize; 547 MS_U32 u32FrameRate; // Unit: ms 548 MS_U8 u8AspectRate; // aspect ration ID; for AVC only 549 MS_U8 u8Interlace; 550 MS_U8 u8AFD; 551 //MS_U8 u8par_width; 552 //MS_U8 u8par_height; 553 MS_U8 bChroma_idc_Mono; // 1: mono 0: colorful, not mono ; AVC only currently. AVS,RM?? 554 MS_U16 u16DispWidth; // Display width or aspect ratio width 555 MS_U16 u16DispHeight; // Display height or aspect ratio height 556 MS_U16 u16CropRight; 557 MS_U16 u16CropLeft; 558 MS_U16 u16CropBottom; 559 MS_U16 u16CropTop; 560 MS_U16 u16Pitch; // ??? 561 MS_U8 u8ColourPrimaries; // Color Primaries in VUI 562 //**************************** 563 MS_U8 u8IsOriginInterlace; // Is Original Interlace mode 564 //****************************** 565 // MS_U16 u16PTSInterval; // ??? not fill 566 // MS_U8 u8MPEG1; // may be removed 567 // MS_U8 u8PlayMode; // ??? not fill 568 // MS_U8 u8FrcMode; // may be removed 569 } HVD_Display_Info; // bytes 570 571 typedef struct 572 { 573 MS_U8 bIsShowErrFrm; 574 MS_U8 bIsRepeatLastField; 575 MS_U8 bIsErrConceal; 576 MS_U8 bIsSyncOn; 577 MS_U8 bIsPlaybackFinish; 578 MS_U8 u8SyncType; // HVD_Sync_Tbl_Type 579 MS_U8 u8SkipMode; // HVD_Skip_Decode_Type 580 MS_U8 u8DropMode; // HVD_Drop_Disp_Type 581 MS_S8 s8DisplaySpeed; // HVD_Disp_Speed 582 MS_U8 u8FrcMode; // HVD_FRC_Mode 583 MS_U8 bIsBlueScreen; 584 MS_U8 bIsFreezeImg; 585 MS_U8 bShowOneField; 586 //***************************** 587 MS_U8 u8reserve8_1; 588 MS_U16 u16reserve16_1; 589 //***************************** 590 } HVD_Mode_Status; // 12 bytes 591 592 typedef struct 593 { 594 MS_U16 u16Width; 595 MS_U16 u16Height; 596 } HVD_PictureSize; 597 598 typedef struct 599 { 600 MS_U32 u32LumaAddr; ///< The start offset of luma data. Unit: byte. 601 MS_U32 u32ChromaAddr; ///< The start offset of chroma data. Unit: byte. 602 MS_U32 u32TimeStamp; ///< Time stamp(DTS, PTS) of current displayed frame. Unit: 90khz. 603 MS_U32 u32ID_L; ///< low part of ID number decided by MDrv_HVD_PushQueue(). 604 MS_U32 u32ID_H; ///< high part of ID number decided by MDrv_HVD_PushQueue(). 605 MS_U8 u8FrmType; ///< HVD_Picture_Type, picture type: I, P, B frame 606 MS_U8 u8FieldType; ///< HVD_Field_Type, none, top , bottom, both field 607 MS_U16 u16Pitch; 608 MS_U16 u16Width; 609 MS_U16 u16Height; 610 MS_U32 u32Status; ///< 0:None, 1:Init, 2:View, 3:Disp, 4:Free 611 MS_U32 u32PrivateData; ///[STB]only for AVC 612 MS_U32 u32LumaAddr_2bit; ///< The start offset of 2bit luma data. Unit: byte. 613 MS_U32 u32ChromaAddr_2bit; ///< The start offset of 2bit chroma data. Unit: byte. 614 MS_U16 u16Pitch_2bit; 615 MS_U8 u8LumaBitdepth; 616 MS_U8 u8ChromaBitdepth; 617 } HVD_Frm_Information; 618 619 typedef struct 620 { 621 MS_BOOL aspect_ratio_info_present_flag; // u(1) 622 MS_U8 aspect_ratio_idc; // u(8) 623 MS_U16 sar_width; // u(16) 624 MS_U16 sar_height; // u(16) 625 MS_BOOL overscan_info_present_flag; // u(1) 626 MS_BOOL overscan_appropriate_flag; // u(1) 627 MS_BOOL video_signal_type_present_flag; // u(1) 628 MS_U8 video_format; // u(3) 629 MS_BOOL video_full_range_flag; // u(1) 630 MS_BOOL colour_description_present_flag; // u(1) 631 MS_U8 colour_primaries; // u(8) 632 MS_U8 transfer_characteristics; // u(8) 633 MS_U8 matrix_coefficients; // u(8) 634 MS_BOOL chroma_location_info_present_flag; // u(1) 635 MS_U8 chroma_sample_loc_type_top_field; // ue(v) 0~5 636 MS_U8 chroma_sample_loc_type_bottom_field; // ue(v) 0~5 637 MS_BOOL timing_info_present_flag; // u(1) 638 MS_BOOL fixed_frame_rate_flag; // u(1) 639 MS_U32 num_units_in_tick; // u(32) 640 MS_U32 time_scale; // u(32) 641 } HVD_AVC_VUI_DISP_INFO; 642 643 typedef struct 644 { 645 MS_U32 u32FrmrateUpBound; //Framerate filter upper bound 646 MS_U32 u32FrmrateLowBound; //Framerate filter lower bound 647 MS_U32 u32MvopUpBound; //mvop filter upper bound 648 MS_U32 u32MvopLowBound; //mvop filter lower bound 649 } HVD_DISP_THRESHOLD; 650 651 typedef struct 652 { 653 // switch 654 MS_U32 u32CodecType; //0x0000 655 MS_U32 u32FrameBufAddr; //0x0004 656 MS_U32 u32FrameBufSize; //0x0008 657 MS_U32 u32CPUClock; //0x000C 658 HVD_Display_Info DispInfo; //0x0010 659 660 // FW -> HK 661 // report info 662 //AFD_Info AFDInfo; 663 MS_U32 u32DispSTC; //0x002C // Current Display Frame STC 664 MS_U32 u32DecodeCnt; //0x0030 // Decoded picture count 665 MS_U32 u32DecErrCnt; //0x0034 // HW decode err or not finish. 666 MS_U32 u32DataErrCnt; //0x0038 // FW process data error, like SPS, slice header .etc. 667 MS_U16 u16ErrCode; //0x003C // Drv/FW error code ; HVD_Err_Code 668 MS_U8 u8FrameMbsOnlyFlag; //0x003E // frame_mbs_only_flag of AVC SPS. 669 MS_U8 u8ForceBreakCnt; //0x003F // 670 MS_U32 u32VPUIdleCnt; //0x0040 // VPU idle count 671 MS_U32 u32FrameRate; //0x0044 // Input Frame Rate 672 MS_U32 u32FrameRateBase; //0x0048 // Input Frame Rate Base 673 HVD_Mode_Status ModeStatus; //0x004C // FW mode 674 HVD_Frm_Information DispFrmInfo; //0x005C // current displayed frame information. 675 HVD_Frm_Information DecoFrmInfo; //0x008C // specified decoded frame information. 676 //MS_U8 u8DecPictType; // Current decode picture type: E_HVD_PICT_TYPE_I: I frm, E_HVD_PICT_TYPE_P: ref(P) , E_HVD_PICT_TYPE_B: non-ref(B) (GP2 need only) 677 #if defined(INTERLEAVE_SW_SEEK) || defined(SW_GETBITS) || defined(INTERLEAVE_SW_PARSE) 678 MS_U32 u32BBUReadPtr; 679 #endif 680 // internal control info 681 MS_U8 bInitDone; //0x00BC 682 MS_U8 bIs1stFrameRdy; //0x00BD // first frame are showed on screen 683 MS_U8 bIsIFrmFound; //0x00BE // 1: First I frame found. 0: fw should set to zero after user cmd, "Flush" 684 MS_U8 bIsSyncStart; //0x00BF // under sync mode, 1: FW start doing sync action. 0: FW freerun or freerun mode. 685 MS_U8 bIsSyncReach; //0x00C0 // under sync mode, 1: FW sync reach. 0: FW freerun or sync not reach. 686 687 //**************************************** 688 689 MS_U8 u8SrcMode; //0x00C1 690 MS_U8 bEnableDispQueue; //0x00C2 691 MS_U8 bEnableDispOutSide; //0x00C3 692 //**************************************** 693 MS_U32 u32FWVersionID; //0x00C4 // FW version ID 694 MS_U32 u32FWIfVersionID; //0x00C8 // FW IF version ID 695 MS_U32 u32ESWritePtr; //0x00CC // the write pointer of bitstream buffer. 696 MS_U16 u16DecQNumb; //0x00D0 // current decoded queue total entry number. old oq size 697 MS_U16 u16DispQNumb; //0x00D2 // current display queue total entry number. old Used Size 698 MS_U32 u32PTStableWptrAddr; //0x00D4 // The address of PTS table write pointer. 699 MS_U32 u32PTStableRptrAddr; //0x00D8 // The address of PTS table read pointer. 700 MS_U32 u32PTStableByteCnt; //0x00DC // The value of byte count of TSP. FW update it after init() and flush(). 701 702 // debug info 703 MS_U32 u32SkipCnt; //0x00E0 // skipped picture count count by command: E_HVD_DECODE_ALL, E_HVD_DECODE_I, E_HVD_DECODE_IP 704 MS_U32 u32DropCnt; //0x00E4 // dorpped decoded picture counter by command: drop_auto or drop_once 705 MS_U32 u32CCBase; //0x00E8 // CC Ring Base Address 706 MS_U32 u32CCSize; //0x00EC // CC Ring Size 707 MS_U32 u32CCWrtPtr; //0x00F0 // CC Ring Write Pointer 708 MS_U32 u32NtscCCBase; //0x00F4 // NTSC CC Ring Base Address 709 MS_U32 u32NtscCCSize; //0x00F8 // NTSC CC Ring Size 710 MS_U32 u32NtscCCWrtPtr; //0x00FC // NTSC CC Ring Write Pointer 711 //**************************************** 712 MS_U32 u32CurrentPts; //0x0100 // only useful when Jump to pts command is activated 713 MS_U32 u32DispCnt; //0x0104 // Display picture count 714 MS_U32 u32FWBaseAddr; //0x0108 715 //**************************************** 716 MS_U32 u32UserCCBase; //0x010C // User CC Base Address 717 MS_U32 u32UserCCIdxWrtPtr; //0x0110 // User CC Idx Write Pointer 718 MS_U8 u8UserCCIdx[USER_CC_IDX_SIZE];//0x0114 // User CC Idx 719 //**************************************** 720 MS_U32 u32VirtualBoxWidth; //0x0120 // Dynamic Scale: DRV -> FW 721 MS_U32 u32VirtualBoxHeight; //0x0124 // Dynamic Scale: DRV -> FW 722 MS_U32 u32SrcWidth; //0x0128 // Dynamic Scale: Source Width 723 MS_U32 u32SrcHeight; //0x012C // Dynamic Scale: Source Height 724 //**************************************** 725 MS_U8 u8IsDivxPlusStream; //0x0130 // 1: Divx Plus Stream, 0: Not Divx Plus Stream 726 //**************************************** 727 728 // -------- AVC info -------- 729 //MS_U32 u32AVC_NalCnt; // Decoded nal count >> change to SRAM 730 MS_U8 u8AVC_SPS_LowDelayHrdFlag; //0x0131 // VUI low_delay_hrd_flag 731 MS_U16 u16AVC_SPS_LevelIDC; //0x0132 // sps level idc 732 MS_U32 u32AVC_VUIDispInfo_Addr; //0x0134 // VUI Display Info Address 733 //MS_U32 u32AVC_SPS_Addr; // FW sps structure start address 734 735 // -------- AVS info -------- 736 // ..... 737 //MS_U32 u32AVS_xxx; 738 739 // -------- RM info -------- 740 // HK -> FW 741 MS_U8 u8RM_Version; //0x0138 742 MS_U8 u8RM_NumSizes; //0x0139 743 //**************************************** 744 MS_U16 reserved16_2; //0x013A 745 //**************************************** 746 HVD_PictureSize pRM_PictureSize[HVD_RM_INIT_PICTURE_SIZE_NUMBER]; //0x013C 747 MS_U32 u32RM_VLCTableAddr; //0x015C 748 749 // -------- common info -------- 750 MS_U32 u32MainLoopCnt; //0x0160 751 MS_U32 u32VsyncCnt; //0x0164 752 HVD_DISP_THRESHOLD DispThreshold; //0x0168 753 MS_U32 u32ESReadPtr; //0x0178 // the read pointer of bitstream buffer. 754 MS_U32 reserved32_0; //0x017C 755 MS_S64 s64PtsStcDiff; //0x0180 // 90Khz 756 MS_U16 u16ChipID; //0x0188 // enum MSTAR_CHIP_ID 757 MS_U16 u16ChipECONum; //0x018A // ECO num of chip 758 MS_U32 u32NextPTS; //0x018C // ms 759 760 761 MS_U16 u16DispQSize; //0x0190 762 MS_U16 u16DispQPtr; //0x0192 763 HVD_Frm_Information DispQueue[HVD_DISP_QUEUE_MAX_SIZE]; //0x0194 764 //---------------------------------------------------------------------- 765 MS_U32 u32RealFrameRate; //0x0974 766 767 MS_U8 bSpsChange; //0x0978 768 MS_U8 bEnableDispCtrl; //0x0979 769 MS_U8 bIsTrigDisp; //0x097A 770 MS_U8 reserved8_3; //0x097B 771 MS_U32 u32FwState; //0x097C 772 MS_U32 u32FwInfo; //0x0980 773 MS_U32 u32IntCount; //0x0984 774 775 //---------------------------------------------------------------------- 776 MS_U16 u16FreeQWtPtr; //0x0988 777 MS_U16 u16FreeQRdPtr; //0x098A 778 MS_U32 FreeQueue[HVD_DISP_QUEUE_MAX_SIZE]; //0x098C 779 780 // --------- MVC info (Sub view buffer and 2nd input pointer) --------- 781 HVD_Frm_Information DispFrmInfo_Sub; //0x0A34 // current displayed Sub frame information. 782 HVD_Frm_Information DecoFrmInfo_Sub; //0x0A64 // specified decoded Sub frame information. 783 MS_U32 u32ES2WritePtr; //0x0A94 784 MS_U32 u32ES2ReadPtr; //0x0A98 785 786 // --------- MJPEG share memory ------------------------------------------ 787 MS_U32 u32MJPEGFrameBuffIdx; //0x0A9C 788 MS_U32 u32MJPEGTimeStamp; //0x0AA0 789 MS_U32 u32MJPEGID_L; //0x0AA4 790 MS_U32 u32MJPEGID_H; //0x0AA8 791 MS_U32 u32MJPEG_NextFrameBuffIdx; //0x0AAC 792 MS_U8 u8MJPEG_bStepPlay; //0x0AB0 793 MS_U8 u8MJPEG_bPlaying; //0x0AB1 794 MS_U8 u8MJPEG_bIsAVSyncOn; //0x0AB2 795 MS_U8 u8MJPEG_bIsReachAVSync; //0x0AB3 796 MS_U8 u8MJPEG_bFlushQueue; //0x0AB4 797 MS_U8 u8MJPEG_bIsDispFinish; //0x0AB5 798 MS_U8 u8MJPEG_bQueueFull; //0x0AB6 799 MS_U8 bIsLeastDispQSize; //0x0AB7 800 801 // --------- SEI: frame packing ------------------------------------------ 802 MS_U32 u32Frm_packing_arr_data_addr; //0x0AB8 803 804 //---------- report 3k/6k for 16/32 Mem-Align DS -------------------------- 805 MS_U32 u32DSBuffSize; //0x0ABC // Dynamic Scale Buffer Size actually used for different DS Mem Align 806 MS_U8 bDSIsRunning; //0x0AC0 807 volatile MS_U8 u8IQmemCtrl; //0x0AC1 808 MS_U8 bIsIQMEMSupport; //0x0AC2 809 MS_U8 bIQmemEnableIfSupport; //0x0AC3 810 MS_U8 u8FlushStatus; //0x0AC4 811 MS_U8 u8DSBufferDepth; //0x0AC5 812 MS_U8 reserved8_5[2]; //0x0AC6 813 MS_U16 u16DispQWptr[2]; //0x0AC8 814 MS_U8 u8ESBufStatus; //0x0ACC 815 MS_U8 u8FieldPicFlag; //0x0ACD 816 MS_U8 reserved8_6[2]; //0x0ACE 817 818 // reserved for MJPEG 819 MS_U32 u32MJPEGDbg_DispStatus; //0x0AD0 820 MS_U8 u8MJPEGDbg_ReadFbIdx; //0x0AD4 821 MS_U8 u8MJPEGDbg_WriteFbIdx; //0x0AD5 822 MS_U8 u8MJPEGDbg_SkipRepeat; //0x0AD6 823 MS_U8 u8MJPEGDbg_reserved8_1; //0x0AD7 824 MS_U32 u32MJPEGDbg_SysTime; //0x0AD8 825 MS_U32 u32MJPEGDbg_VideoPts; //0x0ADC 826 MS_U32 u32MJPEGDbg_SkipRepeatTime; //0x0AE0 827 828 MS_U32 u32DSbufferAddr; //0x0AE4 829 MS_U32 u32DispRepeatCnt; //0x0AE8 830 831 MS_U32 u32ColocateBBUReadPtr; //0x0AEC FW->HK 832 MS_U32 u32ColocateBBUWritePtr; //0x0AF0 HK->FW 833 MS_U8 u8BBUMode; //0x0AF4 0: driver auto bbu mode, 1: fw auto bbu mode(colocate bbu mode) 834 MS_U8 bUseTSPInBBUMode; //0x0AF5 0: disable, 1: enable 835 MS_U8 reserved8_7[2]; //0x0AF6 836 837 MS_U32 u32DmxFrameRate; //0x0AF8 // Demuxer Prefered Input Frame Rate 838 MS_U32 u32DmxFrameRateBase; //0x0AFC // Demuxer Prefered Input Frame Rate Base 839 MS_U32 u32PTSTblRd; //0x0B00 //PTS table read ptr 840 MS_U32 u32PTSTblWr; //0x0B04 //PTS table write ptr 841 MS_U32 u32PreSetControl; //0x0B08 // PreSetControl 842 MS_U32 u32IapGnBufAddr; //0x0B0C 843 MS_U32 u32IapGnBufSize; //0x0B10 844 MS_U32 u32SeamlessTSStatus; //0x0B14 845 MS_U32 u32FWStatusFlag; //0x0B18 846 MS_U32 u32ESBufLevel; //0x0B1C 847 MS_U32 u32ESBuf2Level; //0x0B20 848 MS_U8 reserved8_8[0xFC0-0xB24]; //0x0B24 849 850 MS_U32 u32EVD_MIU_SEL; //0x0FC0 851 MS_U32 u32HVD_PTS_TABLE_ST_OFFSET; //0x0FC4 852 MS_U32 u32HVD_BBU_DRAM_ST_ADDR; //0x0FC8 853 MS_U32 u32HVD_BBU2_DRAM_ST_ADDR; //0x0FCC 854 MS_U32 u32HVD_DYNAMIC_SCALING_ADDR; //0x0FD0 855 MS_U32 u32HVD_SCALER_INFO_ADDR; //0x0FD4 856 MS_U32 u32HVD_AVC_DTVINFO; //0x0FD8 857 MS_U32 u32HVD_AVC_INFO608; //0x0FDC 858 MS_U32 u32HVD_AVC_INFO708; //0x0FE0 859 MS_U32 u32HVD_AVC_USERDATA; //0x0FE4 860 MS_U32 u32HVD_AVC_FRAME_PACKING_SEI;//0x0FE8 861 MS_U32 u32HVD_DBG_DUMP_ADDR; //0x0FEC 862 MS_U32 u32HVD_DUMMY_WRITE_ADDR; //0x0FF0 863 MS_U32 u32VSYNC_BRIGE_SHM_ADDR; //0x0FF4 864 MS_U32 u32COMPARE_INFO_ADDR; //0x0FF8 865 MS_U32 u32COMPARE_MD5_ADDR; //0x0FFC 866 } HVD_ShareMem; 867 868 typedef struct 869 { 870 MS_U32 u32LumaAddr0; ///< The start offset of luma data. Unit: byte. 871 MS_U32 u32ChromaAddr0; ///< The start offset of chroma data. Unit: byte. 872 MS_U32 u32LumaAddr1; ///< The start offset of luma data. Unit: byte. 873 MS_U32 u32ChromaAddr1; ///< The start offset of chroma data. Unit: byte. 874 MS_U32 u32PriData; ///< Index for SEC release frame buffer 875 MS_U32 u32PriData1; ///< Index for SEC release frame buffer 876 MS_U32 u32Status; 877 MS_U16 u16Pitch; 878 MS_U16 u16Width; 879 MS_U16 u16Height; 880 MS_U16 u16CropLeft; 881 MS_U16 u16CropRight; 882 MS_U16 u16CropBottom; 883 MS_U16 u16CropTop; 884 MS_U8 u8FrmType; ///< HVD_Picture_Type, picture type: I, P, B frame 885 MS_U8 u8FieldType; ///< HVD_Field_Type, none, top , bottom, both field 886 MS_U8 u8Interlace; 887 MS_U8 u8ColorFormat; // 0 -> 420, 1 -> 422, 2 -> 420 10 bit 888 MS_U8 u8FrameNum; // if 2, u32LumaAddr1 and u32ChromaAddr1 should be use 889 MS_U8 u8RangeMapY; // for VC1 or 10 BIT frame, 2 bit Y depth 890 MS_U8 u8RangeMapUV; // for VC1 or 10 BIT frame, 2 bit UV depth 891 MS_U8 u8TB_toggle; // 0 -> TOP then BOTTOM 892 MS_U8 u8Tog_Time; 893 MS_U8 u8FirstDispField; 894 MS_U8 u8FieldCtrl; // 0-> Normal, 1->always top, 2->always bot 895 MS_U8 u8DSIndex; 896 MS_U16 u16Pitch1; // for 10 BIT, the 2 bit frame buffer pitch 897 } DISP_FRM_INFO; 898 899 typedef struct 900 { 901 // for vsync bridge dispQ bridge 902 MS_U8 u8DispQueNum; 903 MS_U8 u8McuDispSwitch; 904 MS_U8 u8McuDispQWPtr; 905 MS_U8 u8McuDispQRPtr; 906 DISP_FRM_INFO McuDispQueue[MAX_VSYNC_BRIDGE_DISPQ_NUM]; 907 MS_U8 u8DisableFDMask; 908 MS_U8 u8FdMaskField; 909 MS_U8 u8ToggledTime; 910 MS_U8 u8ToggleMethod; 911 MS_U8 u8Reserve[4]; 912 } MCU_DISPQ_INFO; 913 914 typedef struct 915 { 916 MS_U32 u32ByteCnt; 917 MS_U32 u32PTS; 918 MS_U32 u32ID_L; 919 MS_U32 u32ID_H; 920 } HVD_PTS_Entry; 921 922 // enum 923 typedef enum 924 { 925 E_MSTAR_CHIP_NONE = 0, 926 E_MSTAR_CHIP_U3, 927 E_MSTAR_CHIP_T3, 928 E_MSTAR_CHIP_T4, 929 E_MSTAR_CHIP_JANUS, 930 E_MSTAR_CHIP_U4, 931 E_MSTAR_CHIP_T8, 932 E_MSTAR_CHIP_T9, 933 E_MSTAR_CHIP_M10, 934 E_MSTAR_CHIP_T12, 935 E_MSTAR_CHIP_T13, 936 E_MSTAR_CHIP_J2, 937 E_MSTAR_CHIP_K1, 938 E_MSTAR_CHIP_A1, 939 E_MSTAR_CHIP_A5, 940 E_MSTAR_CHIP_A7, 941 E_MSTAR_CHIP_K2, 942 E_MSTAR_CHIP_A3, 943 E_MSTAR_CHIP_A7P, 944 E_MSTAR_CHIP_AGATE, 945 E_MSTAR_CHIP_M12, 946 E_MSTAR_CHIP_EAGLE, 947 E_MSTAR_CHIP_EMERALD, 948 E_MSTAR_CHIP_EDISON, 949 E_MSTAR_CHIP_EIFFEL, 950 E_MSTAR_CHIP_CEDRIC, 951 E_MSTAR_CHIP_NUGGET, 952 E_MSTAR_CHIP_KAISER, 953 E_MSTAR_CHIP_NIKE, 954 E_MSTAR_CHIP_KENYA, 955 E_MSTAR_CHIP_EINSTEIN, 956 E_MSTAR_CHIP_NIKON, 957 E_MSTAR_CHIP_NAPOLI, 958 E_MSTAR_CHIP_MADISON, 959 E_MSTAR_CHIP_MONACO, 960 E_MSTAR_CHIP_KERES, 961 E_MSTAR_CHIP_MIAMI, 962 E_MSTAR_CHIP_OTHER = 0xFF, 963 } MSTAR_CHIP_ID; 964 965 typedef enum 966 { 967 E_HVD_SRC_MODE_DTV = 0, 968 E_HVD_SRC_MODE_TS_FILE, 969 E_HVD_SRC_MODE_FILE, 970 E_HVD_SRC_MODE_TS_FILE_DUAL_ES, 971 E_HVD_SRC_MODE_FILE_DUAL_ES, 972 } HVD_SRC_MODE; 973 974 typedef enum 975 { 976 E_HVD_Codec_AVC = 0, 977 E_HVD_Codec_AVS, 978 E_HVD_Codec_RM, 979 E_HVD_Codec_MVC, 980 E_HVD_Codec_VP8, 981 E_HVD_Codec_MJPEG, 982 E_HVD_Codec_VP6, 983 E_HVD_Codec_HEVC, 984 E_HVD_Codec_VP9, 985 E_HVD_Codec_UNKNOWN 986 } HVD_Codec_Type; 987 988 typedef enum 989 { 990 E_HVD_PICT_TYPE_I, 991 E_HVD_PICT_TYPE_P, 992 E_HVD_PICT_TYPE_B, 993 } HVD_Picture_Type; 994 995 typedef enum 996 { 997 E_HVD_FIELD_TYPE_NONE = 0, 998 E_HVD_FIELD_TYPE_TOP, 999 E_HVD_FIELD_TYPE_BOTTOM, 1000 E_HVD_FIELD_TYPE_BOTH, 1001 } HVD_Field_Type; 1002 1003 typedef enum 1004 { 1005 E_HVD_DECODE_ALL, 1006 E_HVD_DECODE_I, 1007 E_HVD_DECODE_IP, 1008 } HVD_Skip_Decode_Type; 1009 1010 typedef enum 1011 { 1012 E_HVD_DROP_DISP_AUTO = (1<<0), 1013 E_HVD_DROP_DISP_ONCE = (1<<1), 1014 } HVD_Drop_Disp_Type; 1015 1016 typedef enum 1017 { 1018 E_HVD_FRC_NORMAL = 0, 1019 E_HVD_FRC_32PULLDOWN, //3:2 pulldown mode (ex. 24p a 60i or 60p) 1020 E_HVD_FRC_PAL2NTSC , //PALaNTSC conversion (50i a 60i) 1021 E_HVD_FRC_NTSC2PAL, //NTSCaPAL conversion (60i a 50i) 1022 E_HVD_FRC_DISP_2X, //output rate is twice of input rate (ex. 30p a 60p) 1023 E_HVD_FRC_24_50, //output rate 24P->50P 48I->50I 1024 E_HVD_FRC_50P_60P, //output rate 50P ->60P 1025 E_HVD_FRC_60P_50P, //output rate 60P ->50P 1026 E_HVD_FRC_HALF_I, //output rate 120i -> 60i, 100i -> 50i 1027 E_HVD_FRC_120I_50I, //output rate 120i -> 60i 1028 E_HVD_FRC_100I_60I, //output rate 100i -> 60i 1029 E_HVD_FRC_DISP_4X, //output rate is four times of input rate (ex. 15P a 60P) 1030 E_HVD_FRC_15_50, //output rate 15P->50P 1031 E_HVD_FRC_30_50, //output rate 30i->50i 1032 } HVD_FRC_Mode; 1033 1034 typedef enum 1035 { 1036 E_HVD_FRC_DROP_FRAME = 0, 1037 E_HVD_FRC_DROP_FIELD = 1, 1038 } HVD_FRC_Drop_Mode; 1039 1040 typedef enum 1041 { 1042 E_HVD_DISP_SPEED_F_32X = 32, 1043 E_HVD_DISP_SPEED_F_16X = 16, 1044 E_HVD_DISP_SPEED_F_8X = 8, 1045 E_HVD_DISP_SPEED_F_4X = 4, 1046 E_HVD_DISP_SPEED_F_2X = 2, 1047 E_HVD_DISP_SPEED_1X = 1, 1048 E_HVD_DISP_SPEED_S_2X = -2, 1049 E_HVD_DISP_SPEED_S_4X = -4, 1050 E_HVD_DISP_SPEED_S_8X = -8, 1051 E_HVD_DISP_SPEED_S_16X = -16, 1052 E_HVD_DISP_SPEED_S_32X = -32, 1053 } HVD_Disp_Speed; 1054 1055 typedef enum 1056 { 1057 E_HVD_SYNC_TBL_TYPE_NON, 1058 E_HVD_SYNC_TBL_TYPE_PTS, 1059 E_HVD_SYNC_TBL_TYPE_DTS, 1060 E_HVD_SYNC_TBL_TYPE_STS, //Sorted TimeStamp 1061 } HVD_Sync_Tbl_Type; //only for file mode. Ts , ts file mode always has PTS table 1062 1063 typedef enum 1064 { 1065 E_HVD_FIELD_CTRL_OFF=0, 1066 E_HVD_FIELD_CTRL_TOP, // Always Show Top Field 1067 E_HVD_FIELD_CTRL_BOTTOM, // Always Show Bottom Field 1068 } HVD_Field_Ctrl; 1069 1070 typedef enum 1071 { 1072 E_HVD_BURST_CNT_LV0 = 0, // U3,T3:32 cycle T4~U4: 16 cycle 1073 E_HVD_BURST_CNT_LV1 = 1, // U3,T3:64 cycle T4~U4: 32 cycle 1074 E_HVD_BURST_CNT_LV2 = 2, // U3,T3:96 cycle T4~U4: 48 cycle 1075 E_HVD_BURST_CNT_LV3 = 3, // U3,T3:128 cycle T4~U4: 64 cycle 1076 E_HVD_BURST_CNT_LV4 = 4, // U3,T3:160 cycle T4~U4: 80 cycle 1077 E_HVD_BURST_CNT_LV5 = 5, // U3,T3:192 cycle T4~U4: 96 cycle 1078 E_HVD_BURST_CNT_LV6 = 6, // U3,T3:224 cycle T4~U4: 112 cycle 1079 E_HVD_BURST_CNT_LV7 = 7, // U3,T3:256 cycle T4~U4: 128 cycle 1080 E_HVD_BURST_CNT_DISABLE = 0xFFFFFFFF, 1081 } HVD_MIU_Burst_Cnt_Ctrl; 1082 1083 typedef enum 1084 { 1085 E_HVD_DISPQ_STATUS_NONE = 0, //FW 1086 E_HVD_DISPQ_STATUS_INIT, //FW 1087 E_HVD_DISPQ_STATUS_VIEW, //HK 1088 E_HVD_DISPQ_STATUS_DISP, //HK 1089 E_HVD_DISPQ_STATUS_FREE, //HK 1090 } HVD_DISPQ_STATUS; 1091 1092 typedef enum 1093 { 1094 // invalid cmd 1095 E_HVD_CMD_INVALID_CMD = 0xFFFFFFFFUL, 1096 1097 // SVD old cmd 1098 E_HVD_CMD_SVD_BASE = 0x00010000, 1099 /*0x10001*/E_HVD_CMD_PARSER_BYPASS, // 1 : on :for raw file mode; AVCHVD_CMD_PARSER_BYPASS ; 0: off: TS file mode and live stream 1100 /*0x10002*/E_HVD_CMD_BBU_RESIZE, // svd only; AVCHVD_CMD_BBU_SIZE 1101 /*0x10003*/E_HVD_CMD_FRAME_BUF_RESIZE, // svd only; AVCHVD_CMD_RESIZE_MEM 1102 /*0x10004*/E_HVD_CMD_IGNORE_ERR_REF, // 1: ignore ref error, 0: enable ref error handle; AVCHVD_CMD_IGNORE_LIST + AVCHVD_CMD_OPEN_GOP 1103 /*0x10005*/E_HVD_CMD_ES_FULL_STOP, // ES auto stop: 1: AVCHVD_CMD_ES_STOP; ES not stop 0: AVCHVD_CMD_HANDSHAKE 1104 /*0x10006*/E_HVD_CMD_DROP_DISP_AUTO, // 1:on AVCHVD_CMD_DISP_DROP, 0:off AVCHVD_CMD_DIS_DISP_DROP 1105 /*0x10007*/E_HVD_CMD_DROP_DISP_ONCE, // AVCHVD_CMD_DROP_CNT 1106 /*0x10008*/E_HVD_CMD_FLUSH_DEC_Q, // AVCHVD_CMD_FLUSH_QUEUE 1107 1108 // HVD new cmd 1109 E_HVD_CMD_NEW_BASE = 0x00020000, 1110 // Action 1111 E_HVD_CMD_TYPE_ACTION_MASK = (0x0100|E_HVD_CMD_NEW_BASE), 1112 1113 // state machine action 1114 /*0x20101*/E_HVD_CMD_INIT , // Init FW type: E_HVD_Codec_AVC ; E_HVD_Codec_AVS; E_HVD_Codec_RM 1115 /*0x20102*/E_HVD_CMD_PLAY, // AVCHVD_CMD_GO 1116 /*0x20103*/E_HVD_CMD_PAUSE, // AVCHVD_CMD_PAUSE 1117 /*0x20104*/E_HVD_CMD_STOP, // AVCHVD_CMD_STOP 1118 // run-time action 1119 /*0x20105*/E_HVD_CMD_STEP_DECODE, // AVCHVD_CMD_STEP 1120 /*0x20106*/E_HVD_CMD_FLUSH, // Arg: 1 show last decode, 0 show current diaplay.FW need to clear read pointer of PTS table under SYNC_PTS, SYNC_DTS. ; BBU: AVCHVD_CMD_DROP , DISP: AVCHVD_CMD_FLUSH_DISPLAY , AVCHVD_CMD_SKIPTOI 1121 /*0x20107*/E_HVD_CMD_BLUE_SCREEN, // only for AVC. remove auto blue screen before show first frame on screen 1122 /*0x20108*/E_HVD_CMD_RESET_PTS, // reset PTS table for TS file mode. AVCHVD_CMD_RE_SYNC 1123 /*0x20109*/E_HVD_CMD_FREEZE_IMG, // FW showes the same frame at every Vsync, but background decode process can not stop. 1: freeze image; 0: normal diaplay 1124 /*0x2010A*/E_HVD_CMD_JUMP_TO_PTS, // Arg: PTS(unit: 90kHz). 0: disable this mode. Any not zero value: enable. FW decode to specified PTS by using full speed. During the decoding, FW need not show any decoded frames, just maitain the last frame before get this command. 1125 /*0x2010B*/E_HVD_CMD_SYNC_TOLERANCE, // Arg: any not zero number(unit: 90kHz). AVCHVD_CMD_SLOW_SYNC 1126 /*0x2010C*/E_HVD_CMD_SYNC_VIDEO_DELAY, // Arg: 0~MAX_VIDEO_DELAY(unit: 90kHz): use Arg of video delay. AVCHVD_CMD_AVSYNC 1127 /*0x2010D*/E_HVD_CMD_DISP_ONE_FIELD, // for AVS, AVC only, Arg: HVD_Field_Ctrl. AVCH264_CMD_ONE_FIELD 1128 /*0x2010E*/E_HVD_CMD_FAST_DISP, // Arg: 0: disable, Any not zero value: enable. Always return first frame ready. Don't care the first frame av-sync. 1129 /*0x2010F*/E_HVD_CMD_SKIP_TO_PTS, // Arg: PTS(unit: 90kHz). 0: disable this mode. Any not zero value: enable. FW decode to specified PTS by using full speed. FW need not to decode frame until the first I after the specified PTS. 1130 /*0x20110*/E_HVD_CMD_SYNC_THRESHOLD, // Arg: 0x01~0xFF , frame repeat time. If arg == 0xFF, fw will always repeat last frame when PTS > STC. 1131 /*0x20111*/E_HVD_CMD_FREERUN_THRESHOLD, // Arg: (unit: 90KHz) 0: use default 5 sec (90000 x 5). 1132 /*0x20112*/E_HVD_CMD_FLUSH_FRM_BUF, // Arg: 1 show last decode frame, 0 show current diaplay frame. FW will clear all frame buffer then skip to next I frame. 1133 /*0x20113*/E_HVD_CMD_FORCE_INTERLACE, // Arg: 0; Diable. Arg: 1; Force interlace only support DTV and TS file mode with framerate 25 or 30 (all resolution) 1134 // Arg: 2; Force interlace support DTV and TS file mode with framerate 25 or 30,but only works on 1080P 1135 // Arg: 3; Force interlace support DTV and TS file mode with framerate 23 to 30 and all resolution. 1136 // Arg: 4; Force interlace support DTV and TS file mode with under 30 fps and all resolution. 1137 /*0x20114*/E_HVD_CMD_DUAL_NON_BLOCK_MODE, // Arg: 0 disable Arg:1 For dual decode case, force switch to another task when current task is idle 1138 /*0x20115*/E_HVD_CMD_INPUT_PTS_FREERUN_MODE, // Arg: 0 disable. Arg:1, video free run when the difference between input PTS and current STC is large than E_HVD_CMD_FREERUN_THRESHOLD + 1s; 1139 /*0x20116*/E_HVD_CMD_FREEZE_TO_CHASE, // Arg: 1 enable, 0 disable. Freeze current image when PTS < STC and decode drop / skip frame to sync stc. 1140 1141 // internal control action 1142 1143 // FW settings ( only for driver init) 1144 E_HVD_CMD_SETTINGS_MASK = (0x0200|E_HVD_CMD_NEW_BASE), 1145 /*0x20201*/E_HVD_CMD_PITCH, // Arg:any non-zero number. AVCHVD_CMD_PITCH_1952, AVCHVD_CMD_PITCH_1984 1146 /*0x20202*/E_HVD_CMD_SYNC_EACH_FRM, // 1: TS file mode: on ; 0: live mode: off AVCHVD_CMD_SYNC 1147 /*0x20203*/E_HVD_CMD_MAX_DEC_TICK, // 0: off ; not 0 : in fw.h new value AVCHVD_CMD_MAXT 1148 /*0x20204*/E_HVD_CMD_AUTO_FREE_ES, // 1: on ; 0: off ; for live stream only AVCHVD_CMD_AUTO_FREE 1149 /*0x20205*/E_HVD_CMD_DIS_VDEAD, // 1: on :For PVR , file mode only ; 0 : off: AVCHVD_CMD_DIS_VDEAD 1150 /*0x20206*/E_HVD_CMD_MIN_FRAME_GAP, // Arg: 0~n, 0xFFFFFFFF: don't care frame gap; For file mode only; AVCHVD_CMD_MIN_FRAME_GAP 1151 /*0x20207*/E_HVD_CMD_SYNC_TYPE, // Arg: HVD_Sync_Tbl_Type. //only for file mode. Ts , ts file mode always has PTS table 1152 /*0x20208*/E_HVD_CMD_TIME_UNIT_TYPE, // Set Time unit: 0: 90Khz, 1: 1ms 1153 /*0x20209*/E_HVD_CMD_ISR_TYPE, // Add ISR trigger timing. 1154 /*0x2020A*/E_HVD_CMD_DYNAMIC_SCALE, // 0: disable; 1: enable 1155 /*0x2020B*/E_HVD_CMD_SCALER_INFO_NOTIFY, 1156 /*0x2020C*/E_HVD_CMD_MIU_BURST_CNT, // Arg 0~7 burst cnt level , 0xFFFFFFFF = Disable 1157 /*0x2020D*/E_HVD_CMD_FDMASK_DELAY_CNT, // Arg: 0~0xFF, Fdmask delay count, arg >= 0xFF -> use default. 1158 /*0x2020E*/E_HVD_CMD_FRC_OUTPUT_FRAMERATE, // unit: vsync cnt 1159 /*0x2020F*/E_HVD_CMD_FRC_OUTPUT_INTERLACE, // 0: progressive; 1: interlace 1160 /*0x20210*/E_HVD_CMD_ENABLE_DISP_QUEUE, // 0: Disable; 1:Enable 1161 /*0x20211*/E_HVD_CMD_FORCE_DTV_SPEC, // 0: Disable; 1:Enable, Force to follow H264 DTV Spec, if res>720p && framerate>50, force progessive 1162 // 2: Disable, if frame_mbs_only_flag == TRUE, it's progressive. 1163 /*0x20212*/E_HVD_CMD_SET_USERDATA_MODE, // Arg: HVD_USER_DATA_MODE, use "OR", 0x00: Normal DVB user_data mode; 0x01: ATSC DirectTV CC mode 1164 // 0x02: FPA CallBack, 0x04: ATSC_CC_RAW mode 1165 /*0x20213*/E_HVD_CMD_ENABLE_DISP_OUTSIDE, // 0: Disable; 1:Enable 1166 /*0x20214*/E_HVD_CMD_SUPPORT_AVC_TO_MVC, // Arg: 0: Disable AVC to MVC, 1: Enable AVC to MVC but non-support DS, 2:Enable AVC to MVC and support DS, 1167 /*0x20215*/E_HVD_CMD_ENABLE_NEW_SLOW_MOTION, // Arg: 0: Disable New Slow Motion, 1: Enable New Slow Motion. 1168 /*0x20216*/E_HVD_CMD_FORCE_ALIGN_VSIZE, // Arg: 0: Disable and 3D ouput is frame packing mode. 1: Enable VSIZE would be 4 align and Crop Botton would be additional size; 3D output would not be frame packing mode. 1169 /*0x20217*/E_HVD_CMD_PUSH_DISPQ_WITH_REF_NUM, // Arg: 0: Disable; 1:Enable 1170 /*0x20218*/E_HVD_CMD_GET_MORE_FRM_BUF, // Arg: 0: Disable; 1:Enable. If buffer size is enough, intial more frame buffer to use. 1171 /*0x20219*/E_HVD_CMD_RM_ENABLE_PTS_TBL, // Arg, 0:disable, 1:enable. this command is only used by RM, when enable==1, RM will search pts table and return matched u32ID_L 1172 /*0x2021A*/E_HVD_CMD_DYNAMIC_SCALE_RESV_N_BUFFER, // Arg, 0:disable, 1:enable. use init_dpb_and_frame_buffer_layout_3 to do dynamic layout other than fixed layout 1173 /*0x2021B*/E_HVD_CMD_DS_RESET_XC_DISP_WIN, // Arg, 0: Disable, 1:enable. When Dynamic scaling enable, report the display information change and re-set XC display window. 1174 /*0x2021C*/E_HVD_CMD_AVC_SUPPORT_REF_NUM_OVER_MAX_DPB_SIZE, /// Arg, 0: Disable; 1:enable. AVC support reference number is more than maximum DPB size when frame buffer size was enough. 1175 /*0x2021D*/E_HVD_CMD_FRAMERATE_HANDLING, // Arg 0~60000, 0: Disable, 1000 ~ 60000: Used the arg to set frame rate when the sequence did not have frame rate info. and arg is not zero. (The frame unit is (arg/1000)fps, Exp: 30000 = 30.000 fps), others: Do not thing. 1176 /*0x2021E*/E_HVD_CMD_AUTO_EXHAUST_ES_MODE, // Arg, 0: disable, [31:16]= Upper bound, [15:0] = Lower bound, Unit is 1KBytes, // Auto drop display to consume ES data as soon as possible when ES level is higher than upper bound 1177 /*0x2021F*/E_HVD_CMD_RETURN_INVALID_AFD, // Arg, 0: Disable, 1:enable, return 0 when AFD is invalid 1178 /*0x20220*/E_HVD_CMD_AVC_FORCE_BROKEN_BY_US, // Arg, 0: Disable, 1:enable, force enable broken by us mode, 1179 /*0x20221*/E_HVD_CMD_EXTERNAL_DS_BUF, // Arg, 0: Disable, 1:Enable. 1180 /*0x20222*/E_HVD_CMD_SHOW_FIRST_FRAME_DIRECT, // Arg: 0: Disable; 1:Enable. Push first I frame to display queue directly.. 1181 /*0x20223*/E_HVD_CMD_AVC_RESIZE_DOS_DISP_PEND_BUF, //Arg: Resize disp pending buffer size for display outside mode(dos), default dos disp pending buf size = 4 1182 /*0x20224*/E_HVD_CMD_SET_MIN_TSP_DATA_SIZE, //Arg: Resize HVD_FW_AVC_ES_MIN_TSP_DATA_SIZE 1183 /*0x20225*/E_HVD_CMD_DYNAMIC_SCALE_ENHANCE_SETTINGS, //Arg: 0:None, 1:MHP,... 1184 /*0x20226*/E_HVD_CMD_ONE_PENDING_BUFFER_MODE, // Arg: 0: Disable; 1:Enable. Use only one pending buffer instead of two. 1185 /*0x20227*/E_HVD_CMD_ENABLE_EXTERNAL_CC_608_BUF, // Arg: [7:0] =size, [31:8]= start address, unit =1k bytes , Enable: length/address != 0, Disable: length/address == 0 1186 /*0x20228*/E_HVD_CMD_ENABLE_EXTERNAL_CC_708_BUF, // Arg: [7:0] =size, [31:8]= start address, unit =1k bytes , Enable: length/address != 0, Disable: length/address == 0 1187 /*0x20229*/E_HVD_CMD_SET_DISP_ERROR_TOLERANCE, // Arg: //[15:8]+[7:0] = (err_tolerance(0%~100%)+enable or disable) 1188 /*0x2022A*/E_HVD_CMD_SET_PTS_US_MODE, // Arg: //0: Disable; 1:Enable. return micro seconds PTS in PTS mode 1189 /*0x2022B*/E_HVD_CMD_SET_USERDATA_SHOW_ORDER, // Set user data show order , 0: Display order, 1: Decode order 1190 /*0x2022C*/E_HVD_CMD_RM_ENABLE_MCU_MODE_ES, // Arg: //0: Disable; 1:Enable. RM input data with MCU mode 1191 1192 1193 // Mode ( for AP run-time) 1194 E_HVD_CMD_MODE_MASK = (0x0300|E_HVD_CMD_NEW_BASE), 1195 /*0x20301*/E_HVD_CMD_SKIP_DEC, // E_HVD_DECODE_ALL ;E_HVD_DECODE_I;E_HVD_DECODE_IP; AVCHVD_CMD_DEC_I , AVCHVD_CMD_SKIP_NONREF 1196 /*0x20302*/E_HVD_CMD_DISP_SPEED, // HVD_Disp_Speed ; AVCHVD_CMD_TRICKY 0,1: normal speed N(>0): show N times, slow motion Nx(-2,-4...) ; N(<0): FF speed Nx(2,4,...) AVCHVD_CMD_2X_SPEED 1197 /*0x20303*/E_HVD_CMD_DISP_ERR_FRM, // True: display and error frame; FALSE: not show error frame ; AVCHVD_CMD_ERR_TH 1198 /*0x20304*/E_HVD_CMD_ERR_CONCEAL, // 1: on ; 0: off ; AVCHVD_CMD_PASTE 1199 /*0x20305*/E_HVD_CMD_REPEAT_LAST_FIELD, // 1: ON ; 0: OFF 1200 /*0x20306*/E_HVD_CMD_FRC_MODE, // Arg:HVD_FRC_Mode. AVCHVD_CMD_FRAME_CVT 1201 /*0x20307*/E_HVD_CMD_SYNC_ACTIVE, // Arg: 0: sync off. AVCHVD_CMD_FREE_RUN ; 1: sync on. AVCHVD_CMD_AVSYNC 1202 /*0x20308*/E_HVD_CMD_PLAYBACK_FINISH, // 1: no more input data, FW need to show frame by itself until all buffers being empty. 0: close this mode. 1203 /*0x20309*/E_HVD_CMD_BALANCE_BW, // Arg: Byte0: Quarter Pixel Off Level, Byte1: Deblock Off Level >> 0: off, 1~255: count threshold to enter, Byte2: Upper Bound value. i.e.: Byte0: 1,Byte1: 10,Byte2: 20. 1204 /*0x2030A*/E_HVD_CMD_POWER_SAVING, // Arg: 0: Power Saving Off, 1: Power Saving On 1205 /*0x2030B*/E_HVD_CMD_DIS_DBF, // Disable deblock, Arg: 0: off, 1: disable all frame, 2: only disable non-ref frame 1206 /*0x2030C*/E_HVD_CMD_DIS_QUART_PIXEL, // Disable quarter pixel, Arg: 0: off, 1: disable for all frame, 2: only dsiable non-ref frame 1207 /*0x2030D*/E_HVD_CMD_DPO_CC, // Display Order User Data Command, Arg: 0: off, 1: on. 1208 /*0x2030E*/E_HVD_CMD_DISP_I_DIRECT, // Display I directly, Arg: 0: off, 1: on 1209 /*0x2030F*/E_HVD_CMD_FORCE_RESET_HW, // Arg, 0:disable, 1:enable. Force reset hw when frame start 1210 /*0x20310*/E_HVD_CMD_UPDATE_DISP_THRESHOLD, // Arg, none 1211 /*0x20311*/E_HVD_CMD_FRC_DROP_MODE, // Arg, E_HVD_FRC_DROP_FRAME (0), E_HVD_FRC_DROP_FIELD (1) 1212 /*0x20312*/E_HVD_CMD_UPDATE_DISPQ, // Arg, none. Update Frame Status in Display Queue 1213 /*0x20313*/E_HVD_CMD_SHOW_DECODE_ORDER, // Arg, 0:disable, 1:enable. Show decoder order or display order 1214 /*0x20314*/E_HVD_CMD_3DLR_VIEW_EXCHANGE, // Arg, 0: off, do not thing. 1: on, exchange the L/R views 1215 /*0x20315*/E_HVD_CMD_DISP_IGNORE_CROP, // Arg, 0:disable, 1:enable. Ignore crop information when set V-sync to display 1216 /*0x20316*/E_HVD_CMD_STOP_MVD_PARSER, // Arg, 1:stop mvd parser 1217 /*0x20317*/E_HVD_CMD_SUSPEND_DYNAMIC_SCALE, // Arg, 0:disable, 1:enable. Suspend dynamic scale and raise interrupt. 1218 /*0x20318*/E_HVD_CMD_AVOID_PTS_TBL_OVERFLOW, // Arg, 0:disable, 1:enable. for hw tsp mode, mvd parser will stop when pts table is close to overflow and restart when enough pts is consumed. 1219 /*0x20319*/E_HVD_CMD_IGNORE_PIC_OVERRUN, // Arg, 0:disable, 1:enable. Ignore hw error: PIC overrun error. 1220 /*0x2031A*/E_HVD_CMD_RVU_SETTING_MODE, // Arg, 0:disable, 1:Drop B frame and force IDR. 1221 /*0x2031B*/E_HVD_CMD_RELEASE_DISPQ, // Arg, none. Unlock frame status. 1222 /*0x2031C*/E_HVD_CMD_CTRL_SPEED_IN_DISP_ONLY, // Arg, 0:disable, control in decoding and displaying time; 1:enable, control speed in displaying time only. 1223 /*0x2031D*/E_HVD_CMD_IGNORE_PIC_STRUCT_DISPLAY, // Arg, 0:disable, 1:Ignore Pic_struct when display progressive frame. 1224 /*0x2031E*/E_HVD_CMD_ERR_CONCEAL_SLICE_1ST_MB, // Arg, 0:disable, Error concealment from current/last MB position; 1:enale, Error concealment from current slice first MB.(Need enable E_HVD_CMD_ERR_CONCEAL) 1225 /*0x2031F*/E_HVD_CMD_AUTO_DROP_ES_DATA, // Arg, 0:disable, [31:16]= Upper bound, [15:0] = Lower bound; Unit is 1%~100%: Drop ES data when ES buffer threshold more than 1%~100%. 1226 /*0x20320*/E_HVD_CMD_AUTO_DROP_DISP_QUEUE, // Arg, 0:disable, N = 1~16: Drop display queue when display queue above than N frames. It only support Display Queue mode. (bEnableDispQueue = TRUE) 1227 /*0x20321*/E_HVD_CMD_USE_CPB_REMOVAL_DEALY, // Arg, 0:disable, 1:enable. Use Cpb_Removal_Delay of Picture timing SEI to control PTS. 1228 /*0x20322*/E_HVD_CMD_SKIP_N_FRAME, // Arg, 0:disable, N = 1~63. Skip N frame. 1229 /*0x20323*/E_HVD_CMD_PVR_SEAMLESS_TIMESHIFT, // Arg, 0:disable, 1:pause decode, 2:reset hw and wait for playback with target data, 3:seek_to_I after play 1230 /*0x20324*/E_HVD_CMD_STOP_PARSER_BY_PTS_TABLE_LEVEL, // Arg, 0:disable, [31:16]= Upper bound, [15:0] = Lower bound; Stop parser when PTS table size is more than upper bound. Resume parser when PTS table size is less than low bound. 1231 1232 // test cmd 1233 E_HVD_CMD_TEST_MASK = (0x0400|E_HVD_CMD_NEW_BASE), 1234 /*0x20401*/E_HVD_CMD_INIT_STREAM, // Initialize this stream 1235 /*0x20402*/E_HVD_CMD_RELEASE_STREAM, // Release this stream 1236 1237 // HVD new cmd Max 1238 E_HVD_CMD_NEW_MAX = (0xFFFF|E_HVD_CMD_NEW_BASE), 1239 1240 1241 // Dual Stream Command 1242 E_DUAL_CMD_BASE = 0x00030000, // pass the DRAM offset from argument 1243 1244 E_DUAL_CMD_MODE_MASK = (0x0100|E_DUAL_CMD_BASE), 1245 /*0x30101*/E_DUAL_CMD_TASK0_HVD_TSP, 1246 /*0x30102*/E_DUAL_CMD_TASK0_HVD_BBU, 1247 /*0x30103*/E_DUAL_CMD_TASK0_MVD_TSP, 1248 /*0x30104*/E_DUAL_CMD_TASK0_MVD_SLQ, 1249 1250 /*0x30105*/E_DUAL_CMD_TASK1_HVD_TSP, 1251 /*0x30106*/E_DUAL_CMD_TASK1_HVD_BBU, 1252 /*0x30107*/E_DUAL_CMD_TASK1_MVD_TSP, 1253 /*0x30108*/E_DUAL_CMD_TASK1_MVD_SLQ, 1254 1255 /*0x30109*/E_DUAL_CMD_SINGLE_TASK, //argument: 0:multi(default) 1:single // first cmd 1256 1257 /*0x3010A*/E_DUAL_CMD_MODE, //argument: 0:normal(default) 1:3D wmv 2:Korea 3D 3:Korea 3D Progressive 4:sub view sync main STC 1258 // 5:switch target STC , main view sync sub stc and sub view sync main stc //first cmd 1259 1260 /*0x3010B*/E_DUAL_BURST_MODE, //argument: 0:normal(default) 1:burst command to controller(lots of cmd) 1261 1262 /*0x3010C*/E_DUAL_VERSION, //argument: 0:controller 1:mvd fw 2:hvd fw 3:mvd interface 4:hvd interface 1263 /*0x3010D*/E_DUAL_R2_CMD_EXIT, //for WIN32 testing and let R2 FW return directly. 1264 /*0x3010E*/E_DUAL_CMD_COMMON, //argument: 0:dymanic fb management 1265 1266 E_DUAL_CMD_CTL_MASK = (0x0200|E_DUAL_CMD_BASE), // argument is the id : 0 or 1 1267 /*0x30201*/E_DUAL_CMD_DEL_TASK, 1268 1269 // Dual Stream cmd Max 1270 E_DUAL_CMD_MAX = (0xFFFF|E_DUAL_CMD_BASE), 1271 1272 // N Stream Command 1273 E_NST_CMD_BASE = 0x00040000, // pass the DRAM offset from argument 1274 1275 E_NST_CMD_MODE_MASK = (0x0100|E_NST_CMD_BASE), 1276 /*0x40101*/E_NST_CMD_TASK0_HVD, 1277 /*0x40102*/E_NST_CMD_TASK1_HVD, 1278 /*0x40103*/E_NST_CMD_TASK2_HVD, 1279 1280 E_NST_CMD_CTL_MASK = (0x0200|E_NST_CMD_BASE), // argument is the id : 0 ,1 or 2 1281 /*0x40201*/E_NST_CMD_DEL_TASK, 1282 1283 // N Stream cmd Max 1284 E_NST_CMD_MAX = (0xFFFF|E_NST_CMD_BASE), 1285 1286 // CMD MASK 1287 E_CMD_MASK = 0x00FFFFFF, 1288 1289 // TASK ID MASK 1290 E_ID_CMD_MASK = 0xFF000000, 1291 1292 } HVD_User_Cmd; 1293 1294 // Command 1295 typedef enum 1296 { 1297 // Invalid cmd 1298 E_JPD_CMD_INVALID = 0xffffffffUL, 1299 1300 E_JPD_CMD_GO = 0x00, // Start to show 1301 E_JPD_CMD_SET_FRAME_BUFF_START_ADDR = 0x01, // Set frame buffer address 1302 E_JPD_CMD_SET_FRAME_BUFF_UNIT_SIZE = 0x02, // Set frame buffer size 1303 E_JPD_CMD_SET_FRAME_BUFF_TOTAL_NUM = 0x03, // Set total number of frame buffer 1304 E_JPD_CMD_SET_FRAME_BUFF_IDX = 0x04, // Set frame buffer index 1305 E_JPD_CMD_SET_FRAME_BUFF_IDX_READY = 0x05, // Set frame buffer index ready for display 1306 E_JPD_CMD_SET_WIDTH = 0x06, // Set frame width 1307 E_JPD_CMD_SET_HEIGHT = 0x07, // Set frame height 1308 E_JPD_CMD_SET_PITCH = 0x08, // Set pitch 1309 E_JPD_CMD_SET_FRAME_ID_L = 0x09, // Set frame ID_L 1310 E_JPD_CMD_SET_FRAME_ID_H = 0x0A, // Set frame ID_H 1311 E_JPD_CMD_SET_TIMESTAMP = 0x0B, // Set Time Stamp 1312 E_JPD_CMD_SET_FRAMERATE = 0x0C, // Set FrameRate 1313 E_JPD_CMD_SET_FRAMERATE_BASE = 0x0D, // Set FrameRate Base 1314 E_JPD_CMD_SET_FRAME_BUFF_IDX_VALID = 0x0E, // Set frame buffer index available 1315 E_JPD_CMD_SET_CHIP_ID = 0x0F, // Set Chip ID 1316 1317 E_JPD_CMD_PLAY = 0x20, // Play 1318 E_JPD_CMD_PAUSE = 0x21, // Pause 1319 E_JPD_CMD_RESUME = 0x22, // Resume 1320 E_JPD_CMD_STEP_PLAY = 0x23, // Step play 1321 E_JPD_CMD_SET_SPEED_TYPE = 0x24, // Set play speed type: default, fast, slow 1322 E_JPD_CMD_SET_SPEED = 0x25, // Set play speed 1323 E_JPD_CMD_FLUSH_DISP_QUEUE = 0X26, // Flush display queue 1324 E_JPD_CMD_FREEZE_DISP = 0x27, // Freeze display 1325 E_JPD_CMD_ENABLE_AVSYNC = 0x28, // Enable AV Sync 1326 E_JPD_CMD_SET_AVSYNC_DELAY = 0x29, // Set AV sync delay 1327 E_JPD_CMD_SET_AVSYNC_TOLERENCE = 0x2A, // Set AV sync tolerence 1328 E_JPD_CMD_SET_PTS_BASE = 0x2B, // Set PTS base 1329 E_JPD_CMD_SET_STC_BASE = 0x2C, // Set STC base 1330 E_JPD_CMD_SET_BLUE_SCREEN = 0x2D, // Set Blue Screen 1331 E_JPD_CMD_PUSH_QUEUE_PARA_SETTING = 0x2E, 1332 E_JPD_CMD_SET_DISPLAY_OUTSIDE_MODE = 0x2F, 1333 1334 E_JPD_CMD_GET_NEXT_FREE_FRAME_BUFF_IDX = 0x40, // Get next free frame buffer index 1335 E_JPD_CMD_COMPENSATE_PTS = 0x41, // Ask firmware to compensate PTS 1336 1337 // Display Command Queue 1338 E_JPD_CMD_ENABLE_DISP_CMD_QUEUE = 0x80, // Enable Display Command Queue 1339 E_JPD_CMD_PUSH_DISP_CMD = 0x81, // Push Display Command 1340 E_JPD_CMD_GET_DISP_CMD_Q_VACANCY = 0x82, // Check if the display command queue full or not 1341 1342 E_JPD_CMD_IS_STEP_PLAY_DONE = 0xFF, // 1343 E_JPD_CMD_IS_DISP_FINISH = 0xFE, // 1344 E_JPD_CMD_IS_PLAYING = 0xFC, // 1345 E_JPD_CMD_IS_DISPLAY_QUEUE_FULL = 0xFB, // 1346 E_JPD_CMD_IS_AVSYNC_ON = 0xFA, // 1347 E_JPD_CMD_IS_REACH_AVSYNC = 0xF9, // 1348 E_JPD_CMD_IS_FLUSH_DONE = 0xF8, // Check if flush done 1349 1350 } JPD_User_Cmd; 1351 1352 // Firmware State 1353 typedef enum 1354 { 1355 E_JPD_FW_STATE_MASK = 0xF000, 1356 } JPD_FW_State; 1357 1358 // Error Code 1359 typedef enum 1360 { 1361 // Error code base 1362 E_JPD_ERR_BASE= 0x01000000, 1363 } JPD_Err_Code; 1364 1365 typedef enum 1366 { 1367 E_HVD_FW_STATE_MASK = 0xF000, 1368 1369 // state: INIT 1370 E_HVD_FW_INIT = 0x1000, 1371 E_HVD_FW_INIT_START, 1372 E_HVD_FW_INIT_DONE, 1373 1374 // state: PLAY 1375 E_HVD_FW_PLAY = 0x2000, 1376 E_HVD_FW_PLAY_TYPE_MASK = 0x0C00, 1377 1378 // AVC 1379 E_HVD_FW_PLAY_AVC = (0x0000|E_HVD_FW_PLAY), 1380 E_HVD_FW_AVC_READ_NAL, 1381 E_HVD_FW_AVC_READ_NEW_SLICE, 1382 E_HVD_FW_AVC_PREPARE_SLICE_HEADER, 1383 E_HVD_FW_AVC_DECODE_ONE_SLICE, 1384 E_HVD_FW_AVC_EXIT_PICTURE, 1385 1386 // AVS 1387 E_HVD_FW_PLAY_AVS = (0x0400|E_HVD_FW_PLAY), 1388 1389 // RM 1390 E_HVD_FW_PLAY_RM = (0x0800|E_HVD_FW_PLAY), 1391 1392 // state: PAUSE 1393 E_HVD_FW_PAUSE = 0x3000, 1394 1395 // state: STOP 1396 E_HVD_FW_STOP = 0x4000, 1397 E_HVD_FW_STOP_START, 1398 E_HVD_FW_STOP_DONE, 1399 } HVD_FW_State; 1400 1401 1402 typedef enum 1403 { 1404 // Error code base 1405 E_HVD_ERR_BASE = 0x0000, 1406 1407 // General 1408 E_HVD_ERR_GENERAL_BASE = (0x0000|E_HVD_ERR_BASE), 1409 E_HVD_ERR_OUT_OF_SPEC, 1410 E_HVD_ERR_UNKNOW_ERR, 1411 E_HVD_ERR_HW_BREAK_DOWN, 1412 // TIMEOUT 1413 E_HVD_ERR_HW_DEC_TIMEOUT, 1414 // NOT SUPPORT 1415 E_HVD_ERR_OUT_OF_MEMORY, // required memory size is over frame buffer size. 1416 E_HVD_ERR_UNKNOWN_CODEC, // unknown media codec 1417 1418 // AVC 1419 E_HVD_ERR_AVC_BASE = (0x1000|E_HVD_ERR_BASE), 1420 // decode error 1421 E_HVD_ERR_AVC_SPS_BROKEN, // SPS is not valid 1422 E_HVD_ERR_AVC_SPS_NOT_IN_SPEC, 1423 E_HVD_ERR_AVC_SPS_NOT_ENOUGH_FRM, // DPB size at specified level is smaller than the specified number of reference frames. This is not allowed 1424 E_HVD_ERR_AVC_PPS_BROKEN, // PPS is not valid 1425 E_HVD_ERR_AVC_REF_LIST, 1426 E_HVD_ERR_AVC_NO_REF, 1427 E_HVD_ERR_AVC_RES, // out of supported resolution 1428 1429 // AVS 1430 E_HVD_ERR_AVS_BASE = (0x2000|E_HVD_ERR_BASE), 1431 E_HVD_ERR_AVS_RES, // out of supported resolution 1432 1433 // RM 1434 E_HVD_ERR_RM_BASE = (0x3000|E_HVD_ERR_BASE), 1435 E_HVD_ERR_RM_PACKET_HEADER, 1436 E_HVD_ERR_RM_FRAME_HEADER, 1437 E_HVD_ERR_RM_SLICE_HEADER, 1438 E_HVD_ERR_RM_BYTE_CNT, 1439 E_HVD_ERR_RM_DISP_TIMEOUT, 1440 E_HVD_ERR_RM_NO_REF, 1441 E_HVD_ERR_RM_RES, // out of supported resolution 1442 E_HVD_ERR_RM_VLC, 1443 E_HVD_ERR_RM_SIZE_OUT_FB_LAYOUT, 1444 1445 // VP8 1446 E_HVD_ERR_VP8_BASE = (0x4000|E_HVD_ERR_BASE), 1447 E_HVD_ERR_VP8_RES, // out of supported resolution 1448 } HVD_Err_Code; 1449 1450 1451 typedef enum 1452 { 1453 E_HVD_USER_DATA_DECODE_ORDER = 0, //default use display order 1454 E_HVD_USER_DATA_DISPLAY_ORDER, 1455 1456 }HVD_USER_DATA_SHOW_ORDER; 1457 1458 1459 typedef enum 1460 { 1461 E_HVD_ES_BUF_STATUS_UNKNOWN = 0, 1462 E_HVD_ES_BUF_STATUS_UNDERFLOW = 1, 1463 E_HVD_ES_BUF_STATUS_OVERFLOW = 2, 1464 E_HVD_ES_BUF_STATUS_NORMAL = 3, 1465 1466 }HVD_ES_Buf_Status; 1467 1468 1469 typedef enum 1470 { 1471 E_HVD_SEAMLESS_PAUSE_DECODE = BIT(0), 1472 E_HVD_SEAMLESS_DISPLAY_REPEATING = BIT(1), 1473 E_HVD_SEAMLESS_RESET_HW_DONE = BIT(2), 1474 E_HVD_SEAMLESS_TARGET_FRM_FOUND = BIT(3), 1475 }HVD_Seamless_Status; 1476 1477 #endif // _FW_HVD_IF_H_ 1478 1479