1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
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91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #include "drvHVD_Common.h"
101
102 // Internal Definition
103 #include "drvHVD_def.h"
104 #include "fwHVD_if.h"
105 #include "halHVD.h"
106 #include "regHVD.h"
107 #include "halVPU.h"
108
109 //-------------------------------------------------------------------------------------------------
110 // Driver Compiler Options
111 //-------------------------------------------------------------------------------------------------
112
113 #ifndef REDLION_LINUX_KERNEL_ENVI
114 #if defined(MSOS_TYPE_NOS) //T8, temp define for bring up
115 #if defined(__aarch64__)
116 #define HVD_CACHE_TO_UNCACHE_CONVERT
117 #endif
118 #endif
119 #endif
120
121 //-------------------------------------------------------------------------------------------------
122 // Local Defines
123 //-------------------------------------------------------------------------------------------------
124 #define RV_VLC_TABLE_SIZE 0x20000
125
126 #if HVD_ENABLE_EMBEDDED_FW_BINARY
127
128 static MS_U8 u8HVD_FW_Binary[] =
129 {
130 #include "fwHVD.dat"
131 };
132 #if HVD_ENABLE_RV_FEATURE
133 static MS_U8 u8HVD_VLC_Binary[] =
134 {
135 #include "fwHVD_VLC.dat"
136 };
137 #endif
138
139 #endif
140
141 static HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
142 static MS_U32 u32PTSRptrAddr=0;
143 static MS_U32 u32PTSWptrAddr=0;
144 static MS_U32 u32PTSPreWptr=0;
145 static HVD_PTS_Entry PTSEntry;
146 static MS_U32 u32PTSByteCnt=0;
147 static MS_U32 u32BBUWptr=0;
148 static MS_U8 g_hvd_nal_fill_pair[2][8] = {{0,0,0,0,0,0,0,0}, { 0,0,0,0,0,0,0,0}};
149 static MS_U32 u32BBUEntryNum=0;
150 static MS_U32 u32BBUEntryNumTH=0;
151 static MS_U32 u32RV_VLCTableAddr=0; // offset from Frame buffer start address
152 //---------------------------------- Mutex settings -----------------------------------------
153 #if HAL_HVD_ENABLE_MUTEX_PROTECT
154 static MS_S32 s32HVDMutexID=-1;
155 static MS_U8 _u8HVD_Mutex[] = {"HVD_Mutex"};
156
157 #define _HAL_HVD_MutexCreate() \
158 if( s32HVDMutexID < 0 ) \
159 { \
160 s32HVDMutexID = OSAL_HVD_MutexCreate( _u8HVD_Mutex ); \
161 }
162 #define _HAL_HVD_MutexDelete() \
163 if( s32HVDMutexID >= 0 ) \
164 { \
165 OSAL_HVD_MutexDelete(s32HVDMutexID); \
166 s32HVDMutexID = -1; \
167 }
168 #define _HAL_HVD_Entry() \
169 if( s32HVDMutexID >= 0 ) \
170 { \
171 if (!OSAL_HVD_MutexObtain(s32HVDMutexID, OSAL_HVD_MUTEX_TIMEOUT)) \
172 { \
173 printf("[HAL HVD][%06d] Mutex taking timeout\n", __LINE__); \
174 } \
175 }
176 #define _HAL_HVD_Return(_ret) \
177 { \
178 if( s32HVDMutexID >= 0 ) \
179 { \
180 OSAL_HVD_MutexRelease(s32HVDMutexID); \
181 } \
182 return _ret; \
183 }
184 #define _HAL_HVD_Release() \
185 { \
186 if( s32HVDMutexID >= 0 ) \
187 { \
188 OSAL_HVD_MutexRelease(s32HVDMutexID); \
189 } \
190 }
191
192
193 #else // HAL_HVD_ENABLE_MUTEX_PROTECT
194
195 #define _HAL_HVD_MutexCreate()
196 #define _HAL_HVD_MutexDelete()
197 #define _HAL_HVD_Entry()
198 #define _HAL_HVD_Return(_ret) {return _ret;}
199 #define _HAL_HVD_Release()
200
201 #endif // HAL_HVD_ENABLE_MUTEX_PROTECT
202
203 //------------------------------ MIU SETTINGS ----------------------------------
204 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
205 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
206 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(2))
207 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(1))
208
209 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
210 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
211 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(2))
212 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(1))
213
214 #define HVD_MVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(4)) == BIT(4))
215 #define HVD_MVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12))
216 #define HVD_HVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(2)) == BIT(2))
217 #define HVD_HVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(1)) == BIT(1))
218
219 #define _HVD_MIU_SetReqMask( miu_clients, mask ) \
220 do { \
221 if (HVD_##miu_clients##_ON_MIU1 == 0) \
222 _MaskMiuReq_##miu_clients( mask ); \
223 else \
224 _MaskMiu1Req_##miu_clients( mask ); \
225 }while(0)
226
227 // check RM is supported or not
228 #define HVD_HW_RUBBER3 (HAL_HVD_Get_HWVersionID()& BIT(14) )
229 //-------------------------------------------------------------------------------------------------
230 // Local Structures
231 //-------------------------------------------------------------------------------------------------
232
233
234 //-------------------------------------------------------------------------------------------------
235 // Global Variables
236 //-------------------------------------------------------------------------------------------------
237
238
239 //-------------------------------------------------------------------------------------------------
240 // Local Variables
241 //-------------------------------------------------------------------------------------------------
242 static volatile HVD_ShareMem *pHVDShareMem = NULL;
243 static HVD_Drv_Ctrl *pHVDCtrl_Hal = NULL;
244 static HVD_Pre_Ctrl *pHVDPreCtrl_Hal = NULL;
245 static MS_U32 u32HVDCmdTimeout = 0;
246 static MS_U32 u32VPUClockType = 216;
247 static MS_U32 u32HVDClockType = 216;//144;
248
249 #if defined (__aeon__)
250 static MS_U32 u32HVDRegOSBase = 0xA0200000;
251 #else
252 static MS_U32 u32HVDRegOSBase = 0xBF200000;
253 #endif
254
255 #if defined(UDMA_FPGA_ENVI)
256 static HVD_ShareMem UDMA_pc_HVDShareMem;
257 static MS_U32 UDMA_fpga_HVDShareMemAddr;
258 #endif
259 //-------------------------------------------------------------------------------------------------
260 // Debug Functions
261 //-------------------------------------------------------------------------------------------------
262
263
264 //-------------------------------------------------------------------------------------------------
265 // Local Functions
266 //-------------------------------------------------------------------------------------------------
267 MS_U32 _HAL_HVD_GetBBUQNumb(void);
268
269
_HAL_HVD_GetBBUReadptr(void)270 static MS_U16 _HAL_HVD_GetBBUReadptr(void)
271 {
272 MS_U16 u16Ret=0;
273 //_HAL_HVD_Entry();
274 _HVD_WriteWordMask( HVD_REG_POLL_NAL_RPTR , 0 , HVD_REG_POLL_NAL_RPTR_BIT );
275 _HVD_WriteWordMask( HVD_REG_POLL_NAL_RPTR , HVD_REG_POLL_NAL_RPTR_BIT , HVD_REG_POLL_NAL_RPTR_BIT );
276 u16Ret = _HVD_Read2Byte( HVD_REG_NAL_RPTR_HI );
277 //_HAL_HVD_Return( u16Ret);
278 return u16Ret;
279 }
280
_HAL_HVD_SetBBUWriteptr(MS_U16 u16BBUNewWptr)281 static void _HAL_HVD_SetBBUWriteptr(MS_U16 u16BBUNewWptr )
282 {
283 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI, u16BBUNewWptr );
284 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR , HVD_REG_NAL_WPTR_SYNC , HVD_REG_NAL_WPTR_SYNC); // set bit 3
285 }
286
_HAL_HVD_MBoxSend(MS_U8 u8MBox,MS_U32 u32Msg)287 static MS_BOOL _HAL_HVD_MBoxSend(MS_U8 u8MBox, MS_U32 u32Msg)
288 {
289 MS_BOOL bResult = TRUE;
290 switch(u8MBox)
291 {
292 case E_HVD_HI_0:
293 _HVD_Write4Byte(HVD_REG_HI_MBOX0_L, u32Msg);
294 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET, HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET);
295 break;
296
297 case E_HVD_HI_1:
298 _HVD_Write4Byte(HVD_REG_HI_MBOX1_L, u32Msg);
299 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET, HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET);
300 break;
301 case E_HVD_VPU_HI_0:
302 bResult=HAL_VPU_MBoxSend( VPU_HI_MBOX0 , u32Msg );
303 break;
304
305 case E_HVD_VPU_HI_1:
306 bResult=HAL_VPU_MBoxSend( VPU_HI_MBOX1 , u32Msg );
307 break;
308 default:
309 bResult = FALSE;
310 break;
311 }
312
313 return bResult;
314 }
315
_HAL_HVD_MBoxReady(MS_U8 u8MBox)316 static MS_BOOL _HAL_HVD_MBoxReady(MS_U8 u8MBox)
317 {
318 MS_BOOL bResult = TRUE;
319 switch(u8MBox)
320 {
321 case E_HVD_HI_0:
322 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY, HVD_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
323 break;
324 case E_HVD_HI_1:
325 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY, HVD_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
326 break;
327 case E_HVD_RISC_0:
328 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY, HVD_REG_RISC_MBOX0_RDY) ? TRUE: FALSE;
329 break;
330 case E_HVD_RISC_1:
331 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY, HVD_REG_RISC_MBOX1_RDY) ? TRUE: FALSE;
332 break;
333 case E_HVD_VPU_HI_0:
334 bResult = HAL_VPU_MBoxRdy( VPU_HI_MBOX0);
335 break;
336 case E_HVD_VPU_HI_1:
337 bResult = HAL_VPU_MBoxRdy( VPU_HI_MBOX1);
338 break;
339 case E_HVD_VPU_RISC_0:
340 bResult = HAL_VPU_MBoxRdy( VPU_RISC_MBOX0);
341 break;
342 case E_HVD_VPU_RISC_1:
343 bResult = HAL_VPU_MBoxRdy( VPU_RISC_MBOX1);
344 break;
345 default:
346 break;
347 }
348 return bResult;
349 }
350
_HAL_HVD_MBoxRead(MS_U8 u8MBox,MS_U32 * u32Msg)351 static MS_BOOL _HAL_HVD_MBoxRead(MS_U8 u8MBox, MS_U32 *u32Msg)
352 {
353 MS_BOOL bResult = TRUE;
354 switch(u8MBox)
355 {
356 case E_HVD_HI_0:
357 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX0_L);
358 break;
359 case E_HVD_HI_1:
360 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX1_L);
361 break;
362 case E_HVD_RISC_0:
363 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX0_L);
364 break;
365 case E_HVD_RISC_1:
366 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX1_L);
367 break;
368 case E_HVD_VPU_RISC_0:
369 bResult=HAL_VPU_MBoxRead( VPU_RISC_MBOX0 , u32Msg );
370 break;
371 case E_HVD_VPU_RISC_1:
372 bResult=HAL_VPU_MBoxRead( VPU_RISC_MBOX1 , u32Msg );
373 break;
374 default:
375 bResult = FALSE;
376 break;
377 }
378 return bResult;
379 }
380
_HAL_HVD_MBoxClear(MS_U8 u8MBox)381 static void _HAL_HVD_MBoxClear(MS_U8 u8MBox)
382 {
383 switch(u8MBox)
384 {
385 case E_HVD_RISC_0:
386 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR , HVD_REG_RISC_MBOX0_CLR);
387 break;
388 case E_HVD_RISC_1:
389 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR , HVD_REG_RISC_MBOX1_CLR);
390 break;
391 case E_HVD_VPU_RISC_0:
392 HAL_VPU_MBoxClear( VPU_RISC_MBOX0 );
393 break;
394 case E_HVD_VPU_RISC_1:
395 HAL_VPU_MBoxClear( VPU_RISC_MBOX1 );
396 break;
397 default:
398 break;
399 }
400 }
401
HAL_HVD_Dump_HW_Status(MS_U32 numb)402 void HAL_HVD_Dump_HW_Status(MS_U32 numb)
403 {
404 MS_U32 i=0;
405 MS_U32 value=0;
406 HVD_MSG_DEG("HVD Dump HW status:");
407 for( i=0 ; i <= numb ; i++ )
408 {
409 _HVD_Write2Byte(HVD_REG_DEBUG_SEL, i);
410 value = _HVD_Read2Byte(HVD_REG_DEBUG_DAT_L);
411 value |= ((MS_U32)_HVD_Read2Byte(HVD_REG_DEBUG_DAT_H))<<16;
412 if( value == 0 )
413 {
414 break;
415 }
416 HVD_MSG_DEG(" %lx" , value );
417 if( ((i % 8)+1) ==8)
418 {
419 HVD_MSG_DEG(" |%lu\n" , i +1 );
420 }
421 }
422 HVD_MSG_DEG("\nHVD Dump HW status End: total number:%lu\n" , i );
423 }
424
_HAL_HVD_GetPC(void)425 static MS_U32 _HAL_HVD_GetPC(void)
426 {
427 MS_U32 u32PC=0;
428 u32PC = HAL_VPU_GetProgCnt();
429 // HVD_MSG_DEG("<gdbg>pc0 =0x%lx\n",u32PC);
430 return u32PC;
431 }
432
_HAL_HVD_GetFWState(void)433 static MS_U32 _HAL_HVD_GetFWState(void)
434 {
435 MS_U32 u32Ret=0;
436 if( _HAL_HVD_MBoxRead(HAL_HVD_REG_FW_STATE , &u32Ret ))
437 {
438 return u32Ret;
439 }
440 else
441 {
442 return 0;
443 }
444 }
445
_HAL_HVD_GetESWritePtr(void)446 static MS_U32 _HAL_HVD_GetESWritePtr(void)
447 {
448 MS_U32 data=0;
449 if( (pHVDCtrl_Hal->InitParams.u32ModeFlag&E_HVD_INIT_INPUT_MASK )==E_HVD_INIT_INPUT_DRV)
450 {
451 data=pHVDCtrl_Hal->LastNal.u32NalAddr+pHVDCtrl_Hal->LastNal.u32NalSize;
452 if( data > pHVDCtrl_Hal->MemMap.u32BitstreamBufSize)
453 {
454 data-=pHVDCtrl_Hal->MemMap.u32BitstreamBufSize;
455 HVD_MSG_ERR( "HVD HAL: _HAL_HVD_GetESWritePtr(): app should not put this kind of packet\n");
456 }
457 }
458 else
459 {
460 data =pHVDShareMem->u32ESWritePtr;
461 }
462 return data;
463 }
464
_HAL_HVD_GetESReadPtr(MS_BOOL bDbug)465 static MS_U32 _HAL_HVD_GetESReadPtr(MS_BOOL bDbug)
466 {
467 MS_U32 data=0;
468
469 if(((pHVDCtrl_Hal->InitParams.u32ModeFlag&E_HVD_INIT_INPUT_MASK)==E_HVD_INIT_INPUT_DRV)
470 || (TRUE == bDbug))
471 {
472 // set reg_poll_nal_rptr 0
473 _HVD_WriteWordMask(HVD_REG_ESB_RPTR, 0, HVD_REG_ESB_RPTR_POLL);
474 // set reg_poll_nal_rptr 1
475 _HVD_WriteWordMask(HVD_REG_ESB_RPTR, HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL);
476 // read reg_nal_rptr_hi
477 #if 0
478 if( HVD_HW_RUBBER3 )
479 {
480 data=_HVD_Read2Byte( HVD_REG_ESB_RPTR ) & 0xFF80;
481 data>>=7;
482 data |= _HVD_Read2Byte( HVD_REG_ESB_RPTR_H ) << 9;
483 }
484 else // rubber2
485 #endif
486 //_HAL_HVD_Entry();
487 data=_HVD_Read2Byte( HVD_REG_ESB_RPTR ) & 0xFFC0;
488 data>>=6;
489 data |= _HVD_Read2Byte( HVD_REG_ESB_RPTR_H ) << 10;
490 //_HAL_HVD_Release();
491 // patch for XDemux
492 #if 0
493 /*
494 if( (pHVDCtrl_Hal->InitParams.u32ModeFlag&E_HVD_INIT_INPUT_MASK )==E_HVD_INIT_INPUT_DRV)
495 {
496 MS_U32 u32ESWptr=_HAL_HVD_GetESWritePtr();
497 MS_U32 u32ESWptrtmp=data<<3;
498 if( ( pHVDCtrl_Hal->u32LastESRptr < u32ESWptr )
499 && ( u32ESWptrtmp > u32ESWptr ) )
500 {
501 HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32ESWptrtmp , pHVDCtrl_Hal->u32LastESRptr, u32ESWptr );
502 }
503 }
504 */
505 if( data >= 1)
506 {
507 data -=1;
508 }
509 else
510 {
511 data=(pHVDCtrl_Hal->MemMap.u32BitstreamBufSize>>3)-1;
512 }
513
514 data<<=3;// unit
515
516 #else
517 data<<=3;// unit
518 if( (pHVDCtrl_Hal->InitParams.u32ModeFlag&E_HVD_INIT_INPUT_MASK )==E_HVD_INIT_INPUT_DRV)
519 {
520 MS_U32 u32ESWptr=_HAL_HVD_GetESWritePtr();
521 if( ( pHVDCtrl_Hal->u32LastESRptr < u32ESWptr )
522 && ( data > u32ESWptr ) )
523 {
524 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , data , pHVDCtrl_Hal->u32LastESRptr, u32ESWptr );
525 data = u32ESWptr;
526 }
527 else if( ( pHVDCtrl_Hal->u32LastESRptr == u32ESWptr )
528 && ( data > u32ESWptr ) )
529 {
530 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , data , pHVDCtrl_Hal->u32LastESRptr, u32ESWptr );
531 data = u32ESWptr;
532 }
533 else if( (_HAL_HVD_GetBBUQNumb() ==0) && (( data - u32ESWptr )< 32) && (( _HAL_HVD_GetFWState() & E_HVD_FW_STATE_MASK )==E_HVD_FW_PLAY))
534 {
535 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , data , pHVDCtrl_Hal->u32LastESRptr, u32ESWptr );
536 data = u32ESWptr;
537 }
538 else if (((data > u32ESWptr) && (pHVDCtrl_Hal->u32LastESRptr > data))
539 && ((data - u32ESWptr) < 32)
540 && (pHVDCtrl_Hal->u32FlushRstPtr == 1))
541 {
542 //HVD_MSG_INFO("444HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
543 data = u32ESWptr;
544 }
545 }
546 #endif
547 // remove illegal pointer
548 #if 1
549 if( (pHVDCtrl_Hal->MemMap.u32DrvProcessBufSize !=0) && (pHVDCtrl_Hal->MemMap.u32DrvProcessBufAddr !=0) )
550 {
551 MS_U32 u32PacketStaddr = data + pHVDCtrl_Hal->MemMap.u32BitstreamBufAddr;
552 if( ( (pHVDCtrl_Hal->MemMap.u32DrvProcessBufAddr <= u32PacketStaddr ) &&
553 (u32PacketStaddr < (pHVDCtrl_Hal->MemMap.u32DrvProcessBufAddr + pHVDCtrl_Hal->MemMap.u32DrvProcessBufSize)) ) )
554 {
555 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is located in drv process buffer(%lx %lx)\n" , data , pHVDCtrl_Hal->u32LastESRptr, pHVDCtrl_Hal->MemMap.u32DrvProcessBufAddr , pHVDCtrl_Hal->MemMap.u32DrvProcessBufSize );
556 data = pHVDCtrl_Hal->u32LastESRptr;
557 }
558 }
559 #endif
560 }
561 else
562 {
563 data =pHVDShareMem->u32ESReadPtr;
564 }
565
566 pHVDCtrl_Hal->u32LastESRptr = data;
567 //return data;
568 return data;
569 }
570
_HAL_HVD_SetCMDArg(MS_U32 u32Arg)571 static MS_BOOL _HAL_HVD_SetCMDArg(MS_U32 u32Arg)
572 {
573 MS_U16 u16TimeOut = 0xFFFF;
574 MS_BOOL bResult = FALSE;
575
576 //HVD_MSG_DEG("Send argument 0x%lx to HVD \n", u32Arg);
577 while(--u16TimeOut)
578 {
579 if( _HAL_HVD_MBoxReady(HAL_HVD_CMD_MBOX)&&
580 _HAL_HVD_MBoxReady(HAL_HVD_CMD_ARG_MBOX))
581 {
582 bResult = _HAL_HVD_MBoxSend(HAL_HVD_CMD_ARG_MBOX, u32Arg);
583 break;
584 }
585 }
586 return bResult;
587 }
588
_HAL_HVD_SetCMD(MS_U32 u32Cmd)589 static MS_BOOL _HAL_HVD_SetCMD(MS_U32 u32Cmd)
590 {
591 MS_U16 u16TimeOut = 0xFFFF;
592 MS_BOOL bResult = FALSE;
593
594 //HVD_MSG_DEG("Send CMD 0x%lx to HVD \n", u32Cmd);
595 while(--u16TimeOut)
596 {
597 if(_HAL_HVD_MBoxReady(HAL_HVD_CMD_MBOX))
598 {
599 bResult = _HAL_HVD_MBoxSend(HAL_HVD_CMD_MBOX, u32Cmd);
600 break;
601 }
602 }
603 return bResult;
604 }
605
_HAL_HVD_SendCmd(MS_U32 u32Cmd,MS_U32 u32CmdArg)606 static HVD_Return _HAL_HVD_SendCmd( MS_U32 u32Cmd , MS_U32 u32CmdArg)
607 {
608 MS_U32 u32timeout= HVD_GetSysTime_ms() +u32HVDCmdTimeout ;
609 while( !_HAL_HVD_SetCMDArg( u32CmdArg ) )
610 {
611 if( HVD_GetSysTime_ms() > u32timeout )
612 {
613 HVD_MSG_ERR( "HVD cmd:%lx ;cmd arg timeout:%lx\n" , u32Cmd , u32CmdArg );
614 return E_HVD_RETURN_TIMEOUT;
615 }
616 if( u32Cmd == E_HVD_CMD_STOP )
617 {
618 _HAL_HVD_MBoxSend(HAL_HVD_CMD_MBOX, E_HVD_CMD_STOP);
619 _HAL_HVD_MBoxSend(HAL_HVD_CMD_ARG_MBOX, 0);
620 HVD_MSG_ERR( "HVD cmd force stop:%lx ;cmd arg:%lx\n" , u32Cmd , u32CmdArg );
621 return E_HVD_RETURN_SUCCESS;
622 }
623 //_HAL_HVD_GetPC();
624 HAL_HVD_Dump_FW_Status();
625 HAL_HVD_Dump_HW_Status(HVD_U32_MAX);
626 }
627 u32timeout= HVD_GetSysTime_ms() +u32HVDCmdTimeout ;
628 while( !_HAL_HVD_SetCMD( u32Cmd ) )
629 {
630 if( HVD_GetSysTime_ms() > u32timeout )
631 {
632 HVD_MSG_ERR( " cmd timeout: %lx\n" , u32Cmd );
633 return E_HVD_RETURN_TIMEOUT;
634 }
635 //_HAL_HVD_GetPC();
636 HAL_HVD_Dump_FW_Status();
637 HAL_HVD_Dump_HW_Status(HVD_U32_MAX);
638 }
639 return E_HVD_RETURN_SUCCESS;
640 }
641
_HAL_HVD_SetMIUProtectMask(MS_BOOL bEnable)642 static void _HAL_HVD_SetMIUProtectMask(MS_BOOL bEnable)
643 {
644 #if HAL_HVD_ENABLE_MIU_PROTECT
645 _HVD_MIU_SetReqMask(MVD_RW, bEnable);
646 _HVD_MIU_SetReqMask(MVD_BBU_R, bEnable);
647 _HVD_MIU_SetReqMask(HVD_RW, bEnable);
648 _HVD_MIU_SetReqMask(HVD_BBU_R, bEnable);
649 HAL_VPU_MIU_RW_Protect( bEnable );
650 //HVD_Delay_ms(1);
651 #endif
652 return;
653 }
654
_HAL_HVD_RstMVDParser(void)655 static void _HAL_HVD_RstMVDParser(void)
656 {
657 _HAL_HVD_SetMIUProtectMask(TRUE);
658 // _HVD_WriteRegBit(MVD_REG_STAT_CTRL, 1, MVD_REG_CTRL_RST|MVD_REG_CTRL_INIT);
659 _HVD_WriteWordMask(MVD_REG_STAT_CTRL, MVD_REG_CTRL_RST|MVD_REG_DISCONNECT_MIU, MVD_REG_CTRL_RST|MVD_REG_DISCONNECT_MIU);
660 HVD_Delay_ms(1); // Delay 2ms to make MVD reset complete
661 _HVD_WriteWordMask(MVD_REG_STAT_CTRL, 0, MVD_REG_CTRL_RST|MVD_REG_DISCONNECT_MIU);
662 _HAL_HVD_SetMIUProtectMask(FALSE);
663 return;
664 }
665
_HAL_SVD_Release(void)666 static void _HAL_SVD_Release(void)
667 {
668 // release SW reset
669 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST);
670
671 // release cpu rst
672 HAL_VPU_SwRstRelse();
673 }
674
_HAL_HVD_SetBufferAddr(void)675 static void _HAL_HVD_SetBufferAddr(void)
676 {
677 MS_U16 u16Reg = 0;
678 MS_U32 u32StAddr = 0;
679 MS_BOOL bBitMIU1 = FALSE;
680 MS_BOOL bCodeMIU1 = FALSE;
681
682 // nal table settngs
683 if(pHVDCtrl_Hal->MemMap.u32CodeBufAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr)
684 {
685 bCodeMIU1 = TRUE;
686 }
687 if(pHVDCtrl_Hal->MemMap.u32BitstreamBufAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr)
688 {
689 bBitMIU1 = TRUE;
690 }
691 if(bBitMIU1 != bCodeMIU1)
692 {
693 u32StAddr = pHVDCtrl_Hal->MemMap.u32BitstreamBufAddr +
694 pHVDCtrl_Hal->u32BBUTblInBitstreamBufAddr;
695
696 if(u32StAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr)
697 {
698 u32StAddr -= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr;
699 }
700 }
701 else
702 {
703 u32StAddr = pHVDCtrl_Hal->MemMap.u32CodeBufAddr +
704 HVD_BBU_DRAM_ST_ADDR;
705
706 if(u32StAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr)
707 {
708 u32StAddr -= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr;
709 }
710 }
711 HVD_MSG_DEG("_HAL_HVD_SetBufferAddr: nal StAddr:%lx \n", u32StAddr);
712 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L, (MS_U16)(u32StAddr >> 3));
713 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H, (MS_U16)(u32StAddr >> 19));
714 // -1 is for NAL_TAB_LEN counts from zero.
715 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN, (MS_U16)(u32BBUEntryNum - 1));
716
717 // ES buffer
718 u32StAddr = pHVDCtrl_Hal->MemMap.u32BitstreamBufAddr;
719 if(u32StAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr)
720 {
721 u32StAddr -= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr;
722 }
723 HVD_MSG_DEG("_HAL_HVD_SetBufferAddr: ESb StAddr:%lx \n", u32StAddr);
724 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L, HVD_LWORD(u32StAddr >> 3));
725 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H, HVD_HWORD(u32StAddr >> 3));
726
727 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L,
728 HVD_LWORD(pHVDCtrl_Hal->MemMap.u32BitstreamBufSize >> 3));
729 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H,
730 HVD_HWORD(pHVDCtrl_Hal->MemMap.u32BitstreamBufSize >> 3));
731
732 // others
733 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU);
734 if((pHVDCtrl_Hal->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
735 {
736 u16Reg |= HVD_REG_BBU_TSP_INPUT;
737 }
738 else
739 {
740 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
741 }
742 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
743 if((pHVDCtrl_Hal->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
744 {
745 u16Reg |= HVD_REG_BBU_PASER_DISABLE; // force BBU to remove nothing, RM only
746 }
747 else // AVS or AVC
748 {
749 if((pHVDCtrl_Hal->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
750 {
751 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
752 }
753 else // start code remained
754 {
755 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
756 }
757 }
758 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
759 _HVD_Write2Byte(HVD_REG_MIF_BBU, u16Reg);
760
761 // MIF offset
762 #if 0
763 {
764 MS_U16 offaddr=0;
765 u32StAddr = pHVDCtrl_Hal->MemMap.u32CodeBufAddr;
766 if( u32StAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr )
767 {
768 u32StAddr-=pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr;
769 }
770 HVD_MSG_DEG("_HAL_HVD_SetBufferAddr: MIF offset:%lx \n" , u32StAddr);
771 offaddr = (MS_U16)((u32StAddr )>>20);
772 offaddr &= BMASK( HVD_REG_MIF_OFFSET_L_BITS :0 );//0x1FF; // 9 bits(L + H)
773 u16Reg=_HVD_Read2Byte(HVD_REG_MIF_BBU) ;
774 u16Reg&= ~HVD_REG_MIF_OFFSET_H ;
775 u16Reg&=~(BMASK( HVD_REG_MIF_OFFSET_L_BITS :0)) ;
776 if(offaddr & BIT( HVD_REG_MIF_OFFSET_L_BITS ) )
777 {
778 u16Reg |= HVD_REG_MIF_OFFSET_H;
779 }
780 _HVD_Write2Byte(HVD_REG_MIF_BBU,
781 (u16Reg | (offaddr & BMASK(HVD_REG_MIF_OFFSET_L_BITS:0))));
782 }
783 #endif
784 }
785
_HAL_HVD_GetESLevel(void)786 static MS_U32 _HAL_HVD_GetESLevel(void)
787 {
788 MS_U32 u32Wptr = 0;
789 MS_U32 u32Rptr = 0;
790 MS_U32 u32CurMBX=0;
791 MS_U32 u32ESsize =0;
792 MS_U32 u32Ret=E_HVD_ESB_LEVEL_NORMAL;
793
794 u32Wptr = _HAL_HVD_GetESWritePtr();
795 u32Rptr = _HAL_HVD_GetESReadPtr(FALSE);
796 u32ESsize = pHVDCtrl_Hal->MemMap.u32BitstreamBufSize;
797 if(u32Rptr >= u32Wptr)
798 {
799 u32CurMBX = u32Rptr - u32Wptr;
800 }
801 else
802 {
803 u32CurMBX = u32ESsize - (u32Wptr - u32Rptr);
804 }
805
806 if( u32CurMBX == 0)
807 {
808 u32Ret = E_HVD_ESB_LEVEL_UNDER;
809 }
810 else if (u32CurMBX < HVD_FW_AVC_ES_OVER_THRESHOLD)
811 {
812 u32Ret = E_HVD_ESB_LEVEL_OVER;
813 }
814 else
815 {
816 u32CurMBX = u32ESsize - u32CurMBX;
817 if (u32CurMBX < HVD_FW_AVC_ES_UNDER_THRESHOLD)
818 {
819 u32Ret = E_HVD_ESB_LEVEL_UNDER;
820 }
821 }
822 return u32Ret;
823 }
824
_HAL_HVD_SwCPURst(void)825 MS_BOOL _HAL_HVD_SwCPURst(void)
826 {
827 MS_U16 u16Timeout = 1000;
828
829 _HAL_HVD_SetMIUProtectMask(TRUE);
830
831 // re-setup clock.
832 HAL_HVD_PowerCtrl(TRUE);
833
834 HAL_VPU_SwRst();
835 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST , HVD_REG_RESET_SWRST);
836
837 while(u16Timeout)
838 {
839 if( (_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN))
840 == (HVD_REG_RESET_SWRST_FIN))
841 {
842 break;
843 }
844 u16Timeout--;
845 }
846
847 _HAL_HVD_SetMIUProtectMask(FALSE);
848
849 if( !u16Timeout )
850 {
851 HVD_MSG_ERR("_HAL_HVD_SwCPURst timeout \n");
852 }
853
854 return (u16Timeout>0) ? TRUE : FALSE;
855 }
856
_HAL_HVD_LoadVLCTable(HVD_FWInputSourceType eType)857 MS_BOOL _HAL_HVD_LoadVLCTable(HVD_FWInputSourceType eType )
858 {
859 #if HVD_ENABLE_RV_FEATURE
860 if( eType == E_HVD_FW_INPUT_SOURCE_FLASH )
861 {
862 #if HVD_ENABLE_BDMA_FW_FLASH_2_SDRAM
863 HVD_MSG_DEG("HVD Loading VLC outF2D: dest:0x%lx source:%lx size:%lx\n", (MS_U32)pHVDCtrl_Hal->MemMap.u32FrameBufAddr+u32RV_VLCTableAddr ,
864 ((MS_U32)pHVDCtrl_Hal->MemMap.u32VLCBinaryAddr) , (MS_U32)pHVDCtrl_Hal->MemMap.u32VLCBinarySize);
865 if( pHVDCtrl_Hal->MemMap.u32VLCBinarySize != 0 )
866 {
867 SPIDMA_Dev cpyflag=E_SPIDMA_DEV_MIU1;
868 if( pHVDCtrl_Hal->MemMap.u32FrameBufAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr )
869 {
870 cpyflag = E_SPIDMA_DEV_MIU1;
871 }
872 else
873 {
874 cpyflag = E_SPIDMA_DEV_MIU0;
875 }
876 if( !HVD_FLASHcpy( (MS_U32)pHVDCtrl_Hal->MemMap.u32FrameBufAddr+u32RV_VLCTableAddr , pHVDCtrl_Hal->MemMap.u32VLCBinaryAddr , pHVDCtrl_Hal->MemMap.u32VLCBinarySize , cpyflag ) )
877 {
878 HVD_MSG_ERR("HVD ERR: HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32FWBinaryAddr , pHVDCtrl_Hal->MemMap.u32FWBinarySize , (MS_U32)cpyflag );
879 return FALSE;
880 }
881 }
882 else
883 {
884 HVD_MSG_ERR("HVD ERR: During copy VLC from Flash to Dram, the source size of FW is zero\n");
885 return FALSE;
886 }
887 #else
888 HVD_MSG_ERR("HVD ERR: driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
889 return FALSE;
890 #endif
891 }
892 else
893 {
894 if( eType == E_HVD_FW_INPUT_SOURCE_DRAM)
895 {
896 if( (pHVDCtrl_Hal->MemMap.u32VLCBinaryVAddr!= 0) && ( pHVDCtrl_Hal->MemMap.u32VLCBinarySize!= 0 ) )
897 {
898 HVD_MSG_DEG("HVD Loading VLC outD2D: dest:0x%lx source:%lx size:%lx\n", pHVDCtrl_Hal->MemMap.u32FrameBufVAddr+u32RV_VLCTableAddr ,
899 ((MS_U32)pHVDCtrl_Hal->MemMap.u32VLCBinaryVAddr) , (MS_U32)pHVDCtrl_Hal->MemMap.u32VLCBinarySize);
900 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
901 BDMA_Result bdmaRlt;
902 MS_U32 u32DstAdd=0 , u32SrcAdd=0 , u32tabsize=0;
903 u32DstAdd = pHVDCtrl_Hal->MemMap.u32FrameBufVAddr+u32RV_VLCTableAddr;
904 u32SrcAdd = pHVDCtrl_Hal->MemMap.u32VLCBinaryVAddr;
905 u32tabsize = pHVDCtrl_Hal->MemMap.u32VLCBinarySize;
906 //bdmaRlt = MDrv_BDMA_MemCopy(u32SrcAdd, u32DstAdd, SLQ_TBL_SIZE);
907 HAL_HVD_FlushMemory();
908 bdmaRlt = HVD_dmacpy( u32DstAdd, u32SrcAdd, u32tabsize);
909 if (E_BDMA_OK != bdmaRlt)
910 {
911 HVD_MSG_ERR("HVD Err:MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
912 }
913 #else
914 HVD_memcpy( (void*)( pHVDCtrl_Hal->MemMap.u32FrameBufVAddr+u32RV_VLCTableAddr ),
915 (void*)(((MS_U32)pHVDCtrl_Hal->MemMap.u32VLCBinaryVAddr)) , pHVDCtrl_Hal->MemMap.u32VLCBinarySize);
916 #endif
917 }
918 else
919 {
920 HVD_MSG_ERR("HVD ERR: During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
921 return FALSE;
922 }
923 }
924 else
925 {
926 #if HVD_ENABLE_EMBEDDED_FW_BINARY
927 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
928 MS_U8 *pu8HVD_VLC_Binary;
929 pu8HVD_VLC_Binary = (MS_U8 *)((MS_U32)u8HVD_VLC_Binary | 0xA0000000);
930 HVD_MSG_DEG("HVD Loading VLC inD2D: dest:0x%lx source:%lx size:%lx\n", pHVDCtrl_Hal->MemMap.u32FrameBufVAddr+u32RV_VLCTableAddr,
931 ((MS_U32)pu8HVD_VLC_Binary) , (MS_U32)sizeof(u8HVD_VLC_Binary) );
932 HVD_memcpy( (void*)( pHVDCtrl_Hal->MemMap.u32FrameBufVAddr+u32RV_VLCTableAddr ),
933 (void*)((MS_U32)pu8HVD_VLC_Binary) , sizeof(u8HVD_VLC_Binary) );
934 #else
935 HVD_MSG_DEG("HVD Loading VLC inD2D: dest:0x%lx source:%lx size:%lx\n", pHVDCtrl_Hal->MemMap.u32FrameBufVAddr+u32RV_VLCTableAddr,
936 ((MS_U32)u8HVD_VLC_Binary) , (MS_U32)sizeof(u8HVD_VLC_Binary) );
937 HVD_memcpy( (void*)( pHVDCtrl_Hal->MemMap.u32FrameBufVAddr+u32RV_VLCTableAddr ),
938 (void*)((MS_U32)u8HVD_VLC_Binary) , sizeof(u8HVD_VLC_Binary) );
939 #endif
940 #else
941 HVD_MSG_ERR("HVD ERR: driver not enable to use embedded VLC binary.\n");
942 return FALSE;
943 #endif
944 }
945 }
946 #endif
947 return TRUE;
948 }
949
_HAL_HVD_SetRegCPU(void)950 MS_BOOL _HAL_HVD_SetRegCPU(void)
951 {
952 MS_U32 u32FirmVer = 0;
953 MS_U32 u32Timeout = 20000;
954 MS_BOOL bNeedReloadFW = TRUE;
955
956 HVD_MSG_DEG("HVD HW ver id: 0x%04lx\n", HAL_HVD_Get_HWVersionID() );
957
958 if(!_HAL_HVD_SwCPURst())
959 {
960 HVD_MSG_ERR("HVD reset failed...\n");
961 return FALSE;
962 }
963 #if HVD_ENABLE_TIME_MEASURE
964 HVD_MSG_MUST( "HVD Time Measure:%d (%s %d) \n" , HVD_GetSysTime_ms() - u32InitSysTimeBase , __FUNCTION__, __LINE__ );
965 #endif
966
967 //Check whether need to reload fw or not
968 if((TRUE == pHVDCtrl_Hal->bTurboFWMode)
969 && (FALSE == HAL_VPU_IsNeedReload(E_VPU_DECODER_HVD)))
970 {
971 bNeedReloadFW = FALSE;
972 }
973
974 if(TRUE == bNeedReloadFW)
975 {
976 //If we need to reload fw, need to reset vpu fw decoder type first.
977 HAL_VPU_SetFWDecoder(E_VPU_DECODER_NONE);
978
979 // load binary
980 if( pHVDCtrl_Hal->MemMap.eFWSourceType == E_HVD_FW_INPUT_SOURCE_FLASH )
981 {
982 #if HVD_ENABLE_BDMA_FW_FLASH_2_SDRAM
983 HVD_MSG_DEG("HVD Loading FW outF2D: dest:0x%lx source:%lx size:%lx\n", (MS_U32)pHVDCtrl_Hal->MemMap.u32CodeBufAddr ,
984 ((MS_U32)pHVDCtrl_Hal->MemMap.u32FWBinaryAddr) , (MS_U32)pHVDCtrl_Hal->MemMap.u32FWBinarySize);
985 if( pHVDCtrl_Hal->MemMap.u32FWBinarySize != 0 )
986 {
987 SPIDMA_Dev cpyflag=E_SPIDMA_DEV_MIU1;
988 if( pHVDCtrl_Hal->MemMap.u32CodeBufAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr )
989 {
990 cpyflag = E_SPIDMA_DEV_MIU1;
991 }
992 else
993 {
994 cpyflag = E_SPIDMA_DEV_MIU0;
995 }
996 if( !HVD_FLASHcpy( pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32FWBinaryAddr , pHVDCtrl_Hal->MemMap.u32FWBinarySize , cpyflag ) )
997 {
998 HVD_MSG_ERR("HVD ERR: HVD_BDMAcpy Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32FWBinaryAddr , pHVDCtrl_Hal->MemMap.u32FWBinarySize , (MS_U32)cpyflag );
999 return FALSE;
1000 }
1001 }
1002 else
1003 {
1004 HVD_MSG_ERR("HVD ERR: During copy FW from Flash to Dram, the source size of FW is zero\n");
1005 return FALSE;
1006 }
1007 #else
1008 HVD_MSG_ERR("HVD ERR: driver not enable to use BDMA copy FW Bin from flash 2 sdram.\n");
1009 return FALSE;
1010 #endif
1011 }
1012 else
1013 {
1014 if( pHVDCtrl_Hal->MemMap.eFWSourceType == E_HVD_FW_INPUT_SOURCE_DRAM)
1015 {
1016 if( (pHVDCtrl_Hal->MemMap.u32FWBinaryVAddr != 0) && ( pHVDCtrl_Hal->MemMap.u32FWBinarySize != 0 ) )
1017 {
1018 HVD_MSG_DEG("HVD Loading FW outD2D: dest:0x%lx source:%lx size:%lx\n", pHVDCtrl_Hal->MemMap.u32CodeBufVAddr ,
1019 ((MS_U32)pHVDCtrl_Hal->MemMap.u32FWBinaryVAddr) , (MS_U32)pHVDCtrl_Hal->MemMap.u32FWBinarySize);
1020 HVD_memcpy( (void*)( pHVDCtrl_Hal->MemMap.u32CodeBufVAddr ),
1021 (void*)(((MS_U32)pHVDCtrl_Hal->MemMap.u32FWBinaryVAddr)) , pHVDCtrl_Hal->MemMap.u32FWBinarySize);
1022 }
1023 else
1024 {
1025 HVD_MSG_ERR("HVD ERR: During copy FW from out Dram to Dram, the source size or virtual address of FW is zero\n");
1026 return FALSE;
1027 }
1028 }
1029 else
1030 {
1031 #if HVD_ENABLE_EMBEDDED_FW_BINARY
1032 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
1033 MS_U8 * pu8HVD_FW_Binary;
1034 pu8HVD_FW_Binary = (MS_U8 *)((MS_U32)u8HVD_FW_Binary | 0xA0000000);
1035 HVD_MSG_DEG("HVD Loading FW inD2D: dest:0x%lx source:%lx size:%lx\n", pHVDCtrl_Hal->MemMap.u32CodeBufVAddr ,
1036 ((MS_U32)pu8HVD_FW_Binary) , (MS_U32)sizeof(u8HVD_FW_Binary) );
1037 HVD_memcpy( (void*)( pHVDCtrl_Hal->MemMap.u32CodeBufVAddr ),
1038 (void*)((MS_U32)pu8HVD_FW_Binary), sizeof(u8HVD_FW_Binary) );
1039 #else
1040 HVD_MSG_DEG("HVD Loading FW inD2D: dest:0x%lx source:%lx size:%lx\n", pHVDCtrl_Hal->MemMap.u32CodeBufVAddr ,
1041 ((MS_U32)u8HVD_FW_Binary) , (MS_U32)sizeof(u8HVD_FW_Binary) );
1042 HVD_memcpy( (void*)( pHVDCtrl_Hal->MemMap.u32CodeBufVAddr ),
1043 (void*)((MS_U32)u8HVD_FW_Binary), sizeof(u8HVD_FW_Binary) );
1044 #endif
1045 #else
1046 HVD_MSG_ERR("HVD ERR: driver not enable to use embedded FW binary.\n");
1047 return FALSE;
1048 #endif
1049 }
1050 }
1051
1052 if( ((pHVDCtrl_Hal->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK )
1053 == E_HVD_INIT_HW_RM )
1054 {
1055 if( _HAL_HVD_LoadVLCTable( pHVDCtrl_Hal->MemMap.eFWSourceType ) == FALSE)
1056 {
1057 return FALSE;
1058 }
1059 }
1060 HAL_HVD_FlushMemory();
1061 //HVD_MSG_DEG("HVD FW data compare: dest:0x%lx %lx %lx source:%lx %lx %lx\n",
1062 // *(MS_U32*)(pHVDCtrl_Hal->MemMap.u32CodeBufVAddr+160) ,*(MS_U32*)(pHVDCtrl_Hal->MemMap.u32CodeBufVAddr+164),*(MS_U32*)(pHVDCtrl_Hal->MemMap.u32CodeBufVAddr+168),
1063 // *(MS_U32*)(u8HVD_FW_Binary+160) ,*(MS_U32*)(u8HVD_FW_Binary+164),*(MS_U32*)(u8HVD_FW_Binary+168));
1064
1065 //When complete loading fw, set vpu fw decoder type
1066 HAL_VPU_SetFWDecoder(E_VPU_DECODER_HVD);
1067
1068 HVD_MSG_DEG("HVD Load FW done\n" );
1069 }
1070
1071 {
1072 MS_U32 u32Addr = 0;
1073 u32Addr = pHVDCtrl_Hal->MemMap.u32CodeBufAddr;
1074 /* //From JANUS and the later chip, need not set the offset when VPU setting.
1075 if( u32Addr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr )
1076 {
1077 u32Addr-=pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr;
1078 }
1079 */
1080 HVD_MSG_DEG("_HAL_HVD_SetRegCPU: VPU settings:%lx \n" , u32Addr);
1081 HAL_VPU_CPUSetting(u32Addr);
1082 }
1083
1084 //HVD4, from JANUS and later chip
1085 switch( ((pHVDCtrl_Hal->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) )
1086 {
1087 case E_HVD_INIT_HW_AVS:
1088 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_AVS_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RESET_HK_RM_MODE );
1089 break;
1090 case E_HVD_INIT_HW_RM:
1091 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RM_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RESET_HK_RM_MODE );
1092 if( pHVDCtrl_Hal->InitParams.pRVFileInfo->RV_Version )// RV 9,10
1093 {
1094 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RV9_DEC_MODE , HVD_REG_RESET_HK_RV9_DEC_MODE );
1095 }
1096 else // RV 8
1097 {
1098 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_RV9_DEC_MODE );
1099 }
1100 break;
1101 //case E_HVD_INIT_HW_AVC:
1102 default:
1103 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RESET_HK_RM_MODE );
1104 break;
1105 }
1106
1107 //T8: use miu128bit
1108 HVD_MSG_DEG("(be)Miu128 bits Status = %x <<<<<<<\n",_HVD_Read2Byte(HVD_REG_RESET));
1109 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128));
1110 HVD_MSG_DEG("(af)Miu128 bits Status = %x <<<<<<<\n",_HVD_Read2Byte(HVD_REG_RESET));
1111
1112 _HAL_HVD_SetBufferAddr();
1113 _HAL_HVD_RstMVDParser();
1114
1115 // release sw and cpu rst
1116 _HAL_SVD_Release();
1117 HVD_MSG_DEG("HVD CPU/HW release done\n" );
1118
1119 while(u32Timeout)
1120 {
1121 u32FirmVer = HAL_HVD_GetData(E_HVD_GDATA_FW_INIT_DONE);
1122 if( u32FirmVer != 0)
1123 {
1124 u32FirmVer =HAL_HVD_GetData(E_HVD_GDATA_FW_VERSION_ID);
1125 break;
1126 }
1127 u32Timeout--;
1128 HVD_Delay_ms(1);
1129 }
1130 if(u32Timeout > 0)
1131 {
1132 HVD_MSG_DEG("HVD firmware version binary:0x%lx if:0x%lx\n", u32FirmVer , (MS_U32)HVD_FW_VERSION);
1133 }
1134 else
1135 {
1136 _HAL_HVD_GetPC();
1137 HVD_MSG_ERR("Cannot get HVD firmware version !!%x %lx \n" , (MS_S16)_HVD_Read2Byte(HVD_REG_RESET) , HAL_HVD_GetData(E_HVD_GDATA_FW_VERSION_ID));
1138 return FALSE;
1139 }
1140 #if HVD_ENABLE_TIME_MEASURE
1141 HVD_MSG_MUST( "HVD Time Measure:%d (%s %d) \n" , HVD_GetSysTime_ms() - u32InitSysTimeBase , __FUNCTION__, __LINE__ );
1142 #endif
1143
1144 return TRUE;
1145 }
1146
_HAL_HVD_UpdatePTSTable(HVD_BBU_Info * pInfo)1147 HVD_Return _HAL_HVD_UpdatePTSTable(HVD_BBU_Info* pInfo)
1148 {
1149 MS_U32 u32PTSWptr=HVD_U32_MAX;
1150 MS_U32 u32PTSRptr=HVD_U32_MAX;
1151 MS_U32 u32DestAddr=0;
1152
1153 // update R & W ptr
1154 u32PTSRptr = HAL_VPU_MemRead(u32PTSRptrAddr);
1155
1156 if (0xFFFFFFFF == u32PTSRptr)
1157 {
1158 return E_HVD_RETURN_FAIL;
1159 }
1160
1161 //HVD_MSG_DEG("HVD PTS table RPtr:%lx Wptr:%lx\n" ,u32PTSRptr , HAL_VPU_MemRead( u32PTSWptrAddr ) );
1162
1163 if( u32PTSRptr >= MAX_PTS_TABLE_SIZE )
1164 {
1165 HVD_MSG_ERR("HVD ERR: PTS table Read Ptr(%lx) > max table size(%lx) \n" ,u32PTSRptr ,(MS_U32)MAX_PTS_TABLE_SIZE);
1166 return E_HVD_RETURN_FAIL;
1167 }
1168 // check queue is full or not
1169 u32PTSWptr = u32PTSPreWptr + 1;
1170 u32PTSWptr %= MAX_PTS_TABLE_SIZE;
1171 if( u32PTSWptr == u32PTSRptr )
1172 {
1173 HVD_MSG_ERR("HVD ERR: PTS table full. Read Ptr(%lx) == new Write ptr(%lx) ,Pre Wptr(%lx) \n" ,u32PTSRptr,u32PTSWptr , u32PTSPreWptr );
1174 return E_HVD_RETURN_FAIL;
1175 }
1176 // add one PTS entry
1177 PTSEntry.u32ByteCnt =u32PTSByteCnt&HVD_BYTE_COUNT_MASK;
1178 PTSEntry.u32ID_L=pInfo->u32ID_L;
1179 PTSEntry.u32ID_H=pInfo->u32ID_H;
1180 PTSEntry.u32PTS=pInfo->u32TimeStamp;
1181 #if defined(UDMA_FPGA_ENVI)
1182 u32DestAddr=(pHVDCtrl_Hal->MemMap.u32CodeBufAddr ) +HVD_PTS_TABLE_ST_OFFSET+(u32PTSPreWptr*sizeof(HVD_PTS_Entry));
1183 HVD_UDMA_memcpy( (void*)u32DestAddr , &PTSEntry , sizeof(HVD_PTS_Entry ) );
1184 #else
1185 u32DestAddr=(pHVDCtrl_Hal->MemMap.u32CodeBufVAddr ) +HVD_PTS_TABLE_ST_OFFSET+(u32PTSPreWptr*sizeof(HVD_PTS_Entry));
1186 HVD_memcpy( (void*)u32DestAddr , &PTSEntry , sizeof(HVD_PTS_Entry ) );
1187 HAL_HVD_FlushMemory();
1188 #endif
1189
1190 // update Write ptr
1191 if( !HAL_VPU_MemWrite( u32PTSWptrAddr , u32PTSWptr) )
1192 {
1193 HVD_MSG_ERR("HVD ERR: PTS table SRAM write failed\n" );
1194 return E_HVD_RETURN_FAIL;
1195 }
1196
1197 u32PTSPreWptr=u32PTSWptr;
1198
1199 return E_HVD_RETURN_SUCCESS;
1200 }
1201
_HAL_HVD_UpdateESWptr(MS_U32 nal_offset,MS_U32 nal_len)1202 HVD_Return _HAL_HVD_UpdateESWptr(MS_U32 nal_offset , MS_U32 nal_len)
1203 {
1204 //---------------------------------------------------
1205 // item format in nal table:
1206 // reserved |borken| nal_offset | nal_len
1207 // 13 bits |1bit | 29 bits | 21 bits (total 8 bytes)
1208 //---------------------------------------------------
1209 MS_U32 addr=0;
1210 MS_U32 u32BBUNewWptr = 0;
1211 MS_U8 item[8];
1212
1213 // MS_U8 pbuf[HVD_MAX_PACKET_SIZE]; // temp buffer
1214 u32BBUNewWptr=u32BBUWptr;
1215 u32BBUNewWptr++;
1216 u32BBUNewWptr%=u32BBUEntryNum;
1217
1218 // prepare nal entry
1219 item[0] = nal_len & 0xff;
1220 item[1] = (nal_len >> 8) & 0xff;
1221 item[2] = ((nal_len >> 16) & 0x1f ) | ((nal_offset<<5) & 0xe0);
1222 item[3] = (nal_offset>>3) & 0xff;
1223 item[4] = (nal_offset>>11) & 0xff;
1224 item[5] = (nal_offset>>19) & 0xff;
1225 item[6] = (nal_offset>>27) & 0x07; //including broken bit
1226 item[7] = 0;
1227
1228 // add nal entry
1229 #if defined(UDMA_FPGA_ENVI)
1230 if(u32BBUWptr%2==0)
1231 {
1232 g_hvd_nal_fill_pair[0][0] = item[0];
1233 g_hvd_nal_fill_pair[0][1] = item[1];
1234 g_hvd_nal_fill_pair[0][2] = item[2];
1235 g_hvd_nal_fill_pair[0][3] = item[3];
1236 g_hvd_nal_fill_pair[0][4] = item[4];
1237 g_hvd_nal_fill_pair[0][5] = item[5];
1238 g_hvd_nal_fill_pair[0][6] = item[6];
1239 g_hvd_nal_fill_pair[0][7] = item[7];
1240 g_hvd_nal_fill_pair[1][0] = 0;
1241 g_hvd_nal_fill_pair[1][1] = 0;
1242 g_hvd_nal_fill_pair[1][2] = 0;
1243 g_hvd_nal_fill_pair[1][3] = 0;
1244 g_hvd_nal_fill_pair[1][4] = 0;
1245 g_hvd_nal_fill_pair[1][5] = 0;
1246 g_hvd_nal_fill_pair[1][6] = 0;
1247 g_hvd_nal_fill_pair[1][7] = 0;
1248 }
1249 else
1250 {
1251 g_hvd_nal_fill_pair[1][0] = item[0];
1252 g_hvd_nal_fill_pair[1][1] = item[1];
1253 g_hvd_nal_fill_pair[1][2] = item[2];
1254 g_hvd_nal_fill_pair[1][3] = item[3];
1255 g_hvd_nal_fill_pair[1][4] = item[4];
1256 g_hvd_nal_fill_pair[1][5] = item[5];
1257 g_hvd_nal_fill_pair[1][6] = item[6];
1258 g_hvd_nal_fill_pair[1][7] = item[7];
1259 }
1260 addr = pHVDCtrl_Hal->MemMap.u32CodeBufAddr + HVD_BBU_DRAM_ST_ADDR + ((u32BBUWptr-(u32BBUWptr%2))<<3);
1261 HVD_UDMA_memcpy((void*)addr, (void*)g_hvd_nal_fill_pair, 16);
1262 #else
1263 addr = (pHVDCtrl_Hal->MemMap.u32CodeBufVAddr)+ HVD_BBU_DRAM_ST_ADDR + (u32BBUWptr<<3);
1264 HVD_memcpy((void*)addr, (void*)item, 8);
1265 HAL_HVD_FlushMemory();
1266 //HVD_MSG_DEG( "in UpdateESWptr:%lx %lx %lx\n" , addr , pHVDCtrl_Hal->MemMap.u32CodeBufVAddr , u32BBUWptr );
1267 #endif
1268 // add nal ptr
1269 //_HAL_HVD_SetBBUWriteptr( HVD_LWORD(u32BBUNewWptr) );
1270 u32BBUWptr = u32BBUNewWptr;
1271
1272 return E_HVD_RETURN_SUCCESS;
1273 }
1274
_HAL_HVD_GetVUIDispInfo(void)1275 static MS_U32 _HAL_HVD_GetVUIDispInfo(void)
1276 {
1277 if( (pHVDCtrl_Hal->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC)
1278 {
1279 MS_U32 VUIstaddr = 0;
1280 MS_U16 u16Count=0;
1281 MS_U32 *pData = (MS_U32 *)(&g_hvd_VUIINFO);
1282 HAL_HVD_ReadMemory();
1283 VUIstaddr=pHVDShareMem->u32AVC_VUIDispInfo_Addr;
1284 for(u16Count =0; u16Count < sizeof(HVD_AVC_VUI_DISP_INFO); u16Count+=4)
1285 {
1286 *pData = HAL_VPU_MemRead(VUIstaddr + u16Count);
1287 pData++;
1288 }
1289 }
1290 else
1291 {
1292 HVD_memset( &g_hvd_VUIINFO , 0 , sizeof(HVD_AVC_VUI_DISP_INFO) );
1293 }
1294 return (MS_U32 )(&g_hvd_VUIINFO);
1295 }
1296
_HAL_HVD_GetBBUQNumb(void)1297 MS_U32 _HAL_HVD_GetBBUQNumb(void)
1298 {
1299 MS_U32 u32ReadPtr=0;
1300 MS_U32 eRet=0;
1301
1302 u32ReadPtr =_HAL_HVD_GetBBUReadptr();
1303 //HVD_MSG_DEG("_HAL_HVD_GetBBUQNumb:%lx %lx %lx\n" , u32ReadPtr , u32BBUWptr ,(MS_U32)u32BBUEntryNum );
1304 if( u32BBUWptr >= u32ReadPtr )
1305 {
1306 eRet = u32BBUWptr - u32ReadPtr;
1307 }
1308 else
1309 {
1310 eRet = u32BBUEntryNum -( u32ReadPtr -u32BBUWptr );
1311 }
1312 return eRet;
1313 }
1314
_HAL_HVD_GetPTSQNumb(void)1315 MS_U32 _HAL_HVD_GetPTSQNumb(void)
1316 {
1317 MS_U32 u32ReadPtr=0;
1318 MS_U32 eRet=0;
1319
1320 u32ReadPtr = HAL_VPU_MemRead(u32PTSRptrAddr);
1321
1322 if (0xFFFFFFFF == u32ReadPtr)
1323 {
1324 return 0;
1325 }
1326
1327 if( u32ReadPtr >= MAX_PTS_TABLE_SIZE )
1328 {
1329 HVD_MSG_ERR("HVD ERR: GetPTSQNumb: PTS table Read Ptr(%lx) > max table size(%lx) \n" ,u32ReadPtr ,(MS_U32)MAX_PTS_TABLE_SIZE);
1330 return 0;
1331 }
1332 //HVD_MSG_DEG("_HAL_HVD_GetBBUQNumb:%lx %lx %lx\n" , u32ReadPtr , u32BBUWptr ,(MS_U32)u32BBUEntryNum );
1333 if( u32PTSPreWptr >= u32ReadPtr )
1334 {
1335 eRet = u32PTSPreWptr - u32ReadPtr;
1336 }
1337 else
1338 {
1339 eRet = MAX_PTS_TABLE_SIZE -( u32ReadPtr -u32PTSPreWptr );
1340 }
1341
1342 return eRet;
1343 }
1344
1345 #define _HVD_DQ
1346 #ifdef _HVD_DQ
1347 #define HVD_DISPQ_PREFETCH_COUNT 2
1348 static MS_U16 _u16DispQPtr = 0;
_HAL_HVD_GetNextDispFrame(void)1349 static HVD_Frm_Information* _HAL_HVD_GetNextDispFrame(void)
1350 {
1351 MS_U16 u16QNum = pHVDShareMem->u16DispQNumb;
1352 MS_U16 u16QPtr = pHVDShareMem->u16DispQPtr;
1353 static volatile HVD_Frm_Information *pHvdFrm = NULL;
1354
1355 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT) u16QNum = HVD_DISPQ_PREFETCH_COUNT;
1356
1357 //printf("Q: %d %d\n", u16QNum, u16QPtr);
1358 //search the next frame to display
1359 while (u16QNum != 0)
1360 {
1361 pHvdFrm = (volatile HVD_Frm_Information *)&pHVDShareMem->DispQueue[u16QPtr];
1362
1363 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
1364 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
1365 {
1366 _u16DispQPtr = u16QPtr;
1367 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
1368 HVD_MSG_DEG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%ld\n", u16QPtr,
1369 (MS_U32)pHvdFrm, pHVDShareMem->DispQueue[u16QPtr].u32TimeStamp);
1370 HVD_MSG_INFO("<<< halHVD pts,idH = %lu, %lu [%x]\n", pHvdFrm->u32TimeStamp, pHvdFrm->u32ID_H, u16QPtr); //STS output
1371 return (HVD_Frm_Information *)pHvdFrm;
1372 }
1373 u16QNum--;
1374 //go to next frame in the dispQ
1375 u16QPtr++;
1376 if (u16QPtr == pHVDShareMem->u16DispQSize) u16QPtr = 0; //wrap to the begin
1377 }
1378 return NULL;
1379 }
1380 #endif
1381
HAL_HVD_FlushMemory(void)1382 void HAL_HVD_FlushMemory(void)
1383 {
1384 MsOS_FlushMemory();
1385 }
1386
HAL_HVD_ReadMemory(void)1387 void HAL_HVD_ReadMemory(void)
1388 {
1389 MsOS_ReadMemory();
1390 }
1391
HAL_HVD_CheckMIUSel(MS_BOOL bChange)1392 void HAL_HVD_CheckMIUSel(MS_BOOL bChange)
1393 {
1394 #if 1
1395 return;
1396 #else
1397 #if defined(CHIP_U3)
1398 if( pHVDCtrl_Hal->InitParams.bDynamicScaling )
1399 {
1400 if( pHVDCtrl_Hal->MemMap.u32DynSacalingBufAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr )
1401 {
1402 if( !((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(13)) == BIT(13)) )
1403 {
1404 HVD_MSG_ERR("HVD Drv Err: dynamic scaling address(%lx) is at MIU1, but MIU sel is set(VPU qdma WR) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(13)) );
1405 if( bChange )
1406 {
1407 // VPU qdma WR
1408 _HVD_WriteWordMask(MIU0_REG_SEL2 , BIT(13), BIT(13));
1409 }
1410 }
1411 }
1412 else
1413 {
1414 if( ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(13)) == BIT(13)) )
1415 {
1416 HVD_MSG_ERR("HVD Drv Err: dynamic scaling address(%lx) is at MIU0, but MIU sel is set(VPU qdma WR) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(13)) );
1417 if( bChange )
1418 {
1419 // VPU qdma WR
1420 _HVD_WriteWordMask(MIU0_REG_SEL2 , BIT(13), BIT(13));
1421 }
1422 }
1423 }
1424 }
1425 #endif
1426
1427 if( pHVDCtrl_Hal->MemMap.u32CodeBufAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr )
1428 {
1429 #if defined(CHIP_U3)
1430 if( !((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(9)) == BIT(9)) )
1431 {
1432 HVD_MSG_ERR("HVD Drv Err: code start address(%lx) is at MIU1, but MIU sel is set(VPU d-cache WR) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(9)));
1433 if( bChange )
1434 {
1435 // VPU d-cache WR
1436 _HVD_WriteWordMask(MIU0_REG_SEL2 , BIT(9), BIT(9));
1437 }
1438 }
1439 if( !((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(13)) == BIT(13)) )
1440 {
1441 HVD_MSG_ERR("HVD Drv Err: code start address(%lx) is at MIU1, but MIU sel is set(VPU qdma WR) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(13)) );
1442 if( bChange )
1443 {
1444 // VPU qdma WR
1445 _HVD_WriteWordMask(MIU0_REG_SEL2 , BIT(13), BIT(13));
1446 }
1447 }
1448 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) == BIT(13)) )
1449 {
1450 HVD_MSG_ERR("HVD Drv Err: code start address(%lx) is at MIU1, but MIU sel is set(VPU i-cache WR) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) );
1451 if( bChange )
1452 {
1453 // VPU i-cache WR
1454 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(13), BIT(13));
1455 }
1456 }
1457 #endif
1458 #if defined(CHIP_T3)
1459 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) == BIT(7)) )
1460 {
1461 HVD_MSG_ERR("HVD Drv Err: code start address(%lx) is at MIU1, but MIU sel is set(VPU d-cache WR) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) );
1462 if( bChange )
1463 {
1464 // VPU d-cache WR
1465 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(7), BIT(7));
1466 }
1467 }
1468 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) == BIT(8)) )
1469 {
1470 HVD_MSG_ERR("HVD Drv Err: code start address(%lx) is at MIU1, but MIU sel is set(VPU qdma WR) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) );
1471 if( bChange )
1472 {
1473 // VPU qdma WR
1474 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(8), BIT(8));
1475 }
1476 }
1477 if( !((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(9)) == BIT(9)) )
1478 {
1479 HVD_MSG_ERR("HVD Drv Err: code start address(%lx) is at MIU1, but MIU sel is set(VPU i-cache WR) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr, (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(9)) );
1480 if( bChange )
1481 {
1482 // VPU i-cache WR
1483 _HVD_WriteWordMask(MIU0_REG_SEL2 , BIT(9), BIT(9));
1484 }
1485 }
1486 #endif
1487 }
1488 if( pHVDCtrl_Hal->MemMap.u32FrameBufAddr>= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr )
1489 {
1490 #if defined(CHIP_U3)
1491 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12)) )
1492 {
1493 HVD_MSG_ERR("HVD Drv Err: Frame Buf address(%lx) is at MIU1, but MIU sel is set(HVD RW) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)));
1494 if( bChange )
1495 {
1496 // HVD RW
1497 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(12), BIT(12));
1498 }
1499 }
1500 #endif
1501 #if defined(CHIP_T3)
1502 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(10)) == BIT(10)) )
1503 {
1504 HVD_MSG_ERR("HVD Drv Err: Frame Buf address(%lx) is at MIU1, but MIU sel is set(HVD RW) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(10)) );
1505 if( bChange )
1506 {
1507 // HVD RW
1508 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(10), BIT(10));
1509 }
1510 }
1511 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4)) )
1512 {
1513 HVD_MSG_ERR("HVD Drv Err: Frame Buf address(%lx) is at MIU1, but MIU sel is set(MVD WR) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) );
1514 if( bChange )
1515 {
1516 // MVD WR
1517 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(4), BIT(4));
1518 }
1519 }
1520 #endif
1521 }
1522 if( pHVDCtrl_Hal->MemMap.u32BitstreamBufAddr>= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr )
1523 {
1524 #if defined(CHIP_U3)
1525 if( !((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(0)) == BIT(0)) )
1526 {
1527 HVD_MSG_ERR("HVD Drv Err: Bitstream Buf address(%lx) is at MIU1, but MIU sel is set(HVD BBU R) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(0)) );
1528 if( bChange )
1529 {
1530 // HVD BBU R
1531 _HVD_WriteWordMask(MIU0_REG_SEL2 , BIT(0), BIT(0));
1532 }
1533 }
1534 if( !((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(6)) == BIT(6)) )
1535 {
1536 HVD_MSG_ERR("HVD Drv Err: Bitstream Buf address(%lx) is at MIU1, but MIU sel is set(MVD WR) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr, (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(6)) );
1537 if( bChange )
1538 {
1539 // MVD WR
1540 _HVD_WriteWordMask(MIU0_REG_SEL2 , BIT(6), BIT(6));
1541 }
1542 }
1543 #endif
1544 #if defined(CHIP_T3)
1545 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(11)) == BIT(11)) )
1546 {
1547 HVD_MSG_ERR("HVD Drv Err: Bitstream Buf address(%lx) is at MIU1, but MIU sel is set(HVD BBU R) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(11)) );
1548 if( bChange )
1549 {
1550 // HVD BBU R
1551 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(11), BIT(11));
1552 }
1553 }
1554 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) == BIT(5)) )
1555 {
1556 HVD_MSG_ERR("HVD Drv Err: Bitstream Buf address(%lx) is at MIU1, but MIU sel is set(MVD BBU WR) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) );
1557 if( bChange )
1558 {
1559 // MVD BBU WR
1560 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(5), BIT(5));
1561 }
1562 }
1563 #endif
1564 }
1565 #endif
1566 }
1567
HAL_HVD_Get_HWVersionID(void)1568 MS_U32 HAL_HVD_Get_HWVersionID(void)
1569 {
1570 return _HVD_Read2Byte(HVD_REG_REV_ID);
1571 }
1572
HAL_HVD_PowerCtrl(MS_BOOL bEnable)1573 void HAL_HVD_PowerCtrl(MS_BOOL bEnable)
1574 {
1575 if( bEnable)
1576 {
1577 _HVD_WriteByteMask(REG_TOP_HVD, ~TOP_CKG_HVD_DIS , TOP_CKG_HVD_DIS );
1578 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS);
1579 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK);
1580 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK);
1581 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK);
1582 }
1583 else
1584 {
1585 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_DIS , TOP_CKG_HVD_DIS );
1586 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS);
1587 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK);
1588 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK);
1589 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK);
1590 }
1591 // fix to not inverse
1592 _HVD_WriteByteMask(REG_TOP_HVD, ~TOP_CKG_HVD_INV , TOP_CKG_HVD_INV );
1593 switch( u32HVDClockType )
1594 {
1595 case 216:
1596 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_216MHZ , TOP_CKG_HVD_CLK_MASK);
1597 break;
1598 case 172:
1599 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_172MHZ , TOP_CKG_HVD_CLK_MASK);
1600 break;
1601 case 160:
1602 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_160MHZ , TOP_CKG_HVD_CLK_MASK);
1603 break;
1604 case 144:
1605 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_144MHZ , TOP_CKG_HVD_CLK_MASK);
1606 break;
1607 default:
1608 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_160MHZ , TOP_CKG_HVD_CLK_MASK);
1609 break;
1610 }
1611 return;
1612 }
1613
HAL_HVD_InitRegBase(MS_U32 u32RegBase)1614 void HAL_HVD_InitRegBase(MS_U32 u32RegBase)
1615 {
1616 u32HVDRegOSBase = u32RegBase;
1617 HAL_VPU_InitRegBase( u32RegBase );
1618 }
1619
HAL_HVD_SetPreCtrlVariables(MS_U32 drvprectrl)1620 void HAL_HVD_SetPreCtrlVariables(MS_U32 drvprectrl)
1621 {
1622 HVD_Pre_Ctrl *pHVDPreCtrl_in = (HVD_Pre_Ctrl*)drvprectrl;
1623 pHVDPreCtrl_Hal = pHVDPreCtrl_in;
1624 }
1625
HAL_HVD_InitVariables(MS_U32 drvctrl)1626 HVD_Return HAL_HVD_InitVariables(MS_U32 drvctrl)
1627 {
1628 HVD_Drv_Ctrl *pHVDCtrl_in = (HVD_Drv_Ctrl*)drvctrl;
1629
1630 // local variables
1631 u32PTSPreWptr = 0;
1632 u32PTSRptrAddr = 0;
1633 u32PTSWptrAddr = 0;
1634 u32PTSByteCnt = 0;
1635 u32BBUWptr = 0;
1636
1637 HVD_memset((void *) g_hvd_nal_fill_pair, 0, 16);
1638
1639 // global variables
1640 u32HVDCmdTimeout = pHVDCtrl_in->u32CmdTimeout;
1641 pHVDCtrl_Hal = pHVDCtrl_in;
1642 //u32VPUClockType = (MS_U32)pHVDCtrl_in->InitParams.u16DecoderClock;
1643 //u32HVDClockType = (MS_U32)pHVDCtrl_in->InitParams.u16DecoderClock;
1644 // Create mutex
1645 _HAL_HVD_MutexCreate();
1646
1647 // fill HVD init variables
1648 #if defined(UDMA_FPGA_ENVI)
1649 pHVDShareMem = &UDMA_pc_HVDShareMem;
1650 UDMA_fpga_HVDShareMemAddr = pHVDCtrl_in->MemMap.u32CodeBufVAddr + HVD_SHARE_MEM_ST_OFFSET ;
1651 #else
1652 pHVDShareMem = (volatile HVD_ShareMem *)((pHVDCtrl_in->MemMap.u32CodeBufVAddr) + HVD_SHARE_MEM_ST_OFFSET);
1653 HVD_MSG_DEG("pHVDShareMem = %lx\n", (MS_U32)pHVDShareMem);
1654 #endif
1655
1656 #if HVD_ENABLE_RV_FEATURE
1657 if( ((pHVDCtrl_Hal->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM )
1658 {
1659 u32BBUEntryNum = RVD_BBU_DRAM_TBL_ENTRY;
1660 u32BBUEntryNumTH = RVD_BBU_DRAM_TBL_ENTRY_TH;
1661 if (pHVDCtrl_Hal->MemMap.u32FrameBufSize > RV_VLC_TABLE_SIZE)
1662 {
1663 u32RV_VLCTableAddr = pHVDCtrl_Hal->MemMap.u32FrameBufSize - RV_VLC_TABLE_SIZE;
1664 pHVDCtrl_Hal->MemMap.u32FrameBufSize -= RV_VLC_TABLE_SIZE;
1665 }
1666 else
1667 {
1668 HVD_MSG_ERR("HAL_HVD_InitVariables failed: frame buffer size too small. FB:%lx min:%lx\n",
1669 (MS_U32)pHVDCtrl_Hal->MemMap.u32FrameBufSize, (MS_U32)RV_VLC_TABLE_SIZE);
1670 return E_HVD_RETURN_INVALID_PARAMETER;
1671 }
1672 }
1673 else
1674 #endif
1675 {
1676 u32BBUEntryNum = HVD_BBU_DRAM_TBL_ENTRY;
1677 u32BBUEntryNumTH = HVD_BBU_DRAM_TBL_ENTRY_TH;
1678 u32RV_VLCTableAddr = 0;
1679 }
1680
1681 if( (( (pHVDCtrl_in->MemMap.u32CodeBufVAddr )<= (MS_U32)pHVDShareMem)&& ( (MS_U32)pHVDShareMem <= ((pHVDCtrl_in->MemMap.u32CodeBufVAddr )+ pHVDCtrl_in->MemMap.u32CodeBufSize)))
1682 || (( (pHVDCtrl_in->MemMap.u32BitstreamBufVAddr)<= (MS_U32)pHVDShareMem)&& ( (MS_U32)pHVDShareMem <= ((pHVDCtrl_in->MemMap.u32BitstreamBufVAddr )+ pHVDCtrl_in->MemMap.u32BitstreamBufSize)))
1683 || (( (pHVDCtrl_in->MemMap.u32FrameBufVAddr) <= (MS_U32)pHVDShareMem)&& ( (MS_U32)pHVDShareMem <= ((pHVDCtrl_in->MemMap.u32FrameBufVAddr) + pHVDCtrl_in->MemMap.u32FrameBufSize))) )
1684 {
1685 HVD_MSG_DEG("input memory: %lx %lx %lx %lx\n",
1686 pHVDCtrl_in->MemMap.u32CodeBufAddr,
1687 pHVDCtrl_in->MemMap.u32FrameBufAddr,
1688 pHVDCtrl_in->MemMap.u32BitstreamBufAddr,
1689 pHVDCtrl_in->MemMap.u32MIU1BaseAddr);
1690 return E_HVD_RETURN_SUCCESS;
1691 }
1692 else
1693 {
1694 HVD_MSG_ERR("HAL_HVD_InitVariables failed: %lx %lx %lx %lx %lx\n",
1695 (MS_U32)pHVDShareMem,
1696 pHVDCtrl_in->MemMap.u32CodeBufVAddr,
1697 pHVDCtrl_in->MemMap.u32FrameBufVAddr,
1698 pHVDCtrl_in->MemMap.u32BitstreamBufVAddr,
1699 pHVDCtrl_in->MemMap.u32MIU1BaseAddr);
1700 return E_HVD_RETURN_INVALID_PARAMETER;
1701 }
1702 }
1703
HAL_HVD_InitShareMem(void)1704 HVD_Return HAL_HVD_InitShareMem(void)
1705 {
1706 MS_U32 u32Addr = 0;
1707
1708 HVD_memset((volatile void *)pHVDShareMem, 0, sizeof(HVD_ShareMem));
1709 u32Addr = pHVDCtrl_Hal->MemMap.u32FrameBufAddr;
1710 if (u32Addr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr)
1711 {
1712 u32Addr -= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr;
1713 }
1714 pHVDShareMem->u32FrameRate = pHVDCtrl_Hal->InitParams.u32FrameRate;
1715 pHVDShareMem->u32FrameRateBase = pHVDCtrl_Hal->InitParams.u32FrameRateBase;
1716 pHVDShareMem->u32FrameBufAddr = u32Addr;
1717 pHVDShareMem->u32FrameBufSize = pHVDCtrl_Hal->MemMap.u32FrameBufSize;
1718 pHVDShareMem->DispInfo.u16DispWidth = 1;
1719 pHVDShareMem->DispInfo.u16DispHeight = 1;
1720 pHVDShareMem->u32CodecType = pHVDCtrl_Hal->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK;
1721 pHVDShareMem->u32CPUClock = u32VPUClockType;
1722 pHVDShareMem->u32UserCCIdxWrtPtr = 0xFFFFFFFF;
1723 pHVDShareMem->DispFrmInfo.u32TimeStamp = 0xFFFFFFFF;
1724
1725 // PreSetControl
1726 if (pHVDPreCtrl_Hal->bOnePendingBuffer)
1727 {
1728 pHVDShareMem->u32PreSetControl |= PRESET_ONE_PENDING_BUFFER;
1729 }
1730
1731 if (pHVDPreCtrl_Hal->bFrameRateHandling)
1732 {
1733 pHVDShareMem->u32PreSetControl |= PRESET_FRAMERATE_HANDLING;
1734 pHVDShareMem->u32PreSetFrameRate = pHVDPreCtrl_Hal->u32PreSetFrameRate;
1735 }
1736
1737 //Chip info
1738 pHVDShareMem->u16ChipID = E_MSTAR_CHIP_A3;
1739 pHVDShareMem->u16ChipECONum = 0;
1740
1741 HVD_MSG_DEG("[DBG] pHVDCtrl_Hal->InitParams.u32ModeFlag = 0x%lx\n", pHVDCtrl_Hal->InitParams.u32ModeFlag);
1742
1743 if ((pHVDCtrl_Hal->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_RAW)
1744 {
1745 pHVDShareMem->u8SrcMode = E_HVD_SRC_MODE_FILE;
1746 }
1747 else if ((pHVDCtrl_Hal->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_TS)
1748 {
1749 pHVDShareMem->u8SrcMode = E_HVD_SRC_MODE_TS_FILE;
1750 }
1751 else
1752 {
1753 pHVDShareMem->u8SrcMode = E_HVD_SRC_MODE_DTV;
1754 }
1755
1756 #if 1 //From T4 and the later chips, QDMA can support the address more than MIU1 base.
1757 if(pHVDCtrl_Hal->MemMap.u32CodeBufAddr >= HAL_MIU1_BASE)
1758 {
1759 pHVDShareMem->u32FWBaseAddr = (pHVDCtrl_Hal->MemMap.u32CodeBufAddr-HAL_MIU1_BASE) | 0x40000000; //Bit30 sel miu0/1
1760 }
1761 else
1762 {
1763 pHVDShareMem->u32FWBaseAddr = pHVDCtrl_Hal->MemMap.u32CodeBufAddr;
1764 }
1765 //printf("<DBG>QDMA Addr = %lx <<<<<<<<<<<<<<<<<<<<<<<<\n",pHVDShareMem->u32FWBaseAddr);
1766 #else
1767 u32Addr = pHVDCtrl_Hal->MemMap.u32CodeBufAddr;
1768 if (u32Addr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr)
1769 {
1770 u32Addr -= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr;
1771 }
1772 pHVDShareMem->u32FWBaseAddr = u32Addr;
1773 #endif
1774 // RM only
1775 #if HVD_ENABLE_RV_FEATURE
1776 if( (((pHVDCtrl_Hal->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
1777 && (pHVDCtrl_Hal->InitParams.pRVFileInfo != NULL) )
1778 {
1779 MS_U32 i = 0;
1780 for(i = 0; i < HVD_RM_INIT_PICTURE_SIZE_NUMBER; i++)
1781 {
1782 pHVDShareMem->pRM_PictureSize[i].u16Width = pHVDCtrl_Hal->InitParams.pRVFileInfo->ulPicSizes_w[i];
1783 pHVDShareMem->pRM_PictureSize[i].u16Height = pHVDCtrl_Hal->InitParams.pRVFileInfo->ulPicSizes_h[i];
1784 }
1785 pHVDShareMem->u8RM_Version = (MS_U8)pHVDCtrl_Hal->InitParams.pRVFileInfo->RV_Version;
1786 pHVDShareMem->u8RM_NumSizes = (MS_U8)pHVDCtrl_Hal->InitParams.pRVFileInfo->ulNumSizes;
1787 u32Addr = pHVDCtrl_Hal->MemMap.u32FrameBufAddr + u32RV_VLCTableAddr;
1788 if (u32Addr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr)
1789 {
1790 u32Addr -= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr;
1791 }
1792 pHVDShareMem->u32RM_VLCTableAddr = u32Addr;
1793 }
1794 #endif
1795 #if defined(UDMA_FPGA_ENVI)
1796 HVD_UDMA_memcpy((void *)UDMA_fpga_HVDShareMemAddr,
1797 &UDMA_pc_HVDShareMem,
1798 sizeof(HVD_Display_Info));
1799 #endif
1800 HAL_HVD_FlushMemory();
1801 return E_HVD_RETURN_SUCCESS;
1802 }
1803
HAL_HVD_InitRegCPU(void)1804 HVD_Return HAL_HVD_InitRegCPU( void)
1805 {
1806 MS_BOOL bInitRet=FALSE;
1807
1808 //_HAL_HVD_Entry();
1809 // Init VPU
1810 {
1811 VPU_Init_Params VPUInitParams = { E_VPU_CLOCK_216MHZ , FALSE , -1, VPU_DEFAULT_MUTEX_TIMEOUT, FALSE};
1812 switch( u32VPUClockType )
1813 {
1814 case 216:
1815 VPUInitParams.eClockSpeed=E_VPU_CLOCK_216MHZ;
1816 break;
1817 case 192:
1818 VPUInitParams.eClockSpeed=E_VPU_CLOCK_192MHZ;
1819 break;
1820 case 160:
1821 VPUInitParams.eClockSpeed=E_VPU_CLOCK_160MHZ;
1822 break;
1823 case 144:
1824 VPUInitParams.eClockSpeed=E_VPU_CLOCK_144MHZ;
1825 break;
1826 default:
1827 break;
1828 }
1829 #if HAL_HVD_ENABLE_MUTEX_PROTECT
1830 VPUInitParams.s32VPUMutexID = s32HVDMutexID;
1831 #endif
1832
1833 if(pHVDCtrl_Hal->MemMap.u32CodeBufAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr)
1834 {
1835 VPUInitParams.bInMIU1 = TRUE;
1836 }
1837 else
1838 {
1839 VPUInitParams.bInMIU1 = FALSE;
1840 }
1841
1842 HAL_VPU_Init(&VPUInitParams);
1843 }
1844 HAL_HVD_MVD_PowerCtrl( TRUE );
1845 #if 0
1846 // check MVD power on
1847 if( _HVD_Read2Byte(REG_TOP_MVD) & (TOP_CKG_MHVD_DIS) )
1848 {
1849 HVD_MSG_INFO( "HVD warning: MVD is not power on before HVD init.\n" );
1850 _HVD_WriteWordMask(REG_TOP_MVD, 0 , TOP_CKG_MHVD_DIS );
1851 HVD_Delay_ms(1);
1852 }
1853 // Check VPU power on
1854 if( _HVD_Read2Byte(REG_TOP_VPU) & (TOP_CKG_VPU_DIS) )
1855 {
1856 HVD_MSG_INFO( "HVD warning: VPU is not power on before HVD init.\n" );
1857 _HVD_WriteWordMask(REG_TOP_VPU, 0 , TOP_CKG_VPU_DIS );
1858 HVD_Delay_ms(1);
1859 }
1860 // check HVD power on
1861 if( _HVD_Read2Byte(REG_TOP_HVD) & (TOP_CKG_HVD_DIS) )
1862 {
1863 HVD_MSG_INFO( "HVD warning: HVD is not power on before HVD init.\n" );
1864 HAL_HVD_PowerCtrl(TRUE);
1865 HVD_Delay_ms(1);
1866 }
1867 #endif
1868 bInitRet = _HAL_HVD_SetRegCPU();
1869 if( !bInitRet )
1870 {
1871 //_HAL_HVD_Return( E_HVD_RETURN_FAIL);
1872 return E_HVD_RETURN_FAIL;
1873 }
1874 bInitRet=HAL_HVD_RstPTSCtrlVariable();
1875 if( !bInitRet )
1876 {
1877 //_HAL_HVD_Return( E_HVD_RETURN_FAIL);
1878 return E_HVD_RETURN_FAIL;
1879 }
1880 //_HAL_HVD_Return( E_HVD_RETURN_SUCCESS);
1881 return E_HVD_RETURN_SUCCESS;
1882 }
1883
HAL_HVD_SetData(HVD_SetData u32type,MS_U32 u32Data)1884 HVD_Return HAL_HVD_SetData( HVD_SetData u32type , MS_U32 u32Data)
1885 {
1886 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
1887 //_HAL_HVD_Entry();
1888 switch(u32type)
1889 {
1890 // share memory
1891 // switch
1892 case E_HVD_SDATA_FRAMEBUF_ADDR:
1893 pHVDShareMem->u32FrameBufAddr = u32Data;
1894 break;
1895 case E_HVD_SDATA_FRAMEBUF_SIZE:
1896 pHVDShareMem->u32FrameBufSize= u32Data;
1897 break;
1898 case E_HVD_SDATA_RM_PICTURE_SIZES:
1899 HVD_memcpy( (volatile void*)pHVDShareMem->pRM_PictureSize, (void*)((HVD_PictureSize*)u32Data) , HVD_RM_INIT_PICTURE_SIZE_NUMBER * sizeof( HVD_PictureSize ) );
1900 break;
1901 case E_HVD_SDATA_ERROR_CODE:
1902 pHVDShareMem->u16ErrCode= (MS_U16)u32Data;
1903 break;
1904 case E_HVD_SDATA_DISP_INFO_TH:
1905 HVD_memcpy((volatile void*)&(pHVDShareMem->DispThreshold), (void*)((HVD_DISP_THRESHOLD*)u32Data), sizeof(HVD_DISP_THRESHOLD) );
1906 break;
1907 // SRAM
1908
1909 // Mailbox
1910 case E_HVD_SDATA_TRIGGER_DISP: // HVD HI mbox 0
1911 if( u32Data != 0)
1912 {
1913 _HAL_HVD_MBoxSend( HAL_HVD_REG_DISP_CTL , 1 );
1914 }
1915 else
1916 {
1917 _HAL_HVD_MBoxSend( HAL_HVD_REG_DISP_CTL , 0 );
1918 }
1919 break;
1920
1921 case E_HVD_SDATA_GET_DISP_INFO_DONE:
1922 _HAL_HVD_MBoxClear( HAL_HVD_REG_DISP_INFO_CHANGE );
1923 break;
1924
1925 case E_HVD_SDATA_GET_DISP_INFO_START:
1926 _HAL_HVD_MBoxClear( HAL_HVD_REG_DISP_INFO_COPYED );
1927 break;
1928
1929 case E_HVD_SDATA_VIRTUAL_BOX_WIDTH:
1930 pHVDShareMem->u32VirtualBoxWidth = u32Data;
1931 break;
1932
1933 case E_HVD_SDATA_VIRTUAL_BOX_HEIGHT:
1934 pHVDShareMem->u32VirtualBoxHeight = u32Data;
1935 break;
1936
1937 #ifdef _HVD_DQ
1938 case E_HVD_SDATA_DISPQ_STATUS_VIEW:
1939 if (pHVDShareMem->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_INIT)
1940 {
1941 //printf("DispFrame DqPtr: %d\n", u32Data);
1942 pHVDShareMem->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_VIEW;
1943 }
1944 break;
1945
1946 case E_HVD_SDATA_DISPQ_STATUS_DISP:
1947 if (pHVDShareMem->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
1948 {
1949 //printf("DispFrame DqPtr: %d\n", u32Data);
1950 pHVDShareMem->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_DISP;
1951 }
1952 break;
1953
1954 case E_HVD_SDATA_DISPQ_STATUS_FREE:
1955 if (pHVDShareMem->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
1956 {
1957 pHVDShareMem->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_FREE;
1958 }
1959 break;
1960 #endif //#ifdef _HVD_DQ
1961
1962 default:
1963 break;
1964 }
1965
1966 #if defined(UDMA_FPGA_ENVI)
1967 if( u32type & E_HVD_SDATA_SHARE_MEM )
1968 {
1969 HVD_UDMA_memcpy( (void*)UDMA_fpga_HVDShareMemAddr , &UDMA_pc_HVDShareMem , sizeof(HVD_Display_Info ) );
1970 }
1971 #endif
1972 HAL_HVD_FlushMemory();
1973
1974 //_HAL_HVD_Return( eRet);
1975 return eRet;
1976 }
1977
HAL_HVD_GetData_EX(HVD_GetData eType)1978 MS_S64 HAL_HVD_GetData_EX(HVD_GetData eType)
1979 {
1980 MS_S64 s64Ret = 0;
1981
1982 HAL_HVD_ReadMemory();
1983
1984 switch (eType)
1985 {
1986 // report
1987 case E_HVD_GDATA_PTS_STC_DIFF:
1988 s64Ret = pHVDShareMem->s64PtsStcDiff;
1989 break;
1990
1991 default:
1992 break;
1993 }
1994
1995 return s64Ret;
1996 }
1997
HAL_HVD_GetData(HVD_GetData eType)1998 MS_U32 HAL_HVD_GetData( HVD_GetData eType )
1999 {
2000 MS_U32 u32Ret=0;
2001 //_HAL_HVD_Entry();
2002 #if defined(UDMA_FPGA_ENVI)
2003 if( eType & E_HVD_SDATA_SHARE_MEM )
2004 {
2005 HVD_UDMA_memcpy( &UDMA_pc_HVDShareMem , (void*)UDMA_fpga_HVDShareMemAddr , sizeof(HVD_Display_Info ) );
2006 }
2007 #endif
2008 HAL_HVD_ReadMemory();
2009 switch( eType )
2010 {
2011 // share memory
2012 // switch
2013 case E_HVD_GDATA_DISP_INFO_ADDR:
2014 u32Ret = (MS_U32)(&pHVDShareMem->DispInfo);
2015 break;
2016 // report
2017 case E_HVD_GDATA_PTS:
2018 u32Ret=pHVDShareMem->DispFrmInfo.u32TimeStamp;
2019 break;
2020 case E_HVD_GDATA_DECODE_CNT:
2021 u32Ret=pHVDShareMem->u32DecodeCnt;
2022 break;
2023 case E_HVD_GDATA_DATA_ERROR_CNT:
2024 u32Ret=pHVDShareMem->u32DataErrCnt;
2025 break;
2026 case E_HVD_GDATA_DEC_ERROR_CNT:
2027 u32Ret=pHVDShareMem->u32DecErrCnt;
2028 break;
2029 case E_HVD_GDATA_ERROR_CODE:
2030 u32Ret=(MS_U32)(pHVDShareMem->u16ErrCode);
2031 break;
2032 case E_HVD_GDATA_VPU_IDLE_CNT:
2033 u32Ret=pHVDShareMem->u32VPUIdleCnt;
2034 break;
2035 case E_HVD_GDATA_DISP_FRM_INFO:
2036 u32Ret=(MS_U32)(&(pHVDShareMem->DispFrmInfo));
2037 break;
2038 case E_HVD_GDATA_DEC_FRM_INFO:
2039 u32Ret=(MS_U32)(&(pHVDShareMem->DecoFrmInfo));
2040 break;
2041 case E_HVD_GDATA_ES_LEVEL:
2042 u32Ret=(MS_U32)(_HAL_HVD_GetESLevel());
2043 break;
2044
2045 // user data
2046 case E_HVD_GDATA_USERDATA_WPTR:
2047 u32Ret=(MS_U32)(pHVDShareMem->u32UserCCIdxWrtPtr);
2048 break;
2049 case E_HVD_GDATA_USERDATA_IDX_TBL_ADDR:
2050 u32Ret=(MS_U32)(pHVDShareMem->u8UserCCIdx);
2051 break;
2052 case E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR:
2053 u32Ret=(MS_U32)(pHVDShareMem->u32UserCCBase);
2054 break;
2055 case E_HVD_GDATA_USERDATA_PACKET_SIZE:
2056 u32Ret=(MS_U32)(sizeof(DTV_BUF_type));
2057 break;
2058 case E_HVD_GDATA_USERDATA_IDX_TBL_SIZE:
2059 u32Ret=(MS_U32)(USER_CC_IDX_SIZE);
2060 break;
2061 case E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE:
2062 u32Ret=(MS_U32)(USER_CC_DATA_SIZE);
2063 break;
2064 // report - modes
2065 case E_HVD_GDATA_IS_SHOW_ERR_FRM:
2066 u32Ret=pHVDShareMem->ModeStatus.bIsShowErrFrm;
2067 break;
2068 case E_HVD_GDATA_IS_REPEAT_LAST_FIELD:
2069 u32Ret=pHVDShareMem->ModeStatus.bIsRepeatLastField;
2070 break;
2071 case E_HVD_GDATA_IS_ERR_CONCEAL:
2072 u32Ret=pHVDShareMem->ModeStatus.bIsErrConceal;
2073 break;
2074 case E_HVD_GDATA_IS_SYNC_ON:
2075 u32Ret=pHVDShareMem->ModeStatus.bIsSyncOn;
2076 break;
2077 case E_HVD_GDATA_IS_PLAYBACK_FINISH:
2078 u32Ret=pHVDShareMem->ModeStatus.bIsPlaybackFinish;
2079 break;
2080 case E_HVD_GDATA_SYNC_MODE:
2081 u32Ret=pHVDShareMem->ModeStatus.u8SyncType;
2082 break;
2083 case E_HVD_GDATA_SKIP_MODE:
2084 u32Ret=pHVDShareMem->ModeStatus.u8SkipMode;
2085 break;
2086 case E_HVD_GDATA_DROP_MODE:
2087 u32Ret=pHVDShareMem->ModeStatus.u8DropMode;
2088 break;
2089 case E_HVD_GDATA_DISPLAY_DURATION:
2090 u32Ret=pHVDShareMem->ModeStatus.s8DisplaySpeed;
2091 break;
2092 case E_HVD_GDATA_FRC_MODE:
2093 u32Ret=pHVDShareMem->ModeStatus.u8FrcMode;
2094 break;
2095 case E_HVD_GDATA_NEXT_PTS:
2096 u32Ret=pHVDShareMem->u32NextPTS;
2097 break;
2098 #ifdef _HVD_DQ
2099 case E_HVD_GDATA_DISP_Q_SIZE:
2100 u32Ret=pHVDShareMem->u16DispQSize;
2101 break;
2102 case E_HVD_GDATA_DISP_Q_PTR:
2103 u32Ret=(MS_U32)_u16DispQPtr;//pHVDShareMem->u16DispQPtr;
2104 break;
2105 case E_HVD_GDATA_NEXT_DISP_FRM_INFO:
2106 u32Ret=(MS_U32)_HAL_HVD_GetNextDispFrame();
2107 break;
2108 #endif
2109 case E_HVD_GDATA_REAL_FRAMERATE:
2110 u32Ret=pHVDShareMem->u32RealFrameRate;
2111 break;
2112 case E_HVD_GDATA_IS_ORI_INTERLACE_MODE:
2113 u32Ret=(MS_U32)pHVDShareMem->DispInfo.u8IsOriginInterlace;
2114 break;
2115 case E_HVD_GDATA_FRM_PACKING_SEI_DATA:
2116 u32Ret=(MS_U32)pHVDShareMem->u32Frm_packing_arr_data_addr;
2117 break;
2118 case E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG:
2119 u32Ret=(MS_U32)pHVDShareMem->u8FrameMbsOnlyFlag;
2120 break;
2121
2122 // internal control
2123 case E_HVD_GDATA_IS_1ST_FRM_RDY:
2124 u32Ret=pHVDShareMem->bIs1stFrameRdy;
2125 break;
2126 case E_HVD_GDATA_IS_I_FRM_FOUND:
2127 u32Ret=pHVDShareMem->bIsIFrmFound;
2128 break;
2129 case E_HVD_GDATA_IS_SYNC_START:
2130 u32Ret=pHVDShareMem->bIsSyncStart;
2131 break;
2132 case E_HVD_GDATA_IS_SYNC_REACH:
2133 u32Ret=pHVDShareMem->bIsSyncReach;
2134 break;
2135 case E_HVD_GDATA_FW_VERSION_ID:
2136 u32Ret=pHVDShareMem->u32FWVersionID;
2137 break;
2138 case E_HVD_GDATA_FW_IF_VERSION_ID:
2139 u32Ret=pHVDShareMem->u32FWIfVersionID;
2140 break;
2141 case E_HVD_GDATA_BBU_Q_NUMB:
2142 u32Ret=_HAL_HVD_GetBBUQNumb();
2143 break;
2144 case E_HVD_GDATA_DEC_Q_NUMB:
2145 u32Ret=pHVDShareMem->u16DecQNumb;
2146 break;
2147 case E_HVD_GDATA_DISP_Q_NUMB:
2148 u32Ret=pHVDShareMem->u16DispQNumb;
2149 break;
2150 case E_HVD_GDATA_PTS_Q_NUMB:
2151 u32Ret=_HAL_HVD_GetPTSQNumb();
2152 break;
2153 case E_HVD_GDATA_FW_INIT_DONE:
2154 u32Ret=pHVDShareMem->bInitDone;
2155 break;
2156
2157 // debug
2158 case E_HVD_GDATA_SKIP_CNT:
2159 u32Ret=pHVDShareMem->u32SkipCnt;
2160 break;
2161 case E_HVD_GDATA_GOP_CNT:
2162 u32Ret=pHVDShareMem->u32DropCnt;
2163 break;
2164 case E_HVD_GDATA_DISP_CNT:
2165 u32Ret= pHVDShareMem->u32DispCnt;
2166 break;
2167 case E_HVD_GDATA_DROP_CNT:
2168 u32Ret= pHVDShareMem->u32DropCnt;
2169 break;
2170 case E_HVD_GDATA_DISP_STC:
2171 u32Ret= pHVDShareMem->u32DispSTC;
2172 break;
2173 case E_HVD_GDATA_VSYNC_CNT:
2174 u32Ret= pHVDShareMem->u32VsyncCnt;
2175 break;
2176 case E_HVD_GDATA_MAIN_LOOP_CNT:
2177 u32Ret= pHVDShareMem->u32MainLoopCnt;
2178 break;
2179
2180 // AVC
2181 case E_HVD_GDATA_AVC_LEVEL_IDC:
2182 u32Ret=pHVDShareMem->u16AVC_SPS_LevelIDC;
2183 break;
2184 case E_HVD_GDATA_AVC_LOW_DELAY:
2185 u32Ret=pHVDShareMem->u8AVC_SPS_LowDelayHrdFlag;
2186 break;
2187 case E_HVD_GDATA_AVC_VUI_DISP_INFO:
2188 u32Ret=_HAL_HVD_GetVUIDispInfo();
2189 break;
2190
2191 // SRAM
2192
2193 // Mailbox
2194 case E_HVD_GDATA_FW_STATE: // HVD RISC MBOX 0 (esp. FW init done)
2195 u32Ret=_HAL_HVD_GetFWState();
2196 break;
2197 case E_HVD_GDATA_IS_DISP_INFO_UNCOPYED:
2198 u32Ret=_HAL_HVD_MBoxReady( HAL_HVD_REG_DISP_INFO_COPYED );
2199 break;
2200 case E_HVD_GDATA_IS_DISP_INFO_CHANGE: // HVD RISC MBOX 1 (rdy only)
2201 u32Ret=_HAL_HVD_MBoxReady( HAL_HVD_REG_DISP_INFO_CHANGE );
2202 break;
2203 case E_HVD_GDATA_HVD_ISR_STATUS: // HVD RISC MBOX 1 (value only)
2204 _HAL_HVD_MBoxRead(HAL_HVD_REG_ISR_HVD , &u32Ret );
2205 break;
2206 case E_HVD_GDATA_VPU_ISR_STATUS: // VPU RISC MBOX 1 (value only)
2207 _HAL_HVD_MBoxRead(HAL_HVD_REG_ISR_VPU , &u32Ret );
2208 break;
2209 case E_HVD_GDATA_IS_FRAME_SHOWED: // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable )
2210 if( _HAL_HVD_MBoxReady( HAL_HVD_REG_DISP_CTL ) )
2211 {
2212 u32Ret = TRUE;
2213 }
2214 else
2215 {
2216 u32Ret = FALSE;
2217 }
2218 break;
2219 case E_HVD_GDATA_ES_READ_PTR: //
2220 u32Ret= _HAL_HVD_GetESReadPtr(FALSE);
2221 break;
2222 case E_HVD_GDATA_ES_WRITE_PTR: //
2223 u32Ret= _HAL_HVD_GetESWritePtr();
2224 break;
2225 case E_HVD_GDATA_BBU_READ_PTR:
2226 u32Ret= _HAL_HVD_GetBBUReadptr();
2227 break;
2228 case E_HVD_GDATA_BBU_WRITE_PTR:
2229 u32Ret= u32BBUWptr;
2230 break;
2231 case E_HVD_GDATA_BBU_WRITE_PTR_FIRED:
2232 u32Ret= pHVDCtrl_Hal->u32BBUWptr_Fired;
2233 break;
2234
2235 case E_HVD_GDATA_VPU_PC_CNT:
2236 u32Ret= _HAL_HVD_GetPC();
2237 break;
2238
2239
2240 // FW def
2241 case E_HVD_GDATA_FW_MAX_DUMMY_FIFO: // AVC: 256Bytes AVS: 2kB RM:???
2242 u32Ret=HVD_MAX3( HVD_FW_AVC_DUMMY_FIFO , HVD_FW_AVS_DUMMY_FIFO , HVD_FW_RM_DUMMY_FIFO );
2243 break;
2244
2245 case E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY:
2246 u32Ret=HVD_FW_AVC_MAX_VIDEO_DELAY;
2247 break;
2248 case E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY:
2249 u32Ret=u32BBUEntryNumTH ;
2250 break;
2251 case E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB:
2252 u32Ret=u32BBUEntryNum ;
2253 break;
2254 case E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB:
2255 u32Ret=MAX_PTS_TABLE_SIZE;
2256 break;
2257 case E_HVD_GDATA_FW_DUMMY_WRITE_ADDR:
2258 u32Ret=HVD_DUMMY_WRITE_ADDR ;
2259 break;
2260 case E_HVD_GDATA_FW_DS_BUF_ADDR:
2261 u32Ret=HVD_DYNAMIC_SCALING_ADDR ;
2262 break;
2263 case E_HVD_GDATA_FW_DS_BUF_SIZE:
2264 //u32Ret = HVD_DYNAMIC_SCALING_SIZE;
2265 // ----------------------- yi-chun.pan: for Dynamic Scaling 3k/6k issue ----------20111213---
2266 // ----------------------- modify DRV and AP(SN/MM) first, and then update fw --------------
2267 u32Ret = (1024 * 3);
2268 break;
2269 case E_HVD_GDATA_FW_DS_VECTOR_DEPTH:
2270 u32Ret=HVD_DYNAMIC_SCALING_DEPTH ;
2271 break;
2272 case E_HVD_GDATA_FW_DS_INFO_ADDR:
2273 u32Ret=HVD_SCALER_INFO_ADDR;
2274 break;
2275
2276 default:
2277 break;
2278 }
2279 //_HAL_HVD_Return( u32Ret);
2280 return u32Ret;
2281 }
2282
HAL_HVD_SetCmd(HVD_User_Cmd eUsrCmd,MS_U32 u32CmdArg)2283 HVD_Return HAL_HVD_SetCmd(HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg)
2284 {
2285 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
2286 MS_U32 u32Cmd = (MS_U32) eUsrCmd;
2287
2288 _HAL_HVD_Entry();
2289
2290 // check if old SVD cmds
2291 if (u32Cmd < E_HVD_CMD_SVD_BASE)
2292 {
2293 HVD_MSG_ERR("HVD Err: Old SVD FW cmd(%lx %lx) used in HVD.\n" , u32Cmd, u32CmdArg);
2294
2295 _HAL_HVD_Return(E_HVD_RETURN_INVALID_PARAMETER);
2296 }
2297
2298 HVD_MSG_DEG("HVD DBG: Send cmd:0x%lx Arg:0x%lx\n", u32Cmd, u32CmdArg);
2299
2300 eRet = _HAL_HVD_SendCmd(u32Cmd, u32CmdArg);
2301
2302 _HAL_HVD_Return(eRet);
2303 }
2304
2305
HAL_HVD_DeInit(void)2306 HVD_Return HAL_HVD_DeInit(void)
2307 {
2308 HVD_Return eRet=E_HVD_RETURN_FAIL;
2309 //MS_U32 u32FWState=0;
2310 //MS_U32 Timer=50; // ms
2311 #if HVD_ENABLE_TIME_MEASURE
2312 MS_U32 ExitTimeCnt=0;
2313 ExitTimeCnt = HVD_GetSysTime_ms();
2314 #endif
2315 eRet=HAL_HVD_SetCmd(E_HVD_CMD_PAUSE, 0);
2316 if (E_HVD_RETURN_SUCCESS != eRet)
2317 HVD_MSG_ERR("HVDERR %s(%d) HVD fail to PAUSE %d\n", __FUNCTION__, __LINE__, eRet);
2318
2319 eRet=HAL_HVD_SetCmd(E_HVD_CMD_STOP, 0);
2320 _HAL_HVD_MutexDelete();
2321 /*
2322 while(Timer)
2323 {
2324 HVD_Delay_ms(1);
2325 u32FWState=HAL_HVD_GetData( E_HVD_GDATA_FW_STATE );
2326 switch( (pHVDCtrl_Hal->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK )
2327 {
2328 case E_HVD_INIT_HW_AVC:
2329 if( u32FWState == E_HVD_FW_STOP_DONE)
2330 {
2331 Timer=1;
2332 }
2333 break;
2334 case E_HVD_INIT_HW_AVS:
2335 if( u32FWState == E_HVD_FW_STOP)
2336 {
2337 Timer=1;
2338 }
2339 break;
2340 default:
2341 break;
2342 }
2343 Timer--;
2344 };
2345 */
2346 #if HVD_ENABLE_TIME_MEASURE
2347 HVD_MSG_DEG( "HVD Stop Time(Wait FW):%d\n" , HVD_GetSysTime_ms()-ExitTimeCnt );
2348 #endif
2349 //check MAU idle before reset VPU
2350 {
2351 MS_U32 mau_idle_cnt = 100;// ms
2352 while(mau_idle_cnt)
2353 {
2354 if(TRUE == HAL_VPU_MAU_IDLE())
2355 {
2356 break;
2357 }
2358 mau_idle_cnt--;
2359 HVD_Delay_ms(1);
2360 }
2361
2362 if(mau_idle_cnt == 0)
2363 {
2364 HVD_MSG_ERR("MAU idle time out~~~~~\n");
2365 }
2366 }
2367 HVD_MSG_DEG("%s(%d) HVD hold CPU\n", __FUNCTION__, __LINE__);
2368 HAL_VPU_SwRst(); //CPU hold
2369 {
2370 MS_U16 u16Timeout = 1000;
2371 _HAL_HVD_SetMIUProtectMask(TRUE);
2372 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST , HVD_REG_RESET_SWRST);
2373 while(u16Timeout)
2374 {
2375 if( (_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN))
2376 == (HVD_REG_RESET_SWRST_FIN))
2377 {
2378 break;
2379 }
2380 u16Timeout--;
2381 }
2382
2383 _HAL_HVD_RstMVDParser();
2384
2385 //HAL_VPU_PowerCtrl(FALSE);
2386 HAL_VPU_DeInit();
2387 HAL_VPU_SwRelseMAU();
2388 HAL_HVD_PowerCtrl(FALSE);
2389 HAL_HVD_MVD_PowerCtrl( FALSE );
2390
2391 _HAL_HVD_SetMIUProtectMask(FALSE);
2392 }
2393 //HAL_HVD_MVD_PowerCtrl( FALSE );
2394 return eRet;
2395 }
2396
HAL_HVD_PushPacket(HVD_BBU_Info * pInfo)2397 HVD_Return HAL_HVD_PushPacket(HVD_BBU_Info *pInfo)
2398 {
2399 HVD_Return eRet = E_HVD_RETURN_UNSUPPORTED;
2400 MS_U32 u32Addr = 0;
2401
2402 eRet = _HAL_HVD_UpdatePTSTable(pInfo);
2403
2404 if (E_HVD_RETURN_SUCCESS != eRet)
2405 {
2406 return eRet;
2407 }
2408
2409 #ifdef _HVD_DQ
2410 //printf(">>> halHVD pts,idH = %lu, %lu\n", pInfo->u32TimeStamp, pInfo->u32ID_H); //STS input
2411 #endif
2412
2413 //T9: for 128 bit memory. BBU need to get 2 entry at a time.
2414 eRet = _HAL_HVD_UpdateESWptr(0, 0);
2415
2416 if (E_HVD_RETURN_SUCCESS != eRet)
2417 {
2418 return eRet;
2419 }
2420
2421 u32Addr = pInfo->u32Staddr;
2422
2423 if (pInfo->bRVBrokenPacket)
2424 {
2425 u32Addr = pInfo->u32Staddr | BIT(HVD_RV_BROKENBYUS_BIT);
2426 }
2427
2428 eRet = _HAL_HVD_UpdateESWptr(u32Addr, pInfo->u32Length);
2429
2430 if (E_HVD_RETURN_SUCCESS != eRet)
2431 {
2432 return eRet;
2433 }
2434
2435 u32PTSByteCnt += pInfo->u32Length;
2436
2437 // do not add local pointer
2438 if ((pHVDCtrl_Hal->MemMap.u32DrvProcessBufSize != 0) && (pHVDCtrl_Hal->MemMap.u32DrvProcessBufAddr != 0))
2439 {
2440 MS_U32 u32PacketStAddr = pInfo->u32Staddr + pHVDCtrl_Hal->MemMap.u32BitstreamBufAddr;
2441
2442 if (!((pHVDCtrl_Hal->MemMap.u32DrvProcessBufAddr <= u32PacketStAddr) &&
2443 (u32PacketStAddr < (pHVDCtrl_Hal->MemMap.u32DrvProcessBufAddr + pHVDCtrl_Hal->MemMap.u32DrvProcessBufSize))))
2444 {
2445 pHVDCtrl_Hal->LastNal.u32NalAddr = pInfo->u32Staddr;
2446 pHVDCtrl_Hal->LastNal.u32NalSize = pInfo->u32Length;
2447 }
2448 else
2449 {
2450 //null packet
2451 pHVDCtrl_Hal->LastNal.u32NalAddr = pInfo->u32OriPktAddr;
2452 pHVDCtrl_Hal->LastNal.u32NalSize = 0;
2453 }
2454 }
2455 else
2456 {
2457 pHVDCtrl_Hal->LastNal.u32NalAddr = pInfo->u32Staddr;
2458 pHVDCtrl_Hal->LastNal.u32NalSize = pInfo->u32Length;
2459 }
2460
2461 pHVDCtrl_Hal->LastNal.bRVBrokenPacket = pInfo->bRVBrokenPacket;
2462 pHVDCtrl_Hal->u32BBUPacketCnt++;
2463
2464 return eRet;
2465 }
2466
HAL_HVD_EnableISR(MS_BOOL bEnable)2467 void HAL_HVD_EnableISR(MS_BOOL bEnable)
2468 {
2469 if (bEnable)
2470 {
2471 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, 0, HVD_REG_RISC_ISR_MSK);
2472 }
2473 else
2474 {
2475 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK);
2476 }
2477 }
2478
HAL_HVD_SetForceISR(MS_BOOL bEnable)2479 void HAL_HVD_SetForceISR(MS_BOOL bEnable)
2480 {
2481 if( bEnable )
2482 {
2483 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_ISR_FORCE, HVD_REG_RISC_ISR_FORCE);
2484 }
2485 else
2486 {
2487 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, 0, HVD_REG_RISC_ISR_FORCE);
2488 }
2489 }
2490
HAL_HVD_SetClearISR(void)2491 void HAL_HVD_SetClearISR(void)
2492 {
2493 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_ISR_CLR , HVD_REG_RISC_ISR_CLR);
2494 }
2495
HAL_HVD_IsISROccured(void)2496 MS_BOOL HAL_HVD_IsISROccured(void)
2497 {
2498 return (MS_BOOL)(_HVD_Read2Byte( HVD_REG_RISC_MBOX_RDY )& HVD_REG_RISC_ISR_VALID );
2499 }
2500
HAL_HVD_IsEnableISR(void)2501 MS_BOOL HAL_HVD_IsEnableISR(void)
2502 {
2503 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR) & HVD_REG_RISC_ISR_MSK)
2504 {
2505 return FALSE;
2506 }
2507 else
2508 {
2509 return TRUE;
2510 }
2511 }
2512
HAL_HVD_IsAlive(void)2513 MS_BOOL HAL_HVD_IsAlive(void)
2514 {
2515 if (pHVDCtrl_Hal)
2516 {
2517 if ((pHVDCtrl_Hal->LivingStatus.u32DecCnt == HAL_HVD_GetData(E_HVD_GDATA_DECODE_CNT))
2518 && (pHVDCtrl_Hal->LivingStatus.u32SkipCnt == HAL_HVD_GetData(E_HVD_GDATA_SKIP_CNT))
2519 && (pHVDCtrl_Hal->LivingStatus.u32IdleCnt == HAL_HVD_GetData(E_HVD_GDATA_VPU_IDLE_CNT))
2520 && (pHVDCtrl_Hal->LivingStatus.u32MainLoopCnt == HAL_HVD_GetData(E_HVD_GDATA_MAIN_LOOP_CNT)))
2521 {
2522 return FALSE;
2523 }
2524 else
2525 {
2526 return TRUE;
2527 }
2528 }
2529 else
2530 {
2531 return FALSE;
2532 }
2533 }
2534
HAL_HVD_RstPTSCtrlVariable(void)2535 MS_BOOL HAL_HVD_RstPTSCtrlVariable(void)
2536 {
2537 if( (pHVDCtrl_Hal->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV )
2538 {
2539 #if defined(UDMA_FPGA_ENVI)
2540 HVD_UDMA_memcpy( (void*)UDMA_fpga_HVDShareMemAddr , &UDMA_pc_HVDShareMem , sizeof(HVD_Display_Info ) );
2541 #endif
2542 HAL_HVD_ReadMemory();
2543
2544 u32PTSRptrAddr=pHVDShareMem->u32PTStableRptrAddr;
2545 u32PTSWptrAddr=pHVDShareMem->u32PTStableWptrAddr;
2546 u32PTSByteCnt = pHVDShareMem->u32PTStableByteCnt;
2547 u32PTSPreWptr=HAL_VPU_MemRead( u32PTSWptrAddr );
2548 HVD_MSG_DEG( "HVD hal:PTS table: WptrAddr:%lx RptrAddr:%lx ByteCnt:%lx PreWptr:%lx\n" , u32PTSWptrAddr , u32PTSRptrAddr ,u32PTSByteCnt ,u32PTSPreWptr );
2549 }
2550 return TRUE;
2551 }
2552
HAL_HVD_FlushRstShareMem(void)2553 MS_BOOL HAL_HVD_FlushRstShareMem(void)
2554 {
2555 HVD_memset( &pHVDShareMem->DecoFrmInfo , 0 , sizeof(HVD_Frm_Information) );
2556 HAL_HVD_FlushMemory();
2557 return TRUE;
2558 }
2559
2560
HAL_HVD_UartSwitch2FW(MS_BOOL bEnable)2561 void HAL_HVD_UartSwitch2FW( MS_BOOL bEnable )
2562 {
2563 if( bEnable)
2564 {
2565 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_VD_MHEG5, REG_TOP_UART_SEL_0_MASK);
2566 }
2567 else
2568 {
2569 #if defined (__aeon__)
2570 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
2571 #else // defined (__mips__)
2572 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_PIU_0, REG_TOP_UART_SEL_0_MASK);
2573 #endif
2574 }
2575 }
2576
HAL_HVD_GetData_Dbg(MS_U32 u32Addr)2577 MS_U32 HAL_HVD_GetData_Dbg( MS_U32 u32Addr )
2578 {
2579 return 0;
2580 }
2581
HAL_HVD_SetData_Dbg(MS_U32 u32Addr,MS_U32 u32Data)2582 void HAL_HVD_SetData_Dbg( MS_U32 u32Addr , MS_U32 u32Data)
2583 {
2584 return ;
2585 }
2586
HAL_HVD_GetCorretClock(MS_U16 u16Clock)2587 MS_U16 HAL_HVD_GetCorretClock(MS_U16 u16Clock)
2588 {
2589 //if( u16Clock == 0 )
2590 return 216;//140;
2591 //if( )
2592 }
2593
HAL_HVD_UpdateESWptr_Fire(void)2594 void HAL_HVD_UpdateESWptr_Fire(void)
2595 {
2596 MS_BOOL bBitMIU1 = FALSE;
2597 MS_BOOL bCodeMIU1 = FALSE;
2598 if( pHVDCtrl_Hal->MemMap.u32CodeBufAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr )
2599 {
2600 bCodeMIU1=TRUE;
2601 }
2602 if( pHVDCtrl_Hal->MemMap.u32BitstreamBufAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr )
2603 {
2604 bBitMIU1=TRUE;
2605 }
2606 if( bBitMIU1 != bCodeMIU1 )
2607 {
2608 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
2609 BDMA_Result bdmaRlt;
2610 MS_U32 u32DstAdd=0 , u32SrcAdd=0 , u32tabsize=0;
2611 u32DstAdd = pHVDCtrl_Hal->MemMap.u32BitstreamBufAddr+pHVDCtrl_Hal->u32BBUTblInBitstreamBufAddr;
2612 u32SrcAdd = pHVDCtrl_Hal->MemMap.u32CodeBufAddr + HVD_BBU_DRAM_ST_ADDR;
2613 u32tabsize = u32BBUEntryNum << 3;
2614 //bdmaRlt = MDrv_BDMA_MemCopy(u32SrcAdd, u32DstAdd, SLQ_TBL_SIZE);
2615 HAL_HVD_FlushMemory();
2616 bdmaRlt = HVD_dmacpy( u32DstAdd, u32SrcAdd, u32tabsize);
2617 if (E_BDMA_OK != bdmaRlt)
2618 {
2619 HVD_MSG_ERR("HVD Err:MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
2620 }
2621 #else
2622 MS_U32 u32DstAdd=0 , u32SrcAdd=0 , u32tabsize=0;
2623 u32DstAdd = pHVDCtrl_Hal->MemMap.u32BitstreamBufVAddr+pHVDCtrl_Hal->u32BBUTblInBitstreamBufAddr;
2624 u32SrcAdd = pHVDCtrl_Hal->MemMap.u32CodeBufVAddr + HVD_BBU_DRAM_ST_ADDR;
2625 u32tabsize = u32BBUEntryNum << 3;
2626 HVD_memcpy( u32DstAdd, u32SrcAdd, u32tabsize);
2627 HAL_HVD_FlushMemory();
2628 #endif
2629 }
2630 // HVD_MSG_INFO( "HVD Push packet fire:%lu st:%lx size:%lx BBU:%lu %lu\n", pHVDCtrl_Hal->u32BBUPacketCnt , pHVDCtrl_Hal->LastNal.u32NalAddr , pHVDCtrl_Hal->LastNal.u32NalSize , (MS_U32)_HAL_HVD_GetBBUReadptr() , u32BBUWptr );
2631 _HAL_HVD_SetBBUWriteptr( HVD_LWORD(u32BBUWptr) );
2632 pHVDCtrl_Hal->u32BBUWptr_Fired = u32BBUWptr;
2633 }
2634
HAL_HVD_MVD_PowerCtrl(MS_BOOL bEnable)2635 void HAL_HVD_MVD_PowerCtrl(MS_BOOL bEnable)
2636 {
2637 if( bEnable )
2638 {
2639 _HVD_WriteWordMask(REG_TOP_MVD, 0 , TOP_CKG_MHVD_DIS );
2640 _HVD_WriteWordMask(REG_TOP_MVD2, 0 , TOP_CKG_MHVD2_DIS );
2641 }
2642 else
2643 {
2644 _HVD_WriteWordMask(REG_TOP_MVD, TOP_CKG_MHVD_DIS , TOP_CKG_MHVD_DIS );
2645 _HVD_WriteWordMask(REG_TOP_MVD2, TOP_CKG_MHVD2_DIS , TOP_CKG_MHVD2_DIS );
2646 }
2647 }
2648
HAL_HVD_Dump_FW_Status(void)2649 void HAL_HVD_Dump_FW_Status(void)
2650 {
2651 MS_U32 tmp1=0;
2652 MS_U32 tmp2=0;
2653 HAL_HVD_ReadMemory();
2654
2655 _HAL_HVD_MBoxRead( HAL_HVD_CMD_MBOX , &tmp1 );
2656 _HAL_HVD_MBoxRead( HAL_HVD_CMD_ARG_MBOX , &tmp2 );
2657 HVD_MSG_DEG("=====HVD Dump Systime:%lu FW Ver:%lx status: %lx Err Code: %lx PC: %lx =====\n" , HVD_GetSysTime_ms() , pHVDShareMem->u32FWVersionID , _HAL_HVD_GetFWState() , (MS_U32)pHVDShareMem->u16ErrCode , HAL_VPU_GetProgCnt() );
2658
2659 HVD_MSG_DEG("Time: STC:%lu DispT:%lu Dec:%lu PTS(skip,seek):%lu; Last Cmd:%lx _Arg:%lx _Rdy1:%lx _Rdy2:%lx\n" ,
2660 pHVDShareMem->u32DispSTC , pHVDShareMem->DispFrmInfo.u32TimeStamp , pHVDShareMem->DecoFrmInfo.u32TimeStamp , pHVDShareMem->u32CurrentPts,
2661 tmp1 , tmp2 , (MS_U32)_HAL_HVD_MBoxReady(HAL_HVD_CMD_MBOX) , (MS_U32)_HAL_HVD_MBoxReady(HAL_HVD_CMD_ARG_MBOX) );
2662
2663 HVD_MSG_DEG("Flag: InitDone:%d SPS_change:%d IFrm:%d 1stFrmRdy:%d Sync_Start:%d _Reach:%d \n" ,
2664 pHVDShareMem->bInitDone , _HAL_HVD_MBoxReady( HAL_HVD_REG_DISP_INFO_CHANGE ) , pHVDShareMem->bIsIFrmFound , pHVDShareMem->bIs1stFrameRdy ,
2665 pHVDShareMem->bIsSyncStart , pHVDShareMem->bIsSyncReach );
2666
2667 HVD_MSG_DEG("Queue: BBU:%lu Dec:%d Disp:%d ESR:%lu ESRfromFW:%lu ESW:%lu ESLevel:%lu\n" ,
2668 _HAL_HVD_GetBBUQNumb() , pHVDShareMem->u16DecQNumb , pHVDShareMem->u16DispQNumb ,
2669 _HAL_HVD_GetESReadPtr(TRUE), pHVDShareMem->u32ESReadPtr, _HAL_HVD_GetESWritePtr() , _HAL_HVD_GetESLevel() );
2670
2671 HVD_MSG_DEG("Counter: Dec:%lu Disp:%lu Err_Data:%lu _Dec:%lu Skip:%lu Drop:%lu Idle:%lu Main:%lu Vsync:%lu\n" ,
2672 pHVDShareMem->u32DecodeCnt , pHVDShareMem->u32DispCnt , pHVDShareMem->u32DataErrCnt ,
2673 pHVDShareMem->u32DecErrCnt , pHVDShareMem->u32SkipCnt , pHVDShareMem->u32DropCnt ,
2674 pHVDShareMem->u32VPUIdleCnt , pHVDShareMem->u32MainLoopCnt, pHVDShareMem->u32VsyncCnt);
2675 HVD_MSG_DEG("Mode: ShowErr:%d RepLastField:%d SyncOn:%d FileEnd:%d Skip:%d Drop:%d DispSpeed:%d FRC:%d BlueScreen:%d FreezeImg:%d 1Field:%d\n" ,
2676 pHVDShareMem->ModeStatus.bIsShowErrFrm , pHVDShareMem->ModeStatus.bIsRepeatLastField ,
2677 pHVDShareMem->ModeStatus.bIsSyncOn , pHVDShareMem->ModeStatus.bIsPlaybackFinish ,
2678 pHVDShareMem->ModeStatus.u8SkipMode , pHVDShareMem->ModeStatus.u8DropMode ,
2679 pHVDShareMem->ModeStatus.s8DisplaySpeed , pHVDShareMem->ModeStatus.u8FrcMode ,
2680 pHVDShareMem->ModeStatus.bIsBlueScreen , pHVDShareMem->ModeStatus.bIsFreezeImg ,
2681 pHVDShareMem->ModeStatus.bShowOneField);
2682 HVD_MSG_DEG("====================================\n" );
2683 }
2684
HAL_HVD_GetBBUEntry(MS_U32 u32Idx,MS_U32 * u32NalOffset,MS_U32 * u32NalSize)2685 void HAL_HVD_GetBBUEntry( MS_U32 u32Idx , MS_U32* u32NalOffset , MS_U32* u32NalSize )
2686 {
2687 MS_U8* addr=NULL;
2688 if( u32Idx >= u32BBUEntryNum )
2689 {
2690 return;
2691 }
2692 addr = (MS_U8*)((pHVDCtrl_Hal->MemMap.u32CodeBufVAddr)+ HVD_BBU_DRAM_ST_ADDR + (u32Idx<<3));
2693 *u32NalSize = *(addr +2) & 0x1f;
2694 *u32NalSize <<=8;
2695 *u32NalSize |= *(addr +1) & 0xff;
2696 *u32NalSize <<=8;
2697 *u32NalSize |= *(addr) & 0xff;
2698
2699 *u32NalOffset = ((MS_U32)(*(addr+2) & 0xe0)) >> 5;
2700 *u32NalOffset |= ((MS_U32)(*(addr+3) & 0xff)) << 3;
2701 *u32NalOffset |= ((MS_U32)(*(addr+4) & 0xff)) << 11;
2702 *u32NalOffset |= ((MS_U32)(*(addr+5) & 0xff)) << 19;
2703 }
2704
HAL_HVD_Dump_BBUs(MS_U32 u32StartIdx,MS_U32 u32EndIdx,MS_BOOL bShowEmptyEntry)2705 void HAL_HVD_Dump_BBUs( MS_U32 u32StartIdx, MS_U32 u32EndIdx, MS_BOOL bShowEmptyEntry )
2706 {
2707 MS_U32 u32CurIdx=0;
2708 MS_BOOL bFinished=FALSE;
2709 MS_U32 u32NalOffset=0 ;
2710 MS_U32 u32NalSize=0;
2711 if( (u32StartIdx >= u32BBUEntryNum) || (u32EndIdx >= u32BBUEntryNum) )
2712 {
2713 return;
2714 }
2715 u32CurIdx = u32StartIdx;
2716 do
2717 {
2718 if( u32CurIdx == u32EndIdx )
2719 {
2720 bFinished =TRUE;
2721 }
2722 HAL_HVD_GetBBUEntry( u32CurIdx , &u32NalOffset , &u32NalSize );
2723 if( (bShowEmptyEntry ==FALSE) ||
2724 ( bShowEmptyEntry && (u32NalOffset ==0) && (u32NalSize ==0) ))
2725 {
2726 HVD_MSG_DEG( "HVD BBU Entry: Idx:%lu Offset:%lx Size:%lx\n", u32CurIdx , u32NalOffset , u32NalSize );
2727 }
2728 u32CurIdx++;
2729 if( u32CurIdx >= u32BBUEntryNum )
2730 {
2731 u32CurIdx%=u32BBUEntryNum;
2732 }
2733 }while(bFinished == TRUE);
2734 }
2735
2736 // This function is used by MJPEG driver
HAL_HVD_LoadCode(MS_U32 u32DestAddr,MS_U32 u32Size,MS_U32 u32BinAddr,MS_U8 u8FwSrcType)2737 MS_BOOL HAL_HVD_LoadCode(MS_U32 u32DestAddr, MS_U32 u32Size, MS_U32 u32BinAddr, MS_U8 u8FwSrcType)
2738 {
2739 #if HVD_ENABLE_BDMA_FW_FLASH_2_SDRAM
2740 MS_U32 u32MIU1Base=0;
2741 #ifdef HAL_MIU1_BASE
2742 u32MIU1Base = HAL_MIU1_BASE;
2743 #else
2744 u32MIU1Base=0x08000000;
2745 #endif
2746 #endif
2747
2748 if (u8FwSrcType == E_HVD_FW_INPUT_SOURCE_FLASH)
2749 {
2750 #if HVD_ENABLE_BDMA_FW_FLASH_2_SDRAM
2751 if(u32Size != 0)
2752 {
2753 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
2754 if (u32DestAddr >= u32MIU1Base)
2755 {
2756 cpyflag = E_SPIDMA_DEV_MIU1;
2757 }
2758 else
2759 {
2760 cpyflag = E_SPIDMA_DEV_MIU0;
2761 }
2762
2763 if( ! HVD_FLASHcpy(u32DestAddr, u32BinAddr, u32Size, cpyflag))
2764 {
2765 return FALSE;
2766 }
2767 }
2768 else
2769 {
2770 return FALSE;
2771 }
2772 #else
2773 return FALSE;
2774 #endif
2775 }
2776 else
2777 if (u8FwSrcType == E_HVD_FW_INPUT_SOURCE_DRAM)
2778 {
2779 if(u32BinAddr != 0 && u32Size != 0)
2780 {
2781 HVD_memcpy((void*)(u32DestAddr), (void*)(u32BinAddr), u32Size);
2782 }
2783 else
2784 {
2785 return FALSE;
2786 }
2787 }
2788 else
2789 {
2790 #if HVD_ENABLE_EMBEDDED_FW_BINARY
2791 HVD_memcpy( (void*)(u32DestAddr), (void*)(u8HVD_FW_Binary) , sizeof(u8HVD_FW_Binary));
2792 #else
2793 return FALSE;
2794 #endif
2795 }
2796 //HAL_HVD_FlushMemory();
2797 MAsm_CPU_Sync();
2798 MsOS_FlushMemory();
2799
2800 //Init shareMem
2801 pHVDShareMem = (volatile HVD_ShareMem*)(u32DestAddr + HVD_SHARE_MEM_ST_OFFSET);
2802 HVD_memset( (volatile void*)pHVDShareMem, 0, sizeof( HVD_ShareMem ) );
2803 //Set Chip Id
2804 pHVDShareMem->u16ChipID = E_MSTAR_CHIP_A3;
2805 pHVDShareMem->u16ChipECONum = 0;
2806 HAL_HVD_FlushMemory();
2807
2808 return TRUE;
2809 }
2810
HAL_HVD_SetMiuBurstLevel(HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)2811 void HAL_HVD_SetMiuBurstLevel(HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)
2812 {
2813 if (pHVDCtrl_Hal)
2814 {
2815 pHVDCtrl_Hal->Settings.u32MiuBurstLevel = (MS_U32) eMiuBurstCntCtrl;
2816 }
2817 }
2818
2819 #ifdef _HVD_DQ
HAL_HVD_GetShmMemAddr(void)2820 void* HAL_HVD_GetShmMemAddr(void)
2821 {
2822 return (void*)pHVDShareMem;
2823 }
2824 #endif
2825
2826 #define HVD_HW_MAX_PIXEL (1920*1088*51000ULL) //FullHD@50p
HAL_HVD_GetFrmRateIsSupported(MS_U16 u16HSize,MS_U16 u16VSize,MS_U32 u32FrmRate)2827 MS_BOOL HAL_HVD_GetFrmRateIsSupported(MS_U16 u16HSize, MS_U16 u16VSize, MS_U32 u32FrmRate)
2828 {
2829 HVD_MSG_DEG("%s w:%d, h:%d, fr:%ld, MAX:%lld\n", __FUNCTION__, u16HSize, u16VSize, u32FrmRate, HVD_HW_MAX_PIXEL);
2830 return (((MS_U64)u16HSize*(MS_U64)u16VSize*(MS_U64)u32FrmRate) <= HVD_HW_MAX_PIXEL);
2831 }
2832
2833