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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _FW_HVD_IF_H_ 96 #define _FW_HVD_IF_H_ 97 98 //------------------------------------------------------------------------------------------------- 99 // Hardware Capability 100 //------------------------------------------------------------------------------------------------- 101 #define HVD_FW_VERSION 0x00001993 102 #define HVD_FW_IF_VERSION 0x00310153 103 104 //------------------------------------------------------------------------------------------------- 105 // Macro and Define 106 //------------------------------------------------------------------------------------------------- 107 // TOP 108 //#if (!(defined( MSOS_TYPE_NOS) ||defined( MSOS_TYPE_ECOS) || defined( MSOS_TYPE_LINUX))) 109 #if (!defined( _MS_TYPES_H_) && (!defined(_DRVHVD_COMMON_H_))) 110 typedef unsigned char MS_BOOL; // 1 byte 111 /// data type unsigned char, data length 1 byte 112 typedef unsigned char MS_U8; // 1 byte 113 /// data type unsigned short, data length 2 byte 114 typedef unsigned short MS_U16; // 2 bytes 115 /// data type unsigned int, data length 4 byte 116 typedef unsigned long MS_U32; // 4 bytes 117 /// data type unsigned int64, data length 8 byte 118 typedef unsigned long long MS_U64; // 8 bytes 119 /// data type signed char, data length 1 byte 120 typedef signed char MS_S8; // 1 byte 121 /// data type signed short, data length 2 byte 122 typedef signed short MS_S16; // 2 bytes 123 /// data type signed int, data length 4 byte 124 typedef signed long MS_S32; // 4 bytes 125 /// data type signed int64, data length 8 byte 126 typedef signed long long MS_S64; // 8 bytes 127 #endif 128 129 // FW version 130 #define HVD_FW_VER_RELEASE_VERSION 0x00000080 // BIT(7) 131 #define HVD_FW_VER_DUMP_DEBUG_MSG 0x00000040 // BIT(6) 132 133 // HW settings (Offset base is code buffer address.) 134 #define HVD_SRAM_START 0x20000000UL 135 136 #define HVD_PTS_TABLE_ST_OFFSET 0x70000 137 #define MAX_PTS_TABLE_SIZE 2048 // max (reserve 0x70000~0x78000) //1024 138 #define AVOID_PTS_TABLE_OVERFLOW_THRESHOLD 24 139 #define HVD_BYTE_COUNT_MASK 0x1FFFFFFF // hvd fw reg_byte_pos 29bit 140 141 #define HVD_BBU_DRAM_ST_ADDR 0x78000 // bbu table from dram starting address 142 #define HVD_BBU_DRAM_TBL_ENTRY (0x1000/8) // bbu entry. 64bits(8 bytes) every entry. 143 #define HVD_BBU_DRAM_TBL_ENTRY_TH (HVD_BBU_DRAM_TBL_ENTRY-4) // bbu entry. 64bits(8 bytes) every entry. 144 #define RVD_BBU_DRAM_TBL_ENTRY (0x4000/8) // bbu entry. 64bits(8 bytes) every entry. 145 #define RVD_BBU_DRAM_TBL_ENTRY_TH (RVD_BBU_DRAM_TBL_ENTRY-4) // bbu entry. 64bits(8 bytes) every entry. 146 147 #define HVD_DYNAMIC_SCALING_ADDR 0x7C000 148 //#define HVD_DYNAMIC_SCALING_SIZE 0x1000 // 4K 149 #define HVD_DYNAMIC_SCALING_SIZE 0xF00 // reserve 0x100 for scaler info 150 #define HVD_DYNAMIC_SCALING_DEPTH 0x10 //12//8 151 #define HVD_SCALER_INFO_ADDR 0x7CF00 152 #define HVD_SCALER_INFO_SIZE 0x100 // 256 153 154 #define HVD_SHARE_MEM_ST_OFFSET 0x7D000 155 #define HVD_SHARE_MEM2_ST_OFFSET (HVD_SHARE_MEM_ST_OFFSET + 0x1000) 156 157 #define HVD_AVC_FRAME_PACKING_SEI_SIZE 0x100 158 #define HVD_AVC_FRAME_PACKING_SEI_NUM 2 159 160 #define HVD_DUMMY_WRITE_ADDR 0x8FE00 161 #define HVD_DUMMY_WRITE_MAX_SIZE 0x200 162 163 #define HVD_DBG_DUMP_ADDR 0x90000 164 #define HVD_DBG_DUMP_SIZE 0x70000 165 166 #define HVD_DISP_QUEUE_MAX_SIZE 32 167 // AVC 168 #define HVD_FW_AVC_DUMMY_FIFO 256 // bytes 169 #define HVD_FW_AVC_MAX_DECODE_TICK 100000 // tick ??? 170 #define HVD_FW_AVC_MAX_VIDEO_DELAY 1000 // ms ; based on ??? 171 #define HVD_FW_AVC_ES_MIN_TSP_DATA_SIZE 0x100 172 #define HVD_FW_AVC_ES_UNDER_THRESHOLD 0x800 // 2048 173 #define HVD_FW_AVC_ES_OVER_THRESHOLD 0x12C00 // 75*1024 174 175 // User CC 176 #define USER_CC_DATA_SIZE 32 177 #define USER_CC_IDX_SIZE 12 178 179 // AVS 180 #define HVD_FW_AVS_DUMMY_FIFO 2048 //BYTES 181 182 // RM 183 #define HVD_FW_RM_DUMMY_FIFO 256 // ?? 184 #define HVD_RM_INIT_PICTURE_SIZE_NUMBER 8 185 186 // Debug 187 #define HVD_FW_AVS_OUTPUT_INFO_ADDR 0x20001F00UL 188 #define HVD_FW_AVC_OUTPUT_INFO_ADDR 0x20001F00UL 189 190 #define PRESET_ONE_PENDING_BUFFER (1 << 0) /// For AVC, one pending buffer mode, reduce from two to one 191 #define PRESET_FRAMERATE_HANDLING (1 << 1) /// For AVC, Handle frame rate by input frame rate when sequence did not have frame rate info. 192 193 typedef enum 194 { 195 E_HVD_ISR_EVENT_NONE = 0, ///< disable ISR 196 E_HVD_ISR_EVENT_DISP_ONE = BIT(0), ///< HVD display one frame on screen. 197 E_HVD_ISR_EVENT_DISP_REPEAT = BIT(1), ///< The current displayed frame is repeated frame. 198 E_HVD_ISR_EVENT_DISP_WITH_CC = BIT(2), ///< Current displayed frame should be displayed with user data. 199 E_HVD_ISR_EVENT_DISP_FIRST_FRM = BIT(3), ///< HVD display first frame on screen. 200 201 E_HVD_ISR_EVENT_DEC_ONE = BIT(8), ///< HVD decoded one frame done. 202 E_HVD_ISR_EVENT_DEC_I = BIT(9), ///< HVD decoded one I frame done. 203 E_HVD_ISR_EVENT_DEC_HW_ERR = BIT(10), ///< HVD HW found decode error. 204 E_HVD_ISR_EVENT_DEC_CC_FOUND = BIT(11), ///< HVD found one user data with decoded frame(with display order). 205 E_HVD_ISR_EVENT_DEC_DISP_INFO_CHANGE = BIT(12), ///< HVD found display information change. 206 E_HVD_ISR_EVENT_DEC_DATA_ERR = BIT(13), ///< HVD HW found decode error. 207 E_HVD_ISR_EVENT_DEC_FIRST_FRM = BIT(14), ///< HVD decode first frame. 208 } HVD_ISR_Event_Type; 209 210 /* 211 //interupt flag , value is in VPU RISC MBOX 1 ( for LG GP DTV only) 212 #define HVD_ISR_USER_DATA (1 << 0) 213 #define HVD_ISR_DATA_ERR (1 << 1) 214 #define HVD_ISR_PIC_DEC_ERR (1 << 2) 215 #define HVD_ISR_DEC_OVER (1 << 3) 216 #define HVD_ISR_DEC_UNDER (1 << 4) 217 #define HVD_ISR_DEC_I (1 << 5) 218 #define HVD_ISR_DIS_READY (1 << 6) 219 #define HVD_ISR_SEQ_INFO (1 << 7) 220 #define HVD_ISR_VIDEO_SKIP (1 << 8) 221 #define HVD_ISR_VIDEO_REPEAT (1 << 9) 222 #define HVD_ISR_VIDEO_FREERUN (1 << 10) 223 #define HVD_ISR_INVALID_STREAM (1 << 11) 224 #define HVD_ISR_VIDEO_AVSYNC_DONE (1 << 12) 225 #define HVD_ISR_VIDEO_VSYNC (1 << 31) 226 */ 227 228 //------------------------------------------------------------------------------------------------- 229 // Type and Structure 230 //------------------------------------------------------------------------------------------------- 231 // User CC 232 #define USR_BUF_SIZE (256-16) 233 234 typedef struct _DTV_BUF_type 235 { 236 MS_U8 type; // 0xCC:continue, 0:P 1:B 2:I 237 MS_U8 len; // size byte of buf 238 MS_U8 active; // 0:free 1:already dma out or not assign 2:assign 239 MS_U8 pic_struct; // pic_struct, Reserved when 0, Top Field when 1, Bottom Field when 2, and Frame picture when 3. 240 MS_U32 pts; 241 MS_U16 u16TempRefCnt; // Temp Ref Count for UserData ,Value that increases by 1 for each frame (like time stamp) 242 MS_U16 u16Res; // Reserved 243 MS_U32 u32Res; // Reserved 244 MS_U8 buf[USR_BUF_SIZE]; //user data 245 } DTV_BUF_type; //size should be 256 246 247 #define HVD_FRM_PACKIMG_PAYLOAD_SIZE ((HVD_AVC_FRAME_PACKING_SEI_SIZE/HVD_AVC_FRAME_PACKING_SEI_NUM)-20) /// 20: HVD_Frame_packing_SEI size expect payload data 248 249 typedef struct 250 { 251 MS_BOOL bUsed; 252 MS_BOOL bvaild; 253 MS_U8 u8Frm_packing_arr_cnl_flag; // u(1) 254 MS_U8 u8Frm_packing_arr_type; // u(7) 255 MS_U8 u8content_interpretation_type; // u(6) 256 MS_U8 u1Quincunx_sampling_flag:1; // u(1) 257 MS_U8 u1Spatial_flipping_flag:1; // u(1) 258 MS_U8 u1Frame0_flipping_flag:1; // u(1) 259 MS_U8 u1Field_views_flag:1; // u(1) 260 MS_U8 u1Current_frame_is_frame0_flag:1; // u(1) 261 MS_U8 u1Frame0_self_contained_flag:1; // u(1) 262 MS_U8 u1Frame1_self_contained_flag:1; // u(1) 263 MS_U8 u1Reserved1:1; // u(1) 264 MS_U8 u4Frame0_grid_position_x:4; // u(4) 265 MS_U8 u4Frame0_grid_position_y:4; // u(4) 266 MS_U8 u4Frame1_grid_position_x:4; // u(4) 267 MS_U8 u4Frame1_grid_position_y:4; // u(4) 268 MS_U16 u16CropRight; 269 MS_U16 u16CropLeft; 270 MS_U16 u16CropBottom; 271 MS_U16 u16CropTop; 272 MS_U8 u8payload_len; 273 MS_U8 u8WaitSPS; 274 MS_U8 u8Reserved[2]; 275 MS_U8 u8payload[HVD_FRM_PACKIMG_PAYLOAD_SIZE]; 276 } HVD_Frame_packing_SEI; 277 278 // stuct 279 typedef struct 280 { 281 MS_U16 u16HorSize; 282 MS_U16 u16VerSize; 283 MS_U32 u32FrameRate; // Unit: ms 284 MS_U8 u8AspectRate; // aspect ration ID; for AVC only 285 MS_U8 u8Interlace; 286 MS_U8 u8AFD; 287 //MS_U8 u8par_width; 288 //MS_U8 u8par_height; 289 MS_U8 bChroma_idc_Mono; // 1: mono 0: colorful, not mono ; AVC only currently. AVS,RM?? 290 MS_U16 u16DispWidth; // Display width or aspect ratio width 291 MS_U16 u16DispHeight; // Display height or aspect ratio height 292 MS_U16 u16CropRight; 293 MS_U16 u16CropLeft; 294 MS_U16 u16CropBottom; 295 MS_U16 u16CropTop; 296 MS_U16 u16Pitch; // ??? 297 MS_U8 u8ColourPrimaries; // Color Primaries in VUI 298 //**************************** 299 MS_U8 u8IsOriginInterlace; // Is Original Interlace mode 300 //****************************** 301 // MS_U16 u16PTSInterval; // ??? not fill 302 // MS_U8 u8MPEG1; // may be removed 303 // MS_U8 u8PlayMode; // ??? not fill 304 // MS_U8 u8FrcMode; // may be removed 305 } HVD_Display_Info; // bytes 306 307 typedef struct 308 { 309 MS_U8 bIsShowErrFrm; 310 MS_U8 bIsRepeatLastField; 311 MS_U8 bIsErrConceal; 312 MS_U8 bIsSyncOn; 313 MS_U8 bIsPlaybackFinish; 314 MS_U8 u8SyncType; // HVD_Sync_Tbl_Type 315 MS_U8 u8SkipMode; // HVD_Skip_Decode_Type 316 MS_U8 u8DropMode; // HVD_Drop_Disp_Type 317 MS_S8 s8DisplaySpeed; // HVD_Disp_Speed 318 MS_U8 u8FrcMode; // HVD_FRC_Mode 319 MS_U8 bIsBlueScreen; 320 MS_U8 bIsFreezeImg; 321 MS_U8 bShowOneField; 322 //***************************** 323 MS_U8 u8reserve8_1; 324 MS_U16 u16reserve16_1; 325 //***************************** 326 } HVD_Mode_Status; // 12 bytes 327 328 typedef struct 329 { 330 MS_U16 u16Width; 331 MS_U16 u16Height; 332 } HVD_PictureSize; 333 334 typedef struct 335 { 336 MS_U32 u32LumaAddr; ///< The start offset of luma data. Unit: byte. 337 MS_U32 u32ChromaAddr; ///< The start offset of chroma data. Unit: byte. 338 MS_U32 u32TimeStamp; ///< Time stamp(DTS, PTS) of current displayed frame. Unit: 90khz. 339 MS_U32 u32ID_L; ///< low part of ID number decided by MDrv_HVD_PushQueue(). 340 MS_U32 u32ID_H; ///< high part of ID number decided by MDrv_HVD_PushQueue(). 341 MS_U8 u8FrmType; ///< HVD_Picture_Type, picture type: I, P, B frame 342 MS_U8 u8FieldType; ///< HVD_Field_Type, none, top , bottom, both field 343 MS_U16 u16Pitch; 344 MS_U16 u16Width; 345 MS_U16 u16Height; 346 MS_U32 u32Status; ///< 0:None, 1:Init, 2:View, 3:Disp, 4:Free 347 } HVD_Frm_Information; 348 349 typedef struct 350 { 351 MS_BOOL aspect_ratio_info_present_flag; // u(1) 352 MS_U8 aspect_ratio_idc; // u(8) 353 MS_U16 sar_width; // u(16) 354 MS_U16 sar_height; // u(16) 355 MS_BOOL overscan_info_present_flag; // u(1) 356 MS_BOOL overscan_appropriate_flag; // u(1) 357 MS_BOOL video_signal_type_present_flag; // u(1) 358 MS_U8 video_format; // u(3) 359 MS_BOOL video_full_range_flag; // u(1) 360 MS_BOOL colour_description_present_flag; // u(1) 361 MS_U8 colour_primaries; // u(8) 362 MS_U8 transfer_characteristics; // u(8) 363 MS_U8 matrix_coefficients; // u(8) 364 MS_BOOL chroma_location_info_present_flag; // u(1) 365 MS_U8 chroma_sample_loc_type_top_field; // ue(v) 0~5 366 MS_U8 chroma_sample_loc_type_bottom_field; // ue(v) 0~5 367 MS_BOOL timing_info_present_flag; // u(1) 368 MS_BOOL fixed_frame_rate_flag; // u(1) 369 MS_U32 num_units_in_tick; // u(32) 370 MS_U32 time_scale; // u(32) 371 } HVD_AVC_VUI_DISP_INFO; 372 373 typedef struct 374 { 375 MS_U32 u32FrmrateUpBound; //Framerate filter upper bound 376 MS_U32 u32FrmrateLowBound; //Framerate filter lower bound 377 MS_U32 u32MvopUpBound; //mvop filter upper bound 378 MS_U32 u32MvopLowBound; //mvop filter lower bound 379 } HVD_DISP_THRESHOLD; 380 381 typedef struct 382 { 383 // switch 384 MS_U32 u32CodecType; //0x0000 385 MS_U32 u32FrameBufAddr; //0x0004 386 MS_U32 u32FrameBufSize; //0x0008 387 MS_U32 u32CPUClock; //0x000C 388 HVD_Display_Info DispInfo; //0x0010 389 390 // FW -> HK 391 // report info 392 //AFD_Info AFDInfo; 393 MS_U32 u32DispSTC; //0x002C // Current Display Frame STC 394 MS_U32 u32DecodeCnt; //0x0030 // Decoded picture count 395 MS_U32 u32DecErrCnt; //0x0034 // HW decode err or not finish. 396 MS_U32 u32DataErrCnt; //0x0038 // FW process data error, like SPS, slice header .etc. 397 MS_U16 u16ErrCode; //0x003C // Drv/FW error code ; HVD_Err_Code 398 MS_U8 u8FrameMbsOnlyFlag; //0x003E // frame_mbs_only_flag of AVC SPS. 399 MS_U8 reserved16_5; //0x003F 400 MS_U32 u32VPUIdleCnt; //0x0040 // VPU idle count 401 MS_U32 u32FrameRate; //0x0044 // Input Frame Rate 402 MS_U32 u32FrameRateBase; //0x0048 // Input Frame Rate Base 403 HVD_Mode_Status ModeStatus; //0x004C // FW mode 404 HVD_Frm_Information DispFrmInfo; //0x005C // current displayed frame information. 405 HVD_Frm_Information DecoFrmInfo; //0x007C // specified decoded frame information. 406 //MS_U8 u8DecPictType; // Current decode picture type: E_HVD_PICT_TYPE_I: I frm, E_HVD_PICT_TYPE_P: ref(P) , E_HVD_PICT_TYPE_B: non-ref(B) (GP2 need only) 407 408 // internal control info 409 MS_U8 bInitDone; //0x009C 410 MS_U8 bIs1stFrameRdy; //0x009D // first frame are showed on screen 411 MS_U8 bIsIFrmFound; //0x009E // 1: First I frame found. 0: fw should set to zero after user cmd, "Flush" 412 MS_U8 bIsSyncStart; //0x009F // under sync mode, 1: FW start doing sync action. 0: FW freerun or freerun mode. 413 MS_U8 bIsSyncReach; //0x00A0 // under sync mode, 1: FW sync reach. 0: FW freerun or sync not reach. 414 415 //**************************************** 416 417 MS_U8 u8SrcMode; //0x00A1 418 MS_U16 reserved16_0; //0x00A2 419 //**************************************** 420 MS_U32 u32FWVersionID; //0x00A4 // FW version ID 421 MS_U32 u32FWIfVersionID; //0x00A8 // FW IF version ID 422 MS_U32 u32ESWritePtr; //0x00AC // the write pointer of bitstream buffer. 423 MS_U16 u16DecQNumb; //0x00B0 // current decoded queue total entry number. old oq size 424 MS_U16 u16DispQNumb; //0x00B2 // current display queue total entry number. old Used Size 425 MS_U32 u32PTStableWptrAddr; //0x00B4 // The address of PTS table write pointer. 426 MS_U32 u32PTStableRptrAddr; //0x00B8 // The address of PTS table read pointer. 427 MS_U32 u32PTStableByteCnt; //0x00BC // The value of byte count of TSP. FW update it after init() and flush(). 428 429 // debug info 430 MS_U32 u32SkipCnt; //0x00C0 // skipped picture count count by command: E_HVD_DECODE_ALL, E_HVD_DECODE_I, E_HVD_DECODE_IP 431 MS_U32 u32DropCnt; //0x00C4 // dorpped decoded picture counter by command: drop_auto or drop_once 432 MS_U32 u32CCBase; //0x00C8 // CC Ring Base Address 433 MS_U32 u32CCSize; //0x00CC // CC Ring Size 434 MS_U32 u32CCWrtPtr; //0x00D0 // CC Ring Write Pointer 435 MS_U32 u32NtscCCBase; //0x00D4 // NTSC CC Ring Base Address 436 MS_U32 u32NtscCCSize; //0x00D8 // NTSC CC Ring Size 437 MS_U32 u32NtscCCWrtPtr; //0x00DC // NTSC CC Ring Write Pointer 438 //**************************************** 439 MS_U32 u32CurrentPts; //0x00E0 // only useful when Jump to pts command is activated 440 MS_U32 u32DispCnt; //0x00E4 // Display picture count 441 MS_U32 u32FWBaseAddr; //0x00E8 442 //**************************************** 443 MS_U32 u32UserCCBase; //0x00EC // User CC Base Address 444 MS_U32 u32UserCCIdxWrtPtr; //0x00F0 // User CC Idx Write Pointer 445 MS_U8 u8UserCCIdx[USER_CC_IDX_SIZE];//0x00F4 // User CC Idx 446 //**************************************** 447 MS_U32 u32VirtualBoxWidth; //0x0100 // Dynamic Scale: DRV -> FW 448 MS_U32 u32VirtualBoxHeight; //0x0104 // Dynamic Scale: DRV -> FW 449 MS_U32 u32SrcWidth; //0x0108 // Dynamic Scale: Source Width 450 MS_U32 u32SrcHeight; //0x010C // Dynamic Scale: Source Height 451 //**************************************** 452 MS_U8 reserved8_2; //0x0110 453 //**************************************** 454 455 // -------- AVC info -------- 456 //MS_U32 u32AVC_NalCnt; // Decoded nal count >> change to SRAM 457 MS_U8 u8AVC_SPS_LowDelayHrdFlag; //0x0111 // VUI low_delay_hrd_flag 458 MS_U16 u16AVC_SPS_LevelIDC; //0x0112 // sps level idc 459 MS_U32 u32AVC_VUIDispInfo_Addr; //0x0114 // VUI Display Info Address 460 //MS_U32 u32AVC_SPS_Addr; // FW sps structure start address 461 462 // -------- AVS info -------- 463 // ..... 464 //MS_U32 u32AVS_xxx; 465 466 // -------- RM info -------- 467 // HK -> FW 468 MS_U8 u8RM_Version; //0x0118 469 MS_U8 u8RM_NumSizes; //0x0119 470 //**************************************** 471 MS_U16 reserved16_2; //0x011A 472 //**************************************** 473 HVD_PictureSize pRM_PictureSize[HVD_RM_INIT_PICTURE_SIZE_NUMBER]; //0x011C 474 MS_U32 u32RM_VLCTableAddr; //0x013C 475 476 // -------- common info -------- 477 MS_U32 u32MainLoopCnt; //0x0140 478 MS_U32 u32VsyncCnt; //0x0144 479 HVD_DISP_THRESHOLD DispThreshold; //0x0148 480 MS_U32 u32ESReadPtr; //0x0158 // the read pointer of bitstream buffer. 481 MS_U32 reserved32_0; //0x015C 482 MS_S64 s64PtsStcDiff; //0x0160 // 90Khz 483 MS_U16 u16ChipID; //0x0168 // enum MSTAR_CHIP_ID 484 MS_U16 u16ChipECONum; //0x016A // ECO num of chip 485 MS_U32 u32NextPTS; //0x016C // ms 486 487 MS_U16 u16DispQSize; //0x0170 488 MS_U16 u16DispQPtr; //0x0172 489 HVD_Frm_Information DispQueue[HVD_DISP_QUEUE_MAX_SIZE]; //0x0174 490 MS_U32 u32RealFrameRate; //0x574 491 492 MS_U32 u32Frm_packing_arr_data_addr; //0x578 493 494 /* M12 DTV FBL Threshold */ 495 MS_U32 u32FBMemUsage; //0x57C 496 497 //---------- report 3k/6k for 16/32 Mem-Align DS -------------------------- 498 MS_U32 u32DSBuffSize; //0x580 // Dynamic Scale Buffer Size actually used for different DS Mem Align 499 MS_U8 bDSIsRunning; //0x584 500 MS_U8 reserved8_3[3]; //0x585 501 //-------------------------- PreSetControl ---------------------- 502 MS_U32 u32PreSetControl; //0x588 503 MS_U32 u32PreSetFrameRate; //0x58A // Arg for PRESET_FRAMERATE_HANDLING 504 505 506 // -------- vp6 -------- // these are for experiment 507 //MS_U32 u32BBURptr; // the read pointer of BBU table, updated by fw 508 //MS_U32 u32ESBufAddr; // the ES buffer start address 509 //MS_U32 u32BBUWptr; // the write pointer of BBU table, updated by drv(16 align) 510 //MS_U32 reserved32_3; // don't remove it(for 16 align) 511 //MS_U32 reserved32_4; // don't remove it(for 16 align) 512 } HVD_ShareMem; 513 514 typedef struct 515 { 516 MS_U32 u32ByteCnt; 517 MS_U32 u32PTS; 518 MS_U32 u32ID_L; 519 MS_U32 u32ID_H; 520 } HVD_PTS_Entry; 521 522 // enum 523 typedef enum 524 { 525 E_MSTAR_CHIP_NONE = 0, 526 E_MSTAR_CHIP_U3, 527 E_MSTAR_CHIP_T3, 528 E_MSTAR_CHIP_T4, 529 E_MSTAR_CHIP_JANUS, 530 E_MSTAR_CHIP_U4, 531 E_MSTAR_CHIP_T8, 532 E_MSTAR_CHIP_T9, 533 E_MSTAR_CHIP_M10, 534 E_MSTAR_CHIP_T12, 535 E_MSTAR_CHIP_T13, 536 E_MSTAR_CHIP_J2, 537 E_MSTAR_CHIP_K1, 538 E_MSTAR_CHIP_A1, 539 E_MSTAR_CHIP_A5, 540 E_MSTAR_CHIP_A7, 541 E_MSTAR_CHIP_K2, 542 E_MSTAR_CHIP_A3, 543 E_MSTAR_CHIP_A7P, 544 E_MSTAR_CHIP_AGATE, 545 E_MSTAR_CHIP_M12, 546 E_MSTAR_CHIP_EAGLE, 547 E_MSTAR_CHIP_EMERALD, 548 E_MSTAR_CHIP_EDISON, 549 E_MSTAR_CHIP_EIFFEL, 550 E_MSTAR_CHIP_EDEN, 551 E_MSTAR_CHIP_EULER, 552 E_MSTAR_CHIP_KAPPA, 553 E_MSTAR_CHIP_NIKE, 554 E_MSTAR_CHIP_KELTIC, 555 E_MSTAR_CHIP_OTHER = 0xFF, 556 } MSTAR_CHIP_ID; 557 558 typedef enum 559 { 560 E_HVD_SRC_MODE_DTV = 0, 561 E_HVD_SRC_MODE_TS_FILE, 562 E_HVD_SRC_MODE_FILE, 563 } HVD_SRC_MODE; 564 565 typedef enum 566 { 567 E_HVD_Codec_AVC, 568 E_HVD_Codec_AVS, 569 E_HVD_Codec_RM, 570 E_HVD_Codec_MJPEG, 571 E_HVD_Codec_VP8, 572 E_HVD_Codec_VP6, 573 } HVD_Codec_Type; 574 575 typedef enum 576 { 577 E_HVD_PICT_TYPE_I, 578 E_HVD_PICT_TYPE_P, 579 E_HVD_PICT_TYPE_B, 580 } HVD_Picture_Type; 581 582 typedef enum 583 { 584 E_HVD_FIELD_TYPE_NONE = 0, 585 E_HVD_FIELD_TYPE_TOP, 586 E_HVD_FIELD_TYPE_BOTTOM, 587 E_HVD_FIELD_TYPE_BOTH, 588 } HVD_Field_Type; 589 590 typedef enum 591 { 592 E_HVD_DECODE_ALL, 593 E_HVD_DECODE_I, 594 E_HVD_DECODE_IP, 595 } HVD_Skip_Decode_Type; 596 597 typedef enum 598 { 599 E_HVD_DROP_DISP_AUTO = (1<<0), 600 E_HVD_DROP_DISP_ONCE = (1<<1), 601 } HVD_Drop_Disp_Type; 602 603 typedef enum 604 { 605 E_HVD_FRC_NORMAL = 0, 606 E_HVD_FRC_32PULLDOWN, //3:2 pulldown mode (ex. 24p a 60i or 60p) 607 E_HVD_FRC_PAL2NTSC , //PALaNTSC conversion (50i a 60i) 608 E_HVD_FRC_NTSC2PAL, //NTSCaPAL conversion (60i a 50i) 609 E_HVD_FRC_DISP_2X, //output rate is twice of input rate (ex. 30p a 60p) 610 E_HVD_FRC_24_50, //output rate 24P->50P 48I->50I 611 E_HVD_FRC_50P_60P, //output rate 50P ->60P 612 E_HVD_FRC_60P_50P, //output rate 60P ->50P 613 E_HVD_FRC_HALF_I, //output rate 120i -> 60i, 100i -> 50i 614 E_HVD_FRC_120I_50I, //output rate 120i -> 60i 615 E_HVD_FRC_100I_60I, //output rate 100i -> 60i 616 } HVD_FRC_Mode; 617 618 typedef enum 619 { 620 E_HVD_FRC_DROP_FRAME = 0, 621 E_HVD_FRC_DROP_FIELD = 1, 622 } HVD_FRC_Drop_Mode; 623 624 typedef enum 625 { 626 E_HVD_DISP_SPEED_F_32X = 32, 627 E_HVD_DISP_SPEED_F_16X = 16, 628 E_HVD_DISP_SPEED_F_8X = 8, 629 E_HVD_DISP_SPEED_F_4X = 4, 630 E_HVD_DISP_SPEED_F_2X = 2, 631 E_HVD_DISP_SPEED_1X = 1, 632 E_HVD_DISP_SPEED_S_2X = -2, 633 E_HVD_DISP_SPEED_S_4X = -4, 634 E_HVD_DISP_SPEED_S_8X = -8, 635 E_HVD_DISP_SPEED_S_16X = -16, 636 E_HVD_DISP_SPEED_S_32X = -32, 637 } HVD_Disp_Speed; 638 639 typedef enum 640 { 641 E_HVD_SYNC_TBL_TYPE_NON, 642 E_HVD_SYNC_TBL_TYPE_PTS, 643 E_HVD_SYNC_TBL_TYPE_DTS, 644 E_HVD_SYNC_TBL_TYPE_STS, //Sorted TimeStamp 645 } HVD_Sync_Tbl_Type; //only for file mode. Ts , ts file mode always has PTS table 646 647 typedef enum 648 { 649 E_HVD_FIELD_CTRL_OFF=0, 650 E_HVD_FIELD_CTRL_TOP, // Always Show Top Field 651 E_HVD_FIELD_CTRL_BOTTOM, // Always Show Bottom Field 652 } HVD_Field_Ctrl; 653 654 typedef enum 655 { 656 E_HVD_BURST_CNT_LV0 = 0, // U3,T3:32 cycle T4~U4: 16 cycle 657 E_HVD_BURST_CNT_LV1 = 1, // U3,T3:64 cycle T4~U4: 32 cycle 658 E_HVD_BURST_CNT_LV2 = 2, // U3,T3:96 cycle T4~U4: 48 cycle 659 E_HVD_BURST_CNT_LV3 = 3, // U3,T3:128 cycle T4~U4: 64 cycle 660 E_HVD_BURST_CNT_LV4 = 4, // U3,T3:160 cycle T4~U4: 80 cycle 661 E_HVD_BURST_CNT_LV5 = 5, // U3,T3:192 cycle T4~U4: 96 cycle 662 E_HVD_BURST_CNT_LV6 = 6, // U3,T3:224 cycle T4~U4: 112 cycle 663 E_HVD_BURST_CNT_LV7 = 7, // U3,T3:256 cycle T4~U4: 128 cycle 664 E_HVD_BURST_CNT_DISABLE = 0xFFFFFFFF, 665 } HVD_MIU_Burst_Cnt_Ctrl; 666 667 typedef enum 668 { 669 E_HVD_DISPQ_STATUS_NONE = 0, //FW 670 E_HVD_DISPQ_STATUS_INIT, //FW 671 E_HVD_DISPQ_STATUS_VIEW, //HK 672 E_HVD_DISPQ_STATUS_DISP, //HK 673 E_HVD_DISPQ_STATUS_FREE, //HK 674 } HVD_DISPQ_STATUS; 675 676 typedef enum 677 { 678 // invalid cmd 679 E_HVD_CMD_INVALID_CMD = 0xFFFFFFFFUL, 680 681 // SVD old cmd 682 E_HVD_CMD_SVD_BASE = 0x00010000, 683 /*0x10001*/E_HVD_CMD_PARSER_BYPASS, // 1 : on :for raw file mode; AVCHVD_CMD_PARSER_BYPASS ; 0: off: TS file mode and live stream 684 /*0x10002*/E_HVD_CMD_BBU_RESIZE, // svd only; AVCHVD_CMD_BBU_SIZE 685 /*0x10003*/E_HVD_CMD_FRAME_BUF_RESIZE, // svd only; AVCHVD_CMD_RESIZE_MEM 686 /*0x10004*/E_HVD_CMD_IGNORE_ERR_REF, // 1: ignore ref error, 0: enable ref error handle; AVCHVD_CMD_IGNORE_LIST + AVCHVD_CMD_OPEN_GOP 687 /*0x10005*/E_HVD_CMD_ES_FULL_STOP, // ES auto stop: 1: AVCHVD_CMD_ES_STOP; ES not stop 0: AVCHVD_CMD_HANDSHAKE 688 /*0x10006*/E_HVD_CMD_DROP_DISP_AUTO, // 1:on AVCHVD_CMD_DISP_DROP, 0:off AVCHVD_CMD_DIS_DISP_DROP 689 /*0x10007*/E_HVD_CMD_DROP_DISP_ONCE, // AVCHVD_CMD_DROP_CNT 690 /*0x10008*/E_HVD_CMD_FLUSH_DEC_Q, // AVCHVD_CMD_FLUSH_QUEUE 691 692 // HVD new cmd 693 E_HVD_CMD_NEW_BASE = 0x00020000, 694 // Action 695 E_HVD_CMD_TYPE_ACTION_MASK = (0x0100|E_HVD_CMD_NEW_BASE), 696 697 // state machine action 698 /*0x20101*/E_HVD_CMD_INIT , // Init FW type: E_HVD_Codec_AVC ; E_HVD_Codec_AVS; E_HVD_Codec_RM 699 /*0x20102*/E_HVD_CMD_PLAY, // AVCHVD_CMD_GO 700 /*0x20103*/E_HVD_CMD_PAUSE, // AVCHVD_CMD_PAUSE 701 /*0x20104*/E_HVD_CMD_STOP, // AVCHVD_CMD_STOP 702 // run-time action 703 /*0x20105*/E_HVD_CMD_STEP_DECODE, // AVCHVD_CMD_STEP 704 /*0x20106*/E_HVD_CMD_FLUSH, // Arg: 1 show last decode, 0 show current diaplay.FW need to clear read pointer of PTS table under SYNC_PTS, SYNC_DTS. ; BBU: AVCHVD_CMD_DROP , DISP: AVCHVD_CMD_FLUSH_DISPLAY , AVCHVD_CMD_SKIPTOI 705 /*0x20107*/E_HVD_CMD_BLUE_SCREEN, // only for AVC. remove auto blue screen before show first frame on screen 706 /*0x20108*/E_HVD_CMD_RESET_PTS, // reset PTS table for TS file mode. AVCHVD_CMD_RE_SYNC 707 /*0x20109*/E_HVD_CMD_FREEZE_IMG, // FW showes the same frame at every Vsync, but background decode process can not stop. 1: freeze image; 0: normal diaplay 708 /*0x2010A*/E_HVD_CMD_JUMP_TO_PTS, // Arg: PTS(unit: 90kHz). 0: disable this mode. Any not zero value: enable. FW decode to specified PTS by using full speed. During the decoding, FW need not show any decoded frames, just maitain the last frame before get this command. 709 /*0x2010B*/E_HVD_CMD_SYNC_TOLERANCE, // Arg: any not zero number(unit: 90kHz). AVCHVD_CMD_SLOW_SYNC 710 /*0x2010C*/E_HVD_CMD_SYNC_VIDEO_DELAY, // Arg: 0~MAX_VIDEO_DELAY(unit: 90kHz): use Arg of video delay. AVCHVD_CMD_AVSYNC 711 /*0x2010D*/E_HVD_CMD_DISP_ONE_FIELD, // for AVS, AVC only, Arg: HVD_Field_Ctrl. AVCH264_CMD_ONE_FIELD 712 /*0x2010E*/E_HVD_CMD_FAST_DISP, // Arg: 0: disable, Any not zero value: enable. Always return first frame ready. Don't care the first frame av-sync. 713 /*0x2010F*/E_HVD_CMD_SKIP_TO_PTS, // Arg: PTS(unit: 90kHz). 0: disable this mode. Any not zero value: enable. FW decode to specified PTS by using full speed. FW need not to decode frame until the first I after the specified PTS. 714 /*0x20110*/E_HVD_CMD_SYNC_THRESHOLD, // Arg: 0x01~0xFF , frame repeat time. If arg == 0xFF, fw will always repeat last frame when PTS > STC. 715 /*0x20111*/E_HVD_CMD_FREERUN_THRESHOLD, // Arg: (unit: 90KHz) 0: use default 5 sec (90000 x 5). 716 /*0x20112*/E_HVD_CMD_FLUSH_FRM_BUF, // Arg: 1 show last decode frame, 0 show current diaplay frame. FW will clear all frame buffer then skip to next I frame. 717 /*0x20113*/E_HVD_CMD_FORCE_INTERLACE, // Arg: 1 enable, 0 disable, only support DTV and TS file mode with framerate 25 or 30 718 719 // internal control action 720 721 // FW settings ( only for driver init) 722 E_HVD_CMD_SETTINGS_MASK = (0x0200|E_HVD_CMD_NEW_BASE), 723 /*0x20201*/E_HVD_CMD_PITCH, // Arg:any non-zero number. AVCHVD_CMD_PITCH_1952, AVCHVD_CMD_PITCH_1984 724 /*0x20202*/E_HVD_CMD_SYNC_EACH_FRM, // 1: TS file mode: on ; 0: live mode: off AVCHVD_CMD_SYNC 725 /*0x20203*/E_HVD_CMD_MAX_DEC_TICK, // 0: off ; not 0 : in fw.h new value AVCHVD_CMD_MAXT 726 /*0x20204*/E_HVD_CMD_AUTO_FREE_ES, // 1: on ; 0: off ; for live stream only AVCHVD_CMD_AUTO_FREE 727 /*0x20205*/E_HVD_CMD_DIS_VDEAD, // 1: on :For PVR , file mode only ; 0 : off: AVCHVD_CMD_DIS_VDEAD 728 /*0x20206*/E_HVD_CMD_MIN_FRAME_GAP, // Arg: 0~n, 0xFFFFFFFF: don't care frame gap; For file mode only; AVCHVD_CMD_MIN_FRAME_GAP 729 /*0x20207*/E_HVD_CMD_SYNC_TYPE, // Arg: HVD_Sync_Tbl_Type. //only for file mode. Ts , ts file mode always has PTS table 730 /*0x20208*/E_HVD_CMD_TIME_UNIT_TYPE, // Set Time unit: 0: 90Khz, 1: 1ms 731 /*0x20209*/E_HVD_CMD_ISR_TYPE, // Add ISR trigger timing. 732 /*0x2020A*/E_HVD_CMD_DYNAMIC_SCALE, // 0: disable; 1: enable 733 /*0x2020B*/E_HVD_CMD_SCALER_INFO_NOTIFY, 734 /*0x2020C*/E_HVD_CMD_MIU_BURST_CNT, // Arg 0~7 burst cnt level , 0xFFFFFFFF = Disable 735 /*0x2020D*/E_HVD_CMD_FDMASK_DELAY_CNT, // Arg: 0~0xFF, Fdmask delay count, arg >= 0xFF -> use default. 736 /*0x2020E*/E_HVD_CMD_FRC_OUTPUT_FRAMERATE, // unit: vsync cnt 737 /*0x2020F*/E_HVD_CMD_FRC_OUTPUT_INTERLACE, // 0: progressive; 1: interlace 738 /*0x20210*/E_HVD_CMD_ENABLE_DISP_QUEUE, // 0: Disable; 1:Enable 739 /*0x20211*/E_HVD_CMD_FORCE_DTV_SPEC, // 0: Disable; 1: Enable, Force to follow H264 DTV Spec, if res>720p && framerate>50, force progessive 740 // 2: Disable, if frame_mbs_only_flag == TRUE, it's progressive. 741 /*0x20212*/E_HVD_CMD_SET_USERDATA_MODE, // 0: Normal DVB user_data mode; 1: ATSC DirectTV CC mode 742 /*0x20213*/E_HVD_CMD_PUSH_DISPQ_WITH_REF_NUM, // 0: Disable; 1:Enable 743 /*0x20214*/E_HVD_CMD_GET_MORE_FRM_BUF, // Arg: 0: Disable; 1:Enable. If buffer size is enough, intial more frame buffer to use. 744 /*0x20215*/E_HVD_CMD_SHOW_FIRST_FRAME_DIRECT, // Arg: 0: Disable; 1:Enable. Push first I frame to display queue directly.. 745 /*0x20216*/E_HVD_CMD_ONE_PENDING_BUFFER_MODE, // Arg: 0: Disable; 1:Enable. Use only one pending buffer instead of two. 746 /*0x20217*/E_HVD_CMD_FRAMERATE_HANDLING, // Arg 0~60000, 0: Disable, 1000 ~ 60000: Used the arg to set frame rate when the sequence did not have frame rate info. and arg is not zero. (The frame unit is (arg/1000)fps, Exp: 30000 = 30.000 fps), others: Do not thing. 747 // Arg 0xFFFFFFFF, use default frame rate when no frame rate info in header 748 /*0x20218*/E_HVD_CMD_AUTO_EXHAUST_ES_MODE, // Arg, 0: disable, [31:16]= Upper bound, [15:0] = Lower bound, Unit is 1KBytes, // Auto drop display to consume ES data as soon as possible when ES level is higher than upper bound 749 /*0x20219*/E_HVD_CMD_SET_MIN_TSP_DATA_SIZE, // Arg: Resize HVD_FW_AVC_ES_MIN_TSP_DATA_SIZE 750 /*0x2021A*/E_HVD_CMD_AVC_SUPPORT_REF_NUM_OVER_MAX_DPB_SIZE, // Arg, 0: Disable; 1:enable. AVC support referece number is more than maximum DPB size when buffer buffer size was enought. 751 752 753 // Mode ( for AP run-time) 754 E_HVD_CMD_MODE_MASK = (0x0300|E_HVD_CMD_NEW_BASE), 755 /*0x20301*/E_HVD_CMD_SKIP_DEC, // E_HVD_DECODE_ALL ;E_HVD_DECODE_I;E_HVD_DECODE_IP; AVCHVD_CMD_DEC_I , AVCHVD_CMD_SKIP_NONREF 756 /*0x20302*/E_HVD_CMD_DISP_SPEED, // HVD_Disp_Speed ; AVCHVD_CMD_TRICKY 0,1: normal speed N(>0): show N times, slow motion Nx(-2,-4...) ; N(<0): FF speed Nx(2,4,...) AVCHVD_CMD_2X_SPEED 757 /*0x20303*/E_HVD_CMD_DISP_ERR_FRM, // True: display and error frame; FALSE: not show error frame ; AVCHVD_CMD_ERR_TH 758 /*0x20304*/E_HVD_CMD_ERR_CONCEAL, // 1: on ; 0: off ; AVCHVD_CMD_PASTE 759 /*0x20305*/E_HVD_CMD_REPEAT_LAST_FIELD, // 1: ON ; 0: OFF 760 /*0x20306*/E_HVD_CMD_FRC_MODE, // Arg:HVD_FRC_Mode. AVCHVD_CMD_FRAME_CVT 761 /*0x20307*/E_HVD_CMD_SYNC_ACTIVE, // Arg: 0: sync off. AVCHVD_CMD_FREE_RUN ; 1: sync on. AVCHVD_CMD_AVSYNC 762 /*0x20308*/E_HVD_CMD_PLAYBACK_FINISH, // 1: no more input data, FW need to show frame by itself until all buffers being empty. 0: close this mode. 763 /*0x20309*/E_HVD_CMD_BALANCE_BW, // Arg: Byte0: Quarter Pixel Off Level, Byte1: Deblock Off Level >> 0: off, 1~255: count threshold to enter, Byte2: Upper Bound value. i.e.: Byte0: 1,Byte1: 10,Byte2: 20. 764 /*0x2030A*/E_HVD_CMD_POWER_SAVING, // Arg: 0: Power Saving Off, 1: Power Saving On 765 /*0x2030B*/E_HVD_CMD_DIS_DBF, // Disable deblock, Arg: 0: off, 1: disable all frame, 2: only disable non-ref frame 766 /*0x2030C*/E_HVD_CMD_DIS_QUART_PIXEL, // Disable quarter pixel, Arg: 0: off, 1: disable for all frame, 2: only dsiable non-ref frame 767 /*0x2030D*/E_HVD_CMD_DPO_CC, // Display Order User Data Command, Arg: 0: off, 1: on. 768 /*0x2030E*/E_HVD_CMD_DISP_I_DIRECT, // Display I directly, Arg: 0: off, 1: on 769 /*0x2030F*/E_HVD_CMD_FORCE_RESET_HW, // Arg, 0:disable, 1:enable. Force reset hw when frame start 770 /*0x20310*/E_HVD_CMD_UPDATE_DISP_THRESHOLD, // Arg, none 771 /*0x20311*/E_HVD_CMD_FRC_DROP_MODE, // Arg, E_HVD_FRC_DROP_FRAME (0), E_HVD_FRC_DROP_FIELD (1) 772 /*0x20312*/E_HVD_CMD_UPDATE_DISPQ, // Arg, none. Update Frame Status in Display Queue 773 /*0x20313*/E_HVD_CMD_SHOW_DECODE_ORDER, // Arg, 0:disable, 1:enable. Show decoder order or display order 774 /*0x20314*/E_HVD_CMD_DISP_IGNORE_CROP, // Arg, 0:disable, 1:enable. Ignore crop information when set V-sync to display 775 /*0x20315*/E_HVD_CMD_AVOID_PTS_TBL_OVERFLOW, // Arg, 0:disable, 1:enable. for hw tsp mode, mvd parser will stop when pts table is close to overflow and restart when enough pts is consumed. 776 /*0x20316*/E_HVD_CMD_CTRL_SPEED_IN_DISP_ONLY, // Arg, 0:disable, control in decoding and displaying time; 1:enable, control speed in displaying time only. 777 /*0x20317*/E_HVD_CMD_ERR_CONCEAL_SLICE_1ST_MB, // Arg, 0:disable, Error concealment from current/last MB position; 1:enale, Error concealment from current slice first MB.(Need enable E_HVD_CMD_ERR_CONCEAL) 778 779 // test cmd 780 E_HVD_CMD_TEST_MASK = (0x0400|E_HVD_CMD_NEW_BASE), 781 /*0x20401*/E_HVD_CMD_INIT_STREAM, // Initialize this stream 782 /*0x20402*/E_HVD_CMD_RELEASE_STREAM, // Release this stream 783 784 // HVD new cmd Max 785 E_HVD_CMD_NEW_MAX = (0xFFFF|E_HVD_CMD_NEW_BASE), 786 787 } HVD_User_Cmd; 788 789 typedef enum 790 { 791 E_HVD_FW_STATE_MASK = 0xF000, 792 793 // state: INIT 794 E_HVD_FW_INIT = 0x1000, 795 E_HVD_FW_INIT_START, 796 E_HVD_FW_INIT_DONE, 797 798 // state: PLAY 799 E_HVD_FW_PLAY = 0x2000, 800 E_HVD_FW_PLAY_TYPE_MASK = 0x0C00, 801 802 // AVC 803 E_HVD_FW_PLAY_AVC = (0x0000|E_HVD_FW_PLAY), 804 E_HVD_FW_AVC_READ_NAL, 805 E_HVD_FW_AVC_READ_NEW_SLICE, 806 E_HVD_FW_AVC_PREPARE_SLICE_HEADER, 807 E_HVD_FW_AVC_DECODE_ONE_SLICE, 808 E_HVD_FW_AVC_EXIT_PICTURE, 809 810 // AVS 811 E_HVD_FW_PLAY_AVS = (0x0400|E_HVD_FW_PLAY), 812 813 // RM 814 E_HVD_FW_PLAY_RM = (0x0800|E_HVD_FW_PLAY), 815 816 // state: PAUSE 817 E_HVD_FW_PAUSE = 0x3000, 818 819 // state: STOP 820 E_HVD_FW_STOP = 0x4000, 821 E_HVD_FW_STOP_START, 822 E_HVD_FW_STOP_DONE, 823 } HVD_FW_State; 824 825 826 typedef enum 827 { 828 // Error code base 829 E_HVD_ERR_BASE = 0x0000, 830 831 // General 832 E_HVD_ERR_GENERAL_BASE = (0x0000|E_HVD_ERR_BASE), 833 E_HVD_ERR_OUT_OF_SPEC, 834 E_HVD_ERR_UNKNOW_ERR, 835 E_HVD_ERR_HW_BREAK_DOWN, 836 // TIMEOUT 837 E_HVD_ERR_HW_DEC_TIMEOUT, 838 // NOT SUPPORT 839 E_HVD_ERR_OUT_OF_MEMORY, // required memory size is over frame buffer size. 840 E_HVD_ERR_UNKNOWN_CODEC, // unknown media codec 841 842 // AVC 843 E_HVD_ERR_AVC_BASE = (0x1000|E_HVD_ERR_BASE), 844 // decode error 845 E_HVD_ERR_AVC_SPS_BROKEN, // SPS is not valid 846 E_HVD_ERR_AVC_SPS_NOT_IN_SPEC, 847 E_HVD_ERR_AVC_SPS_NOT_ENOUGH_FRM, // DPB size at specified level is smaller than the specified number of reference frames. This is not allowed 848 E_HVD_ERR_AVC_PPS_BROKEN, // PPS is not valid 849 E_HVD_ERR_AVC_REF_LIST, 850 E_HVD_ERR_AVC_NO_REF, 851 E_HVD_ERR_AVC_RES, 852 853 // AVS 854 E_HVD_ERR_AVS_BASE = (0x2000|E_HVD_ERR_BASE), 855 E_HVD_ERR_AVS_RES, 856 857 // RM 858 E_HVD_ERR_RM_BASE = (0x3000|E_HVD_ERR_BASE), 859 E_HVD_ERR_RM_PACKET_HEADER, 860 E_HVD_ERR_RM_FRAME_HEADER, 861 E_HVD_ERR_RM_SLICE_HEADER, 862 E_HVD_ERR_RM_BYTE_CNT, 863 E_HVD_ERR_RM_DISP_TIMEOUT, 864 E_HVD_ERR_RM_NO_REF, 865 E_HVD_ERR_RM_VLC, 866 E_HVD_ERR_RM_SIZE, 867 E_HVD_ERR_RM_RES, 868 } HVD_Err_Code; 869 870 #endif // _FW_HVD_IF_H_ 871 872