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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 // 94 /// @file regMVD.h 95 /// @brief Hardware register definition for Video Decoder 96 /// @author MStar Semiconductor Inc. 97 // 98 /////////////////////////////////////////////////////////////////////////////////// 99 100 #ifndef _REG_MVD_H_ 101 #define _REG_MVD_H_ 102 103 104 //////////////////////////////////////////////////////////////////////////////// 105 // Constant & Macro Definition 106 //////////////////////////////////////////////////////////////////////////////// 107 //------------------------------------------------------------------------------ 108 // Base Address 109 //------------------------------------------------------------------------------ 110 #define MVD_REG_BASE 0x1100 // 0x1100 - 0x11FF 111 #define CHIP_REG_BASE 0x1E00 // 0x1E00 - 0x1EFF 112 #define VD_MHEG5_REG_BASE 0x0300 113 114 #define MIU0_REG_BASE 0x1200 115 #define MIU1_REG_BASE 0x0600 116 117 118 //------------------------------------------------------------------------------ 119 // MIU register 120 //------------------------------------------------------------------------------ 121 //MIU request mask 122 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2) 123 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1) 124 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2) 125 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1) 126 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2) 127 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1) 128 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2) 129 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1) 130 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0) 131 #define MIU0_SEL0_H (MIU0_REG_BASE + 0xF1) 132 #define MIU0_SEL2_L (MIU0_REG_BASE + 0xF4) 133 #define MIU0_SEL2_H (MIU0_REG_BASE + 0xF5) 134 #define MIU0_SEL3_L (MIU0_REG_BASE + 0xF6) 135 #define MIU0_SEL3_H (MIU0_REG_BASE + 0xF7) 136 137 #define MIU1_RQ0_MASK_L (MIU1_REG_BASE + 0x23*2) 138 #define MIU1_RQ0_MASK_H (MIU1_REG_BASE + 0x23*2 +1) 139 #define MIU1_RQ1_MASK_L (MIU1_REG_BASE + 0x33*2) 140 #define MIU1_RQ1_MASK_H (MIU1_REG_BASE + 0x33*2 +1) 141 #define MIU1_RQ2_MASK_L (MIU1_REG_BASE + 0x43*2) 142 #define MIU1_RQ2_MASK_H (MIU1_REG_BASE + 0x43*2 +1) 143 #define MIU1_RQ3_MASK_L (MIU1_REG_BASE + 0x53*2) 144 #define MIU1_RQ3_MASK_H (MIU1_REG_BASE + 0x53*2 +1) 145 146 147 //------------------------------------------------------------------------------ 148 // CPU register 149 //------------------------------------------------------------------------------ 150 // CPU (VD_MHEG5) 151 #define REG_H264_CPU_SDR_BASE_L (VD_MHEG5_REG_BASE + 0xE4) 152 #define REG_H264_CPU_SDR_BASE_H (VD_MHEG5_REG_BASE + 0xE2) 153 154 #define REG_VD_MHEG5_RESET (VD_MHEG5_REG_BASE + 0xB0) 155 #define REG_VD_MHEG_RESET_CPURST BIT1 156 157 #define REG_VD_MHEG5_ENABLE (VD_MHEG5_REG_BASE + 0xF0) 158 #define REG_VD_MHEG_ENABLE_COPRO BIT0 159 #define REG_VD_MHEG_ENABLE_SWRST BIT1 160 161 #define REG_MHG_QMEM_DMASK 0x03e8 //QMEM Mask 162 #define REG_MHG_QMEM_DADDR 0x03ec //QMEM Addr 163 #define REG_MHG_SPI_BASE 0x03fe //SPI base 164 #define REG_MHG_REG32_BASE 0x03f8 165 #define MHG_REG32_BASE_MVD 0x8008 166 #define REG_MHG_SDR_BASE 0x03f4 167 #define REG_MHG_INSN_BASE_0 0x03e4 168 #define REG_MHG_INSN_BASE_1 0x03e5 169 #define REG_MHG_INSN_BASE_2 0x03e3 170 #define REG_MHG_INSN_BASE_3 0x03e7 171 172 173 //------------------------------------------------------------------------------ 174 // MVD Reg 175 //------------------------------------------------------------------------------ 176 #define MVD_CTRL_RST BIT0//1: reset MVD; 0: release reset 177 #define MVD_CTRL_CLR_INT BIT2//Clear MVD interrupt. 178 #define MVD_CTRL_CLK_SYNCMODE BIT4//1: sync_mode; 0: async_mode 179 #define MVD_CTRL_CLK_ALLON BIT5//1: enable all clocks in mvd 180 #define MVD_CTRL_DISCONNECT_MIU BIT6//1: disconnect; 0: release reset 181 #define MVD_CTRL (MVD_REG_BASE + 0x00) 182 183 #define MVD_STATUS_READY BIT1 184 #define MVD_STATUS (MVD_REG_BASE + 0x01) 185 #define MVD_T8_MIU_128_0 BIT2 // enable MVD to 128 bit mode 186 #define MVD_T8_MIU_128_1 BIT3 // enable MVD to 128 bit mode 187 #define MVD_COMMAND (MVD_REG_BASE + 0x02) 188 #define MVD_ARG0 (MVD_REG_BASE + 0x04) 189 #define MVD_ARG1 (MVD_REG_BASE + 0x05) 190 #define MVD_ARG2 (MVD_REG_BASE + 0x06) 191 #define MVD_ARG3 (MVD_REG_BASE + 0x07) 192 #define MVD_ARG4 (MVD_REG_BASE + 0x08) 193 #define MVD_ARG5 (MVD_REG_BASE + 0x09) 194 195 #define MVD_SLQCTRL_WADR_RELOAD BIT0 //reload "slq_wadr" into write address 196 //w reload: program 1, then program 0, and reload complete 197 #define MVD_SLQCTRL_RADR_PROBE BIT1 //SLQ read address probe 198 #define MVD_SLQCTRL_WADR_PROBE BIT2 //SLQ write address probe 199 //r/w probe: program 1, then program 0, and read "slq_caddr" 200 #define MVD_SLQCTRL (MVD_REG_BASE + 0x16) 201 202 //SLQ write address value[24:0] 203 #define MVD_SLQ_WADR0 (MVD_REG_BASE + 0x18) 204 #define MVD_SLQ_WADR1 (MVD_REG_BASE + 0x19) 205 #define MVD_SLQ_WADR2 (MVD_REG_BASE + 0x1A) 206 #define MVD_SLQ_WADR3 (MVD_REG_BASE + 0x1B) 207 208 //SLQ probe address value[24:0] 209 #define MVD_SLQ_CADR0 (MVD_REG_BASE + 0x1C) 210 #define MVD_SLQ_CADR1 (MVD_REG_BASE + 0x1D) 211 #define MVD_SLQ_CADR2 (MVD_REG_BASE + 0x1E) 212 #define MVD_SLQ_CADR3 (MVD_REG_BASE + 0x1F) 213 214 #define REG_CHIPTOP_BASE 0x0b00 215 216 #define REG_CKG_MVD_SYNC (REG_CHIPTOP_BASE + 0x38*2 +1) 217 #define CKG_MVD_SYNC_GATED BIT0 218 219 #define REG_CKG_MVD (REG_CHIPTOP_BASE + 0x39*2) 220 #define CKG_MVD_GATED BIT0 221 #define CKG_MVD_INVERT BIT1 222 #define CKG_MVD_MASK (BIT4 | BIT3 | BIT2) 223 #define CKG_MVD_216MHZ (0 << 2) 224 #define CKG_MVD_192MHZ (1 << 2) 225 #define CKG_MVD_172MHZ (2 << 2) 226 #define CKG_MVD_144MHZ (3 << 2) 227 #define CKG_MVD_CLK_MIU (4 << 2) //clk_miu_p 228 #define CKG_MVD_123MHZ (5 << 2) 229 #define CKG_MVD_MPLL_DIV2 (6 << 2) //mempll_clk_buf_div2 230 #define CKG_MVD_XTAL_CLK (7 << 2) //XTAL clock 231 232 #define REG_CKG_MVD2 (REG_CHIPTOP_BASE + 0x39*2 +1) 233 #define CKG_MVD2_GATED BIT0 234 #define CKG_MVD2_INVERT BIT1 235 #define CKG_MVD2_MASK (BIT4 | BIT3 | BIT2) 236 #define CKG_MVD2_216MHZ (0 << 2) 237 #define CKG_MVD2_192MHZ (1 << 2) 238 #define CKG_MVD2_172MHZ (2 << 2) 239 #define CKG_MVD2_144MHZ (3 << 2) 240 #define CKG_MVD2_CLK_MIU (4 << 2) //clk_miu_p 241 #define CKG_MVD2_123MHZ (5 << 2) 242 #define CKG_MVD2_MPLL_DIV2 (6 << 2) //mempll_clk_buf_div2 243 #define CKG_MVD2_XTAL_CLK (7 << 2) //XTAL clock 244 245 #define REG_CKG_MVD_CHROMA_A (REG_CHIPTOP_BASE + 0x3d*2) 246 #define CKG_MVD_CHROMA_A_GATED BIT0 247 #define CKG_MVD_CHROMA_A_INVERT BIT1 248 249 #define REG_CKG_MVD_CHROMA_B (REG_CHIPTOP_BASE + 0x3d*2) 250 #define CKG_MVD_CHROMA_B_GATED BIT4 251 #define CKG_MVD_CHROMA_B_INVERT BIT5 252 253 #define REG_CKG_MVD_CHROMA_C (REG_CHIPTOP_BASE + 0x3d*2 + 1) 254 #define CKG_MVD_CHROMA_C_GATED BIT0 255 #define CKG_MVD_CHROMA_C_INVERT BIT1 256 257 #define REG_CKG_MVD_LUMA_A (REG_CHIPTOP_BASE + 0x3a*2 + 1) 258 #define CKG_MVD_LUMA_A_GATED BIT0 259 #define CKG_MVD_LUMA_A_INVERT BIT1 260 261 #define REG_CKG_MVD_LUMA_B (REG_CHIPTOP_BASE + 0x3b*2) 262 #define CKG_MVD_LUMA_B_GATED BIT0 263 #define CKG_MVD_LUMA_B_INVERT BIT1 264 265 #define REG_CKG_MVD_LUMA_C (REG_CHIPTOP_BASE + 0x3b*2 + 1) 266 #define CKG_MVD_LUMA_C_GATED BIT0 267 #define CKG_MVD_LUMA_C_INVERT BIT1 268 269 270 #define REG_CKG_MVD_RMEM (REG_CHIPTOP_BASE + 0x3c*2) 271 #define CKG_MVD_RMEM_GATED BIT0 272 #define CKG_MVD_RMEM_INVERT BIT1 273 274 #define REG_CKG_MVD_RMEM1 (REG_CHIPTOP_BASE + 0x3c*2 + 1) 275 #define CKG_MVD_RMEM1_GATED BIT0 276 #define CKG_MVD_RMEM1_INVERT BIT1 277 278 #define REG_CKG_MVD_RREFDAT (REG_CHIPTOP_BASE + 0x3e*2) 279 #define CKG_MVD_RREFDAT_GATED BIT0 280 #define CKG_MVD_RREFDAT_INVERT BIT1 281 282 #define REG_CKG_VD_AEON (REG_CHIPTOP_BASE + 0x30*2) 283 #define CKG_VD_AEON_GATED BIT0 284 #define CKG_VD_AEON_INVERT BIT1 285 #define CKG_VD_AEON_MASK (BIT3 | BIT2) 286 #define CKG_VD_AEON_160MHZ (0 << 2) 287 //Notice: The clock 160M comes from UTMI. 288 //Please start UTMI's clock before you switch to 160M 289 #define CKG_VD_AEON_144MHZ (1 << 2) 290 #define CKG_VD_AEON_123MHZ (2 << 2) 291 #define CKG_VD_AEON_108MHZ (3 << 2) 292 293 294 #define REG_CHIP_ID_MAJOR (CHIP_REG_BASE + 0xCC) 295 #define REG_CHIP_ID_MINOR (CHIP_REG_BASE + 0xCD) 296 #define REG_CHIP_VERSION (CHIP_REG_BASE + 0xCE) 297 #define REG_CHIP_REVISION (CHIP_REG_BASE + 0xCF) 298 299 #endif // _REG_MVD_H_ 300 301