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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _HAL_VPU_EX_H_ 96 #define _HAL_VPU_EX_H_ 97 98 //------------------------------------------------------------------------------------------------- 99 // Macro and Define 100 //------------------------------------------------------------------------------------------------- 101 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE) 102 103 #if defined(REDLION_LINUX_KERNEL_ENVI) 104 #define ENABLE_VPU_MUTEX_PROTECTION 0 105 #define VPU_DEFAULT_MUTEX_TIMEOUT 0xFFFFFFFFUL 106 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 107 #else 108 #define ENABLE_VPU_MUTEX_PROTECTION 1 109 #define VPU_DEFAULT_MUTEX_TIMEOUT MSOS_WAIT_FOREVER 110 111 #if defined(FW_EXTERNAL_BIN) 112 #define VPU_ENABLE_EMBEDDED_FW_BINARY 0 113 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 1 114 #else 115 #define VPU_ENABLE_EMBEDDED_FW_BINARY 1 116 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 117 #endif 118 119 #endif 120 121 //============================================================================= 122 #define ONE_SETTING_FOR_DUAL_VPU 123 124 #define MAX_VPU_NUM 2 125 #define ENABLE_TWO_VPU_STRUCTURE 1 //used to reduce variable size 126 127 #define VPU_DISPATCH_POLICY USE_MAIN_EVD_IN_LITE_NDEC_IN_HICODEC 128 129 #define USE_FIRST_VPU_ONLY 1 // both on first vpu 130 #define USE_SECOND_VPU_ONLY 2 // for evd test 131 #define USE_KANO_RULE 3 // second evd use evd_lite 132 #define USE_KANO_INV_RULE 4 // second evd use hi_codec 133 #define USE_MAIN_EVD_IN_LITE 5 // SN PIP patch for STC, main task evd use evd_lite 134 #ifdef VDEC3 135 #define USE_MAIN_EVD_IN_LITE_NDEC_IN_HICODEC 6 // main task evd use evd_lite, N-decode task use evd_hicodec 136 #endif 137 //============================================================================= 138 139 #define VPU_FORCE_MIU_MODE 1 140 #define HVD_ENABLE_IQMEM 0 141 #define VPU_IQMEM_BASE 0xe0000000 142 143 144 #define ENABLE_DECOMPRESS_FUNCTION TRUE 145 146 #define VPU_CLOCK_480MHZ BITS(6:2,3) 147 #define VPU_CLOCK_432MHZ BITS(6:2,6) 148 #define VPU_CLOCK_384MHZ BITS(6:2,7) 149 #define VPU_ICG_EN BIT(8) 150 #define VPU_LITE_ICG_EN BIT(9) 151 152 #define VPU_HI_MBOX0 0 153 #define VPU_HI_MBOX1 1 154 #define VPU_RISC_MBOX0 2 155 #define VPU_RISC_MBOX1 3 156 157 158 #define VPU_EX_TimerDelayMS(x) \ 159 do \ 160 { \ 161 volatile MS_U32 ticks = 0; \ 162 while (ticks < (((MS_U32) (x)) << 13)) \ 163 { \ 164 ticks++; \ 165 } \ 166 } while(0) 167 168 #ifdef VDEC3 169 #define HAL_VPU_INVALID_BBU_ID 0xFFFFFFFF 170 #define VPU_MAX_DEC_NUM 16 171 #else 172 #define VPU_MAX_DEC_NUM 2 173 #endif 174 #define CHECK_NULL_PTR(vbbu_addr) (((void *)(vbbu_addr)) == NULL) 175 176 //------------------------------------------------------------------------------------------------- 177 // Type and Structure 178 //------------------------------------------------------------------------------------------------- 179 typedef enum 180 { 181 E_HAL_HVD_STREAM_NONE = 0x0, 182 183 //Support TSP/TS/File mode 184 E_HAL_HVD_MAIN_STREAM_BASE = 0x10, 185 E_HAL_HVD_MAIN_STREAM0 = E_HAL_HVD_MAIN_STREAM_BASE, 186 E_HAL_HVD_MAIN_STREAM_MAX, 187 188 //Only support file mode 189 E_HAL_HVD_SUB_STREAM_BASE = 0x20, 190 E_HAL_HVD_SUB_STREAM0 = E_HAL_HVD_SUB_STREAM_BASE, 191 E_HAL_HVD_SUB_STREAM1, 192 E_HAL_HVD_SUB_STREAM_MAX, 193 194 #ifdef VDEC3 195 E_HAL_HVD_N_STREAM_BASE = 0x40, 196 E_HAL_HVD_N_STREAM0 = E_HAL_HVD_N_STREAM_BASE, 197 E_HAL_HVD_N_STREAM_MAX = E_HAL_HVD_N_STREAM0 + VPU_MAX_DEC_NUM, 198 #endif 199 200 //Only support MVC stream 201 E_HAL_HVD_MVC_STREAM_BASE = 0xF0, 202 E_HAL_HVD_MVC_Main_View = E_HAL_HVD_MVC_STREAM_BASE, 203 E_HAL_HVD_MVC_Sub_View, 204 E_HAL_HVD_MVC_STREAM_MAX, 205 } HAL_HVD_StreamId; 206 207 typedef enum 208 { 209 E_VPU_EX_DECODER_NONE = 0, 210 E_VPU_EX_DECODER_GET, 211 E_VPU_EX_DECODER_GET_MVC, 212 E_VPU_EX_DECODER_MVD, 213 E_VPU_EX_DECODER_HVD, 214 E_VPU_EX_DECODER_MJPEG, 215 E_VPU_EX_DECODER_RVD, 216 E_VPU_EX_DECODER_MVC, 217 E_VPU_EX_DECODER_VP8, 218 #ifdef VDEC3 219 E_VPU_EX_DECODER_EVD, 220 #if SUPPORT_G2VP9 221 E_VPU_EX_DECODER_G2VP9, 222 #endif 223 #endif 224 } VPU_EX_DecoderType; 225 226 #ifdef CONFIG_MSTAR_CLKM 227 typedef enum 228 { 229 E_VPU_EX_CLKPORT_MVD = 0, 230 E_VPU_EX_CLKPORT_MVD_CORE, 231 E_VPU_EX_CLKPORT_MVD_PAS, 232 E_VPU_EX_CLKPORT_HVD, 233 E_VPU_EX_CLKPORT_HVD_IDB, 234 E_VPU_EX_CLKPORT_HVD_AEC, 235 E_VPU_EX_CLKPORT_HVD_AEC_LITE, 236 E_VPU_EX_CLKPORT_VP8, 237 E_VPU_EX_CLKPORT_EVD, 238 E_VPU_EX_CLKPORT_EVD_PPU, 239 E_VPU_EX_CLKPORT_EVD_LITE, 240 E_VPU_EX_CLKPORT_EVD_PPU_LITE, 241 E_VPU_EX_CLKPORT_VD_MHEG5, 242 E_VPU_EX_CLKPORT_VD_MHEG5_LITE, 243 } VPU_EX_ClkPortType; 244 #endif 245 246 typedef enum 247 { 248 E_VPU_EX_CLOCK_480MHZ = VPU_CLOCK_480MHZ, 249 E_VPU_EX_CLOCK_432MHZ = VPU_CLOCK_432MHZ, 250 E_VPU_EX_CLOCK_384MHZ = VPU_CLOCK_384MHZ, 251 } VPU_EX_ClockSpeed; 252 253 typedef enum 254 { 255 E_HAL_VPU_STREAM_NONE = 0x0, 256 257 //Support TSP/TS File/File mode 258 E_HAL_VPU_MAIN_STREAM_BASE = 0x10, 259 E_HAL_VPU_MAIN_STREAM0 = E_HAL_VPU_MAIN_STREAM_BASE, 260 E_HAL_VPU_MAIN_STREAM_MAX, 261 262 //Only support file mode 263 E_HAL_VPU_SUB_STREAM_BASE = 0x20, 264 E_HAL_VPU_SUB_STREAM0 = E_HAL_VPU_SUB_STREAM_BASE, 265 E_HAL_VPU_SUB_STREAM_MAX, 266 267 #ifdef VDEC3 268 E_HAL_VPU_N_STREAM_BASE = 0x40, 269 E_HAL_VPU_N_STREAM0 = E_HAL_VPU_N_STREAM_BASE, 270 E_HAL_VPU_N_STREAM_MAX = E_HAL_VPU_N_STREAM0 + VPU_MAX_DEC_NUM, 271 #endif 272 273 //Only support MVC stream 274 E_HAL_VPU_MVC_STREAM_BASE = 0xF0, 275 E_HAL_VPU_MVC_MAIN_VIEW = E_HAL_VPU_MVC_STREAM_BASE, 276 E_HAL_VPU_MVC_SUB_VIEW, 277 E_HAL_VPU_MVC_STREAM_MAX, 278 } HAL_VPU_StreamId; 279 280 typedef enum 281 { 282 //Support TSP/TS/File mode 283 E_HAL_VPU_MAIN_STREAM, 284 285 //Only support file mode 286 E_HAL_VPU_SUB_STREAM, 287 288 //Only support MVC mode 289 E_HAL_VPU_MVC_STREAM, 290 291 #ifdef VDEC3 292 E_HAL_VPU_N_STREAM, 293 #endif 294 } HAL_VPU_StreamType; 295 296 typedef enum 297 { 298 //Support TSP/TS/File mode 299 E_VPU_EX_INPUT_TSP, 300 //Only support file mode 301 E_VPU_EX_INPUT_FILE, 302 E_VPU_EX_INPUT_NONE, 303 } VPU_EX_SourceType; 304 305 typedef enum 306 { 307 E_VPU_EX_UART_LEVEL_NONE = 0, ///< Disable all uart message. 308 E_VPU_EX_UART_LEVEL_ERR, ///< Only output error message 309 E_VPU_EX_UART_LEVEL_INFO, ///< output general message, and above. 310 E_VPU_EX_UART_LEVEL_DBG, ///< output debug message, and above. 311 E_VPU_EX_UART_LEVEL_TRACE, ///< output function trace message, and above. 312 E_VPU_EX_UART_LEVEL_FW, ///< output FW message, and above. 313 } VPU_EX_UartLevel; 314 315 typedef enum 316 { 317 E_VPU_EX_FW_VER_CTRLR = 0, 318 E_VPU_EX_FW_VER_MVD_FW, 319 E_VPU_EX_FW_VER_HVD_FW, 320 E_VPU_EX_FW_VER_MVD_IF, 321 E_VPU_EX_FW_VER_HVD_IF, 322 } VPU_EX_FWVerType; 323 324 /// DecodeMode for f/w tasks 325 typedef enum 326 { 327 E_VPU_DEC_MODE_DUAL_INDIE, ///< Two independent tasks 328 E_VPU_DEC_MODE_DUAL_3D, ///< Two dependent tasks for 3D 329 E_VPU_DEC_MODE_SINGLE, ///< One task use the whole SRAM 330 E_VPU_DEC_MODE_MVC = E_VPU_DEC_MODE_SINGLE, 331 } VPU_EX_DecMode; 332 333 /// CmdMode for KOREA3D or PIP mode 334 typedef enum 335 { 336 //Group1:Set Korea3DTV mode 337 E_VPU_CMD_MODE_KR3D_BASE = 0x0000, 338 E_VPU_CMD_MODE_KR3D_INTERLACE = E_VPU_CMD_MODE_KR3D_BASE, 339 E_VPU_CMD_MODE_KR3D_FORCE_P, 340 E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH, 341 E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH, 342 343 //Group2:Set PIP mode 344 E_VPU_CMD_MODE_PIP_BASE = 0x1000, 345 E_VPU_CMD_MODE_PIP_SYNC_INDIE = E_VPU_CMD_MODE_PIP_BASE, 346 E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC, 347 E_VPU_CMD_MODE_PIP_SYNC_SWITCH 348 } VPU_EX_CmdMode; 349 350 #if defined(MSOS_TYPE_LINUX) 351 #if 1 352 #define CMA_DRV_DIRECT_INIT 353 #else 354 #define CMA_FW_INIT 355 #endif 356 #endif 357 358 #ifdef CMA_DRV_DIRECT_INIT 359 /// input source select enumerator 360 typedef enum 361 { 362 ///DTV mode 363 E_VPU_EX_SRC_MODE_DTV = 0, 364 ///TS file mode 365 E_VPU_EX_SRC_MODE_TS_FILE, 366 ///generic file mode 367 E_VPU_EX_SRC_MODE_FILE, 368 /// TS file and dual ES buffer mode 369 E_VPU_EX_SRC_MODE_TS_FILE_DUAL_ES, 370 ///generic file and dual ES buffer mode 371 E_VPU_EX_SRC_MODE_FILE_DUAL_ES, 372 } VPU_EX_SrcMode; 373 374 #endif 375 376 /// codec type enumerator 377 typedef enum 378 { 379 ///unsupported codec type 380 E_VPU_EX_CODEC_TYPE_NONE = 0, 381 ///MPEG 1/2 382 E_VPU_EX_CODEC_TYPE_MPEG2, 383 ///H263 (short video header) 384 E_VPU_EX_CODEC_TYPE_H263, 385 ///MPEG4 (default) 386 E_VPU_EX_CODEC_TYPE_MPEG4, 387 ///MPEG4 (Divx311) 388 E_VPU_EX_CODEC_TYPE_DIVX311, 389 ///MPEG4 (Divx412) 390 E_VPU_EX_CODEC_TYPE_DIVX412, 391 ///FLV 392 E_VPU_EX_CODEC_TYPE_FLV, 393 ///VC1 advanced profile (VC1) 394 E_VPU_EX_CODEC_TYPE_VC1_ADV, 395 ///VC1 main profile (RCV) 396 E_VPU_EX_CODEC_TYPE_VC1_MAIN, 397 ///Real Video version 8 398 E_VPU_EX_CODEC_TYPE_RV8, 399 ///Real Video version 9 and 10 400 E_VPU_EX_CODEC_TYPE_RV9, 401 ///H264 402 E_VPU_EX_CODEC_TYPE_H264, 403 ///AVS 404 E_VPU_EX_CODEC_TYPE_AVS, 405 ///MJPEG 406 E_VPU_EX_CODEC_TYPE_MJPEG, 407 ///MVC 408 E_VPU_EX_CODEC_TYPE_MVC, 409 ///VP8 410 E_VPU_EX_CODEC_TYPE_VP8, 411 ///HEVC 412 E_VPU_EX_CODEC_TYPE_HEVC, 413 ///VP9 414 E_VPU_EX_CODEC_TYPE_VP9, 415 E_VPU_EX_CODEC_TYPE_NUM 416 } VPU_EX_CodecType; 417 418 typedef struct 419 { 420 VPU_EX_ClockSpeed eClockSpeed; 421 MS_BOOL bClockInv; 422 MS_S32 s32VPUMutexID; 423 MS_U32 u32VPUMutexTimeout; 424 MS_U8 u8MiuSel; 425 } VPU_EX_InitParam; 426 427 typedef struct 428 { 429 MS_U32 u32Id; 430 HAL_VPU_StreamId eVpuId; 431 VPU_EX_SourceType eSrcType; 432 VPU_EX_DecoderType eDecType; 433 MS_U8 u8HalId; // hal MVD/HVD id 434 MS_U32 u32HeapSize; 435 } VPU_EX_TaskInfo; 436 437 typedef struct 438 { 439 MS_VIRT u32DstAddr; 440 MS_VIRT u32DstSize; 441 MS_VIRT u32BinSize; 442 MS_VIRT u32BinAddr; 443 MS_U8 u8SrcType; 444 } VPU_EX_FWCodeCfg; 445 446 typedef struct 447 { 448 MS_VIRT u32DstAddr; 449 MS_VIRT u32BinAddr; 450 MS_VIRT u32BinSize; 451 MS_VIRT u32FrameBufAddr; 452 MS_VIRT u32VLCTableOffset; 453 } VPU_EX_VLCTblCfg; 454 455 #ifdef VDEC3 456 typedef struct 457 { 458 MS_VIRT u32FrameBufAddr; 459 MS_VIRT u32FrameBufSize; 460 } VPU_EX_FBCfg; 461 #endif 462 463 /// VPU init parameters for dual decoder 464 typedef struct 465 { 466 VPU_EX_FWCodeCfg *pFWCodeCfg; 467 VPU_EX_TaskInfo *pTaskInfo; 468 VPU_EX_VLCTblCfg *pVLCCfg; 469 #ifdef VDEC3 470 VPU_EX_FBCfg *pFBCfg; 471 #endif 472 } VPU_EX_NDecInitPara; 473 474 typedef struct 475 { 476 MS_U8 u8DecMod; 477 MS_U8 u8CodecCnt; 478 MS_U8 u8CodecType[VPU_MAX_DEC_NUM]; 479 MS_U8 u8ArgSize; 480 MS_U32 u32Arg; 481 } VPU_EX_DecModCfg; 482 483 typedef enum 484 { 485 E_VDEC_EX_CODEC_PROFILE_NONE, 486 487 E_VDEC_EX_CODEC_PROFILE_MP2_MAIN, 488 489 E_VDEC_EX_CODEC_PROFILE_MP4_ASP, 490 491 E_VDEC_EX_CODEC_PROFILE_H263_BASELINE, 492 493 E_VDEC_EX_CODEC_PROFILE_VC1_AP, 494 495 E_VDEC_EX_CODEC_PROFILE_RCV_MAIN, 496 497 E_VDEC_EX_CODEC_PROFILE_VP9_0, 498 E_VDEC_EX_CODEC_PROFILE_VP9_2, 499 500 E_VDEC_EX_CODEC_PROFILE_H264_CBP, 501 E_VDEC_EX_CODEC_PROFILE_H264_BP, 502 E_VDEC_EX_CODEC_PROFILE_H264_XP, 503 E_VDEC_EX_CODEC_PROFILE_H264_MP, 504 E_VDEC_EX_CODEC_PROFILE_H264_HIP, 505 E_VDEC_EX_CODEC_PROFILE_H264_PHIP, 506 E_VDEC_EX_CODEC_PROFILE_H264_CHIP, 507 E_VDEC_EX_CODEC_PROFILE_H264_HI10P, 508 E_VDEC_EX_CODEC_PROFILE_H264_HI422P, 509 E_VDEC_EX_CODEC_PROFILE_H264_HI444PP, 510 511 E_VDEC_EX_CODEC_PROFILE_H265_MAIN, 512 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_10, 513 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_12, 514 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_422_10, 515 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_422_12, 516 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444, 517 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444_10, 518 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444_12, 519 520 E_VDEC_EX_CODEC_PROFILE_AVS_BROADCASTING, 521 522 523 } VDEC_EX_CODEC_CAP_PROFILE_INFO; 524 525 typedef enum 526 { 527 E_VDEC_EX_CODEC_LEVEL_NONE, 528 529 E_VDEC_EX_CODEC_LEVEL_MP2_HIGH, 530 531 E_VDEC_EX_CODEC_LEVEL_MP4_L5, 532 533 E_VDEC_EX_CODEC_LEVEL_VC1_L3, 534 535 E_VDEC_EX_CODEC_LEVEL_RCV_HIGH, 536 537 538 E_VDEC_EX_CODEC_LEVEL_H264_1, 539 E_VDEC_EX_CODEC_LEVEL_H264_1B, 540 E_VDEC_EX_CODEC_LEVEL_H264_1_1, 541 E_VDEC_EX_CODEC_LEVEL_H264_1_2, 542 E_VDEC_EX_CODEC_LEVEL_H264_1_3, 543 E_VDEC_EX_CODEC_LEVEL_H264_2, 544 E_VDEC_EX_CODEC_LEVEL_H264_2_1, 545 E_VDEC_EX_CODEC_LEVEL_H264_2_2, 546 E_VDEC_EX_CODEC_LEVEL_H264_3, 547 E_VDEC_EX_CODEC_LEVEL_H264_3_1, 548 E_VDEC_EX_CODEC_LEVEL_H264_3_2, 549 E_VDEC_EX_CODEC_LEVEL_H264_4, 550 E_VDEC_EX_CODEC_LEVEL_H264_4_1, 551 E_VDEC_EX_CODEC_LEVEL_H264_4_2, 552 E_VDEC_EX_CODEC_LEVEL_H264_5, 553 E_VDEC_EX_CODEC_LEVEL_H264_5_1, 554 E_VDEC_EX_CODEC_LEVEL_H264_5_2, 555 556 E_VDEC_EX_CODEC_LEVEL_H265_1, 557 E_VDEC_EX_CODEC_LEVEL_H265_2, 558 E_VDEC_EX_CODEC_LEVEL_H265_2_1, 559 E_VDEC_EX_CODEC_LEVEL_H265_3, 560 E_VDEC_EX_CODEC_LEVEL_H265_3_1, 561 E_VDEC_EX_CODEC_LEVEL_H265_4_MT, 562 E_VDEC_EX_CODEC_LEVEL_H265_4_HT, 563 E_VDEC_EX_CODEC_LEVEL_H265_4_1_MT, 564 E_VDEC_EX_CODEC_LEVEL_H265_4_1_HT, 565 E_VDEC_EX_CODEC_LEVEL_H265_5_MT, 566 E_VDEC_EX_CODEC_LEVEL_H265_5_HT, 567 E_VDEC_EX_CODEC_LEVEL_H265_5_1_MT, 568 E_VDEC_EX_CODEC_LEVEL_H265_5_1_HT, 569 E_VDEC_EX_CODEC_LEVEL_H265_5_2_MT, 570 E_VDEC_EX_CODEC_LEVEL_H265_5_2_HT, 571 E_VDEC_EX_CODEC_LEVEL_H265_6_MT, 572 E_VDEC_EX_CODEC_LEVEL_H265_6_HT, 573 E_VDEC_EX_CODEC_LEVEL_H265_6_1_MT, 574 E_VDEC_EX_CODEC_LEVEL_H265_6_1_HT, 575 E_VDEC_EX_CODEC_LEVEL_H265_6_2_MT, 576 E_VDEC_EX_CODEC_LEVEL_H265_6_2_HT, 577 578 E_VDEC_EX_CODEC_LEVEL_AVS_6010860, 579 580 } VDEC_EX_CODEC_CAP_LEVEL_INFO; 581 582 583 typedef enum 584 { 585 E_VDEC_EX_CODEC_VERSION_NONE, 586 587 E_VDEC_EX_CODEC_VERSION_DIVX_311, 588 E_VDEC_EX_CODEC_VERSION_DIVX_4, 589 E_VDEC_EX_CODEC_VERSION_DIVX_5, 590 E_VDEC_EX_CODEC_VERSION_DIVX_6, 591 592 E_VDEC_EX_CODEC_VERSION_FLV_1, 593 594 E_VDEC_EX_CODEC_VERSION_H263_1, 595 596 } VDEC_EX_CODEC_CAP_VERSION_INFO; 597 598 typedef struct 599 { 600 MS_U16 u16CodecCapWidth; 601 MS_U16 u16CodecCapHeight; 602 MS_U8 u8CodecCapFrameRate; 603 VDEC_EX_CODEC_CAP_PROFILE_INFO u8CodecCapProfile; 604 VDEC_EX_CODEC_CAP_VERSION_INFO u8CodecCapVersion; 605 VDEC_EX_CODEC_CAP_LEVEL_INFO u8CodecCapLevel; 606 MS_U32 u32CodecType; 607 MS_U32 u32Reserved1; 608 }VDEC_EX_CODEC_CAP_INFO; 609 610 //------------------------------------------------------------------------------------------------- 611 // Function and Variable 612 //------------------------------------------------------------------------------------------------- 613 MS_BOOL HAL_VPU_EX_SetSTCMode(MS_U32 u32Id,MS_U32 u32STCindex) ; 614 MS_BOOL HAL_VPU_EX_SetDecodeMode(MS_U32 u32Id, VPU_EX_DecModCfg *pstCfg); 615 MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable); 616 #ifdef VDEC3 617 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara, MS_BOOL bFWdecideFB, MS_U32 u32BBUId); 618 #else 619 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara); 620 #endif 621 MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara); 622 MS_BOOL HAL_VPU_EX_SetFWReload(MS_U32 u32Id, MS_BOOL bReload); 623 624 MS_BOOL HAL_VPU_EX_LoadCode(MS_U32 u32Id, VPU_EX_FWCodeCfg *pFWCodeCfg); 625 void HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase); 626 627 #ifdef VDEC3 628 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType, MS_BOOL bIsEVD, MS_BOOL bIsNStreamMode); 629 #else 630 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType, MS_BOOL bIsEVD); 631 #endif 632 MS_BOOL HAL_VPU_EX_Init(MS_U32 u32Id, VPU_EX_InitParam *InitParams); 633 MS_BOOL HAL_VPU_EX_DeInit(MS_U32 u32Id); 634 void HAL_VPU_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable); 635 void HAL_VPU_EX_MIU_RW_Protect(MS_U32 u32Id, MS_BOOL bEnable); 636 MS_BOOL HAL_VPU_EX_CPUSetting(MS_U32 u32Id, MS_PHY u32StAddr); 637 MS_BOOL HAL_VPU_EX_SwRst(MS_U32 u32Id, MS_BOOL bCheckMauIdle); 638 void HAL_VPU_EX_SwRstRelse(MS_U32 u32Id); 639 void HAL_VPU_EX_SwRelseMAU(MS_U32 u32Id); 640 MS_U32 HAL_VPU_EX_MemRead(MS_VIRT u32Address); 641 MS_BOOL HAL_VPU_EX_MemWrite(MS_VIRT u32Address, MS_U32 u32Value); 642 MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32Id, MS_U32 u32type); 643 MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32Id, MS_U32 u32type, MS_U32 *u32Msg); 644 void HAL_VPU_EX_MBoxClear(MS_U32 u32Id, MS_U32 u32type); 645 MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32Id, MS_U32 u32type, MS_U32 u32Msg); 646 MS_U32 HAL_VPU_EX_GetProgCnt(MS_U32 u32Id); 647 MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id); 648 void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_VIRT u32ShmAddr); 649 MS_VIRT HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id); 650 MS_BOOL HAL_VPU_EX_IsPowered(MS_U32 u32Id); 651 MS_BOOL HAL_VPU_EX_IsRsted(MS_U32 u32Id); 652 MS_BOOL HAL_VPU_EX_IsEVDR2(MS_U32 u32Id); 653 MS_BOOL HAL_VPU_EX_MVDInUsed(MS_U32 u32Id); 654 MS_BOOL HAL_VPU_EX_HVDInUsed(MS_U32 u32Id); 655 #ifdef VDEC3 656 MS_BOOL HAL_VPU_EX_EVDInUsed(MS_U32 u32Id); 657 #if SUPPORT_G2VP9 658 MS_BOOL HAL_VPU_EX_G2VP9InUsed(MS_U32 u32Id); 659 #endif 660 #endif 661 void HAL_VPU_EX_IQMemSetDAMode(MS_U32 u32Id, MS_BOOL bEnable); 662 void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel); 663 MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType); 664 MS_BOOL HAL_VPU_EX_Init_Share_Mem(void); 665 MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap); 666 MS_BOOL HAL_VPU_EX_GetCodecCapInfo( int eCodecType, VDEC_EX_CODEC_CAP_INFO *pCodecCapInfo); 667 #ifdef VDEC3 668 void HAL_VPU_EX_SetCidx(MS_U32 u32Id, MS_BOOL bIsEVD, MS_BOOL bIsNStreamMode); 669 #else 670 void HAL_VPU_EX_SetCidx(MS_U32 u32Id, MS_BOOL bIsEVD); 671 #endif 672 673 MS_U8 HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id); 674 MS_PHY HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id); 675 void HAL_VPU_EX_Mutex_Lock(void); 676 void HAL_VPU_EX_Mutex_UnLock(void); 677 678 MS_VIRT HAL_VPU_EX_MIU1BASE(void); 679 MS_VIRT HAL_VPU_EX_GetSHMAddr(void); 680 MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable); 681 MS_BOOL HAL_VPU_EX_GetSecurityMode(void); 682 MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr); 683 MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void); 684 MS_BOOL HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass); 685 686 #ifdef VDEC3 687 typedef enum 688 { 689 E_HVD_CMDQ_CMD, 690 E_HVD_CMDQ_ARG, 691 } HVD_COMMAND_QUEUE_TYPE; 692 693 typedef enum 694 { 695 E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL, 696 E_HVD_COMMAND_QUEUE_NOT_INITIALED, 697 E_HVD_COMMAND_QUEUE_FULL, 698 E_HVD_COMMAND_QUEUE_SEND_FAIL, 699 } HVD_DRAM_COMMAND_QUEUE_SEND_STATUS; 700 701 702 typedef struct 703 { 704 MS_VIRT u32Offset; ///< Packet offset from bitstream buffer base address. unit: byte. 705 MS_U32 u32Length; ///< Packet size. unit: byte. ==> Move _VDEC_EX_ReparseVP8Packet to FW 706 MS_U64 u64TimeStamp; ///< Packet time stamp. unit: ms. 707 MS_U32 u32ID_L; ///< Packet ID low part. 708 MS_U32 u32ID_H; ///< Packet ID high part. 709 } HAL_VPU_EX_PacketInfo; 710 // *****************Virtual BBU function***************** 711 MS_BOOL HAL_VPU_EX_Push2VBBU(MS_U32 u32Id, HAL_VPU_EX_PacketInfo *stVpuPkt, MS_VIRT u32VBBUAddr); 712 MS_U32 HAL_VPU_EX_GetVBBUVacancy(MS_U32 u32Id, MS_VIRT u32VBBUAddr); 713 MS_VIRT HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr); 714 MS_VIRT HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr); 715 MS_BOOL HAL_VPU_EX_IsVBBUEmpty(MS_U32 u32Id, MS_VIRT u32VBBUAddr); 716 // *****************General dram command queue function***************** 717 MS_BOOL HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd); 718 MS_BOOL HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd); 719 MS_BOOL HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr, MS_U32 u32Msg); 720 // *****************Dram command queue function***************** 721 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsEmpty(void *cmd_queue); 722 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsFull(void *cmd_queue); 723 MS_U32 HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg); 724 // *****************Display dram command queue function***************** 725 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void *cmd_queue); 726 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsFull(void *cmd_queue); 727 MS_U32 HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg); 728 // *****************General purpose function***************** 729 MS_BOOL HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id, MS_VIRT u32BsAddr); 730 MS_U32 HAL_VPU_EX_GetBBUId(MS_U32 u32Id, VPU_EX_TaskInfo *pTaskInfo, MS_BOOL bIsNstreamMode); 731 MS_BOOL HAL_VPU_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_TaskInfo *pTaskInfo); 732 MS_SIZE HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType); 733 #ifdef CMA_DRV_DIRECT_INIT 734 // *****************CMA function***************** 735 MS_BOOL HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType, VPU_EX_SrcMode eSrcMode, 736 MS_U64 *offset, MS_SIZE *length, MS_U64 total_length, MS_SIZE unUseSize); 737 #endif 738 #endif 739 #ifdef VDEC3_FB 740 MS_BOOL HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType); 741 #endif 742 void HAL_VPU_EX_DynamicFBMode(MS_U32 u32Id, MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size); 743 MS_BOOL HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx); 744 MS_U8 HAL_VPU_EX_CheckFreeStream(void); 745 #ifdef CONFIG_MSTAR_CLKM 746 void HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType, MS_BOOL bEnable); 747 #endif 748 749 750 #else 751 typedef struct 752 { 753 MS_PHY Bitstream_Addr_Main; 754 MS_U32 Bitstream_Len_Main; 755 MS_PHY Bitstream_Addr_Sub; 756 MS_U32 Bitstream_Len_Sub; 757 MS_PHY MIU1_BaseAddr; 758 } VPU_EX_LOCK_DOWN_REGISTER; 759 760 761 MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr); 762 MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param,MS_U8 u8IsHVD); 763 764 #endif 765 #endif // _HAL_VPU_EX_H_ 766 767