xref: /utopia/UTPA2-700.0.x/modules/vd/hal/maldives/vbi/regVBI.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
1*53ee8cc1Swenshuai.xi //<MStar Software>
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77*53ee8cc1Swenshuai.xi //<MStar Software>
78*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
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92*53ee8cc1Swenshuai.xi //
93*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
94*53ee8cc1Swenshuai.xi 
95*53ee8cc1Swenshuai.xi #ifndef _REG_VBI_H
96*53ee8cc1Swenshuai.xi #define _REG_VBI_H
97*53ee8cc1Swenshuai.xi 
98*53ee8cc1Swenshuai.xi #define VBI_REG_BASE                0x3700  // 0x3700 - 0x37FF
99*53ee8cc1Swenshuai.xi #define AFEC_REG_BASE               0x3500  // 0x3500 - 0x35FF
100*53ee8cc1Swenshuai.xi #define CHIP_REG_BASE               0x1E00  // 0x1E00 - 0x1EFF
101*53ee8cc1Swenshuai.xi #define ADC_ATOP_REG_BASE           0x2500  // 0x2500 - 0x25FF
102*53ee8cc1Swenshuai.xi 
103*53ee8cc1Swenshuai.xi #define BK_REG_L( x, y )            ((x) | (((y) << 1)))
104*53ee8cc1Swenshuai.xi #define BK_REG_H( x, y )            (((x) | (((y) << 1))) + 1)
105*53ee8cc1Swenshuai.xi 
106*53ee8cc1Swenshuai.xi #define CC_BUF_BIT 28
107*53ee8cc1Swenshuai.xi #define TTX_BUF_BIT 28
108*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
109*53ee8cc1Swenshuai.xi // VBI register
110*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
111*53ee8cc1Swenshuai.xi #define BK_VBI_1D  (VBI_REG_BASE+0x1D)
112*53ee8cc1Swenshuai.xi #define BK_VBI_2A  (VBI_REG_BASE+0x2A)
113*53ee8cc1Swenshuai.xi #define BK_VBI_40  (VBI_REG_BASE+0x40)
114*53ee8cc1Swenshuai.xi #define BK_VBI_41  (VBI_REG_BASE+0x41)
115*53ee8cc1Swenshuai.xi #define BK_VBI_42  (VBI_REG_BASE+0x42)
116*53ee8cc1Swenshuai.xi #define BK_VBI_44  (VBI_REG_BASE+0x44)
117*53ee8cc1Swenshuai.xi #define BK_VBI_45  (VBI_REG_BASE+0x45)
118*53ee8cc1Swenshuai.xi #define BK_VBI_46  (VBI_REG_BASE+0x46)
119*53ee8cc1Swenshuai.xi #define BK_VBI_4A  (VBI_REG_BASE+0x4A)
120*53ee8cc1Swenshuai.xi #define BK_VBI_4B  (VBI_REG_BASE+0x4B)
121*53ee8cc1Swenshuai.xi #define BK_VBI_4D  (VBI_REG_BASE+0x4D)
122*53ee8cc1Swenshuai.xi #define BK_VBI_4F  (VBI_REG_BASE+0x4F)
123*53ee8cc1Swenshuai.xi #define BK_VBI_50  (VBI_REG_BASE+0x50)
124*53ee8cc1Swenshuai.xi #define BK_VBI_51  (VBI_REG_BASE+0x51)
125*53ee8cc1Swenshuai.xi #define BK_VBI_53  (VBI_REG_BASE+0x53)
126*53ee8cc1Swenshuai.xi #define BK_VBI_55  (VBI_REG_BASE+0x55)
127*53ee8cc1Swenshuai.xi #define BK_VBI_56  (VBI_REG_BASE+0x56)
128*53ee8cc1Swenshuai.xi #define BK_VBI_57  (VBI_REG_BASE+0x57)
129*53ee8cc1Swenshuai.xi #define BK_VBI_58  (VBI_REG_BASE+0x58)
130*53ee8cc1Swenshuai.xi #define BK_VBI_59  (VBI_REG_BASE+0x59)
131*53ee8cc1Swenshuai.xi #define BK_VBI_5A  (VBI_REG_BASE+0x5A)
132*53ee8cc1Swenshuai.xi #define BK_VBI_5B  (VBI_REG_BASE+0x5B)
133*53ee8cc1Swenshuai.xi #define BK_VBI_5C  (VBI_REG_BASE+0x5C)
134*53ee8cc1Swenshuai.xi #define BK_VBI_5D  (VBI_REG_BASE+0x5D)
135*53ee8cc1Swenshuai.xi #define BK_VBI_5E  (VBI_REG_BASE+0x5E)
136*53ee8cc1Swenshuai.xi #define BK_VBI_5F  (VBI_REG_BASE+0x5F)
137*53ee8cc1Swenshuai.xi #define BK_VBI_70  (VBI_REG_BASE+0x70)
138*53ee8cc1Swenshuai.xi #define BK_VBI_71  (VBI_REG_BASE+0x71)
139*53ee8cc1Swenshuai.xi #define BK_VBI_72  (VBI_REG_BASE+0x72)
140*53ee8cc1Swenshuai.xi #define BK_VBI_77  (VBI_REG_BASE+0x77)
141*53ee8cc1Swenshuai.xi #define BK_VBI_7C  (VBI_REG_BASE+0x7C)
142*53ee8cc1Swenshuai.xi #define BK_VBI_7D  (VBI_REG_BASE+0x7D)
143*53ee8cc1Swenshuai.xi #define BK_VBI_7E  (VBI_REG_BASE+0x7E)
144*53ee8cc1Swenshuai.xi #define BK_VBI_7F  (VBI_REG_BASE+0x7F)
145*53ee8cc1Swenshuai.xi #define BK_VBI_81  (VBI_REG_BASE+0x81)
146*53ee8cc1Swenshuai.xi #define BK_VBI_82  (VBI_REG_BASE+0x82)
147*53ee8cc1Swenshuai.xi #define BK_VBI_83  (VBI_REG_BASE+0x83)
148*53ee8cc1Swenshuai.xi #define BK_VBI_86  (VBI_REG_BASE+0x86)
149*53ee8cc1Swenshuai.xi #define BK_VBI_89  (VBI_REG_BASE+0x89)
150*53ee8cc1Swenshuai.xi #define BK_VBI_8A  (VBI_REG_BASE+0x8A)
151*53ee8cc1Swenshuai.xi #define BK_VBI_8B  (VBI_REG_BASE+0x8B)
152*53ee8cc1Swenshuai.xi #define BK_VBI_8D  (VBI_REG_BASE+0x8D)
153*53ee8cc1Swenshuai.xi #define BK_VBI_90  (VBI_REG_BASE+0x90)
154*53ee8cc1Swenshuai.xi #define BK_VBI_91  (VBI_REG_BASE+0x91)
155*53ee8cc1Swenshuai.xi #define BK_VBI_92  (VBI_REG_BASE+0x92)
156*53ee8cc1Swenshuai.xi #define BK_VBI_99  (VBI_REG_BASE+0x99)
157*53ee8cc1Swenshuai.xi #define BK_VBI_9A  (VBI_REG_BASE+0x9A)
158*53ee8cc1Swenshuai.xi #define BK_VBI_A6  (VBI_REG_BASE+0xA6)
159*53ee8cc1Swenshuai.xi #define BK_VBI_A7  (VBI_REG_BASE+0xA7)
160*53ee8cc1Swenshuai.xi #define BK_VBI_AD  (VBI_REG_BASE+0xAD)
161*53ee8cc1Swenshuai.xi #define BK_VBI_AE  (VBI_REG_BASE+0xAE)
162*53ee8cc1Swenshuai.xi #define BK_VBI_AF  (VBI_REG_BASE+0xAF)
163*53ee8cc1Swenshuai.xi #define BK_VBI_B4  (VBI_REG_BASE+0xB4)
164*53ee8cc1Swenshuai.xi #define BK_VBI_B5  (VBI_REG_BASE+0xB5)
165*53ee8cc1Swenshuai.xi #define BK_VBI_B7  (VBI_REG_BASE+0xB7)
166*53ee8cc1Swenshuai.xi #define BK_VBI_B8  (VBI_REG_BASE+0xB8)
167*53ee8cc1Swenshuai.xi #define BK_VBI_BB  (VBI_REG_BASE+0xBB)
168*53ee8cc1Swenshuai.xi #define BK_VBI_BF  (VBI_REG_BASE+0xBF)
169*53ee8cc1Swenshuai.xi #define BK_VBI_C4  (VBI_REG_BASE+0xC4)
170*53ee8cc1Swenshuai.xi #define BK_VBI_CA  (VBI_REG_BASE+0xCA)
171*53ee8cc1Swenshuai.xi #define BK_VBI_CB  (VBI_REG_BASE+0xCB)
172*53ee8cc1Swenshuai.xi #define BK_VBI_CC  (VBI_REG_BASE+0xCC)
173*53ee8cc1Swenshuai.xi #define BK_VBI_CD  (VBI_REG_BASE+0xCD)
174*53ee8cc1Swenshuai.xi #define BK_VBI_CE  (VBI_REG_BASE+0xCE)
175*53ee8cc1Swenshuai.xi 
176*53ee8cc1Swenshuai.xi #define BK_VBI_DE  (VBI_REG_BASE+0xDE)
177*53ee8cc1Swenshuai.xi #define BK_VBI_DF  (VBI_REG_BASE+0xDF)
178*53ee8cc1Swenshuai.xi #define BK_VBI_E0  (VBI_REG_BASE+0xE0)
179*53ee8cc1Swenshuai.xi #define BK_VBI_E1  (VBI_REG_BASE+0xE1)
180*53ee8cc1Swenshuai.xi #define BK_VBI_E2  (VBI_REG_BASE+0xE2)
181*53ee8cc1Swenshuai.xi #define BK_VBI_E3  (VBI_REG_BASE+0xE3)
182*53ee8cc1Swenshuai.xi #define BK_VBI_E4  (VBI_REG_BASE+0xE4)
183*53ee8cc1Swenshuai.xi #define BK_VBI_E5  (VBI_REG_BASE+0xE5)
184*53ee8cc1Swenshuai.xi #define BK_VBI_E6  (VBI_REG_BASE+0xE6)
185*53ee8cc1Swenshuai.xi #define BK_VBI_E7  (VBI_REG_BASE+0xE7)
186*53ee8cc1Swenshuai.xi 
187*53ee8cc1Swenshuai.xi #define VBI_INTERRUPT_MASK      0x6C + (VBI_REG_BASE)
188*53ee8cc1Swenshuai.xi #define VBI_INTERRUPT_CLEAR     0x6D + (VBI_REG_BASE)
189*53ee8cc1Swenshuai.xi #define VBI_INTERRUPT_STATUS    0x6E + (VBI_REG_BASE)
190*53ee8cc1Swenshuai.xi #define VBI_INTERRUPT_RAW       0x6F + (VBI_REG_BASE)
191*53ee8cc1Swenshuai.xi 
192*53ee8cc1Swenshuai.xi #define VBI_VPS_COUNT           0xA5 + (VBI_REG_BASE)
193*53ee8cc1Swenshuai.xi #define VBI_WSS_COUNT           0xA5 + (VBI_REG_BASE)
194*53ee8cc1Swenshuai.xi 
195*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
196*53ee8cc1Swenshuai.xi // Other registers
197*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
198*53ee8cc1Swenshuai.xi #define BK_AFEC_6B              (AFEC_REG_BASE + 0x6B)
199*53ee8cc1Swenshuai.xi #define L_BK_ADC_ATOP(x)        BK_REG_L(ADC_ATOP_REG_BASE, x)
200*53ee8cc1Swenshuai.xi #define H_BK_ADC_ATOP(x)        BK_REG_H(ADC_ATOP_REG_BASE, x)
201*53ee8cc1Swenshuai.xi #define L_BK_CHIPTOP(x)         BK_REG_L(CHIP_REG_BASE, x)
202*53ee8cc1Swenshuai.xi #define H_BK_CHIPTOP(x)         BK_REG_H(CHIP_REG_BASE, x)
203*53ee8cc1Swenshuai.xi 
204*53ee8cc1Swenshuai.xi /********************************************************************************/
205*53ee8cc1Swenshuai.xi /*                           Start of Teletext Register definitions                                                          */
206*53ee8cc1Swenshuai.xi /********************************************************************************/
207*53ee8cc1Swenshuai.xi #define TT_ENABLE           0x10 + (VBI_REG_BASE)
208*53ee8cc1Swenshuai.xi 
209*53ee8cc1Swenshuai.xi // DMA and Tag Search Register
210*53ee8cc1Swenshuai.xi #define DMASRC_ADR_L     0x11 + (VBI_REG_BASE) // DMA Source Linear Address
211*53ee8cc1Swenshuai.xi #define DMASRC_ADR_M    0x12 + (VBI_REG_BASE)
212*53ee8cc1Swenshuai.xi #define DMASRC_ADR_H    0x13 + (VBI_REG_BASE)
213*53ee8cc1Swenshuai.xi 
214*53ee8cc1Swenshuai.xi #define DMADES_ADR_L     0x14 + (VBI_REG_BASE)// DMA Destination Linear Address
215*53ee8cc1Swenshuai.xi #define DMADES_ADR_M    0x15 + (VBI_REG_BASE)
216*53ee8cc1Swenshuai.xi #define DMADES_ADR_H    0x16 + (VBI_REG_BASE)
217*53ee8cc1Swenshuai.xi 
218*53ee8cc1Swenshuai.xi #define DMAQW_CNT_L     0x17 + (VBI_REG_BASE)// DMA Block Move Count
219*53ee8cc1Swenshuai.xi #define DMAQW_CNT_H     0x18 + (VBI_REG_BASE)
220*53ee8cc1Swenshuai.xi 
221*53ee8cc1Swenshuai.xi #define DMA_FUNC            0x19 + (VBI_REG_BASE)// DMA Function Seletction
222*53ee8cc1Swenshuai.xi     #define DMA_HEADER                  0x01
223*53ee8cc1Swenshuai.xi     #define DMA_PACKET1_TO_25    0x02
224*53ee8cc1Swenshuai.xi     #define DMA_BTT                         0x04
225*53ee8cc1Swenshuai.xi     #define DMA_AIT                         0x05
226*53ee8cc1Swenshuai.xi     #define DMA_MCU_READ              0x0D
227*53ee8cc1Swenshuai.xi     #define DMA_MCU_WRITE            0x0E
228*53ee8cc1Swenshuai.xi     #define DMA_PACKET26_28_29   0x03
229*53ee8cc1Swenshuai.xi     #define DMA_PACKET27               0x06
230*53ee8cc1Swenshuai.xi     #define DMA_TAG_READ              0x1D
231*53ee8cc1Swenshuai.xi     #define DMA_TAG_WRITE            0x1E
232*53ee8cc1Swenshuai.xi     #define DMA_ERASE                     0x1F
233*53ee8cc1Swenshuai.xi 
234*53ee8cc1Swenshuai.xi #define DMA_COMMAND             0x1A + (VBI_REG_BASE)
235*53ee8cc1Swenshuai.xi     #define DMA_READY           _BIT1
236*53ee8cc1Swenshuai.xi     #define DMA_FIRE              _BIT0
237*53ee8cc1Swenshuai.xi 
238*53ee8cc1Swenshuai.xi #define DMAERASE_DATA         0x1B + (VBI_REG_BASE)
239*53ee8cc1Swenshuai.xi 
240*53ee8cc1Swenshuai.xi #define VBI_BIT24_ADDR      0x1D + (VBI_REG_BASE)
241*53ee8cc1Swenshuai.xi     #define CCBASE_ADDR24   _BIT7
242*53ee8cc1Swenshuai.xi     #define TTBASE_ADDR24   _BIT6
243*53ee8cc1Swenshuai.xi     #define DMASRC_ADDR24   _BIT5
244*53ee8cc1Swenshuai.xi     #define DMADES_ADDR24   _BIT4
245*53ee8cc1Swenshuai.xi     #define TAGBASE_ADDR24   _BIT2
246*53ee8cc1Swenshuai.xi     #define PAGEBASE_ADDR24   _BIT1
247*53ee8cc1Swenshuai.xi     #define TTBASE2_ADDR24   _BIT0
248*53ee8cc1Swenshuai.xi 
249*53ee8cc1Swenshuai.xi #define TTDEC_COMMAND         0x1F + (VBI_REG_BASE)
250*53ee8cc1Swenshuai.xi 
251*53ee8cc1Swenshuai.xi #define TTDEC_STATIS            0x20 + (VBI_REG_BASE)
252*53ee8cc1Swenshuai.xi     #define VBIREADY                _BIT7
253*53ee8cc1Swenshuai.xi 
254*53ee8cc1Swenshuai.xi #define SLICERREADY             0x21 + (VBI_REG_BASE)
255*53ee8cc1Swenshuai.xi 
256*53ee8cc1Swenshuai.xi #define MCU_ADDR_PORT       0x22 + (VBI_REG_BASE)
257*53ee8cc1Swenshuai.xi     #define BURST_RD_MD        _BIT7
258*53ee8cc1Swenshuai.xi     #define BURST_WR_MD       _BIT6
259*53ee8cc1Swenshuai.xi 
260*53ee8cc1Swenshuai.xi 
261*53ee8cc1Swenshuai.xi #define MCU_DATA_PORT       0x23 + (VBI_REG_BASE)
262*53ee8cc1Swenshuai.xi 
263*53ee8cc1Swenshuai.xi #define TAGRW_POS_L             0x24 + (VBI_REG_BASE)
264*53ee8cc1Swenshuai.xi #define TAGRW_POS_H             0x25 + (VBI_REG_BASE)
265*53ee8cc1Swenshuai.xi 
266*53ee8cc1Swenshuai.xi #define PAGEBUF_ADDR_L      0x26 + (VBI_REG_BASE)
267*53ee8cc1Swenshuai.xi #define PAGEBUF_ADDR_M      0x27 + (VBI_REG_BASE)
268*53ee8cc1Swenshuai.xi #define PAGEBUF_ADDR_H      0x28 + (VBI_REG_BASE)
269*53ee8cc1Swenshuai.xi 
270*53ee8cc1Swenshuai.xi #define PAGEBUF_CNT_L           0x29 + (VBI_REG_BASE)
271*53ee8cc1Swenshuai.xi #define PAGEBUF_CNT_H           0x2A + (VBI_REG_BASE)
272*53ee8cc1Swenshuai.xi 
273*53ee8cc1Swenshuai.xi #define FUNCTION                    0x2B + (VBI_REG_BASE)
274*53ee8cc1Swenshuai.xi 
275*53ee8cc1Swenshuai.xi #define TAG_MAGAZINE           0x2C + (VBI_REG_BASE)
276*53ee8cc1Swenshuai.xi #define TAG_PAGE                   0x2D + (VBI_REG_BASE)
277*53ee8cc1Swenshuai.xi #define TAG_SUBCODE_H        0x2E + (VBI_REG_BASE)
278*53ee8cc1Swenshuai.xi #define TAG_SUBCODE_L         0x2F + (VBI_REG_BASE)
279*53ee8cc1Swenshuai.xi 
280*53ee8cc1Swenshuai.xi 
281*53ee8cc1Swenshuai.xi #define TAG_BASE_L              0x30 + (VBI_REG_BASE)
282*53ee8cc1Swenshuai.xi #define TAG_BASE_H              0x31 + (VBI_REG_BASE)
283*53ee8cc1Swenshuai.xi 
284*53ee8cc1Swenshuai.xi #define PAGE_BASE_L             0x32 + (VBI_REG_BASE)
285*53ee8cc1Swenshuai.xi #define PAGE_BASE_H             0x33 + (VBI_REG_BASE)
286*53ee8cc1Swenshuai.xi 
287*53ee8cc1Swenshuai.xi #define PAGE_SIZE               0x34 + (VBI_REG_BASE) // Per 8 Bytes
288*53ee8cc1Swenshuai.xi 
289*53ee8cc1Swenshuai.xi #define TAG_PHT_SIZE_L      0x35 + (VBI_REG_BASE)
290*53ee8cc1Swenshuai.xi #define TAG_PHT_SIZE_H      0x36 + (VBI_REG_BASE)
291*53ee8cc1Swenshuai.xi 
292*53ee8cc1Swenshuai.xi 
293*53ee8cc1Swenshuai.xi #define TAG_COMMAND             0x37 + (VBI_REG_BASE)
294*53ee8cc1Swenshuai.xi     #define BUF_ADDR_RDY        _BIT3
295*53ee8cc1Swenshuai.xi     #define HIT_STATUS             _BIT2
296*53ee8cc1Swenshuai.xi     #define TAG_READY              _BIT1
297*53ee8cc1Swenshuai.xi     #define TAG_FIRE                 _BIT0
298*53ee8cc1Swenshuai.xi 
299*53ee8cc1Swenshuai.xi 
300*53ee8cc1Swenshuai.xi #define VBI_BASEADDR_L      0x38 + (VBI_REG_BASE)
301*53ee8cc1Swenshuai.xi #define VBI_BASEADDR_M      0x39 + (VBI_REG_BASE)
302*53ee8cc1Swenshuai.xi #define VBI_BASEADDR_H      0x3A + (VBI_REG_BASE)
303*53ee8cc1Swenshuai.xi #define VBI_BUF_LEN           0x3B + (VBI_REG_BASE)
304*53ee8cc1Swenshuai.xi #define VBI_BUF_LEN_H           0x3C + (VBI_REG_BASE)
305*53ee8cc1Swenshuai.xi 
306*53ee8cc1Swenshuai.xi #define VBI_W_COUNT            0x3D + (VBI_REG_BASE)
307*53ee8cc1Swenshuai.xi #define VBI_PKTCNT_L             0x3D + (VBI_REG_BASE)
308*53ee8cc1Swenshuai.xi 
309*53ee8cc1Swenshuai.xi 
310*53ee8cc1Swenshuai.xi #define TT_LineUpdDef              0x72 + (VBI_REG_BASE)
311*53ee8cc1Swenshuai.xi #define TT_DAT_LN_STR1          0x7C + (VBI_REG_BASE)
312*53ee8cc1Swenshuai.xi #define TT_DAT_LN_END1          0x7D + (VBI_REG_BASE)
313*53ee8cc1Swenshuai.xi #define TT_DAT_LN_STR2          0x7E + (VBI_REG_BASE)
314*53ee8cc1Swenshuai.xi #define TT_DAT_LN_END2          0x7F + (VBI_REG_BASE)
315*53ee8cc1Swenshuai.xi #define TTSLCTHRD                   0x8D + (VBI_REG_BASE)
316*53ee8cc1Swenshuai.xi 
317*53ee8cc1Swenshuai.xi #define TT_CLK_RUN_IN_START_POINT 0x77 + (VBI_REG_BASE)
318*53ee8cc1Swenshuai.xi 
319*53ee8cc1Swenshuai.xi #endif
320*53ee8cc1Swenshuai.xi 
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