1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. 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If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 /////////////////////////////////////////////////////////////////////////////// 79 // 80 // File name: Lib_Host20.H 81 // Version: 1.0 82 // Date: 2004/12/08 83 // 84 // Author: Bruce 85 // Phone: (03) 578-7888 86 // Company: Faraday Tech. Corp. 87 // 88 // Description: 1.EHCI Data Structure 89 // 2.EHCI Register 90 // 3.Others 91 /////////////////////////////////////////////////////////////////////////////// 92 #ifndef LIB_HOST200__H 93 #define LIB_HOST200__H 94 95 #include "../drvUsbHostConfig.h" 96 #include "MsCommon.h" 97 #include "MsIRQ.h" 98 #include "MsOS.h" 99 #if 0 100 typedef unsigned char UINT8; // 1 byte 101 /// data type unsigned short, data length 2 byte 102 typedef unsigned int UINT16; // 2 bytes 103 /// data type unsigned int, data length 4 byte 104 typedef unsigned long UINT32; // 4 bytes 105 /// data type signed char, data length 1 byte 106 #endif 107 108 #ifndef ATV_SERISE_USE 109 #ifdef CERAMAL_SERISE_USE 110 111 #else 112 113 #endif 114 #define USBDELAY(x) MsOS_DelayTask(x) 115 #else 116 #define BOOLEAN UINT8 117 #define INT32U UINT32 118 #define INT16U UINT16 119 #define INT8U UINT8 120 #endif 121 122 extern void USB_Write_REG32_Port3(UINT8 addr,UINT32 val); 123 extern U32 USB_BUFFER_START_ADR_4K_ALIGN_Var_Port3; 124 125 //=================== 1.Condition Definition ============================================================ 126 //======================================================================================================== 127 128 129 #define FUSBH200_HOST_ONLY 130 131 132 #define Host20_Debug_Info 0x01 133 #define IRQ_USB_Host20 40 134 #define Host20_Set_Address 0x03 135 136 //Host Configuration 137 #define Host20_QHD_Nat_Counter 0x00//Temp Solution from 15 to 0 //Bit28~31 138 //#define Host20_EOF1Time 0x00//For Full Speed Device 139 #define Host20_EOF1Time 0x03//For High Speed Device 140 141 //=================== 2.Variable Definition ============================================================ 142 //======================================================================================================== 143 #define HOST20_OK 0x00 144 #define HOST20_FAIL 0x01 145 #define HOST20_FATAL 0x02 146 #define HOST20_DEVICE_STALL 0x03 147 #define HOST20_TRANSACTION_ERROR 0x04 148 //---------------------------------- 149 #define USB_OK 0 150 #define USB_DISCONNECTED 1 151 #define USB_TIMEOUT 2 152 #define USB_TRANS_ERROR 3 153 #define USB_EJECT 4 154 #define USB_INIT_FAIL 5 155 156 //**************************** 157 // Data Structure Allocation 158 //**************************** 159 // 0x3000000~0x3001000 =>qHD 160 // 0x3001000~0x3002000 =>qTD 161 // 0x3002000~0x3003000 =>iTD 162 // 163 164 165 // #if (USB_BUFFER_START_ADR_4K_ALIGN % 4096 != 0) 166 // #error USB_BUFFER_START_ADR_4K_ALIGN needs 4K-byte alignment 167 // #endif 168 169 170 #define Host20_qHD_SIZE 0x40//(48bytes), for alignment 171 #define Host20_qHD_MAX 10//(10 ) 172 173 #define Host20_qTD_SIZE 0x20//(32bytes) 174 #define Host20_qTD_MAX 0x10//(50 ) 175 176 // Control Transfer Data stage buffer size 177 #define CONTROL_DMA_BUF_LEN 0x1000 178 #define CONTROL_BUF_LEN 0x1000 179 180 181 182 // #define Host20_STRUCTURE_iTD_BASE_ADDRESS (Host20_STRUCTURE_BASE_ADDRESS+0x10000)//(DRAM=48M) 183 // #define Host20_iTD_SIZE 0x40//(64bytes) 184 // #define Host20_iTD_MAX 1024//(10 ) 185 186 187 188 189 #define Host20_MEM_TYPE_qTD 0x00 190 #define Host20_MEM_TYPE_iTD 0x01 191 #define Host20_MEM_TYPE_4K_BUFFER 0x02 192 #define Host20_MEM_TYPE_siTD 0x03 193 194 195 196 #define Host20_MEM_FREE 0x01 197 #define Host20_MEM_USED 0x02 198 199 200 #if 0 // use the define in DataType.h #define BIT8 0x00000100 201 #define BIT8 0x00000100 202 #define BIT9 0x00000200 203 #define BIT10 0x00000400 204 #define BIT11 0x00000800 205 #define BIT12 0x00001000 206 #define BIT13 0x00002000 207 #define BIT14 0x00004000 208 #define BIT15 0x00008000 209 #endif 210 #define BIT16 0x00010000 211 #define BIT17 0x00020000 212 #define BIT18 0x00040000 213 #define BIT19 0x00080000 214 #define BIT20 0x00100000 215 #define BIT21 0x00200000 216 #define BIT22 0x00400000 217 #define BIT23 0x00800000 218 219 #define BIT24 0x01000000 220 #define BIT25 0x02000000 221 #define BIT26 0x04000000 222 #define BIT27 0x08000000 223 #define BIT28 0x10000000 224 #define BIT29 0x20000000 225 #define BIT30 0x40000000 226 #define BIT31 0x80000000 227 228 229 #define OTGH_Dir_IN 0x01 230 #define OTGH_Dir_Out 0x00 231 #define OTGH_NULL 0x00 232 #define OTGH_ED_ISO 0x01 233 #define OTGH_ED_BULK 0x02 234 #define OTGH_ED_INT 0x03 235 #define OTGH_ED_Control 0x00 236 #define OTGH_FARADAY_TEST_AP 0x10237856 237 #define OTGH_SRP_HNP_Enable 0x03 238 #define OTGH_Remote_Wake_UP 0x00000400 239 #define OTGH_Remote_Wake_UP_INT 0x00000008 240 241 242 unsigned char mwHost20Port_Port3(int bOffset); 243 void mwHost20Port_wr_Port3(int bOffset, int value); 244 int mwHost20Bit_Rd_Port3(int bByte,int wBitNum); 245 void mwHost20Bit_Set_Port3(int bByte,int wBitNum); 246 void mwHost20Bit_Clr_Port3(int bByte,int wBitNum); 247 248 //=================== 2.Define Register Macro ================================================================ 249 //======================================================================================================== 250 extern U32 gUHC3_BASE; 251 //<1>.Macro volatile 252 // #define Host20_BASE_ADDRESS UHC_BASE//0x92500000 253 // #define mwHost20Port(bOffset) *((UINT8 volatile xdata *) ( Host20_BASE_ADDRESS | bOffset)) 254 // #define mwHost20Port(bOffset) *((UINT8 volatile xdata *) ( gUHC2_BASE | bOffset)) 255 // #define mwHost20Bit_Rd(bByte,wBitNum) (mwHost20Port(bByte)&wBitNum) 256 // #define mwHost20Bit_Set(bByte,wBitNum) (mwHost20Port(bByte)|=wBitNum) 257 // #define mwHost20Bit_Clr(bByte,wBitNum) (mwHost20Port(bByte)&=~wBitNum) 258 #define mwHost20Port_word(bOffset) *((UINT16 volatile *) ( gUHC3_BASE | bOffset)) 259 260 //<2>.0x000(Capability Register) 261 //#define mwHost20_HCIVersion_Rd() ((mwHost20Port(0x00)>>16)&0x0000FFFF) 262 //#define mwHost20_CapLength_Rd() (mwHost20Port(0x00)&0x000000FF) 263 264 //<3>.0x004(HCSPARAMS - Structural Parameters) 265 #define mwHost20_NumPorts_Rd() ((mwHost20Port_Port3(0x04)&0x0000000F) 266 267 //<4>.0x008(HCCPARAMS - Capability Parameters) 268 #define mbHost20_ProgrammableFrameListFlag_Rd() (mwHost20Bit_Rd_Port3(0x08,BIT1)) //Bit 1 269 270 //<4>.0x010(USBCMD - USB Command Register) 271 //#define mwHost20_USBCMD_IntThreshold_Rd() ((mwHost20Port(0x010)>>16)&0x0000FFFF) //Bit 16~23 272 //#define mbHost20_USBCMD_IntThreshold_Set(bValue) (mwHost20Port(0x010)=((mwHost20Port(0x010)&0xFF00FFFF)|(((UINT32)(bValue))<<16)) //Bit 16~23 273 //----->Add "Asynchronous schedule Park mode ENable" 274 //----->Add "ASYNchronous schedule Park mode CouNT" 275 276 //#define mbHost20_USBCMD_ParkMode_Rd() (mwHost20Bit_Rd(0x10,BIT11)>>11) 277 //#define mbHost20_USBCMD_ParkMode_Set() (mwHost20Bit_Set(0x10,BIT11)) 278 //#define mbHost20_USBCMD_ParkMode_Clr() (mwHost20Bit_Clr(0x10,BIT11)) 279 280 #define mbHost20_USBCMD_ParkMode_CNT_Rd() ((mwHost20Port_Port3(0x10)>>8)&0x00000003) 281 #define mbHost20_USBCMD_ParkMode_CNT_Set(bValue) (mwHost20Port_Port3(0x011)=(mwHost20Port_Port3(0x011)&0xFC)|(( (UINT8) bValue )<<8) ) //Bit 8~9 282 283 #define mbHost20_USBCMD_InterruptOnAsync_Rd() (mwHost20Bit_Rd_Port3(0x10,BIT6)) //Bit 6 284 #define mbHost20_USBCMD_InterruptOnAsync_Set() (mwHost20Bit_Set_Port3(0x10,BIT6)) //Bit 6 285 #define mbHost20_USBCMD_InterruptOnAsync_Clr() (mwHost20Bit_Clr_Port3(0x10,BIT6)) //Bit 6 286 287 #define mbHost20_USBCMD_AsynchronousEnable_Rd() (mwHost20Bit_Rd_Port3(0x10,BIT5)) //Bit 5 288 #define mbHost20_USBCMD_AsynchronousEnable_Set() (mwHost20Bit_Set_Port3(0x10,BIT5)) //Bit 5 289 #define mbHost20_USBCMD_AsynchronousEnable_Clr() (mwHost20Bit_Clr_Port3(0x10,BIT5)) //Bit 5 290 291 #define mbHost20_USBCMD_PeriodicEnable_Rd() (mwHost20Bit_Rd_Port3(0x10,BIT4) ) //Bit 4 292 #define mbHost20_USBCMD_PeriodicEnable_Set() (mwHost20Bit_Set_Port3(0x10,BIT4)) //Bit 4 293 #define mbHost20_USBCMD_PeriodicEnable_Clr() (mwHost20Bit_Clr_Port3(0x10,BIT4)) //Bit 4 294 295 #define mbHost20_USBCMD_FrameListSize_Rd() ((mwHost20Port_Port3(0x10)>>2)&0x00000003) //Bit 2~3 296 #define mbHost20_USBCMD_FrameListSize_Set(bValue) (mwHost20Port_wr_Port3(0x10, (mwHost20Port_Port3(0x10)&0xF3)|(((UINT8)(bValue))<<2)) ) //Bit 2~3 297 298 #define HOST20_USBCMD_FrameListSize_1024 0x00 299 #define HOST20_USBCMD_FrameListSize_512 0x01 300 #define HOST20_USBCMD_FrameListSize_256 0x02 301 302 #define mbHost20_USBCMD_HCReset_Rd() (mwHost20Bit_Rd_Port3(0x10,BIT1)) //Bit 1 303 #define mbHost20_USBCMD_HCReset_Set() (mwHost20Bit_Set_Port3(0x10,BIT1)) //Bit 1 304 305 #define mbHost20_USBCMD_RunStop_Rd() (mwHost20Bit_Rd_Port3(0x10,BIT0) ) //Bit 0 306 #define mbHost20_USBCMD_RunStop_Set() (mwHost20Bit_Set_Port3(0x10,BIT0)) //Bit 0 307 #define mbHost20_USBCMD_RunStop_Clr() (mwHost20Bit_Clr_Port3(0x10,BIT0)) //Bit 0 308 309 310 #define HOST20_Enable 0x01 311 #define HOST20_Disable 0x00 312 313 314 315 316 //<5>.0x014(USBSTS - USB Status Register) 317 #define mwHost20_USBSTS_Rd() (mwHost20Port_Port3(0x14)) 318 #define mwHost20_USBSTS_Set(wValue) mwHost20Port_wr_Port3(0x14,wValue) 319 320 #define mwHost20_USBSTS_AsynchronousStatus_Rd() (mwHost20Bit_Rd_Port3(0x15,BIT7)) //14->Bit 15 321 322 #define mwHost20_USBSTS_PeriodicStatus_Rd() (mwHost20Bit_Rd_Port3(0x15,BIT6)) //Bit 14 323 324 // #define mwHost20_USBSTS_Reclamation_Rd() (mwHost20Bit_Rd(0x14,BIT13)) //Bit 13 325 326 // #define mwHost20_USBSTS_HCHalted_Rd() (mwHost20Bit_Rd(0x14,BIT12)) //Bit 12 327 328 #define mwHost20_USBSTS_IntOnAsyncAdvance_Rd() (mwHost20Bit_Rd_Port3(0x14,BIT5)) //Bit 5 329 #define mwHost20_USBSTS_IntOnAsyncAdvance_Set() (mwHost20Bit_Set_Port3(0x14,BIT5)) //Bit 5 330 331 #define mwHost20_USBSTS_SystemError_Rd() (mwHost20Bit_Rd_Port3(0x14,BIT4) ) //Bit 4 332 #define mwHost20_USBSTS_SystemError_Set() (mwHost20Bit_Set_Port3(0x14,BIT4)) //Bit 4 333 334 #define mwHost20_USBSTS_FrameRollover_Rd() (mwHost20Bit_Rd_Port3(0x14,BIT3)) //Bit 3 335 #define mwHost20_USBSTS_FrameRollover_Set() (mwHost20Bit_Set_Port3(0x14,BIT3)) //Bit 3 336 337 #define mwHost20_USBSTS_PortChangeDetect_Rd() (mwHost20Bit_Rd_Port3(0x14,BIT2)) //Bit 2 338 #define mwHost20_USBSTS_PortChangeDetect_Set() (mwHost20Bit_Set_Port3(0x14,BIT2)) //Bit 2 339 340 #define mwHost20_USBSTS_USBError_Rd() (mwHost20Bit_Rd_Port3(0x14,BIT1)) //Bit 1 341 #define mwHost20_USBSTS_USBError_Set() (mwHost20Bit_Set_Port3(0x14,BIT1)) //Bit 1 342 343 #define mwHost20_USBSTS_CompletionOfTransaction_Rd() (mwHost20Bit_Rd_Port3(0x14,BIT0)) //Bit 0 344 #define mwHost20_USBSTS_CompletionOfTransaction_Set() (mwHost20Bit_Set_Port3(0x14,BIT0)) //Bit 0 345 346 //<6>.0x018(USBINTR - USB Interrupt Enable Register) 347 #define mwHost20_USBINTR_Rd() (mwHost20Port_Port3(0x18)) 348 #define mwHost20_USBINTR_Set(bValue) mwHost20Port_wr_Port3(0x18,bValue) 349 350 #define mwHost20_USBINTR_IntOnAsyncAdvance_Rd() (mwHost20Bit_Rd_Port3(0x18,BIT5) ) //Bit 5 351 #define mwHost20_USBINTR_IntOnAsyncAdvance_Set() (mwHost20Bit_Set_Port3(0x18,BIT5)) //Bit 5 352 #define mwHost20_USBINTR_IntOnAsyncAdvance_Clr() (mwHost20Bit_Clr_Port3(0x18,BIT5)) //Bit 5 353 354 #define mwHost20_USBINTR_SystemError_Rd() (mwHost20Bit_Rd_Port3(0x18,BIT4)) //Bit 4 355 #define mwHost20_USBINTR_SystemError_Set() (mwHost20Bit_Set_Port3(0x18,BIT4)) //Bit 4 356 #define mwHost20_USBINTR_SystemError_Clr() (mwHost20Bit_Clr_Port3(0x18,BIT4)) //Bit 4 357 358 #define mwHost20_USBINTR_FrameRollover_Rd() (mwHost20Bit_Rd_Port3(0x18,BIT3) ) //Bit 3 359 #define mwHost20_USBINTR_FrameRollover_Set() (mwHost20Bit_Set_Port3(0x18,BIT3)) //Bit 3 360 #define mwHost20_USBINTR_FrameRollover_Clr() (mwHost20Bit_Clr_Port3(0x18,BIT3)) //Bit 3 361 362 #define mwHost20_USBINTR_PortChangeDetect_Rd() (mwHost20Bit_Rd_Port3(0x18,BIT2) ) //Bit 2 363 #define mwHost20_USBINTR_PortChangeDetect_Set() (mwHost20Bit_Set_Port3(0x18,BIT2)) //Bit 2 364 #define mwHost20_USBINTR_PortChangeDetect_Clr() (mwHost20Bit_Clr_Port3(0x18,BIT2)) //Bit 2 365 366 #define mwHost20_USBINTR_USBError_Rd() (mwHost20Bit_Rd_Port3(0x18,BIT1) ) //Bit 1 367 #define mwHost20_USBINTR_USBError_Set() (mwHost20Bit_Set_Port3(0x18,BIT1)) //Bit 1 368 #define mwHost20_USBINTR_USBError_Clr() (mwHost20Bit_Clr_Port3(0x18,BIT1)) //Bit 1 369 370 #define mwHost20_USBINTR_CompletionOfTransaction_Rd() (mwHost20Bit_Rd_Port3(0x18,BIT0) ) //Bit 0 371 #define mwHost20_USBINTR_CompletionOfTransaction_Set() (mwHost20Bit_Set_Port3(0x18,BIT0)) //Bit 0 372 #define mwHost20_USBINTR_CompletionOfTransaction_Clr() (mwHost20Bit_Clr_Port3(0x18,BIT0)) //Bit 0 373 374 #define HOST20_USBINTR_IntOnAsyncAdvance 0x20 375 #define HOST20_USBINTR_SystemError 0x10 376 #define HOST20_USBINTR_FrameRollover 0x08 377 #define HOST20_USBINTR_PortChangeDetect 0x04 378 #define HOST20_USBINTR_USBError 0x02 379 #define HOST20_USBINTR_CompletionOfTransaction 0x01 380 381 //<7>.0x01C(FRINDEX - Frame Index Register (Address = 01Ch)) 382 #define mwHost20_FrameIndex_Rd() (mwHost20Port_Port3(0x1C)&0x00001FFF) //Only Read Bit0~Bit12(Skip Bit 13) 383 //#define mwHost20_FrameIndex14Bit_Rd() (mwHost20Port(0x1C)&0x00003FFF) //Only Read Bit0~Bit12(Skip Bit 13) 384 //#define mwHost20_FrameIndex_Set(wValue) (mwHost20Port(0x1C)=wValue) 385 386 //<8>.0x024(PERIODICLISTBASE - Periodic Frame List Base Address Register (Address = 024h)) 387 //#define mwHost20_PeriodicBaseAddr_Rd() (mwHost20Port(0x24)) 388 #define mwHost20_PeriodicBaseAddr_Set(wValue) USB_Write_REG32_Port3(0x24,wValue) 389 390 //<9>.0x028(ASYNCLISTADDR - Current Asynchronous List Address Register (Address = 028h)) 391 //#define mwHost20_CurrentAsynchronousAddr_Rd() (mwHost20Port(0x28) ) 392 #define mwHost20_CurrentAsynchronousAddr_Set(wValue) USB_Write_REG32_Port3(0x28,wValue) 393 394 //<10>.0x030(PORTSC - Port Status and Control Register(Address = 030h)) 395 #define mwHost20_PORTSC_Rd() mwHost20Port_Port3(0x30) 396 397 // #define mwHost20_PORTSC_LineStatus_Rd() ((mwHost20Port(0x30)>>10)&0x00000003) 398 399 #define mwHost20_PORTSC_PortReset_Rd() mwHost20Bit_Rd_Port3(0x31,BIT0) 400 #define mwHost20_PORTSC_PortReset_Set() mwHost20Bit_Set_Port3(0x31,BIT0) 401 #define mwHost20_PORTSC_PortReset_Clr() mwHost20Bit_Clr_Port3(0x31,BIT0) 402 403 #define mwHost20_PORTSC_ForceSuspend_Rd() mwHost20Bit_Rd_Port3(0x30,BIT7) 404 #define mwHost20_PORTSC_ForceSuspend_Set() mwHost20Bit_Set_Port3(0x30,BIT7) 405 406 #define mwHost20_PORTSC_ForceResume_Rd() mwHost20Bit_Rd_Port3(0x30,BIT6) 407 #define mwHost20_PORTSC_ForceResume_Set() mwHost20Bit_Set_Port3(0x30,BIT6) 408 #define mwHost20_PORTSC_ForceResume_Clr() mwHost20Bit_Clr_Port3(0x30,BIT6) 409 410 #define mwHost20_PORTSC_EnableDisableChange_Rd() mwHost20Bit_Rd_Port3(0x30,BIT3) 411 #define mwHost20_PORTSC_EnableDisableChange_Set() mwHost20Bit_Set_Port3(0x30,BIT3) 412 413 #define mwHost20_PORTSC_EnableDisable_Rd() mwHost20Bit_Rd_Port3(0x30,BIT2) 414 #define mwHost20_PORTSC_EnableDisable_Set() mwHost20Bit_Set_Port3(0x30,BIT2) 415 #define mwHost20_PORTSC_EnableDisable_Clr() mwHost20Bit_Clr_Port3(0x30,BIT2) 416 #define mwHost20_PORTSC_EnableDisable_Write_0() (mwHost20Port_Port3(0x30)=0x00) 417 418 419 #define mwHost20_PORTSC_ConnectChange_Rd() mwHost20Bit_Rd_Port3(0x30,BIT1) 420 #define mwHost20_PORTSC_ConnectChange_Set() mwHost20Bit_Set_Port3(0x30,BIT1) 421 422 #define mwHost20_PORTSC_ConnectStatus_Rd() mwHost20Bit_Rd_Port3(0x30,BIT0) 423 424 425 426 //<10>.0x034(Misc. Register(Address = 034h)) 427 #define mwHost20_Misc_EOF1Time_Set(bValue) mwHost20Port_wr_Port3(0x34, ((mwHost20Port_Port3(0x34)&0xF3)|(((U8)(bValue))<<2)) ) //Bit 2~3 428 429 //<10>.0x034(Misc. Register(Address = 40h)) 430 #define mwHost20_Control_LineStatus_Rd() (mwHost20Port_Port3(0x40)& BIT11) 431 #define mwHost20_Control_LineStatus_Set() (mwHost20Bit_Set_Port3(0x40,BIT11)) 432 #define mwHost20_Control_LineStatus_Clr() (mwHost20Bit_Clr_Port3(0x40,BIT11)) 433 434 #define mwOTG20_Control_HOST_SPD_TYP_Rd() ((mwHost20Port_Port3(0x41)>>1)&0x03) 435 436 #define mwHost20_Control_ForceFullSpeed_Rd() (mwHost20Port_Port3(0x40)& BIT7) 437 #define mwHost20_Control_ForceFullSpeed_Set() (mwHost20Bit_Set_Port3(0x40,BIT7)) 438 #define mwHost20_Control_ForceFullSpeed_Clr() (mwHost20Bit_Clr_Port3(0x40,BIT7)) 439 440 #define mwHost20_Control_ForceHighSpeed_Rd() (mwHost20Port_Port3(0x40)& BIT6) 441 #define mwHost20_Control_ForceHighSpeed_Set() (mwHost20Bit_Set_Port3(0x40,BIT6)) 442 #define mwHost20_Control_ForceHighSpeed_Clr() (mwHost20Bit_Clr_Port3(0x40,BIT6)) 443 444 #define mwOTG20_Control_Phy_Reset_Set() (mwHost20Bit_Set_Port3(0x40,BIT5)) 445 #define mwOTG20_Control_Phy_Reset_Clr() (mwHost20Bit_Clr_Port3(0x40,BIT5)) 446 447 #define mwOTG20_Control_Half_Speed() (mwHost20Bit_Set_Port3(0x40,BIT2)) 448 449 // #define mwHost20_Control_711MA_FS_Issue_Solve() (mwHost20Bit_Set(0x40,BIT12)) //0x40 Bit-12 450 451 #ifndef VA2PA 452 #if defined(CPU_TYPE_ARM) 453 #define VA2PA(addr) MsOS_VA2PA((U32)addr) 454 #else 455 #define VA2PA(addr) ((void *)(((U32)addr) & 0x1fffffff)) 456 #endif 457 #endif 458 459 #if defined(CPU_TYPE_ARM) 460 #define VirtoPhyAddr(x) MsOS_VA2PA((U32)x) 461 #define PhytoVirAddr(x) MsOS_PA2KSEG1((U32)x) 462 #define PhytoCacheAddr(x) MsOS_PA2KSEG0((U32)x) 463 #else 464 #define VirtoPhyAddr(x) (x) 465 #define PhytoVirAddr(x) (x) 466 #define PhytoCacheAddr(x) (x) 467 #endif 468 469 #define flib_Host20_Allocate_QHD_Macro(x,y,z,w,u,v) \ 470 { x->bType=y; \ 471 x->bDeviceAddress=z; \ 472 x->bHeadOfReclamationListFlag=w; \ 473 x->bEdNumber=u; \ 474 x->bMaxPacketSize=v; } 475 #if 0 476 #define flib_Host20_Allocate_QHD_Port3(x,y,z,w,u,v) \ 477 { \ 478 flib_Host20_Allocate_QHD_Macro(x,y,z,w,u,v) ; \ 479 flib_Host20_Allocate_QHD1_Port3(x); } 480 #endif 481 //=================== 3.Structure Definition ============================================================= 482 //======================================================================================================== 483 484 //<3.1>iTD Structure Definition**************************************** 485 #define Host20_Preiodic_Frame_List_MAX 256 486 //<3.1>iTD Structure Definition**************************************** 487 typedef struct { 488 489 //<1>.Next_Link_Pointer Word 490 U32 bTerminal:1; 491 U32 bType:2; 492 U32 bReserved:2; 493 U32 bLinkPointer:27; 494 } Periodic_Frame_List_Cell_Structure; 495 496 497 typedef struct { 498 499 Periodic_Frame_List_Cell_Structure sCell[Host20_Preiodic_Frame_List_MAX]; 500 501 } Periodic_Frame_List_Structure; 502 503 //<3.2>qTD Structure Definition**************************************** 504 typedef struct _BufferPointer 505 { 506 U8 Byte0; 507 U8 Byte1; 508 U8 Byte2; 509 U8 Byte3; 510 }BufferPointer_Struct; 511 512 typedef struct _qTD { 513 514 //<1>.Next_qTD_Pointer Word 515 U32 bTerminate:1; 516 U32 bReserve_1:4; 517 U32 bNextQTDPointer:27; 518 519 //<2>.Alternate Next qTD Word 520 U32 bAlternateTerminate:1; 521 U32 bReserve_2:4; 522 U32 bAlternateQTDPointer:27; 523 524 //<3>.Status Word 525 U32 bStatus_PingState:1; 526 U32 bStatus_SplitState:1; 527 U32 bStatus_MissMicroFrame:1; 528 U32 bStatus_Transaction_Err:1; 529 U32 bStatus_Babble:1; 530 U32 bStatus_Buffer_Err:1; 531 U32 bStatus_Halted:1; 532 U32 bStatus_Active:1; 533 534 U32 bPID:2; 535 U32 bErrorCounter:2; 536 U32 CurrentPage:3; 537 U32 bInterruptOnComplete:1; 538 U32 bTotalBytes:15; 539 U32 bDataToggle:1; 540 541 542 //<4>.Buffer Pointer Word Array 543 U32 ArrayBufferPointer_Word[5]; 544 } qTD_Structure; 545 546 #define HOST20_qTD_PID_OUT 0x00 547 #define HOST20_qTD_PID_IN 0x01 548 #define HOST20_qTD_PID_SETUP 0x02 549 550 551 #define HOST20_qTD_STATUS_Active 0x80 552 #define HOST20_qTD_STATUS_Halted 0x40 553 #define HOST20_qTD_STATUS_BufferError 0x20 554 #define HOST20_qTD_STATUS_Babble 0x10 555 #define HOST20_qTD_STATUS_TransactionError 0x08 556 #define HOST20_qTD_STATUS_MissMicroFrame 0x04 557 #define HOST20_qTD_STATUS_Split 0x02 558 #define HOST20_qTD_STATUS_Ping 0x01 559 560 561 //<3.3>qHD Structure Definition**************************************** 562 typedef struct _qHD { 563 564 //<1>.Next_qHD_Pointer Word 565 U32 bTerminate:1; 566 U32 bType:2; 567 U32 bReserve_1:2; 568 U32 bNextQHDPointer:27; 569 570 //<2>.qHD_2 Word 571 U32 bDeviceAddress:7; 572 U32 bInactiveOnNextTransaction:1; 573 U32 bEdNumber:4; 574 U32 bEdSpeed:2; 575 U32 bDataToggleControl:1; 576 U32 bHeadOfReclamationListFlag:1; 577 U32 bMaxPacketSize:11; 578 U32 bControlEdFlag:1; 579 U32 bNakCounter:4; 580 581 //<3>.qHD_3 Word 582 U32 bInterruptScheduleMask:8; 583 U32 bSplitTransactionMask:8; 584 U32 bHubAddr:7; 585 U32 bPortNumber:7; 586 U32 bHighBandwidth:2; 587 588 //<4>.Overlay_CurrentqTD 589 U32 bOverlay_CurrentqTD; 590 591 //<5>.Overlay_NextqTD 592 U32 bOverlay_NextTerminate:1; 593 U32 bOverlay_Reserve2:4; 594 U32 bOverlay_NextqTD:27; 595 596 //<6>.Overlay_AlternateNextqTD 597 U32 bOverlay_AlternateNextTerminate:1; 598 U32 bOverlay_NanCnt:4; 599 U32 bOverlay_AlternateqTD:27; 600 601 //<7>.Overlay_TotalBytes 602 U32 bOverlay_Status:8; 603 U32 bOverlay_PID:2; 604 U32 bOverlay_ErrorCounter:2; 605 U32 bOverlay_C_Page:3; 606 U32 bOverlay_InterruptOnComplete:1; 607 U32 bOverlay_TotalBytes:15; 608 U32 bOverlay_Direction:1; 609 610 //<8>.Overlay_BufferPointer0 611 U32 bOverlay_CurrentOffset:12; 612 U32 bOverlay_BufferPointer_0:20; 613 614 //<9>.Overlay_BufferPointer1 615 U32 bOverlay_C_Prog_Mask:8; 616 U32 bOverlay_Reserve3:4; 617 U32 bOverlay_BufferPointer_1:20; 618 619 //<10>.Overlay_BufferPointer2 620 U32 bOverlay_FrameTag:5; 621 U32 bOverlay_S_Bytes:7; 622 U32 bOverlay_BufferPointer_2:20; 623 624 //<11>.Overlay_BufferPointer3 625 U32 bOverlay_Reserve4:12; 626 U32 bOverlay_BufferPointer_3:20; 627 628 //<12>.Overlay_BufferPointer4 629 U32 bOverlay_Reserve5:12; 630 U32 bOverlay_BufferPointer_4:20; 631 632 } qHD_Structure; 633 634 #define HOST20_HD_Type_iTD 0x00 635 #define HOST20_HD_Type_QH 0x01 636 #define HOST20_HD_Type_siTD 0x02 637 #define HOST20_HD_Type_FSTN 0x03 638 639 //<3.4>.Test Condition Definition**************************************** 640 641 642 typedef struct { 643 644 UINT8 bStructureEnable; //Enable = 0x66 Disable=>Others 645 UINT8 bInterruptThreshod; //01,02,04,08,10,20,40 646 UINT8 bAsynchronousParkMode; //00=>Disable,01=>Enable 647 UINT8 bAsynchronousParkModeCounter; //01,02,03 648 UINT8 bFrameSize; //00,01,02 649 650 } Host20_Init_Condition_Structure; 651 652 653 #define HOST20_FrameSize_1024 0x00 654 #define HOST20_FrameSize_512 0x01 655 #define HOST20_FrameSize_256 0x02 656 657 658 //<3.5>.Host20's Attach Device Info Structure**************************************** 659 660 //OTGHost Device Structure 661 typedef struct 662 { 663 UINT8 bDEVICE_LENGTH; // bLength 664 UINT8 bDT_DEVICE; // bDescriptorType 665 UINT8 bVerLowByte; // bcdUSB 666 UINT8 bVerHighByte; 667 668 UINT8 bDeviceClass; // bDeviceClass 669 UINT8 bDeviceSubClass; // bDeviceSubClas; 670 UINT8 bDeviceProtocol; // bDeviceProtocol 671 UINT8 bEP0MAXPACKETSIZE; // bMaxPacketSize0 672 673 UINT8 bVIDLowByte; // idVendor 674 UINT8 bVIDHighByte; 675 UINT8 bPIDLowByte; // idProduct 676 UINT8 bPIDHighByte; 677 UINT8 bRNumLowByte; // bcdDeviceReleaseNumber 678 UINT8 bRNumHighByte; 679 680 UINT8 bManufacturer; // iManufacturer 681 UINT8 bProduct; // iProduct 682 UINT8 bSerialNumber; // iSerialNumber 683 UINT8 bCONFIGURATION_NUMBER; // bNumConfigurations 684 }OTGH_Descriptor_Device_Struct; 685 686 687 //<3.6>.OTGHost Configuration Structure => Only Support 2 Configuration / 5 Interface / 1 Class / 5 Endpoint /1 OTG 688 689 #define HOST20_CONFIGURATION_NUM_MAX 0X02 690 #define HOST20_INTERFACE_NUM_MAX 0X05 691 #define HOST20_ENDPOINT_NUM_MAX 0X05 692 #define HOST20_CLASS_NUM_MAX 0x01 693 694 695 #define HOST20_CONFIGURATION_LENGTH 0X09 696 #define HOST20_INTERFACE_LENGTH 0X09 697 #define HOST20_ENDPOINT_LENGTHX 0X07 698 #define HOST20_CLASS_LENGTHX 0X09 699 700 typedef struct 701 { 702 703 //<3>.Define for ED-OTG 704 UINT8 bED_OTG_Length; 705 UINT8 bED_OTG_bDescriptorType; 706 UINT8 bED_OTG_bAttributes; 707 708 709 }OTGH_Descriptor_OTG_Struct; 710 711 typedef struct 712 { 713 //<3>.Define for ED-1 714 UINT8 bED_Length; 715 UINT8 bED_bDescriptorType; 716 UINT8 bED_EndpointAddress; 717 UINT8 bED_bmAttributes; 718 UINT8 bED_wMaxPacketSizeLowByte; 719 UINT8 bED_wMaxPacketSizeHighByte; 720 UINT8 bED_Interval; 721 722 }OTGH_Descriptor_EndPoint_Struct; 723 724 725 typedef struct 726 { 727 728 UINT8 bClass_LENGTH; 729 UINT8 bClaNumberss; 730 UINT8 bClassVerLowByte; 731 UINT8 bClassVerHighByte; 732 UINT8 bCityNumber; 733 UINT8 bFollowDescriptorNum; 734 UINT8 bReport; 735 UINT8 bLengthLowByte; 736 UINT8 bLengthHighByte; 737 738 }OTGH_Descriptor_Class_Struct; 739 740 741 742 743 744 745 typedef struct 746 { 747 748 //<2>.Define for Interface-1 749 UINT8 bINTERFACE_LENGTH; // bLength 750 UINT8 bDT_INTERFACE; // bDescriptorType INTERFACE 751 UINT8 bInterfaceNumber; // bInterfaceNumber 752 UINT8 bAlternateSetting; // bAlternateSetting 753 UINT8 bEP_NUMBER; // bNumEndpoints(excluding endpoint zero) 754 UINT8 bInterfaceClass; // bInterfaceClass 755 UINT8 bInterfaceSubClass; // bInterfaceSubClass 756 UINT8 bInterfaceProtocol; // bInterfaceProtocol 757 UINT8 bInterface; // iInterface 758 759 OTGH_Descriptor_Class_Struct sClass[HOST20_CLASS_NUM_MAX]; 760 OTGH_Descriptor_EndPoint_Struct sED[HOST20_ENDPOINT_NUM_MAX]; 761 762 763 764 }OTGH_Descriptor_Interface_Struct; 765 766 767 768 typedef struct 769 { 770 771 UINT8 bCONFIG_LENGTH; // bLength 772 UINT8 bDT_CONFIGURATION; // bDescriptorType CONFIGURATION 773 UINT8 bTotalLengthLowByte; // wTotalLength, include all descriptors 774 UINT8 bTotalLengthHighByte; 775 UINT8 bINTERFACE_NUMBER; // bNumInterface 776 UINT8 bConfigurationValue; // bConfigurationValue 777 UINT8 bConfiguration; // iConfiguration 778 UINT8 bAttribute; // bmAttribute 779 UINT8 bMaxPower; // iMaxPower (2mA units) 780 781 OTGH_Descriptor_Interface_Struct sInterface[HOST20_INTERFACE_NUM_MAX]; 782 783 784 }OTGH_Descriptor_Configuration_Only_Struct; 785 786 787 788 //Support Configuration x2 789 // Interface x5 790 // EndPoint x5 791 // OTG X1 792 793 typedef struct 794 { 795 796 //<1>.Basic Information 797 // UINT8 bDeviceOnHub; 798 // UINT8 bOnHubPortNumber; 799 UINT8 bAdd; 800 // UINT8 bConnectStatus; 801 // UINT8 bPortEnableDisableStatus; 802 // UINT8 bSpeed; //0=>Low Speed / 1=>Full Speed / 2 => High Speed 803 // UINT8 bPortReset; 804 // UINT8 bSuspend; 805 // volatile UINT8 bRemoteWakeUpDetected; 806 // UINT8 bSendOK; 807 UINT8 bSendStatusError; 808 809 810 // qTD_Structure *psSendLastqTD; 811 UINT16 bDataBuffer; 812 //<2>.Descriptor Information 813 OTGH_Descriptor_Device_Struct sDD; 814 OTGH_Descriptor_Configuration_Only_Struct saCD[HOST20_CONFIGURATION_NUM_MAX]; 815 OTGH_Descriptor_OTG_Struct sOTG; 816 817 // UINT8 bReportDescriptor[0x74]; 818 UINT8 bStringLanguage[10]; 819 UINT8 bStringManufacture[64]; 820 UINT8 bStringProduct[64]; 821 // UINT8 bStringSerialN[0xFF]; 822 //<3>.For ISO Information 823 // UINT8 bISOTransferEnable; 824 // UINT32 wISOiTDAddress[1024]; 825 826 }Host20_Attach_Device_Structure; 827 828 #define HOST20_Attach_Device_Speed_Full 0x00 829 #define HOST20_Attach_Device_Speed_Low 0x01 830 #define HOST20_Attach_Device_Speed_High 0x02 831 832 //<3.7>.Control Command Structure 833 typedef struct { 834 835 UINT8 bmRequestType; //(In/Out),(Standard...),(Device/Interface...) 836 UINT8 bRequest; //GetStatus ..... 837 UINT8 wValueLow; //Byte2 838 UINT8 wValueHigh; //Byte3 839 UINT8 wIndexLow; //Byte4 840 UINT8 wIndexHigh; //Byte5 841 UINT8 wLengthLow; //Byte6 842 UINT8 wLengthHigh; //Byte7 843 844 845 } Host20_Control_Command_Structure; 846 847 #define HOST20_CONTROL_GetStatus 0x00 848 #define HOST20_CONTROL_ClearFeature 0x01 849 #define HOST20_CONTROL_SetFeature 0x03 850 #define HOST20_CONTROL_SetAddress 0x05 851 #define HOST20_CONTROL_GetDescriptor 0x06 852 #define HOST20_CONTROL_SetDescriptor 0x07 853 #define HOST20_CONTROL_GetConfiguration 0x08 854 #define HOST20_CONTROL_GetInterface 0x0A 855 #define HOST20_CONTROL_SetInterface 0x0B 856 #define HOST20_CONTROL_SyncFrame 0x0C 857 858 859 #define HOST20_HID_GetReport 0x01 860 #define HOST20_HID_GetIdle 0x02 861 #define HOST20_HID_GetProtocol 0x03 862 #define HOST20_HID_SetReport 0x09 863 #define HOST20_HID_SetIdle 0x0A 864 #define HOST20_HID_SetProtocol 0x0B 865 866 867 //<3.8>.BufferPointerArray 868 typedef struct { 869 UINT32 BufferPointerArray[8]; 870 } Host20_BufferPointerArray_Structure; 871 872 873 874 875 876 //=================== 4.Extern Function Definition ======================================================= 877 //======================================================================================================== 878 879 extern BOOLEAN flib_OTGH_Init_Port3(UINT8 wForDevice_B); 880 extern U8 flib_Host20_Close_Port3(void); 881 extern BOOLEAN USB_Hub_Handle_Port3(U8 port) ; 882 extern U8 Usb_Hub_Port_Num_Port3(void); 883 884 //extern UINT8 flib_Host20_ISR(void); 885 extern UINT8 flib_Host20_PortBusReset_Port3(void); 886 extern void flib_Host20_Suspend_Port3(void); 887 extern UINT8 flib_Host20_Issue_Control_Port3 (UINT8 bEdNum,UINT8* pbCmd,UINT16 hwDataSize,UINT8* pbData); 888 extern UINT8 flib_Host20_Issue_Bulk_Port3(UINT8 bArrayListNum,UINT16 hwSize,UINT32,UINT8 bDirection); 889 extern UINT8 flib_Host20_Enumerate_Port3 (UINT8 bNormalEnumerate,UINT8 bAddress); 890 extern UINT8 _flib_Host20_Enumerate_Port3 (UINT8 bNormalEnumerate,UINT8 bAddress); 891 extern UINT8 flib_Host20_Issue_Control_CBI_Port3 (UINT8* pbCmd,UINT16 hwDataSize,UINT8* pbData); 892 893 extern void flib_DumpDeviceDescriptor_Port3 (OTGH_Descriptor_Device_Struct *sDevice); 894 extern void flib_PrintDeviceInfo_Port3 (void); 895 extern void flib_PrintDeviceInfo_ByInput_Port3 (Host20_Attach_Device_Structure *psAttachDevice); 896 extern void flib_Host20_TimerISR_Port3(void); 897 // extern void flib_Host20_TimerEnable(UINT32 wTime_ms); 898 extern void flib_Host20_InitStructure_Port3(void); 899 extern qTD_Structure *flib_Host20_GetStructure_Port3(UINT8 Type); 900 extern void flib_Host20_ReleaseStructure_Port3(U8 Type,U32 pwAddress); 901 extern void flib_Host20_QHD_Control_Init_Port3(void); 902 extern UINT8 flib_Host20_Send_qTD_Port3(qTD_Structure *spHeadqTD ,qHD_Structure *spTempqHD,U16 wTimeOutSec); 903 extern void flib_Host20_Allocate_QHD_Port3(qHD_Structure *psQHTemp,UINT8 bNextType,UINT8 bAddress,UINT8 bHead,UINT8 bEndPt, UINT32 wMaxPacketSize); 904 905 extern UINT8 flib_Host20_Issue_Control_Turbo_Port3 (UINT8 bEdNum,UINT8* pbCmd,UINT32 wDataSize,UINT32 *pwPageAddress,UINT32 wCurrentOffset); 906 extern void flib_Host20_Control_Command_Request_Port3(Host20_Control_Command_Structure *pbCMD,UINT8 bmRequestType_Temp,UINT8 bRequest_Temp,UINT16 wValue_Temp,UINT16 wIndex_Temp,UINT16 wLength_Temp); 907 extern void flib_DumpString_Port3 (UINT8 *pbTemp,UINT8 bSize); 908 extern void flib_Host20_Interrupt_Init_Port3(UINT8 bAddr); 909 extern U8 flib_Host20_Issue_Interrupt_Port3(U32 buf,U32 hwSize); 910 911 extern void flib_Host20_Asynchronous_Enable_Port3(void); 912 extern void flib_Host20_Asynchronous_Disable_Port3(void); 913 914 extern UINT8 flib_OTGH_Checking_RemoteWakeUp_Port3(void); 915 extern UINT8 flib_OTGH_RemoteWakeEnable_Port3(void); 916 extern void flib_Host20_StopRun_Setting_Port3(UINT8 bOption); 917 // extern void flib_Host20_Asynchronous_Setting(UINT8 bOption); 918 extern void flib_Host20_Periodic_Setting_Port3(UINT8 bOption); 919 // extern void flib_Host20_TimerEnable_UnLock(UINT32 wTime_Tick); 920 // extern void flib_Host20_TimerDisable_UnLock(void); 921 922 extern void flib_Host20_RemoteWakeUp_Processing_Port3(void); 923 924 // extern void SetPointer_Port3(UINT16 addr, UINT32 val); 925 // extern void SetValue(UINT16 addr, UINT8 StartBit, UINT8 BitNum, UINT8 val); 926 void FillBufferArray_Port3(qTD_Structure xdata *spTempqTD,UINT16 bpDataPage); 927 //void SetPointer_Port3( qHD_Structure xdata *qhd, UINT32 val); 928 qTD_Structure *GetPointer_Port3(UINT8* ptr); 929 void SetPointer_Port3( UINT8 *ptr, UINT32 val); 930 931 932 //=================== 5.Call Extern Function Definition ======================================================= 933 //======================================================================================================== 934 935 extern void flib_Debug_LED_Init(void); 936 extern void flib_Debug_LED_On_All(void); 937 extern void flib_Debug_LED_Off_All(void); 938 939 940 //=================== 6.Extern Variable Definition ======================================================= 941 //======================================================================================================== 942 943 extern code UINT8 OTGH_GETDESCRIPTOR_DEVICE_PORT3[]; 944 extern code UINT8 OTGH_GETDESCRIPTOR_CONFIG_PORT3[]; 945 extern code UINT8 OTGH_SETADDRESS_PORT3[]; 946 extern code UINT8 OTGH_SETCONFIGURATION_PORT3[]; 947 extern code UINT8 OTGH_GETDESCRIPTOR_OTG[]; 948 extern code UINT8 OTGH_SET_FEATURE_OTG[]; 949 extern code UINT8 OTGH_SETDESCRIPTOR_DEVICE[]; 950 extern code UINT8 OTGH_GETDESCRIPTOR_STR70[]; 951 extern code UINT8 OTGH_SETDESCRIPTOR_STR70[]; 952 extern code UINT8 OTGH_GETDESCRIPTOR_STR80[]; 953 extern code UINT8 OTGH_SETDESCRIPTOR_STR80[]; 954 extern code UINT8 waIntervalMap[]; 955 // extern volatile UINT32 wOTG_Timer_Counter; 956 // extern qHD_Structure *psHost20_qHD_List_Control[3]; 957 // extern qHD_Structure *psHost20_qHD_List_Bulk[3]; 958 extern qHD_Structure *pHost20_qHD_List_Control0_Port3; 959 extern qHD_Structure *pHost20_qHD_List_Bulk0_Port3; 960 extern qHD_Structure *pHost20_qHD_List_Control1_Port3; 961 extern qHD_Structure *pHost20_qHD_List_Bulk1_Port3; 962 963 extern UINT8 Host20_qTD_Manage_Port3[Host20_qTD_MAX]; //1=>Free 2=>used 964 // extern UINT8 Host20_iTD_Manage[Host20_iTD_MAX]; //1=>Free 2=>used 965 //extern UINT8 Host20_DataPage_Manage[Host20_Page_MAX]; //1=>Free 2=>used 966 967 extern Host20_Init_Condition_Structure sInitCondition; 968 extern Host20_Attach_Device_Structure xdata *psAttachDevice_Port3; 969 extern volatile UINT32 wOTG_Timer_Counter; 970 // extern Periodic_Frame_List_Structure *psHost20_FramList; 971 // extern volatile UINT32 gwLastiTDSendOK; 972 973 // extern Host20_ISO_FixBufferMode_Structure sISOFixBufferMode; 974 // extern UINT8 bForceSpeed;//0=>All Clear 1=>Full Speed 2=>High Speed 975 976 977 extern Host20_Attach_Device_Structure *psDevice_AP; 978 // extern UINT32 Host20_STRUCTURE_qHD_BASE_ADDRESS,Host20_STRUCTURE_qTD_BASE_ADDRESS; 979 //extern UINT32 Host20_STRUCTURE_Preiodic_Frame_List_BASE_ADDRESS,Host20_STRUCTURE_iTD_BASE_ADDRESS; 980 981 // Write dirty cache lines to memory and invalidate the cache entries 982 // for the given address range. 983 // Aeon2 does not have an explicit invalidate memory instruction, so use 984 // flush are necessary. 985 //#ifdef NOS_MIPS 986 #if defined(CPU_TYPE_MIPS) || defined(CPU_TYPE_ARM) 987 void mhal_dcache_flush(unsigned long u32Base, unsigned long u32Size ); 988 #define MY_HAL_DCACHE_FLUSH mhal_dcache_flush 989 #else //NOS_MIPS 990 #ifdef __AEONR2__ 991 #if 0 992 #define MY_HAL_DCACHE_FLUSH( _base_ , _size_ ) \ 993 CYG_MACRO_START \ 994 U32 size_once = _size_, base_once = _base_; \ 995 U32 addr, end; \ 996 end = base_once + ((size_once < HAL_DCACHE_SIZE) ? \ 997 size_once : HAL_DCACHE_SIZE); \ 998 for (addr = end; addr >= base_once; addr -= HAL_DCACHE_LINE_SIZE) { \ 999 __asm__ __volatile__( \ 1000 "l.flush_line 0(%0), 0\n" /* way 0 */ \ 1001 "l.flush_line 0(%0), 1\n" /* way 1 */ \ 1002 "l.flush_line 0(%0), 2\n" /* way 2 */ \ 1003 "l.flush_line 0(%0), 3\n" /* way 3 */ \ 1004 "l.invalidate_line 0(%0), 0\n" /* way 0 */ \ 1005 "l.invalidate_line 0(%0), 1\n" /* way 1 */ \ 1006 "l.invalidate_line 0(%0), 2\n" /* way 2 */ \ 1007 "l.invalidate_line 0(%0), 3\n" /* way 3 */ \ 1008 : : "r"(addr) \ 1009 ); \ 1010 } \ 1011 __asm__ __volatile__( "l.syncwritebuffer\n" ); \ 1012 CYG_MACRO_END 1013 #else //Janus 1014 void mhal_dcache_flush(unsigned long u32Base, unsigned long u32Size ); 1015 #define MY_HAL_DCACHE_FLUSH mhal_dcache_flush 1016 #endif 1017 #else 1018 #define MY_HAL_DCACHE_FLUSH( _base_ , _size_ ) \ 1019 CYG_MACRO_START \ 1020 U32 size_once = _size_, base_once = _base_; \ 1021 U32 addr, end; \ 1022 end = base_once + ((size_once < HAL_DCACHE_SIZE) ? \ 1023 size_once : HAL_DCACHE_SIZE); \ 1024 for (addr = end; addr >= base_once; addr -= HAL_DCACHE_LINE_SIZE) { \ 1025 __asm__ __volatile__( \ 1026 "l.flush_line 0(%0), 0\n" /* way 0 */ \ 1027 "l.flush_line 0(%0), 1\n" /* way 1 */ \ 1028 "l.invalidate_line 0(%0), 0\n" /* way 0 */ \ 1029 "l.invalidate_line 0(%0), 1\n" /* way 1 */ \ 1030 : : "r"(addr) \ 1031 ); \ 1032 } \ 1033 __asm__ __volatile__( "l.syncwritebuffer\n" ); \ 1034 CYG_MACRO_END 1035 #endif 1036 #endif 1037 1038 1039 1040 1041 #endif //LIB_HOST200__H 1042 1043 1044 1045 1046 1047