1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. 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If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 /////////////////////////////////////////////////////////////////////////////// 79 // 80 // File name: Lib_Host20.H 81 // Version: 1.0 82 // Date: 2004/12/08 83 // 84 // Author: Bruce 85 // Phone: (03) 578-7888 86 // Company: Faraday Tech. Corp. 87 // 88 // Description: 1.EHCI Data Structure 89 // 2.EHCI Register 90 // 3.Others 91 /////////////////////////////////////////////////////////////////////////////// 92 #ifndef LIB_HOST200__H 93 #define LIB_HOST200__H 94 95 #include "../drvUsbHostConfig.h" 96 #include "MsCommon.h" 97 #include "MsIRQ.h" 98 #include "MsOS.h" 99 #if 0 100 typedef unsigned char UINT8; // 1 byte 101 /// data type unsigned short, data length 2 byte 102 typedef unsigned int UINT16; // 2 bytes 103 /// data type unsigned int, data length 4 byte 104 typedef unsigned long UINT32; // 4 bytes 105 /// data type signed char, data length 1 byte 106 #endif 107 108 #ifndef ATV_SERISE_USE 109 #ifdef CERAMAL_SERISE_USE 110 111 #else 112 113 #endif 114 #define USBDELAY(x) MsOS_DelayTask(x) 115 #else 116 #define BOOLEAN UINT8 117 #define INT32U UINT32 118 #define INT16U UINT16 119 #define INT8U UINT8 120 #endif 121 122 extern void USB_Write_REG32(UINT8 addr,UINT32 val); 123 extern U32 USB_BUFFER_START_ADR_4K_ALIGN_Var; 124 125 //=================== 1.Condition Definition ============================================================ 126 //======================================================================================================== 127 128 129 #define FUSBH200_HOST_ONLY 130 131 132 #define Host20_Debug_Info 0x01 133 #define IRQ_USB_Host20 40 134 #define Host20_Set_Address 0x03 135 136 //Host Configuration 137 #define Host20_QHD_Nat_Counter 0x00//Temp Solution from 15 to 0 //Bit28~31 138 //#define Host20_EOF1Time 0x00//For Full Speed Device 139 #define Host20_EOF1Time 0x03//For High Speed Device 140 141 //=================== 2.Variable Definition ============================================================ 142 //======================================================================================================== 143 #define HOST20_OK 0x00 144 #define HOST20_FAIL 0x01 145 #define HOST20_FATAL 0x02 146 #define HOST20_DEVICE_STALL 0x03 147 #define HOST20_TRANSACTION_ERROR 0x04 148 //---------------------------------- 149 #define USB_OK 0 150 #define USB_DISCONNECTED 1 151 #define USB_TIMEOUT 2 152 #define USB_TRANS_ERROR 3 153 #define USB_EJECT 4 154 #define USB_INIT_FAIL 5 155 156 //**************************** 157 // Data Structure Allocation 158 //**************************** 159 // 0x3000000~0x3001000 =>qHD 160 // 0x3001000~0x3002000 =>qTD 161 // 0x3002000~0x3003000 =>iTD 162 // 163 164 165 // #if (USB_BUFFER_START_ADR_4K_ALIGN % 4096 != 0) 166 // #error USB_BUFFER_START_ADR_4K_ALIGN needs 4K-byte alignment 167 // #endif 168 169 170 171 172 #define Host20_qHD_SIZE 0x40//(48bytes), for alignment 173 #define Host20_qHD_MAX 10//(10 ) 174 175 #define Host20_qTD_SIZE 0x20//(32bytes) 176 #define Host20_qTD_MAX 0x10//(50 ) 177 178 // Control Transfer Data stage buffer size 179 #define CONTROL_DMA_BUF_LEN 0x1000 180 #define CONTROL_BUF_LEN 0x1000 181 182 183 184 // #define Host20_STRUCTURE_iTD_BASE_ADDRESS (Host20_STRUCTURE_BASE_ADDRESS+0x10000)//(DRAM=48M) 185 // #define Host20_iTD_SIZE 0x40//(64bytes) 186 // #define Host20_iTD_MAX 1024//(10 ) 187 188 189 190 191 #define Host20_MEM_TYPE_qTD 0x00 192 #define Host20_MEM_TYPE_iTD 0x01 193 #define Host20_MEM_TYPE_4K_BUFFER 0x02 194 #define Host20_MEM_TYPE_siTD 0x03 195 196 197 198 #define Host20_MEM_FREE 0x01 199 #define Host20_MEM_USED 0x02 200 201 202 #if 0 // use the define in DataType.h 203 #define BIT8 0x00000100 204 #define BIT9 0x00000200 205 #define BIT10 0x00000400 206 #define BIT11 0x00000800 207 #define BIT12 0x00001000 208 #define BIT13 0x00002000 209 #define BIT14 0x00004000 210 #define BIT15 0x00008000 211 #endif 212 #define BIT16 0x00010000 213 #define BIT17 0x00020000 214 #define BIT18 0x00040000 215 #define BIT19 0x00080000 216 #define BIT20 0x00100000 217 #define BIT21 0x00200000 218 #define BIT22 0x00400000 219 #define BIT23 0x00800000 220 221 #define BIT24 0x01000000 222 #define BIT25 0x02000000 223 #define BIT26 0x04000000 224 #define BIT27 0x08000000 225 #define BIT28 0x10000000 226 #define BIT29 0x20000000 227 #define BIT30 0x40000000 228 #define BIT31 0x80000000 229 230 231 #define OTGH_Dir_IN 0x01 232 #define OTGH_Dir_Out 0x00 233 #define OTGH_NULL 0x00 234 #define OTGH_ED_ISO 0x01 235 #define OTGH_ED_BULK 0x02 236 #define OTGH_ED_INT 0x03 237 #define OTGH_ED_Control 0x00 238 #define OTGH_FARADAY_TEST_AP 0x10237856 239 #define OTGH_SRP_HNP_Enable 0x03 240 #define OTGH_Remote_Wake_UP 0x00000400 241 #define OTGH_Remote_Wake_UP_INT 0x00000008 242 243 244 unsigned char mwHost20Port(int bOffset); 245 void mwHost20Port_wr(int bOffset, int value); 246 int mwHost20Bit_Rd(int bByte,int wBitNum); 247 void mwHost20Bit_Set(int bByte,int wBitNum); 248 void mwHost20Bit_Clr(int bByte,int wBitNum); 249 250 //=================== 2.Define Register Macro ================================================================ 251 //======================================================================================================== 252 extern U32 gUHC_BASE; 253 //<1>.Macro volatile 254 // #define Host20_BASE_ADDRESS UHC_BASE//0x92500000 255 // #define mwHost20Port(bOffset) *((UINT8 volatile xdata *) ( Host20_BASE_ADDRESS | bOffset)) 256 // #define mwHost20Port(bOffset) *((UINT8 volatile xdata *) ( gUHC_BASE | bOffset)) 257 /// #define mwHost20Port(bOffset) *((U16 volatile *) ( gUHC_BASE | bOffset)) 258 /// #define mwHost20Bit_Rd(bByte,wBitNum) (mwHost20Port(bByte)&wBitNum) 259 /// #define mwHost20Bit_Set(bByte,wBitNum) (mwHost20Port(bByte)|=wBitNum) 260 /// #define mwHost20Bit_Clr(bByte,wBitNum) (mwHost20Port(bByte)&=~wBitNum) 261 #define mwHost20Port_word(bOffset) *((UINT16 volatile *) ( gUHC_BASE | bOffset)) 262 263 //<2>.0x000(Capability Register) 264 //#define mwHost20_HCIVersion_Rd() ((mwHost20Port(0x00)>>16)&0x0000FFFF) 265 //#define mwHost20_CapLength_Rd() (mwHost20Port(0x00)&0x000000FF) 266 267 //<3>.0x004(HCSPARAMS - Structural Parameters) 268 #define mwHost20_NumPorts_Rd() ((mwHost20Port(0x04)&0x0000000F) 269 270 //<4>.0x008(HCCPARAMS - Capability Parameters) 271 #define mbHost20_ProgrammableFrameListFlag_Rd() (mwHost20Bit_Rd(0x08,BIT1)) //Bit 1 272 273 //<4>.0x010(USBCMD - USB Command Register) 274 //#define mwHost20_USBCMD_IntThreshold_Rd() ((mwHost20Port(0x010)>>16)&0x0000FFFF) //Bit 16~23 275 //#define mbHost20_USBCMD_IntThreshold_Set(bValue) (mwHost20Port(0x010)=((mwHost20Port(0x010)&0xFF00FFFF)|(((UINT32)(bValue))<<16)) //Bit 16~23 276 //----->Add "Asynchronous schedule Park mode ENable" 277 //----->Add "ASYNchronous schedule Park mode CouNT" 278 279 //#define mbHost20_USBCMD_ParkMode_Rd() (mwHost20Bit_Rd(0x10,BIT11)>>11) 280 //#define mbHost20_USBCMD_ParkMode_Set() (mwHost20Bit_Set(0x10,BIT11)) 281 //#define mbHost20_USBCMD_ParkMode_Clr() (mwHost20Bit_Clr(0x10,BIT11)) 282 283 #define mbHost20_USBCMD_ParkMode_CNT_Rd() ((mwHost20Port(0x10)>>8)&0x00000003) 284 #define mbHost20_USBCMD_ParkMode_CNT_Set(bValue) (mwHost20Port(0x011)=(mwHost20Port(0x011)&0xFC)|(( (UINT8) bValue )<<8) ) //Bit 8~9 285 286 #define mbHost20_USBCMD_InterruptOnAsync_Rd() (mwHost20Bit_Rd(0x10,BIT6)) //Bit 6 287 #define mbHost20_USBCMD_InterruptOnAsync_Set() (mwHost20Bit_Set(0x10,BIT6)) //Bit 6 288 #define mbHost20_USBCMD_InterruptOnAsync_Clr() (mwHost20Bit_Clr(0x10,BIT6)) //Bit 6 289 290 #define mbHost20_USBCMD_AsynchronousEnable_Rd() (mwHost20Bit_Rd(0x10,BIT5)) //Bit 5 291 #define mbHost20_USBCMD_AsynchronousEnable_Set() (mwHost20Bit_Set(0x10,BIT5)) //Bit 5 292 #define mbHost20_USBCMD_AsynchronousEnable_Clr() (mwHost20Bit_Clr(0x10,BIT5)) //Bit 5 293 294 #define mbHost20_USBCMD_PeriodicEnable_Rd() (mwHost20Bit_Rd(0x10,BIT4) ) //Bit 4 295 #define mbHost20_USBCMD_PeriodicEnable_Set() (mwHost20Bit_Set(0x10,BIT4)) //Bit 4 296 #define mbHost20_USBCMD_PeriodicEnable_Clr() (mwHost20Bit_Clr(0x10,BIT4)) //Bit 4 297 298 #define mbHost20_USBCMD_FrameListSize_Rd() ((mwHost20Port(0x10)>>2)&0x00000003) //Bit 2~3 299 //#define mbHost20_USBCMD_FrameListSize_Set(bValue) ((mwHost20Port(0x10)=((mwHost20Port(0x10)&0xF3)|(((UINT8)(bValue))<<2))) //Bit 2~3 300 #define mbHost20_USBCMD_FrameListSize_Set(bValue) (mwHost20Port_wr(0x10, (mwHost20Port(0x10)&0xF3)|(((UINT8)(bValue))<<2)) ) //Bit 2~3 301 302 #define HOST20_USBCMD_FrameListSize_1024 0x00 303 #define HOST20_USBCMD_FrameListSize_512 0x01 304 #define HOST20_USBCMD_FrameListSize_256 0x02 305 306 #define mbHost20_USBCMD_HCReset_Rd() (mwHost20Bit_Rd(0x10,BIT1)) //Bit 1 307 #define mbHost20_USBCMD_HCReset_Set() (mwHost20Bit_Set(0x10,BIT1)) //Bit 1 308 309 #define mbHost20_USBCMD_RunStop_Rd() (mwHost20Bit_Rd(0x10,BIT0) ) //Bit 0 310 #define mbHost20_USBCMD_RunStop_Set() (mwHost20Bit_Set(0x10,BIT0)) //Bit 0 311 #define mbHost20_USBCMD_RunStop_Clr() (mwHost20Bit_Clr(0x10,BIT0)) //Bit 0 312 313 314 #define HOST20_Enable 0x01 315 #define HOST20_Disable 0x00 316 317 318 319 320 //<5>.0x014(USBSTS - USB Status Register) 321 #define mwHost20_USBSTS_Rd() (mwHost20Port(0x14)) 322 #define mwHost20_USBSTS_Set(wValue) mwHost20Port_wr(0x14,wValue) 323 324 #define mwHost20_USBSTS_AsynchronousStatus_Rd() (mwHost20Bit_Rd(0x15,BIT7)) //14->Bit 15 325 326 #define mwHost20_USBSTS_PeriodicStatus_Rd() (mwHost20Bit_Rd(0x15,BIT6)) //Bit 14 327 328 // #define mwHost20_USBSTS_Reclamation_Rd() (mwHost20Bit_Rd(0x14,BIT13)) //Bit 13 329 330 // #define mwHost20_USBSTS_HCHalted_Rd() (mwHost20Bit_Rd(0x14,BIT12)) //Bit 12 331 332 #define mwHost20_USBSTS_IntOnAsyncAdvance_Rd() (mwHost20Bit_Rd(0x14,BIT5)) //Bit 5 333 #define mwHost20_USBSTS_IntOnAsyncAdvance_Set() (mwHost20Bit_Set(0x14,BIT5)) //Bit 5 334 335 #define mwHost20_USBSTS_SystemError_Rd() (mwHost20Bit_Rd(0x14,BIT4) ) //Bit 4 336 #define mwHost20_USBSTS_SystemError_Set() (mwHost20Bit_Set(0x14,BIT4)) //Bit 4 337 338 #define mwHost20_USBSTS_FrameRollover_Rd() (mwHost20Bit_Rd(0x14,BIT3)) //Bit 3 339 #define mwHost20_USBSTS_FrameRollover_Set() (mwHost20Bit_Set(0x14,BIT3)) //Bit 3 340 341 #define mwHost20_USBSTS_PortChangeDetect_Rd() (mwHost20Bit_Rd(0x14,BIT2)) //Bit 2 342 #define mwHost20_USBSTS_PortChangeDetect_Set() (mwHost20Bit_Set(0x14,BIT2)) //Bit 2 343 344 #define mwHost20_USBSTS_USBError_Rd() (mwHost20Bit_Rd(0x14,BIT1)) //Bit 1 345 #define mwHost20_USBSTS_USBError_Set() (mwHost20Bit_Set(0x14,BIT1)) //Bit 1 346 347 #define mwHost20_USBSTS_CompletionOfTransaction_Rd() (mwHost20Bit_Rd(0x14,BIT0)) //Bit 0 348 #define mwHost20_USBSTS_CompletionOfTransaction_Set() (mwHost20Bit_Set(0x14,BIT0)) //Bit 0 349 350 //<6>.0x018(USBINTR - USB Interrupt Enable Register) 351 #define mwHost20_USBINTR_Rd() (mwHost20Port(0x18)) 352 #define mwHost20_USBINTR_Set(bValue) mwHost20Port_wr(0x18,bValue) 353 354 #define mwHost20_USBINTR_IntOnAsyncAdvance_Rd() (mwHost20Bit_Rd(0x18,BIT5) ) //Bit 5 355 #define mwHost20_USBINTR_IntOnAsyncAdvance_Set() (mwHost20Bit_Set(0x18,BIT5)) //Bit 5 356 #define mwHost20_USBINTR_IntOnAsyncAdvance_Clr() (mwHost20Bit_Clr(0x18,BIT5)) //Bit 5 357 358 #define mwHost20_USBINTR_SystemError_Rd() (mwHost20Bit_Rd(0x18,BIT4)) //Bit 4 359 #define mwHost20_USBINTR_SystemError_Set() (mwHost20Bit_Set(0x18,BIT4)) //Bit 4 360 #define mwHost20_USBINTR_SystemError_Clr() (mwHost20Bit_Clr(0x18,BIT4)) //Bit 4 361 362 #define mwHost20_USBINTR_FrameRollover_Rd() (mwHost20Bit_Rd(0x18,BIT3) ) //Bit 3 363 #define mwHost20_USBINTR_FrameRollover_Set() (mwHost20Bit_Set(0x18,BIT3)) //Bit 3 364 #define mwHost20_USBINTR_FrameRollover_Clr() (mwHost20Bit_Clr(0x18,BIT3)) //Bit 3 365 366 #define mwHost20_USBINTR_PortChangeDetect_Rd() (mwHost20Bit_Rd(0x18,BIT2) ) //Bit 2 367 #define mwHost20_USBINTR_PortChangeDetect_Set() (mwHost20Bit_Set(0x18,BIT2)) //Bit 2 368 #define mwHost20_USBINTR_PortChangeDetect_Clr() (mwHost20Bit_Clr(0x18,BIT2)) //Bit 2 369 370 #define mwHost20_USBINTR_USBError_Rd() (mwHost20Bit_Rd(0x18,BIT1) ) //Bit 1 371 #define mwHost20_USBINTR_USBError_Set() (mwHost20Bit_Set(0x18,BIT1)) //Bit 1 372 #define mwHost20_USBINTR_USBError_Clr() (mwHost20Bit_Clr(0x18,BIT1)) //Bit 1 373 374 #define mwHost20_USBINTR_CompletionOfTransaction_Rd() (mwHost20Bit_Rd(0x18,BIT0) ) //Bit 0 375 #define mwHost20_USBINTR_CompletionOfTransaction_Set() (mwHost20Bit_Set(0x18,BIT0)) //Bit 0 376 #define mwHost20_USBINTR_CompletionOfTransaction_Clr() (mwHost20Bit_Clr(0x18,BIT0)) //Bit 0 377 378 #define HOST20_USBINTR_IntOnAsyncAdvance 0x20 379 #define HOST20_USBINTR_SystemError 0x10 380 #define HOST20_USBINTR_FrameRollover 0x08 381 #define HOST20_USBINTR_PortChangeDetect 0x04 382 #define HOST20_USBINTR_USBError 0x02 383 #define HOST20_USBINTR_CompletionOfTransaction 0x01 384 385 //<7>.0x01C(FRINDEX - Frame Index Register (Address = 01Ch)) 386 #define mwHost20_FrameIndex_Rd() (mwHost20Port(0x1C)&0x1FFF) //Only Read Bit0~Bit12(Skip Bit 13) 387 //#define mwHost20_FrameIndex14Bit_Rd() (mwHost20Port(0x1C)&0x00003FFF) //Only Read Bit0~Bit12(Skip Bit 13) 388 //#define mwHost20_FrameIndex_Set(wValue) (mwHost20Port(0x1C)=wValue) 389 390 //<8>.0x024(PERIODICLISTBASE - Periodic Frame List Base Address Register (Address = 024h)) 391 //#define mwHost20_PeriodicBaseAddr_Rd() (mwHost20Port(0x24)) 392 #define mwHost20_PeriodicBaseAddr_Set(wValue) USB_Write_REG32(0x24,wValue) 393 394 //<9>.0x028(ASYNCLISTADDR - Current Asynchronous List Address Register (Address = 028h)) 395 //#define mwHost20_CurrentAsynchronousAddr_Rd() (mwHost20Port(0x28) ) 396 #define mwHost20_CurrentAsynchronousAddr_Set(wValue) USB_Write_REG32(0x28,wValue) 397 398 //<10>.0x030(PORTSC - Port Status and Control Register(Address = 030h)) 399 #define mwHost20_PORTSC_Rd() mwHost20Port(0x30) 400 401 // #define mwHost20_PORTSC_LineStatus_Rd() ((mwHost20Port(0x30)>>10)&0x00000003) 402 403 #define mwHost20_PORTSC_PortReset_Rd() mwHost20Bit_Rd(0x31,BIT0) 404 #define mwHost20_PORTSC_PortReset_Set() mwHost20Bit_Set(0x31,BIT0) 405 #define mwHost20_PORTSC_PortReset_Clr() mwHost20Bit_Clr(0x31,BIT0) 406 407 #define mwHost20_PORTSC_ForceSuspend_Rd() mwHost20Bit_Rd(0x30,BIT7) 408 #define mwHost20_PORTSC_ForceSuspend_Set() mwHost20Bit_Set(0x30,BIT7) 409 410 #define mwHost20_PORTSC_ForceResume_Rd() mwHost20Bit_Rd(0x30,BIT6) 411 #define mwHost20_PORTSC_ForceResume_Set() mwHost20Bit_Set(0x30,BIT6) 412 #define mwHost20_PORTSC_ForceResume_Clr() mwHost20Bit_Clr(0x30,BIT6) 413 414 #define mwHost20_PORTSC_EnableDisableChange_Rd() mwHost20Bit_Rd(0x30,BIT3) 415 #define mwHost20_PORTSC_EnableDisableChange_Set() mwHost20Bit_Set(0x30,BIT3) 416 417 #define mwHost20_PORTSC_EnableDisable_Rd() mwHost20Bit_Rd(0x30,BIT2) 418 #define mwHost20_PORTSC_EnableDisable_Set() mwHost20Bit_Set(0x30,BIT2) 419 #define mwHost20_PORTSC_EnableDisable_Clr() mwHost20Bit_Clr(0x30,BIT2) 420 #define mwHost20_PORTSC_EnableDisable_Write_0() (mwHost20Port(0x30)=0x00) 421 422 423 #define mwHost20_PORTSC_ConnectChange_Rd() mwHost20Bit_Rd(0x30,BIT1) 424 #define mwHost20_PORTSC_ConnectChange_Set() mwHost20Bit_Set(0x30,BIT1) 425 426 #define mwHost20_PORTSC_ConnectStatus_Rd() mwHost20Bit_Rd(0x30,BIT0) 427 428 429 430 //<10>.0x034(Misc. Register(Address = 034h)) 431 #define mwHost20_Misc_EOF1Time_Set(bValue) mwHost20Port_wr(0x34, ((mwHost20Port(0x34)&0xF3)|(((U8)(bValue))<<2)) ) //Bit 2~3 432 433 //<10>.0x034(Misc. Register(Address = 40h)) 434 #define mwHost20_Control_LineStatus_Rd() (mwHost20Port(0x40)& BIT11) 435 #define mwHost20_Control_LineStatus_Set() (mwHost20Bit_Set(0x40,BIT11)) 436 #define mwHost20_Control_LineStatus_Clr() (mwHost20Bit_Clr(0x40,BIT11)) 437 438 #define mwOTG20_Control_HOST_SPD_TYP_Rd() ((mwHost20Port(0x41)>>1)&0x03) 439 440 #define mwHost20_Control_ForceFullSpeed_Rd() (mwHost20Port(0x40)& BIT7) 441 #define mwHost20_Control_ForceFullSpeed_Set() (mwHost20Bit_Set(0x40,BIT7)) 442 #define mwHost20_Control_ForceFullSpeed_Clr() (mwHost20Bit_Clr(0x40,BIT7)) 443 444 #define mwHost20_Control_ForceHighSpeed_Rd() (mwHost20Port(0x40)& BIT6) 445 #define mwHost20_Control_ForceHighSpeed_Set() (mwHost20Bit_Set(0x40,BIT6)) 446 #define mwHost20_Control_ForceHighSpeed_Clr() (mwHost20Bit_Clr(0x40,BIT6)) 447 448 #define mwOTG20_Control_Phy_Reset_Set() (mwHost20Bit_Set(0x40,BIT5)) 449 #define mwOTG20_Control_Phy_Reset_Clr() (mwHost20Bit_Clr(0x40,BIT5)) 450 451 #define mwOTG20_Control_Half_Speed() (mwHost20Bit_Set(0x40,BIT2)) 452 453 // #define mwHost20_Control_711MA_FS_Issue_Solve() (mwHost20Bit_Set(0x40,BIT12)) //0x40 Bit-12 454 455 #ifndef VA2PA 456 #if defined(CPU_TYPE_ARM) 457 #define VA2PA(addr) MsOS_VA2PA((U32)addr) 458 #else 459 #define VA2PA(addr) ((void *)(((U32)addr) & 0x1fffffff)) 460 #endif 461 #endif 462 463 #if defined(CPU_TYPE_ARM) 464 #define VirtoPhyAddr(x) MsOS_VA2PA((U32)x) 465 #define PhytoVirAddr(x) MsOS_PA2KSEG1((U32)x) 466 #define PhytoCacheAddr(x) MsOS_PA2KSEG0((U32)x) 467 #else 468 #define VirtoPhyAddr(x) (x) 469 #define PhytoVirAddr(x) (x) 470 #define PhytoCacheAddr(x) (x) 471 #endif 472 473 #define flib_Host20_Allocate_QHD_Macro(x,y,z,w,u,v) \ 474 { x->bType=y; \ 475 x->bDeviceAddress=z; \ 476 x->bHeadOfReclamationListFlag=w; \ 477 x->bEdNumber=u; \ 478 x->bMaxPacketSize=v; } 479 #if 0 480 #define flib_Host20_Allocate_QHD(x,y,z,w,u,v) \ 481 { \ 482 flib_Host20_Allocate_QHD_Macro(x,y,z,w,u,v) ; \ 483 flib_Host20_Allocate_QHD1(x); } 484 #endif 485 //=================== 3.Structure Definition ============================================================= 486 //======================================================================================================== 487 488 //<3.1>iTD Structure Definition**************************************** 489 #define Host20_Preiodic_Frame_List_MAX 256 490 //<3.1>iTD Structure Definition**************************************** 491 typedef struct { 492 493 //<1>.Next_Link_Pointer Word 494 U32 bTerminal:1; 495 U32 bType:2; 496 U32 bReserved:2; 497 U32 bLinkPointer:27; 498 } Periodic_Frame_List_Cell_Structure; 499 500 501 typedef struct { 502 503 Periodic_Frame_List_Cell_Structure sCell[Host20_Preiodic_Frame_List_MAX]; 504 505 } Periodic_Frame_List_Structure; 506 507 //<3.2>qTD Structure Definition**************************************** 508 typedef struct _BufferPointer 509 { 510 U8 Byte0; 511 U8 Byte1; 512 U8 Byte2; 513 U8 Byte3; 514 }BufferPointer_Struct; 515 516 517 typedef struct _qTD { 518 519 U32 bTerminate:1; 520 U32 bReserve_1:4; 521 U32 bNextQTDPointer:27; 522 523 //<2>.Alternate Next qTD Word 524 U32 bAlternateTerminate:1; 525 U32 bReserve_2:4; 526 U32 bAlternateQTDPointer:27; 527 528 //<3>.Status Word 529 U32 bStatus_PingState:1; 530 U32 bStatus_SplitState:1; 531 U32 bStatus_MissMicroFrame:1; 532 U32 bStatus_Transaction_Err:1; 533 U32 bStatus_Babble:1; 534 U32 bStatus_Buffer_Err:1; 535 U32 bStatus_Halted:1; 536 U32 bStatus_Active:1; 537 538 U32 bPID:2; 539 U32 bErrorCounter:2; 540 U32 CurrentPage:3; 541 U32 bInterruptOnComplete:1; 542 U32 bTotalBytes:15; 543 U32 bDataToggle:1; 544 545 546 //<4>.Buffer Pointer Word Array 547 U32 ArrayBufferPointer_Word[5]; 548 549 550 } qTD_Structure; 551 #define HOST20_qTD_PID_OUT 0x00 552 #define HOST20_qTD_PID_IN 0x01 553 #define HOST20_qTD_PID_SETUP 0x02 554 555 556 #define HOST20_qTD_STATUS_Active 0x80 557 #define HOST20_qTD_STATUS_Halted 0x40 558 #define HOST20_qTD_STATUS_BufferError 0x20 559 #define HOST20_qTD_STATUS_Babble 0x10 560 #define HOST20_qTD_STATUS_TransactionError 0x08 561 #define HOST20_qTD_STATUS_MissMicroFrame 0x04 562 #define HOST20_qTD_STATUS_Split 0x02 563 #define HOST20_qTD_STATUS_Ping 0x01 564 565 typedef struct _qHD { 566 567 //<1>.Next_qHD_Pointer Word 568 U32 bTerminate:1; 569 U32 bType:2; 570 U32 bReserve_1:2; 571 U32 bNextQHDPointer:27; 572 573 //<2>.qHD_2 Word 574 U32 bDeviceAddress:7; 575 U32 bInactiveOnNextTransaction:1; 576 U32 bEdNumber:4; 577 U32 bEdSpeed:2; 578 U32 bDataToggleControl:1; 579 U32 bHeadOfReclamationListFlag:1; 580 U32 bMaxPacketSize:11; 581 U32 bControlEdFlag:1; 582 U32 bNakCounter:4; 583 584 //<3>.qHD_3 Word 585 U32 bInterruptScheduleMask:8; 586 U32 bSplitTransactionMask:8; 587 U32 bHubAddr:7; 588 U32 bPortNumber:7; 589 U32 bHighBandwidth:2; 590 591 //<4>.Overlay_CurrentqTD 592 U32 bOverlay_CurrentqTD; 593 594 //<5>.Overlay_NextqTD 595 U32 bOverlay_NextTerminate:1; 596 U32 bOverlay_Reserve2:4; 597 U32 bOverlay_NextqTD:27; 598 599 //<6>.Overlay_AlternateNextqTD 600 U32 bOverlay_AlternateNextTerminate:1; 601 U32 bOverlay_NanCnt:4; 602 U32 bOverlay_AlternateqTD:27; 603 604 //<7>.Overlay_TotalBytes 605 U32 bOverlay_Status:8; 606 U32 bOverlay_PID:2; 607 U32 bOverlay_ErrorCounter:2; 608 U32 bOverlay_C_Page:3; 609 U32 bOverlay_InterruptOnComplete:1; 610 U32 bOverlay_TotalBytes:15; 611 U32 bOverlay_Direction:1; 612 613 //<8>.Overlay_BufferPointer0 614 U32 bOverlay_CurrentOffset:12; 615 U32 bOverlay_BufferPointer_0:20; 616 617 //<9>.Overlay_BufferPointer1 618 U32 bOverlay_C_Prog_Mask:8; 619 U32 bOverlay_Reserve3:4; 620 U32 bOverlay_BufferPointer_1:20; 621 622 //<10>.Overlay_BufferPointer2 623 U32 bOverlay_FrameTag:5; 624 U32 bOverlay_S_Bytes:7; 625 U32 bOverlay_BufferPointer_2:20; 626 627 //<11>.Overlay_BufferPointer3 628 U32 bOverlay_Reserve4:12; 629 U32 bOverlay_BufferPointer_3:20; 630 631 //<12>.Overlay_BufferPointer4 632 U32 bOverlay_Reserve5:12; 633 U32 bOverlay_BufferPointer_4:20; 634 635 } qHD_Structure; 636 637 638 #define HOST20_HD_Type_iTD 0x00 639 #define HOST20_HD_Type_QH 0x01 640 #define HOST20_HD_Type_siTD 0x02 641 #define HOST20_HD_Type_FSTN 0x03 642 643 //<3.4>.Test Condition Definition**************************************** 644 645 646 typedef struct { 647 648 UINT8 bStructureEnable; //Enable = 0x66 Disable=>Others 649 UINT8 bInterruptThreshod; //01,02,04,08,10,20,40 650 UINT8 bAsynchronousParkMode; //00=>Disable,01=>Enable 651 UINT8 bAsynchronousParkModeCounter; //01,02,03 652 UINT8 bFrameSize; //00,01,02 653 654 } Host20_Init_Condition_Structure; 655 656 657 #define HOST20_FrameSize_1024 0x00 658 #define HOST20_FrameSize_512 0x01 659 #define HOST20_FrameSize_256 0x02 660 661 662 //<3.5>.Host20's Attach Device Info Structure**************************************** 663 664 //OTGHost Device Structure 665 typedef struct 666 { 667 UINT8 bDEVICE_LENGTH; // bLength 668 UINT8 bDT_DEVICE; // bDescriptorType 669 UINT8 bVerLowByte; // bcdUSB 670 UINT8 bVerHighByte; 671 672 UINT8 bDeviceClass; // bDeviceClass 673 UINT8 bDeviceSubClass; // bDeviceSubClas; 674 UINT8 bDeviceProtocol; // bDeviceProtocol 675 UINT8 bEP0MAXPACKETSIZE; // bMaxPacketSize0 676 677 UINT8 bVIDLowByte; // idVendor 678 UINT8 bVIDHighByte; 679 UINT8 bPIDLowByte; // idProduct 680 UINT8 bPIDHighByte; 681 UINT8 bRNumLowByte; // bcdDeviceReleaseNumber 682 UINT8 bRNumHighByte; 683 684 UINT8 bManufacturer; // iManufacturer 685 UINT8 bProduct; // iProduct 686 UINT8 bSerialNumber; // iSerialNumber 687 UINT8 bCONFIGURATION_NUMBER; // bNumConfigurations 688 }OTGH_Descriptor_Device_Struct; 689 690 691 //<3.6>.OTGHost Configuration Structure => Only Support 2 Configuration / 5 Interface / 1 Class / 5 Endpoint /1 OTG 692 693 #define HOST20_CONFIGURATION_NUM_MAX 0X02 694 #define HOST20_INTERFACE_NUM_MAX 0X05 695 #define HOST20_ENDPOINT_NUM_MAX 0X05 696 #define HOST20_CLASS_NUM_MAX 0x01 697 698 699 #define HOST20_CONFIGURATION_LENGTH 0X09 700 #define HOST20_INTERFACE_LENGTH 0X09 701 #define HOST20_ENDPOINT_LENGTHX 0X07 702 #define HOST20_CLASS_LENGTHX 0X09 703 704 typedef struct 705 { 706 707 //<3>.Define for ED-OTG 708 UINT8 bED_OTG_Length; 709 UINT8 bED_OTG_bDescriptorType; 710 UINT8 bED_OTG_bAttributes; 711 712 713 }OTGH_Descriptor_OTG_Struct; 714 715 typedef struct 716 { 717 //<3>.Define for ED-1 718 UINT8 bED_Length; 719 UINT8 bED_bDescriptorType; 720 UINT8 bED_EndpointAddress; 721 UINT8 bED_bmAttributes; 722 UINT8 bED_wMaxPacketSizeLowByte; 723 UINT8 bED_wMaxPacketSizeHighByte; 724 UINT8 bED_Interval; 725 726 }OTGH_Descriptor_EndPoint_Struct; 727 728 729 typedef struct 730 { 731 732 UINT8 bClass_LENGTH; 733 UINT8 bClaNumberss; 734 UINT8 bClassVerLowByte; 735 UINT8 bClassVerHighByte; 736 UINT8 bCityNumber; 737 UINT8 bFollowDescriptorNum; 738 UINT8 bReport; 739 UINT8 bLengthLowByte; 740 UINT8 bLengthHighByte; 741 742 }OTGH_Descriptor_Class_Struct; 743 744 745 746 747 748 749 typedef struct 750 { 751 752 //<2>.Define for Interface-1 753 UINT8 bINTERFACE_LENGTH; // bLength 754 UINT8 bDT_INTERFACE; // bDescriptorType INTERFACE 755 UINT8 bInterfaceNumber; // bInterfaceNumber 756 UINT8 bAlternateSetting; // bAlternateSetting 757 UINT8 bEP_NUMBER; // bNumEndpoints(excluding endpoint zero) 758 UINT8 bInterfaceClass; // bInterfaceClass 759 UINT8 bInterfaceSubClass; // bInterfaceSubClass 760 UINT8 bInterfaceProtocol; // bInterfaceProtocol 761 UINT8 bInterface; // iInterface 762 763 OTGH_Descriptor_Class_Struct sClass[HOST20_CLASS_NUM_MAX]; 764 OTGH_Descriptor_EndPoint_Struct sED[HOST20_ENDPOINT_NUM_MAX]; 765 766 767 768 }OTGH_Descriptor_Interface_Struct; 769 770 771 772 typedef struct 773 { 774 775 UINT8 bCONFIG_LENGTH; // bLength 776 UINT8 bDT_CONFIGURATION; // bDescriptorType CONFIGURATION 777 UINT8 bTotalLengthLowByte; // wTotalLength, include all descriptors 778 UINT8 bTotalLengthHighByte; 779 UINT8 bINTERFACE_NUMBER; // bNumInterface 780 UINT8 bConfigurationValue; // bConfigurationValue 781 UINT8 bConfiguration; // iConfiguration 782 UINT8 bAttribute; // bmAttribute 783 UINT8 bMaxPower; // iMaxPower (2mA units) 784 785 OTGH_Descriptor_Interface_Struct sInterface[HOST20_INTERFACE_NUM_MAX]; 786 787 788 }OTGH_Descriptor_Configuration_Only_Struct; 789 790 791 792 //Support Configuration x2 793 // Interface x5 794 // EndPoint x5 795 // OTG X1 796 797 typedef struct 798 { 799 800 //<1>.Basic Information 801 // UINT8 bDeviceOnHub; 802 // UINT8 bOnHubPortNumber; 803 UINT8 bAdd; 804 // UINT8 bConnectStatus; 805 // UINT8 bPortEnableDisableStatus; 806 // UINT8 bSpeed; //0=>Low Speed / 1=>Full Speed / 2 => High Speed 807 // UINT8 bPortReset; 808 // UINT8 bSuspend; 809 // volatile UINT8 bRemoteWakeUpDetected; 810 // UINT8 bSendOK; 811 UINT8 bSendStatusError; 812 813 814 // qTD_Structure *psSendLastqTD; 815 UINT16 bDataBuffer; 816 //<2>.Descriptor Information 817 OTGH_Descriptor_Device_Struct sDD; 818 OTGH_Descriptor_Configuration_Only_Struct saCD[HOST20_CONFIGURATION_NUM_MAX]; 819 OTGH_Descriptor_OTG_Struct sOTG; 820 821 // UINT8 bReportDescriptor[0x74]; 822 UINT8 bStringLanguage[10]; 823 UINT8 bStringManufacture[64]; 824 UINT8 bStringProduct[64]; 825 // UINT8 bStringSerialN[0xFF]; 826 //<3>.For ISO Information 827 // UINT8 bISOTransferEnable; 828 // UINT32 wISOiTDAddress[1024]; 829 830 }Host20_Attach_Device_Structure; 831 832 #define HOST20_Attach_Device_Speed_Full 0x00 833 #define HOST20_Attach_Device_Speed_Low 0x01 834 #define HOST20_Attach_Device_Speed_High 0x02 835 836 //<3.7>.Control Command Structure 837 typedef struct { 838 839 UINT8 bmRequestType; //(In/Out),(Standard...),(Device/Interface...) 840 UINT8 bRequest; //GetStatus ..... 841 UINT8 wValueLow; //Byte2 842 UINT8 wValueHigh; //Byte3 843 UINT8 wIndexLow; //Byte4 844 UINT8 wIndexHigh; //Byte5 845 UINT8 wLengthLow; //Byte6 846 UINT8 wLengthHigh; //Byte7 847 848 849 } Host20_Control_Command_Structure; 850 851 #define HOST20_CONTROL_GetStatus 0x00 852 #define HOST20_CONTROL_ClearFeature 0x01 853 #define HOST20_CONTROL_SetFeature 0x03 854 #define HOST20_CONTROL_SetAddress 0x05 855 #define HOST20_CONTROL_GetDescriptor 0x06 856 #define HOST20_CONTROL_SetDescriptor 0x07 857 #define HOST20_CONTROL_GetConfiguration 0x08 858 #define HOST20_CONTROL_GetInterface 0x0A 859 #define HOST20_CONTROL_SetInterface 0x0B 860 #define HOST20_CONTROL_SyncFrame 0x0C 861 862 863 #define HOST20_HID_GetReport 0x01 864 #define HOST20_HID_GetIdle 0x02 865 #define HOST20_HID_GetProtocol 0x03 866 #define HOST20_HID_SetReport 0x09 867 #define HOST20_HID_SetIdle 0x0A 868 #define HOST20_HID_SetProtocol 0x0B 869 870 871 //<3.8>.BufferPointerArray 872 typedef struct { 873 UINT32 BufferPointerArray[8]; 874 } Host20_BufferPointerArray_Structure; 875 876 877 878 879 880 //=================== 4.Extern Function Definition ======================================================= 881 //======================================================================================================== 882 883 extern BOOLEAN flib_OTGH_Init(UINT8 wForDevice_B); 884 extern U8 flib_Host20_Close(void); 885 extern BOOLEAN USB_Hub_Handle(U8 port) ; 886 extern U8 Usb_Hub_Port_Num(void); 887 888 //extern UINT8 flib_Host20_ISR(void); 889 extern UINT8 flib_Host20_PortBusReset(void); 890 extern void flib_Host20_Suspend(void); 891 extern UINT8 flib_Host20_Issue_Control (UINT8 bEdNum,UINT8* pbCmd,UINT16 hwDataSize,UINT8* pbData); 892 extern UINT8 flib_Host20_Issue_Bulk(UINT8 bArrayListNum,UINT16 hwSize,UINT32,UINT8 bDirection); 893 extern UINT8 flib_Host20_Enumerate (UINT8 bNormalEnumerate,UINT8 bAddress); 894 extern UINT8 _flib_Host20_Enumerate (UINT8 bNormalEnumerate,UINT8 bAddress); 895 extern UINT8 flib_Host20_Issue_Control_CBI (UINT8* pbCmd,UINT16 hwDataSize,UINT8* pbData); 896 897 extern void flib_DumpDeviceDescriptor (OTGH_Descriptor_Device_Struct *sDevice); 898 extern void flib_PrintDeviceInfo (void); 899 extern void flib_PrintDeviceInfo_ByInput (Host20_Attach_Device_Structure *psAttachDevice); 900 extern void flib_Host20_TimerISR(void); 901 // extern void flib_Host20_TimerEnable(UINT32 wTime_ms); 902 extern void flib_Host20_InitStructure(void); 903 extern qTD_Structure *flib_Host20_GetStructure(UINT8 Type); 904 extern void flib_Host20_ReleaseStructure(U8 Type,U32 pwAddress); 905 extern void flib_Host20_QHD_Control_Init(void); 906 extern UINT8 flib_Host20_Send_qTD(qTD_Structure *spHeadqTD ,qHD_Structure *spTempqHD,U16 wTimeOutSec); 907 extern void flib_Host20_Allocate_QHD(qHD_Structure *psQHTemp,UINT8 bNextType,UINT8 bAddress,UINT8 bHead,UINT8 bEndPt, UINT32 wMaxPacketSize); 908 909 extern UINT8 flib_Host20_Issue_Control_Turbo (UINT8 bEdNum,UINT8* pbCmd,UINT32 wDataSize,UINT32 *pwPageAddress,UINT32 wCurrentOffset); 910 extern void flib_Host20_Control_Command_Request(Host20_Control_Command_Structure *pbCMD,UINT8 bmRequestType_Temp,UINT8 bRequest_Temp,UINT16 wValue_Temp,UINT16 wIndex_Temp,UINT16 wLength_Temp); 911 extern void flib_DumpString (UINT8 *pbTemp,UINT8 bSize); 912 extern void flib_Host20_Interrupt_Init(UINT8 bAddr); 913 extern U8 flib_Host20_Issue_Interrupt(U32 buf,U32 hwSize); 914 915 extern void flib_Host20_Asynchronous_Enable(void); 916 extern void flib_Host20_Asynchronous_Disable(void); 917 918 extern UINT8 flib_OTGH_Checking_RemoteWakeUp(void); 919 extern UINT8 flib_OTGH_RemoteWakeEnable(void); 920 extern void flib_Host20_StopRun_Setting(UINT8 bOption); 921 // extern void flib_Host20_Asynchronous_Setting(UINT8 bOption); 922 extern void flib_Host20_Periodic_Setting(UINT8 bOption); 923 // extern void flib_Host20_TimerEnable_UnLock(UINT32 wTime_Tick); 924 // extern void flib_Host20_TimerDisable_UnLock(void); 925 926 extern void flib_Host20_RemoteWakeUp_Processing(void); 927 928 // extern void SetPointer(UINT16 addr, UINT32 val); 929 // extern void SetValue(UINT16 addr, UINT8 StartBit, UINT8 BitNum, UINT8 val); 930 void FillBufferArray(qTD_Structure xdata *spTempqTD,UINT16 bpDataPage); 931 //void SetPointer( qHD_Structure xdata *qhd, UINT32 val); 932 qTD_Structure *GetPointer(UINT8* ptr); 933 void SetPointer( UINT8 *ptr, UINT32 val); 934 935 936 //=================== 5.Call Extern Function Definition ======================================================= 937 //======================================================================================================== 938 939 extern void flib_Debug_LED_Init(void); 940 extern void flib_Debug_LED_On_All(void); 941 extern void flib_Debug_LED_Off_All(void); 942 943 944 //=================== 6.Extern Variable Definition ======================================================= 945 //======================================================================================================== 946 947 extern code UINT8 OTGH_GETDESCRIPTOR_DEVICE[]; 948 extern code UINT8 OTGH_GETDESCRIPTOR_CONFIG[]; 949 extern code UINT8 OTGH_SETADDRESS[]; 950 extern code UINT8 OTGH_SETCONFIGURATION[]; 951 extern code UINT8 OTGH_GETDESCRIPTOR_OTG[]; 952 extern code UINT8 OTGH_SET_FEATURE_OTG[]; 953 extern code UINT8 OTGH_SETDESCRIPTOR_DEVICE[]; 954 extern code UINT8 OTGH_GETDESCRIPTOR_STR70[]; 955 extern code UINT8 OTGH_SETDESCRIPTOR_STR70[]; 956 extern code UINT8 OTGH_GETDESCRIPTOR_STR80[]; 957 extern code UINT8 OTGH_SETDESCRIPTOR_STR80[]; 958 extern code UINT8 waIntervalMap[]; 959 // extern volatile UINT32 wOTG_Timer_Counter; 960 // extern qHD_Structure *psHost20_qHD_List_Control[3]; 961 // extern qHD_Structure *psHost20_qHD_List_Bulk[3]; 962 #if 0 963 extern qHD_Structure xdata Host20_qHD_List_Control0; 964 extern qHD_Structure xdata Host20_qHD_List_Bulk0; 965 extern qHD_Structure xdata Host20_qHD_List_Control1; 966 extern qHD_Structure xdata Host20_qHD_List_Bulk1; 967 #endif 968 extern qHD_Structure *pHost20_qHD_List_Control0; 969 extern qHD_Structure *pHost20_qHD_List_Bulk0; 970 extern qHD_Structure *pHost20_qHD_List_Control1; 971 extern qHD_Structure *pHost20_qHD_List_Bulk1; 972 973 extern UINT8 Host20_qTD_Manage[Host20_qTD_MAX]; //1=>Free 2=>used 974 // extern UINT8 Host20_iTD_Manage[Host20_iTD_MAX]; //1=>Free 2=>used 975 //extern UINT8 Host20_DataPage_Manage[Host20_Page_MAX]; //1=>Free 2=>used 976 977 extern Host20_Init_Condition_Structure sInitCondition; 978 extern Host20_Attach_Device_Structure xdata sAttachDevice; 979 extern volatile UINT32 wOTG_Timer_Counter; 980 // extern Periodic_Frame_List_Structure *psHost20_FramList; 981 // extern volatile UINT32 gwLastiTDSendOK; 982 983 // extern Host20_ISO_FixBufferMode_Structure sISOFixBufferMode; 984 // extern UINT8 bForceSpeed;//0=>All Clear 1=>Full Speed 2=>High Speed 985 986 987 extern Host20_Attach_Device_Structure *psDevice_AP; 988 // extern UINT32 Host20_STRUCTURE_qHD_BASE_ADDRESS,Host20_STRUCTURE_qTD_BASE_ADDRESS; 989 //extern UINT32 Host20_STRUCTURE_Preiodic_Frame_List_BASE_ADDRESS,Host20_STRUCTURE_iTD_BASE_ADDRESS; 990 991 992 // Write dirty cache lines to memory and invalidate the cache entries 993 // for the given address range. 994 // Aeon2 does not have an explicit invalidate memory instruction, so use 995 // flush are necessary. 996 //#ifdef NOS_MIPS 997 #if defined(CPU_TYPE_MIPS) || defined(CPU_TYPE_ARM) 998 void mhal_dcache_flush(unsigned long u32Base, unsigned long u32Size ); 999 #define MY_HAL_DCACHE_FLUSH mhal_dcache_flush 1000 #else //NOS_MIPS 1001 #ifdef __AEONR2__ 1002 #if 0 1003 #define MY_HAL_DCACHE_FLUSH( _base_ , _size_ ) \ 1004 CYG_MACRO_START \ 1005 U32 size_once = _size_, base_once = _base_; \ 1006 U32 addr, end; \ 1007 end = base_once + ((size_once < HAL_DCACHE_SIZE) ? \ 1008 size_once : HAL_DCACHE_SIZE); \ 1009 for (addr = end; addr >= base_once; addr -= HAL_DCACHE_LINE_SIZE) { \ 1010 __asm__ __volatile__( \ 1011 "l.flush_line 0(%0), 0\n" /* way 0 */ \ 1012 "l.flush_line 0(%0), 1\n" /* way 1 */ \ 1013 "l.flush_line 0(%0), 2\n" /* way 2 */ \ 1014 "l.flush_line 0(%0), 3\n" /* way 3 */ \ 1015 "l.invalidate_line 0(%0), 0\n" /* way 0 */ \ 1016 "l.invalidate_line 0(%0), 1\n" /* way 1 */ \ 1017 "l.invalidate_line 0(%0), 2\n" /* way 2 */ \ 1018 "l.invalidate_line 0(%0), 3\n" /* way 3 */ \ 1019 : : "r"(addr) \ 1020 ); \ 1021 } \ 1022 __asm__ __volatile__( "l.syncwritebuffer\n" ); \ 1023 CYG_MACRO_END 1024 #else //Janus 1025 void mhal_dcache_flush(unsigned long u32Base, unsigned long u32Size ); 1026 #define MY_HAL_DCACHE_FLUSH mhal_dcache_flush 1027 #endif 1028 #else 1029 #define MY_HAL_DCACHE_FLUSH( _base_ , _size_ ) \ 1030 CYG_MACRO_START \ 1031 U32 size_once = _size_, base_once = _base_; \ 1032 U32 addr, end; \ 1033 end = base_once + ((size_once < HAL_DCACHE_SIZE) ? \ 1034 size_once : HAL_DCACHE_SIZE); \ 1035 for (addr = end; addr >= base_once; addr -= HAL_DCACHE_LINE_SIZE) { \ 1036 __asm__ __volatile__( \ 1037 "l.flush_line 0(%0), 0\n" /* way 0 */ \ 1038 "l.flush_line 0(%0), 1\n" /* way 1 */ \ 1039 "l.invalidate_line 0(%0), 0\n" /* way 2 */ \ 1040 "l.invalidate_line 0(%0), 1\n" /* way 3 */ \ 1041 : : "r"(addr) \ 1042 ); \ 1043 } \ 1044 __asm__ __volatile__( "l.syncwritebuffer\n" ); \ 1045 CYG_MACRO_END 1046 #endif 1047 #endif//NOS_MIPS 1048 1049 1050 #endif //LIB_HOST200__H 1051 1052 1053 1054 1055 1056