1*53ee8cc1Swenshuai.xi //<MStar Software>
2*53ee8cc1Swenshuai.xi //******************************************************************************
3*53ee8cc1Swenshuai.xi // MStar Software
4*53ee8cc1Swenshuai.xi // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5*53ee8cc1Swenshuai.xi // All software, firmware and related documentation herein ("MStar Software") are
6*53ee8cc1Swenshuai.xi // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7*53ee8cc1Swenshuai.xi // law, including, but not limited to, copyright law and international treaties.
8*53ee8cc1Swenshuai.xi // Any use, modification, reproduction, retransmission, or republication of all
9*53ee8cc1Swenshuai.xi // or part of MStar Software is expressly prohibited, unless prior written
10*53ee8cc1Swenshuai.xi // permission has been granted by MStar.
11*53ee8cc1Swenshuai.xi //
12*53ee8cc1Swenshuai.xi // By accessing, browsing and/or using MStar Software, you acknowledge that you
13*53ee8cc1Swenshuai.xi // have read, understood, and agree, to be bound by below terms ("Terms") and to
14*53ee8cc1Swenshuai.xi // comply with all applicable laws and regulations:
15*53ee8cc1Swenshuai.xi //
16*53ee8cc1Swenshuai.xi // 1. MStar shall retain any and all right, ownership and interest to MStar
17*53ee8cc1Swenshuai.xi // Software and any modification/derivatives thereof.
18*53ee8cc1Swenshuai.xi // No right, ownership, or interest to MStar Software and any
19*53ee8cc1Swenshuai.xi // modification/derivatives thereof is transferred to you under Terms.
20*53ee8cc1Swenshuai.xi //
21*53ee8cc1Swenshuai.xi // 2. You understand that MStar Software might include, incorporate or be
22*53ee8cc1Swenshuai.xi // supplied together with third party`s software and the use of MStar
23*53ee8cc1Swenshuai.xi // Software may require additional licenses from third parties.
24*53ee8cc1Swenshuai.xi // Therefore, you hereby agree it is your sole responsibility to separately
25*53ee8cc1Swenshuai.xi // obtain any and all third party right and license necessary for your use of
26*53ee8cc1Swenshuai.xi // such third party`s software.
27*53ee8cc1Swenshuai.xi //
28*53ee8cc1Swenshuai.xi // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29*53ee8cc1Swenshuai.xi // MStar`s confidential information and you agree to keep MStar`s
30*53ee8cc1Swenshuai.xi // confidential information in strictest confidence and not disclose to any
31*53ee8cc1Swenshuai.xi // third party.
32*53ee8cc1Swenshuai.xi //
33*53ee8cc1Swenshuai.xi // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34*53ee8cc1Swenshuai.xi // kind. Any warranties are hereby expressly disclaimed by MStar, including
35*53ee8cc1Swenshuai.xi // without limitation, any warranties of merchantability, non-infringement of
36*53ee8cc1Swenshuai.xi // intellectual property rights, fitness for a particular purpose, error free
37*53ee8cc1Swenshuai.xi // and in conformity with any international standard. You agree to waive any
38*53ee8cc1Swenshuai.xi // claim against MStar for any loss, damage, cost or expense that you may
39*53ee8cc1Swenshuai.xi // incur related to your use of MStar Software.
40*53ee8cc1Swenshuai.xi // In no event shall MStar be liable for any direct, indirect, incidental or
41*53ee8cc1Swenshuai.xi // consequential damages, including without limitation, lost of profit or
42*53ee8cc1Swenshuai.xi // revenues, lost or damage of data, and unauthorized system use.
43*53ee8cc1Swenshuai.xi // You agree that this Section 4 shall still apply without being affected
44*53ee8cc1Swenshuai.xi // even if MStar Software has been modified by MStar in accordance with your
45*53ee8cc1Swenshuai.xi // request or instruction for your use, except otherwise agreed by both
46*53ee8cc1Swenshuai.xi // parties in writing.
47*53ee8cc1Swenshuai.xi //
48*53ee8cc1Swenshuai.xi // 5. If requested, MStar may from time to time provide technical supports or
49*53ee8cc1Swenshuai.xi // services in relation with MStar Software to you for your use of
50*53ee8cc1Swenshuai.xi // MStar Software in conjunction with your or your customer`s product
51*53ee8cc1Swenshuai.xi // ("Services").
52*53ee8cc1Swenshuai.xi // You understand and agree that, except otherwise agreed by both parties in
53*53ee8cc1Swenshuai.xi // writing, Services are provided on an "AS IS" basis and the warranty
54*53ee8cc1Swenshuai.xi // disclaimer set forth in Section 4 above shall apply.
55*53ee8cc1Swenshuai.xi //
56*53ee8cc1Swenshuai.xi // 6. Nothing contained herein shall be construed as by implication, estoppels
57*53ee8cc1Swenshuai.xi // or otherwise:
58*53ee8cc1Swenshuai.xi // (a) conferring any license or right to use MStar name, trademark, service
59*53ee8cc1Swenshuai.xi // mark, symbol or any other identification;
60*53ee8cc1Swenshuai.xi // (b) obligating MStar or any of its affiliates to furnish any person,
61*53ee8cc1Swenshuai.xi // including without limitation, you and your customers, any assistance
62*53ee8cc1Swenshuai.xi // of any kind whatsoever, or any information; or
63*53ee8cc1Swenshuai.xi // (c) conferring any license or right under any intellectual property right.
64*53ee8cc1Swenshuai.xi //
65*53ee8cc1Swenshuai.xi // 7. These terms shall be governed by and construed in accordance with the laws
66*53ee8cc1Swenshuai.xi // of Taiwan, R.O.C., excluding its conflict of law rules.
67*53ee8cc1Swenshuai.xi // Any and all dispute arising out hereof or related hereto shall be finally
68*53ee8cc1Swenshuai.xi // settled by arbitration referred to the Chinese Arbitration Association,
69*53ee8cc1Swenshuai.xi // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70*53ee8cc1Swenshuai.xi // Rules of the Association by three (3) arbitrators appointed in accordance
71*53ee8cc1Swenshuai.xi // with the said Rules.
72*53ee8cc1Swenshuai.xi // The place of arbitration shall be in Taipei, Taiwan and the language shall
73*53ee8cc1Swenshuai.xi // be English.
74*53ee8cc1Swenshuai.xi // The arbitration award shall be final and binding to both parties.
75*53ee8cc1Swenshuai.xi //
76*53ee8cc1Swenshuai.xi //******************************************************************************
77*53ee8cc1Swenshuai.xi //<MStar Software>
78*53ee8cc1Swenshuai.xi
79*53ee8cc1Swenshuai.xi //=============================================================================
80*53ee8cc1Swenshuai.xi #include <MsCommon.h>
81*53ee8cc1Swenshuai.xi #include <cyg/hal/hal_if.h>
82*53ee8cc1Swenshuai.xi #include <cyg/hal/hal_arch.h>
83*53ee8cc1Swenshuai.xi #include "include/drvConfig.h"
84*53ee8cc1Swenshuai.xi #include "include/drvPorts.h"
85*53ee8cc1Swenshuai.xi #include "include/drvKernel.h"
86*53ee8cc1Swenshuai.xi #include "include/drvBitops.h"
87*53ee8cc1Swenshuai.xi
88*53ee8cc1Swenshuai.xi #if 1
89*53ee8cc1Swenshuai.xi #define NOCACHE_MEMORY_SIZE SZ_128K //SZ_64K, Kaiserin
90*53ee8cc1Swenshuai.xi //#define NOCACHE_MEMORY_REGION MEM_REGION_8M
91*53ee8cc1Swenshuai.xi //#define NOCACHE_REGION_NUM 3
92*53ee8cc1Swenshuai.xi //#define NOCACHE_MIN_ALIGN 32
93*53ee8cc1Swenshuai.xi //#define NCMEM_BUFFER_POOLS 4
94*53ee8cc1Swenshuai.xi
95*53ee8cc1Swenshuai.xi extern int BaseOfFreeMemory;
96*53ee8cc1Swenshuai.xi extern int TopOfFreeMemory;
97*53ee8cc1Swenshuai.xi extern int BaseOfHeap;
98*53ee8cc1Swenshuai.xi extern int TopOfHeap;
99*53ee8cc1Swenshuai.xi
100*53ee8cc1Swenshuai.xi #define NCM_DEBUG
101*53ee8cc1Swenshuai.xi
102*53ee8cc1Swenshuai.xi #ifdef NCM_DEBUG
103*53ee8cc1Swenshuai.xi #define NCM_Dbg(x,...) diag_printf(x,__VA_ARGS__)
104*53ee8cc1Swenshuai.xi #else
105*53ee8cc1Swenshuai.xi #define NCM_Dbg(x,...)
106*53ee8cc1Swenshuai.xi #endif
107*53ee8cc1Swenshuai.xi
108*53ee8cc1Swenshuai.xi struct ncmem_pool_tag { /* the pool */
109*53ee8cc1Swenshuai.xi U32 base_addr;
110*53ee8cc1Swenshuai.xi size_t pages_per_pool;
111*53ee8cc1Swenshuai.xi U32 *bitmap;
112*53ee8cc1Swenshuai.xi };
113*53ee8cc1Swenshuai.xi static struct ncmem_pool_tag ncmem_pool;
114*53ee8cc1Swenshuai.xi
115*53ee8cc1Swenshuai.xi U32 ncmem_addr;
116*53ee8cc1Swenshuai.xi U32 ncmem_base;
117*53ee8cc1Swenshuai.xi
118*53ee8cc1Swenshuai.xi /*******************************************************************************
119*53ee8cc1Swenshuai.xi * Routine name : ncmem_free_page
120*53ee8cc1Swenshuai.xi * returns : none
121*53ee8cc1Swenshuai.xi * Created by : Peter Liao
122*53ee8cc1Swenshuai.xi * Date created : 2004/01/25
123*53ee8cc1Swenshuai.xi * Description : Create a non-cacheable and non-bufferable page memory pool via
124*53ee8cc1Swenshuai.xi * CPU memoryt region declaration API. Page momery pool is splited
125*53ee8cc1Swenshuai.xi * by the size of page memory. Each page memory is aligned to
126*53ee8cc1Swenshuai.xi * page_size bytes.
127*53ee8cc1Swenshuai.xi * Notes :
128*53ee8cc1Swenshuai.xi *******************************************************************************/
init_cache_memory(void)129*53ee8cc1Swenshuai.xi void init_cache_memory(void)
130*53ee8cc1Swenshuai.xi {
131*53ee8cc1Swenshuai.xi int mapsize;
132*53ee8cc1Swenshuai.xi
133*53ee8cc1Swenshuai.xi
134*53ee8cc1Swenshuai.xi ncmem_addr=(U32)KSEG02KSEG1(Usb_AllocateNonCachedMemory(NOCACHE_MEMORY_SIZE + PAGE_SIZE));
135*53ee8cc1Swenshuai.xi
136*53ee8cc1Swenshuai.xi USB_ASSERT(ncmem_addr, "Allocate ncmem buffer fail\n");
137*53ee8cc1Swenshuai.xi ncmem_base = (ncmem_addr + PAGE_SIZE)&(~(PAGE_SIZE-1));
138*53ee8cc1Swenshuai.xi NCM_Dbg("The base address is 0x%8lX\n", ncmem_base);
139*53ee8cc1Swenshuai.xi
140*53ee8cc1Swenshuai.xi // Initialize non-cached memory pool information
141*53ee8cc1Swenshuai.xi ncmem_pool.pages_per_pool = (NOCACHE_MEMORY_SIZE/PAGE_SIZE);
142*53ee8cc1Swenshuai.xi mapsize = ncmem_pool.pages_per_pool;
143*53ee8cc1Swenshuai.xi mapsize = (mapsize + BITS_PER_LONG - 1) / BITS_PER_LONG;
144*53ee8cc1Swenshuai.xi mapsize *= sizeof (U32);
145*53ee8cc1Swenshuai.xi ncmem_pool.base_addr =(U32) KSEG02KSEG1(ncmem_base); // convert cached address to uncached
146*53ee8cc1Swenshuai.xi // ncmem_pool.bitmap = (U32 *)LIB_MemoryAllocate(mapsize, MALLOC_CACHED_ADDR);
147*53ee8cc1Swenshuai.xi ncmem_pool.bitmap = (U32*)Usb_AllocateNonCachedMemory(mapsize);
148*53ee8cc1Swenshuai.xi memset(ncmem_pool.bitmap, ((U32)-1), mapsize);//Bitmap: 0-used 1-unused
149*53ee8cc1Swenshuai.xi
150*53ee8cc1Swenshuai.xi NCM_Dbg("Base addr is 0x%08lX\n",ncmem_pool.base_addr);
151*53ee8cc1Swenshuai.xi NCM_Dbg("Top addr is 0x%08lX\n",ncmem_pool.base_addr+NOCACHE_MEMORY_SIZE-1);
152*53ee8cc1Swenshuai.xi NCM_Dbg("Pages per pool is %d\n",ncmem_pool.pages_per_pool);
153*53ee8cc1Swenshuai.xi NCM_Dbg("Bit map base addr is %p\n",ncmem_pool.bitmap);
154*53ee8cc1Swenshuai.xi }
155*53ee8cc1Swenshuai.xi
156*53ee8cc1Swenshuai.xi /*******************************************************************************
157*53ee8cc1Swenshuai.xi * Routine name : ncmem_alloc_page
158*53ee8cc1Swenshuai.xi * returns : 0 - pointer to allocated virtual address
159*53ee8cc1Swenshuai.xi * dma_addr : pointer to allocated physical address
160*53ee8cc1Swenshuai.xi * Created by : Peter Liao
161*53ee8cc1Swenshuai.xi * Date created : 2004/01/25
162*53ee8cc1Swenshuai.xi * Description : It will allocate a new non-cacheable and non-bufferable memory
163*53ee8cc1Swenshuai.xi * (size = page_size) from non-cacheable page memory pool for callee
164*53ee8cc1Swenshuai.xi * PAGE_SIZE is defined in pci_mem.h file
165*53ee8cc1Swenshuai.xi * Notes :
166*53ee8cc1Swenshuai.xi *******************************************************************************/
ncmem_alloc_page(dma_addr_t * dma_addr)167*53ee8cc1Swenshuai.xi void *ncmem_alloc_page(dma_addr_t *dma_addr)
168*53ee8cc1Swenshuai.xi {
169*53ee8cc1Swenshuai.xi U32 i;
170*53ee8cc1Swenshuai.xi int map, page;
171*53ee8cc1Swenshuai.xi size_t offset;
172*53ee8cc1Swenshuai.xi void *retval;
173*53ee8cc1Swenshuai.xi U32 flags;
174*53ee8cc1Swenshuai.xi
175*53ee8cc1Swenshuai.xi spin_lock_irqsave (&pool->lock, flags);
176*53ee8cc1Swenshuai.xi /* only cachable accesses here ... */
177*53ee8cc1Swenshuai.xi for (map = 0, i = 0;
178*53ee8cc1Swenshuai.xi i < ncmem_pool.pages_per_pool;
179*53ee8cc1Swenshuai.xi i += BITS_PER_LONG, map++)
180*53ee8cc1Swenshuai.xi {
181*53ee8cc1Swenshuai.xi if (ncmem_pool.bitmap[map] == 0)
182*53ee8cc1Swenshuai.xi continue;
183*53ee8cc1Swenshuai.xi page = ffz (~ ncmem_pool.bitmap [map]);
184*53ee8cc1Swenshuai.xi if ((i + page) < ncmem_pool.pages_per_pool) {
185*53ee8cc1Swenshuai.xi clear_bit ( page, &ncmem_pool.bitmap [map],U32);
186*53ee8cc1Swenshuai.xi offset = (BITS_PER_LONG * map) + page;
187*53ee8cc1Swenshuai.xi offset *= PAGE_SIZE;
188*53ee8cc1Swenshuai.xi goto ready;
189*53ee8cc1Swenshuai.xi }
190*53ee8cc1Swenshuai.xi }
191*53ee8cc1Swenshuai.xi
192*53ee8cc1Swenshuai.xi NCM_Dbg("ERROR: No enough non-cached memory space !!%s\n","");
193*53ee8cc1Swenshuai.xi retval = 0;
194*53ee8cc1Swenshuai.xi goto done;
195*53ee8cc1Swenshuai.xi
196*53ee8cc1Swenshuai.xi ready:
197*53ee8cc1Swenshuai.xi retval = (void*) (offset + (size_t) (ncmem_pool.base_addr));
198*53ee8cc1Swenshuai.xi *dma_addr = (dma_addr_t)USB_VA2PA((U32)retval); // Convert to physical address for DMA
199*53ee8cc1Swenshuai.xi done:
200*53ee8cc1Swenshuai.xi spin_unlock_irqrestore (&pool->lock, flags);
201*53ee8cc1Swenshuai.xi NCM_Dbg("The allocated addr is %p, bit_map[%d] is 0x%08lX\n",retval,map,(U32)(ncmem_pool.bitmap[map]));
202*53ee8cc1Swenshuai.xi return retval;
203*53ee8cc1Swenshuai.xi }
204*53ee8cc1Swenshuai.xi
205*53ee8cc1Swenshuai.xi /*******************************************************************************
206*53ee8cc1Swenshuai.xi * Routine name : ncmem_free_page
207*53ee8cc1Swenshuai.xi * returns : none
208*53ee8cc1Swenshuai.xi * addr : allocated virtual base address
209*53ee8cc1Swenshuai.xi * Created by : Peter Liao
210*53ee8cc1Swenshuai.xi * Date created : 2004/01/25
211*53ee8cc1Swenshuai.xi * Description : It will de-allocate/release the allocated non-cacheable memory
212*53ee8cc1Swenshuai.xi * page to non-cacheable page memory pool.
213*53ee8cc1Swenshuai.xi * Notes :
214*53ee8cc1Swenshuai.xi *******************************************************************************/
ncmem_free_page(U32 addr)215*53ee8cc1Swenshuai.xi void ncmem_free_page(U32 addr)
216*53ee8cc1Swenshuai.xi {
217*53ee8cc1Swenshuai.xi U32 flags;
218*53ee8cc1Swenshuai.xi int map, page;
219*53ee8cc1Swenshuai.xi
220*53ee8cc1Swenshuai.xi page = addr - ncmem_pool.base_addr;
221*53ee8cc1Swenshuai.xi page /= PAGE_SIZE;
222*53ee8cc1Swenshuai.xi map = page / BITS_PER_LONG;
223*53ee8cc1Swenshuai.xi page %= BITS_PER_LONG;
224*53ee8cc1Swenshuai.xi spin_lock_irqsave (NULL, flags);
225*53ee8cc1Swenshuai.xi set_bit (page, &(ncmem_pool.bitmap[map]), U32);
226*53ee8cc1Swenshuai.xi NCM_Dbg("Free Block: bitmap[%d] is 0x%08lX",map,(U32)ncmem_pool.bitmap[map]);
227*53ee8cc1Swenshuai.xi spin_unlock_irqrestore (&pool->lock, flags);
228*53ee8cc1Swenshuai.xi }
229*53ee8cc1Swenshuai.xi /*******************************************************************************
230*53ee8cc1Swenshuai.xi * Routine name : ncmem_alloc
231*53ee8cc1Swenshuai.xi * returns : 0 - pointer to allocated virtual address
232*53ee8cc1Swenshuai.xi * dma_addr : pointer to allocated physical address
233*53ee8cc1Swenshuai.xi * Created by : Peter Liao
234*53ee8cc1Swenshuai.xi * Date created : 2004/02/10
235*53ee8cc1Swenshuai.xi * Description : It will allocate a new non-cacheable and non-bufferable memory
236*53ee8cc1Swenshuai.xi * (size = user specific) from non-cacheable page memory pool for callee
237*53ee8cc1Swenshuai.xi * Therefore, it may waste up memory space if the size is not mutiply
238*53ee8cc1Swenshuai.xi * of page size. Callee should call this function before calling
239*53ee8cc1Swenshuai.xi * ncmem_alloc_page because of continuous issue.
240*53ee8cc1Swenshuai.xi * Notes :
241*53ee8cc1Swenshuai.xi *******************************************************************************/
ncmem_alloc(dma_addr_t * dma_addr,U32 size)242*53ee8cc1Swenshuai.xi void *ncmem_alloc(dma_addr_t *dma_addr, U32 size)
243*53ee8cc1Swenshuai.xi {
244*53ee8cc1Swenshuai.xi U32 flags;
245*53ee8cc1Swenshuai.xi U32 i;
246*53ee8cc1Swenshuai.xi U32 map, page;
247*53ee8cc1Swenshuai.xi U32 num_of_pages;
248*53ee8cc1Swenshuai.xi size_t offset;
249*53ee8cc1Swenshuai.xi void *retval;
250*53ee8cc1Swenshuai.xi
251*53ee8cc1Swenshuai.xi //If the size is not multiply of PAGE_SIZE, just allocate a PAGE for remaining space
252*53ee8cc1Swenshuai.xi if ( size%PAGE_SIZE != 0)
253*53ee8cc1Swenshuai.xi size = size/PAGE_SIZE +1;
254*53ee8cc1Swenshuai.xi else
255*53ee8cc1Swenshuai.xi size = size/PAGE_SIZE;
256*53ee8cc1Swenshuai.xi num_of_pages = size/PAGE_SIZE;
257*53ee8cc1Swenshuai.xi spin_lock_irqsave (&pool->lock, flags);
258*53ee8cc1Swenshuai.xi /* only cachable accesses here ... */
259*53ee8cc1Swenshuai.xi for (map = 0, i = 0;
260*53ee8cc1Swenshuai.xi i < ncmem_pool.pages_per_pool;
261*53ee8cc1Swenshuai.xi i += BITS_PER_LONG, map++)
262*53ee8cc1Swenshuai.xi {
263*53ee8cc1Swenshuai.xi if (ncmem_pool.bitmap[map] == 0)
264*53ee8cc1Swenshuai.xi continue;
265*53ee8cc1Swenshuai.xi page = ffz (~ ncmem_pool.bitmap [map]);
266*53ee8cc1Swenshuai.xi if ((i + page) < ncmem_pool.pages_per_pool) {
267*53ee8cc1Swenshuai.xi offset = (BITS_PER_LONG * map) + page;
268*53ee8cc1Swenshuai.xi offset *= PAGE_SIZE;
269*53ee8cc1Swenshuai.xi goto ready;
270*53ee8cc1Swenshuai.xi }
271*53ee8cc1Swenshuai.xi }
272*53ee8cc1Swenshuai.xi NCM_Dbg("ERROR: No enough non-cached memory space !!%s\n","");
273*53ee8cc1Swenshuai.xi retval = 0;
274*53ee8cc1Swenshuai.xi goto done;
275*53ee8cc1Swenshuai.xi
276*53ee8cc1Swenshuai.xi ready:
277*53ee8cc1Swenshuai.xi //Allocate enough pages for required memory space
278*53ee8cc1Swenshuai.xi for(i=0;(i < num_of_pages);i++)
279*53ee8cc1Swenshuai.xi {
280*53ee8cc1Swenshuai.xi if ( page >= BITS_PER_LONG )
281*53ee8cc1Swenshuai.xi {
282*53ee8cc1Swenshuai.xi page = 0;
283*53ee8cc1Swenshuai.xi map++;
284*53ee8cc1Swenshuai.xi }
285*53ee8cc1Swenshuai.xi clear_bit ( page++, &ncmem_pool.bitmap [map],U32);
286*53ee8cc1Swenshuai.xi }
287*53ee8cc1Swenshuai.xi retval = (void*) (offset + (size_t) (ncmem_pool.base_addr));
288*53ee8cc1Swenshuai.xi *dma_addr = (dma_addr_t)USB_VA2PA((U32)retval);
289*53ee8cc1Swenshuai.xi done:
290*53ee8cc1Swenshuai.xi spin_unlock_irqrestore (&pool->lock, flags);
291*53ee8cc1Swenshuai.xi NCM_Dbg("The allocated addr = %p, size = %ld pages = %ld, end of bitmap[%ld]=0x%08lX",retval ,size, num_of_pages, map,(U32)ncmem_pool.bitmap[map]);
292*53ee8cc1Swenshuai.xi return retval;
293*53ee8cc1Swenshuai.xi }
294*53ee8cc1Swenshuai.xi
295*53ee8cc1Swenshuai.xi /*******************************************************************************
296*53ee8cc1Swenshuai.xi * Routine name : ncmem_free
297*53ee8cc1Swenshuai.xi * returns : none
298*53ee8cc1Swenshuai.xi * addr : allocated virtual base address
299*53ee8cc1Swenshuai.xi * size : allocated size
300*53ee8cc1Swenshuai.xi * Created by : Peter Liao
301*53ee8cc1Swenshuai.xi * Date created : 2004/02/10
302*53ee8cc1Swenshuai.xi * Description : It will de-allocate/release the allocated non-cacheable memory
303*53ee8cc1Swenshuai.xi * space groupged by pages.
304*53ee8cc1Swenshuai.xi * Notes :
305*53ee8cc1Swenshuai.xi *******************************************************************************/
ncmem_free(U32 addr,U32 size)306*53ee8cc1Swenshuai.xi void ncmem_free(U32 addr,U32 size)
307*53ee8cc1Swenshuai.xi {
308*53ee8cc1Swenshuai.xi U32 flags;
309*53ee8cc1Swenshuai.xi int i;
310*53ee8cc1Swenshuai.xi int map, page, num_of_pages;
311*53ee8cc1Swenshuai.xi
312*53ee8cc1Swenshuai.xi if ( size%PAGE_SIZE != 0)
313*53ee8cc1Swenshuai.xi size = size/PAGE_SIZE +1;
314*53ee8cc1Swenshuai.xi else
315*53ee8cc1Swenshuai.xi size = size/PAGE_SIZE;
316*53ee8cc1Swenshuai.xi num_of_pages = size/PAGE_SIZE;
317*53ee8cc1Swenshuai.xi
318*53ee8cc1Swenshuai.xi page = ncmem_pool.base_addr - addr;
319*53ee8cc1Swenshuai.xi page /= PAGE_SIZE;
320*53ee8cc1Swenshuai.xi map = page / BITS_PER_LONG;
321*53ee8cc1Swenshuai.xi page %= BITS_PER_LONG;
322*53ee8cc1Swenshuai.xi spin_lock_irqsave (&pool->lock, flags);
323*53ee8cc1Swenshuai.xi for(i=0;(i < num_of_pages);i++)
324*53ee8cc1Swenshuai.xi {
325*53ee8cc1Swenshuai.xi if ( page >= BITS_PER_LONG )
326*53ee8cc1Swenshuai.xi {
327*53ee8cc1Swenshuai.xi page = 0;
328*53ee8cc1Swenshuai.xi map++;
329*53ee8cc1Swenshuai.xi }
330*53ee8cc1Swenshuai.xi set_bit (page, &(ncmem_pool.bitmap[map]), U32);
331*53ee8cc1Swenshuai.xi }
332*53ee8cc1Swenshuai.xi NCM_Dbg("Free non-cacheable memory : size = %ld = %d pages, end of bitmap[%d]=0x%08lX",size, num_of_pages, map,(U32)ncmem_pool.bitmap[map]);
333*53ee8cc1Swenshuai.xi spin_unlock_irqrestore (&pool->lock, flags);
334*53ee8cc1Swenshuai.xi }
335*53ee8cc1Swenshuai.xi
Destory_NC_mem(void)336*53ee8cc1Swenshuai.xi void Destory_NC_mem(void)
337*53ee8cc1Swenshuai.xi {
338*53ee8cc1Swenshuai.xi #if 0
339*53ee8cc1Swenshuai.xi LIB_MemoryFree((void*) ncmem_base);
340*53ee8cc1Swenshuai.xi #else
341*53ee8cc1Swenshuai.xi //MsOS_FreeMemory((void*)CYGARC_CACHED_ADDRESS( ncmem_addr),gs32NonCachedPoolID_MIU0 );
342*53ee8cc1Swenshuai.xi Usb_FreeNonCachedMemory((void*)CYGARC_CACHED_ADDRESS( ncmem_addr));
343*53ee8cc1Swenshuai.xi #endif
344*53ee8cc1Swenshuai.xi }
345*53ee8cc1Swenshuai.xi
346*53ee8cc1Swenshuai.xi extern void MsOS_FlushMemory(void);
Chip_Flush_Memory(void)347*53ee8cc1Swenshuai.xi void Chip_Flush_Memory(void)
348*53ee8cc1Swenshuai.xi {
349*53ee8cc1Swenshuai.xi MsOS_FlushMemory();
350*53ee8cc1Swenshuai.xi }
351*53ee8cc1Swenshuai.xi
352*53ee8cc1Swenshuai.xi #endif //#ifdef
353*53ee8cc1Swenshuai.xi
354