1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 #ifndef DRV_USBHOST_CONFIG_H 79 #define DRV_USBHOST_CONFIG_H 80 81 #include <MsIRQ.h> 82 #include <drvUSB_eCos.h> // for root hub support only, applying the configuration 83 84 #define ECOS_USB_HOST_LOCAL_VER "20170310" 85 86 /*** eCos USB Host driver exclusive default setting ***/ 87 #define URB_TIMEOUT_BY_WAIT_EVENT 88 89 //#define USB_EHCI_TT 90 91 #define ECOS_XHC_COMPANION_SUPPORT 92 93 //#define ENABLE_LEGACY_CACHE_SETTING 94 95 #define ENABLE_DISCONNECT_FAST_RESPONSE 96 97 /* 20140630 quick response for file read/write root hub disconnected */ 98 #define ENABLE_RW_DISCONNECTING 99 100 #define ENABLE_ROOTHUB_DISCONN_REINIT 101 102 /* 20140715 maximum hub top level to restric hub_probe */ 103 #ifdef USB_NOT_SUPPORT_EX_HUB 104 #define MAX_HUB_TOPO_LEVEL 1 105 #else 106 #define MAX_HUB_TOPO_LEVEL 6 107 #endif 108 109 /*** Definition by chip attribute ***/ 110 //#define CPU_TYPE_AEON 111 #if defined(CHIP_KAISER) || \ 112 defined(CHIP_CLIPPERS) || \ 113 defined(CHIP_KANO) || \ 114 defined(CHIP_K6) || \ 115 defined(CHIP_CURRY) || \ 116 defined(CHIP_K6LITE) 117 #define CPU_TYPE_ARM 118 #else 119 #define CPU_TYPE_MIPS 120 #endif 121 122 #if defined(CPU_TYPE_AEON) 123 #define OS_BASE_ADDR 0xa0000000 124 #elif defined(CPU_TYPE_MIPS) // U4, K1, K2 125 #if defined(TITANIA2_SERIAL_USE) 126 #define OS_BASE_ADDR 0xbf800000 127 #else 128 #define OS_BASE_ADDR 0xbf200000 129 #endif 130 #define _MSTAR_PM_BASE 0xbf000000 131 #define MIPS_TOOLCHAIN_482_ISSUE 132 #define MIPS_L1_CACHE_SIZE 32 133 #elif defined(CPU_TYPE_ARM) // K3 134 #define OS_BASE_ADDR 0xfd200000 135 #define _MSTAR_PM_BASE 0xfd000000 136 #define MIPS_L1_CACHE_SIZE 32 137 #else 138 #No CPU type for USB 139 #endif 140 141 #ifdef ENABLE_LEGACY_CACHE_SETTING 142 #define CPU_L1_CACHE_BOUND (15) 143 #else 144 #define CPU_L1_CACHE_BOUND (MIPS_L1_CACHE_SIZE-1) 145 #endif 146 147 #define KAISERIN_CHIP_TOP_BASE (OS_BASE_ADDR+(0x1E00*2)) 148 149 #define BASE_USBBC_NULL (0) 150 151 /****** USB port RIU base address ******/ 152 /* port 0 */ 153 #define BASE_UTMI0 (OS_BASE_ADDR+(0x3A80*2)) 154 #define BASE_UHC0 (OS_BASE_ADDR+(0x2400*2)) 155 #define BASE_USBC0 (OS_BASE_ADDR+(0x0700*2)) 156 #define BASE_USBBC0_KAPPA (OS_BASE_ADDR+(0x20500*2)) 157 #define BASE_USBBC0_KIWI (OS_BASE_ADDR+(0x20500*2)) 158 #define BASE_USBBC0_KELTIC (OS_BASE_ADDR+(0x11700*2)) 159 #define BASE_USBBC0_KRATOS (OS_BASE_ADDR+(0x20500*2)) 160 #define BASE_USBBC0_KENYA (OS_BASE_ADDR+(0x205E0*2)) 161 #define BASE_USBBC0_KAISER (OS_BASE_ADDR+(0x22F00*2)) 162 #define BASE_USBBC0_KERES (OS_BASE_ADDR+(0x13700*2)) 163 #define BASE_USBBC0_CLIPPERS (OS_BASE_ADDR+(0x23600*2)) 164 #define BASE_USBBC0_KANO BASE_USBBC0_KERES 165 #define BASE_USBBC0_K6 BASE_USBBC0_KERES 166 #define BASE_USBBC0_CURRY BASE_USBBC0_KERES 167 #define BASE_USBBC0_K6LITE BASE_USBBC0_CLIPPERS 168 #define E_IRQ_UHC (E_INT_IRQ_UHC) 169 #define E_IRQ_USBC (E_INT_IRQ_USB) 170 171 /* port 1 */ 172 #define BASE_UTMI1 (OS_BASE_ADDR+(0x3A00*2)) 173 #define BASE_UHC1 (OS_BASE_ADDR+(0x0D00*2)) 174 #define BASE_USBC1 (OS_BASE_ADDR+(0x0780*2)) 175 #define BASE_USBBC1_KENYA (OS_BASE_ADDR+(0x205C0*2)) 176 #define BASE_USBBC1_KAISER (OS_BASE_ADDR+(0x22F40*2)) 177 #define BASE_USBBC1_KERES (OS_BASE_ADDR+(0x13740*2)) 178 #define BASE_USBBC1_KRATOS (OS_BASE_ADDR+(0x20540*2)) 179 #define BASE_USBBC1_CLIPPERS (OS_BASE_ADDR+(0x23620*2)) 180 #define BASE_USBBC1_KIWI (OS_BASE_ADDR+(0x20540*2)) 181 #define BASE_USBBC1_KANO (OS_BASE_ADDR+(0x13720*2)) 182 #define BASE_USBBC1_K6 BASE_USBBC1_KERES 183 #define BASE_USBBC1_CURRY BASE_USBBC1_KANO 184 #define BASE_USBBC1_K6LITE BASE_USBBC1_CLIPPERS 185 #define E_IRQ_UHC1 (E_INT_IRQ_UHC1) 186 #define E_IRQ_USBC1 (E_INT_IRQ_USB1) 187 188 /* port 2 */ 189 #define BASE_UTMI2 (OS_BASE_ADDR+(0x2A00*2)) 190 #define BASE_UTMI2_CLIPPERS (OS_BASE_ADDR+(0x3900*2)) 191 #define BASE_UTMI2_KANO BASE_UTMI2_CLIPPERS 192 #define BASE_UTMI2_CURRY BASE_UTMI2_CLIPPERS 193 #define BASE_UTMI2_K6 (OS_BASE_ADDR+(0x3800*2)) 194 #define BASE_UTMI2_K6LITE BASE_UTMI2_K6 195 #define BASE_UHC2 (OS_BASE_ADDR+(0x10300*2)) 196 #define BASE_UHC2_CLIPPERS (OS_BASE_ADDR+(0x13900*2)) 197 #define BASE_UHC2_K6 (OS_BASE_ADDR+(0x40400*2)) 198 #define BASE_UHC2_K6LITE BASE_UHC2_CLIPPERS 199 #define BASE_USBC2 (OS_BASE_ADDR+(0x10200*2)) 200 #define BASE_USBC2_CLIPPERS (OS_BASE_ADDR+(0x13800*2)) 201 #define BASE_USBC2_K6 (OS_BASE_ADDR+(0x40600*2)) 202 #define BASE_USBC2_K6LITE BASE_USBC2_CLIPPERS 203 #define BASE_USBBC2_KAISER (OS_BASE_ADDR+(0x22F80*2)) 204 #define BASE_USBBC2_CLIPPERS (OS_BASE_ADDR+(0x23640*2)) 205 #define BASE_USBBC2_KANO (OS_BASE_ADDR+(0x13740*2)) 206 #define BASE_USBBC2_K6 (OS_BASE_ADDR+(0x13780*2)) 207 #define BASE_USBBC2_CURRY BASE_USBBC2_KANO 208 #define BASE_USBBC2_K6LITE BASE_USBBC2_CLIPPERS 209 #define E_IRQ_UHC2 (E_INT_IRQ_UHC2) 210 #define E_IRQ_USBC2 (E_INT_IRQ_USB2) 211 #define E_IRQ_UHC2_K6 (E_INT_IRQ_USB30_HS_UHC_INT) 212 #define E_IRQ_USBC2_K6 (E_INT_IRQ_USB30_HS_USB_INT) 213 214 /* port 3 */ 215 #define BASE_UTMI3 (OS_BASE_ADDR+(0x20A00*2)) 216 #define BASE_UTMI3_KANO (OS_BASE_ADDR+(0x3800*2)) 217 #define BASE_UHC3 (OS_BASE_ADDR+(0x20900*2)) 218 #define BASE_UHC3_KANO (OS_BASE_ADDR+(0x40400*2)) 219 #define BASE_USBC3 (OS_BASE_ADDR+(0x20800*2)) 220 #define BASE_USBC3_KANO (OS_BASE_ADDR+(0x40600*2)) 221 #define BASE_USBBC3_KANO (OS_BASE_ADDR+(0x13780*2)) 222 #define E_IRQ_UHC3 (E_INT_IRQ_UHC3) 223 #define E_IRQ_USBC3 (E_INT_IRQ_USB3) 224 #define E_IRQ_UHC3_KANO (E_INT_IRQ_USB30_HS_UHC_INT) 225 #define E_IRQ_USBC3_KANO (E_INT_IRQ_USB30_HS_USB_INT) 226 227 /* port 4 */ 228 #define BASE_UTMI4_KANO (OS_BASE_ADDR+(0x03880*2)) 229 #define BASE_UHC4_KANO (OS_BASE_ADDR+(0x40500*2)) 230 #define BASE_USBC4_KANO (OS_BASE_ADDR+(0x40680*2)) 231 #define BASE_USBBC4_KANO (OS_BASE_ADDR+(0x137a0*2)) 232 #define E_IRQ_UHC4 (E_INT_IRQ_UHC4) 233 #define E_IRQ_USBC4 (E_INT_IRQ_USB4) 234 #define E_IRQ_UHC4_KANO (E_INT_IRQ_USB30_HS1_UHC_INT) 235 #define E_IRQ_USBC4_KANO (E_INT_IRQ_USB30_HS1_USB_INT) 236 237 /* struct xhc_comp */ 238 #ifdef ECOS_XHC_COMPANION_SUPPORT 239 #if defined(CHIP_KANO) || \ 240 defined(CHIP_K6) 241 #define ENABLE_XHC_COMPANION 242 #define XHC_COMP_NONE {0, 0, 0, 0, 0} 243 #define XHCI_SINGLE_PORT_ENABLE_MAC 244 #define XHCI_ENABLE_PD_OVERRIDE 245 #endif 246 #endif 247 248 #if defined(CHIP_KANO) 249 #define XHCI_PORT0_ADDR (OS_BASE_ADDR+(0xc0000<<1)+0x0440) 250 #define XHCI_PORT1_ADDR (OS_BASE_ADDR+(0xc0000<<1)+0x0450) 251 #define MSTAR_U3TOP_BASE (OS_BASE_ADDR+(0x40200*2)) 252 #define MSTAR_U3PHY_P0_A_BASE (OS_BASE_ADDR+(0x02100 << 1)) 253 #define MSTAR_U3PHY_P0_D_BASE (OS_BASE_ADDR+(0x02000 << 1)) 254 #define MSTAR_U3PHY_P1_A_BASE (OS_BASE_ADDR+(0x02300 << 1)) 255 #define MSTAR_U3PHY_P1_D_BASE (OS_BASE_ADDR+(0x02200 << 1)) 256 #define XHC_COMP_PORT0 {0, XHCI_PORT0_ADDR, MSTAR_U3TOP_BASE, MSTAR_U3PHY_P0_A_BASE, MSTAR_U3PHY_P0_D_BASE} 257 #define XHC_COMP_PORT1 {1, XHCI_PORT1_ADDR, MSTAR_U3TOP_BASE, MSTAR_U3PHY_P1_A_BASE, MSTAR_U3PHY_P1_D_BASE} 258 #elif defined(CHIP_K6) 259 #define XHCI_PORT0_ADDR (OS_BASE_ADDR+(0xf0000<<1)+0x0430) 260 #define MSTAR_U3TOP_BASE (OS_BASE_ADDR+(0x40200*2)) 261 #define MSTAR_U3PHY_P0_A_BASE (OS_BASE_ADDR+(0x02100 << 1)) 262 #define MSTAR_U3PHY_P0_D_BASE (OS_BASE_ADDR+(0x02000 << 1)) 263 #define XHC_COMP_PORT0 {0, XHCI_PORT0_ADDR, MSTAR_U3TOP_BASE, MSTAR_U3PHY_P0_A_BASE, MSTAR_U3PHY_P0_D_BASE} 264 #endif 265 266 /* define UHC port enable */ 267 /* two ports is default, else extra needs to be defined */ 268 #if defined(CHIP_U4) || \ 269 defined(CHIP_K2) || \ 270 defined(CHIP_KAISER) || \ 271 defined(CHIP_CLIPPERS) || \ 272 defined(CHIP_KANO) || \ 273 defined(CHIP_K6) || \ 274 defined(CHIP_CURRY) || \ 275 defined(CHIP_K6LITE) 276 #define ENABLE_THIRD_EHC 277 #endif 278 279 #if defined(CHIP_K2) || \ 280 (defined(CHIP_KANO) && defined(ENABLE_XHC_COMPANION)) 281 #define ENABLE_FOURTH_EHC 282 #endif 283 284 #if (defined(CHIP_KANO) && defined(ENABLE_XHC_COMPANION)) 285 #define ENABLE_FIFTH_EHC 286 #endif 287 288 #if (defined(CHIP_KANO) && defined(ENABLE_XHC_COMPANION)) 289 #define NUM_OF_ROOT_HUB 5 290 #elif defined(CHIP_K2) 291 #define NUM_OF_ROOT_HUB 4 292 #elif defined(CHIP_U4) || \ 293 defined(CHIP_KAISER) || \ 294 defined(CHIP_CLIPPERS) || \ 295 defined(CHIP_KANO) || \ 296 (defined(CHIP_K6) && defined(ENABLE_XHC_COMPANION)) || \ 297 defined(CHIP_CURRY) || \ 298 defined(CHIP_K6LITE) 299 #define NUM_OF_ROOT_HUB 3 300 #else 301 #define NUM_OF_ROOT_HUB 2 302 #endif 303 304 //------ Hardware ECO enable switch ---------------------------------- 305 //---- 1. fix pv2mi bridge mis-behavior, list chip before Kris 306 #if defined(CHIP_KAPPA) || \ 307 defined(CHIP_KELTIC) || \ 308 defined(CHIP_KENYA) || \ 309 defined(CHIP_KRITI) || \ 310 defined(CHIP_CLIPPERS) || \ 311 defined(CHIP_KERES) || \ 312 defined(CHIP_KIRIN) || \ 313 defined(CHIP_KRIS) 314 #define ENABLE_PV2MI_BRIDGE_ECO 315 #endif 316 317 //---- 2. Reduce EOF1 to 16us for performance imporvement 318 #if !defined(CHIP_U4) && !defined(CHIP_K1) && !defined(CHIP_K2) 319 /* Enlarge EOF1 from 12us to 16us for babble prvention under hub case. 320 * However, we keep the "old config name". 20130121 321 */ 322 #define ENABLE_16US_EOF1 323 #endif 324 325 //---- 3. Enable UTMI 240 as 120 phase 326 #if !defined(CHIP_U4) && !defined(CHIP_K1) && !defined(CHIP_K2) 327 #define ENABLE_UTMI_240_AS_120_PHASE_ECO 328 #endif 329 330 //---- 4. Change to 55 interface 331 #if !defined(CHIP_U4) && !defined(CHIP_K1) && !defined(CHIP_K2) 332 #define ENABLE_UTMI_55_INTERFACE 333 #endif 334 335 //---- 5. tx/rx reset clock gating cause XIU timeout 336 #if !defined(CHIP_U4) && \ 337 !defined(CHIP_K1) && \ 338 !defined(CHIP_K2) 339 #define ENABLE_TX_RX_RESET_CLK_GATING_ECO 340 #endif 341 342 //---- 6. Setting PV2MI bridge read/write burst size to minimum 343 #if 0 // every chip must apply it, so far 344 #define _USB_MINI_PV2MI_BURST_SIZE 0 345 #else 346 #define _USB_MINI_PV2MI_BURST_SIZE 1 347 #endif 348 349 //---- 7. HS connection fail problem (Gate into VFALL state) 350 #if defined(CHIP_KELTIC) || \ 351 defined(CHIP_KERES) || \ 352 defined(CHIP_KIRIN) || \ 353 defined(CHIP_KRIS) || \ 354 defined(CHIP_KAYLA) || \ 355 defined(CHIP_CLIPPERS) || \ 356 defined(CHIP_KRATOS) || \ 357 defined(CHIP_KIWI) || \ 358 defined(CHIP_KANO) || \ 359 defined(CHIP_K6) || \ 360 defined(CHIP_CURRY) || \ 361 defined(CHIP_K6LITE) || \ 362 defined(CHIP_K5TN) 363 #define ENABLE_HS_CONNECTION_FAIL_INTO_VFALL_ECO 364 #endif 365 366 //---- 8. Enable UHC Preamble ECO function 367 #if defined(CHIP_KIWI) || \ 368 defined(CHIP_KRATOS) || \ 369 defined(CHIP_KAYLA) || \ 370 defined(CHIP_KANO) || \ 371 defined(CHIP_K6) || \ 372 defined(CHIP_CURRY) || \ 373 defined(CHIP_K6LITE) || \ 374 defined(CHIP_K5TN) 375 #define ENABLE_UHC_PREAMBLE_ECO 376 #endif 377 378 //---- 9. Enable HS ISO IN Camera Cornor case ECO function 379 #if defined(CHIP_KRATOS) || \ 380 defined(CHIP_KIWI) || \ 381 defined(CHIP_KAYLA) || \ 382 defined(CHIP_KANO) || \ 383 defined(CHIP_K6) || \ 384 defined(CHIP_CURRY) || \ 385 defined(CHIP_K6LITE) || \ 386 defined(CHIP_K5TN) 387 #define ENABLE_HS_ISO_IN_CORNER_ECO 388 #endif 389 390 //---- 10. Don't close RUN bit when device disconnect, default enable after KIWI 391 #if defined(CHIP_KERES) || \ 392 defined(CHIP_CLIPPERS) || \ 393 defined(CHIP_KIRIN) || \ 394 defined(CHIP_KRIS) || \ 395 defined(CHIP_KRATOS) || \ 396 defined(CHIP_KANO) 397 #define ENABLE_UHC_RUN_BIT_ALWAYS_ON_ECO 398 #endif 399 400 //---- 11. Port is disabled when device is dosconnected 401 #if 0 // no chip must apply it, it can't work with RUN_BIT_ALWAYS_ON_ECO 402 #define ENABLE_DISCONNECT_PE_CLR_ECO 403 #endif 404 405 //---- 12. 406 #if defined(CHIP_KRITI) 407 #define ENABLE_HS_DISCONNECTION_DEBOUNCE_ECO 408 #endif 409 410 //---- 13. UHC speed type report should be reset by device disconnection 411 #if defined(CHIP_K6LITE) || \ 412 defined(CHIP_K5TN) 413 #define ENABLE_DISCONNECT_SPEED_REPORT_RESET_ECO 414 #endif 415 416 //---- 14. Port Change Detect (PCD) is triggered by babble. Pulse trigger will not hang this condition. 417 /* 1'b0: level trigger 418 * 1'b1: one-pulse trigger 419 */ 420 #if defined(CHIP_K6LITE) || \ 421 defined(CHIP_K5TN) 422 #define ENABLE_BABBLE_PCD_ONE_PULSE_TRIGGER_ECO 423 #endif 424 425 //---- 15. generation of hhc_reset_u 426 /* 1'b0: hhc_reset is_u double sync of hhc_reset 427 * 1'b1: hhc_reset_u is one-pulse of hhc_reset 428 */ 429 #if defined(CHIP_K6LITE) || \ 430 defined(CHIP_K5TN) 431 #define ENABLE_HC_RESET_FAIL_ECO 432 #endif 433 434 //---- 16. Do SRAM clock gating automatically to save power */ 435 #if defined(CHIP_K6LITE) || \ 436 defined(CHIP_K5TN) 437 #define ENABLE_SRAM_CLK_GATING_ECO 438 #endif 439 440 //------ Software patch enable switch ---------------------------------- 441 //---- 1. Monkey Test software Patch 442 #if defined(CHIP_U4) || defined(CHIP_K1) || defined(CHIP_K2) 443 #define _USB_HS_CUR_DRIVE_DM_ALLWAYS_HIGH_PATCH 1 444 #else 445 #define _USB_HS_CUR_DRIVE_DM_ALLWAYS_HIGH_PATCH 0 446 #endif 447 448 //---- 2. Clock phase adjustment software Patch 449 #if defined(CHIP_KERES) 450 #define _USB_CLOCK_PHASE_ADJ_PATCH 1 451 #else 452 #define _USB_CLOCK_PHASE_ADJ_PATCH 0 453 #endif 454 455 //---- 3. enabe PVCI i_miwcplt wait for mi2uh_last_done_z 456 #if defined(CHIP_KERES) || \ 457 defined(CHIP_KIRIN) || \ 458 defined(CHIP_KRIS) || \ 459 defined(CHIP_KAYLA) || \ 460 defined(CHIP_CLIPPERS) || \ 461 defined(CHIP_KRATOS) || \ 462 defined(CHIP_KIWI) || \ 463 defined(CHIP_KANO) || \ 464 defined(CHIP_K6) || \ 465 defined(CHIP_CURRY) || \ 466 defined(CHIP_K6LITE) || \ 467 defined(CHIP_K5TN) 468 #define _USB_MIU_WRITE_WAIT_LAST_DONE_Z_PATCH 1 469 #else 470 #define _USB_MIU_WRITE_WAIT_LAST_DONE_Z_PATCH 0 471 #endif 472 473 //---- 4. data structure (qtd ,...) must be 128-byte aligment 474 #define _USB_128_ALIGMENT 1 475 476 //---- 5. OBF application should enable BDMA function to move QH head 477 #if defined(CHIP_K6) || \ 478 defined(CHIP_CURRY) || \ 479 defined(CHIP_KANO) 480 #define _USB_ENABLE_BDMA_PATCH 481 #define EHCI_CHECK_MIU1 1 482 #if defined(CHIP_CURRY) || \ 483 defined(CHIP_KANO) 484 #define EHCI_CHECK_ECO_VER 1 485 #endif 486 #ifdef CHIP_CURRY 487 #define CHIP_BDMA_ECO_VER 0x2 488 #endif 489 #ifdef CHIP_KANO 490 #define CHIP_BDMA_ECO_VER 0x3 491 #endif 492 #endif 493 494 #ifdef _USB_ENABLE_BDMA_PATCH 495 #define MIU0_RIU_BASE (_MSTAR_PM_BASE+0x101200*2) 496 #define MIU1_RIU_BASE (_MSTAR_PM_BASE+0x100600*2) 497 #define MIU_DRAMOBF_READY_OFFSET (0x2a*2) 498 #define MIU_DRAMOBF_READY_BIT (1 << 15) 499 #define MIU_64BIT_CIPHER_OFFSET (0xd8*2) 500 #define MIU_64BIT_CIPHER_BIT (1 << 10) 501 502 #ifdef EHCI_CHECK_ECO_VER 503 #define CHIP_VER_TOP (_MSTAR_PM_BASE+0x1E00*2) 504 #define CHIP_VER_OFFSET (0xCE*2) 505 #define CHIP_VER_SHIFT 8 506 #define CHIP_VER_MASK 0xff 507 #endif 508 #endif 509 //----------------------------------------- 510 // U4_series_usb_init flag: 511 // Use low word as flag 512 #define EHCFLAG_NONE 0x0 513 #define EHCFLAG_DPDM_SWAP 0x1 514 #define EHCFLAG_TESTPKG 0x2 515 #define EHCFLAG_DOUBLE_DATARATE 0x4 516 #define EHCFLAG_USBBC_OFF 0x8 517 #define EHCFLAF_XHC_COMP 0x10 518 // Use high word as data 519 #define EHCFLAG_DDR_MASK 0xF0000000 520 #define EHCFLAG_DDR_x15 0x10000000 //480MHz x1.5 521 #define EHCFLAG_DDR_x18 0x20000000 //480MHz x1.8 522 //----------------------------------------- 523 524 #define HUB_STACK_SIZE 0x2000 525 526 #ifndef MSTAR_USB_DEBUG 527 #define MSTAR_USB_DEBUG 0 528 #endif 529 530 /* Debug print definition */ 531 #define DBG_MSG 532 //#define DBG_WARN 533 //#define DBG_FUNC 534 //#define DBG_DEBUG 535 #define DBG_ERR 536 537 #undef ms_debug_msg 538 #undef ms_debug_warn 539 #undef ms_debug_err 540 #undef ms_debug_func 541 #undef ms_debug_debug 542 543 #ifdef DBG_MSG 544 #define ms_debug_msg(fmt, arg...) \ 545 do {diag_printf(fmt, ##arg);} while(0) 546 #else 547 #define ms_debug_msg(fmt, arg...) do {} while (0) 548 #endif 549 550 #ifdef DBG_DEBUG 551 #define ms_debug_debug(fmt, arg...) \ 552 do {diag_printf(fmt, ##arg);} while(0) 553 #else 554 #define ms_debug_debug(fmt, arg...) do {} while (0) 555 #endif 556 557 #ifdef DBG_WARN 558 #define ms_debug_warn(fmt, arg...) \ 559 do {diag_printf(fmt, ##arg);} while(0) 560 #else 561 #define ms_debug_warn(fmt, arg...) do {} while (0) 562 #endif 563 564 #ifdef DBG_ERR 565 #define ms_debug_err(fmt, arg...) \ 566 do {diag_printf(fmt, ##arg);} while(0) 567 #else 568 #define ms_debug_err(fmt, arg...) do {} while (0) 569 #endif 570 571 #ifdef DBG_FUNC 572 #define ms_debug_func(fmt, arg...) \ 573 do {diag_printf(fmt, ##arg);} while(0) 574 #else 575 #define ms_debug_func(fmt, arg...) do {} while (0) 576 #endif 577 578 #define ms_usbhost_msg ms_debug_msg 579 #define ms_usbhost_warn ms_debug_warn 580 #define ms_usbhost_debug ms_debug_debug 581 #define ms_usbhost_err ms_debug_err 582 583 //------ UTMI disconnect level parameters --------------------------------- 584 // 0x00: 550mv, 0x20: 575, 0x40: 600, 0x60: 625 585 #if defined(CHIP_KIWI) || \ 586 defined(CHIP_KAYLA) || \ 587 defined(CHIP_KRATOS) || \ 588 defined(CHIP_KANO) || \ 589 defined(CHIP_K6) || \ 590 defined(CHIP_CURRY) || \ 591 defined(CHIP_K6LITE) || \ 592 defined(CHIP_K5TN) 593 #define UTMI_DISCON_LEVEL_2A (0x60) 594 #else 595 #define UTMI_DISCON_LEVEL_2A (0x0) 596 #endif 597 598 //------ UTMI eye diagram parameters --------------------------------- 599 #if 0 600 // for 40nm 601 #define UTMI_EYE_SETTING_2C (0x98) 602 #define UTMI_EYE_SETTING_2D (0x02) 603 #define UTMI_EYE_SETTING_2E (0x10) 604 #define UTMI_EYE_SETTING_2F (0x01) 605 #elif 0 606 // for 40nm after Agate, use 55nm setting7 607 #define UTMI_EYE_SETTING_2C (0x90) 608 #define UTMI_EYE_SETTING_2D (0x03) 609 #define UTMI_EYE_SETTING_2E (0x30) 610 #define UTMI_EYE_SETTING_2F (0x81) 611 #elif 0 612 // for 40nm after Agate, use 55nm setting6 613 #define UTMI_EYE_SETTING_2C (0x10) 614 #define UTMI_EYE_SETTING_2D (0x03) 615 #define UTMI_EYE_SETTING_2E (0x30) 616 #define UTMI_EYE_SETTING_2F (0x81) 617 #elif 0 618 // for 40nm after Agate, use 55nm setting5 619 #define UTMI_EYE_SETTING_2C (0x90) 620 #define UTMI_EYE_SETTING_2D (0x02) 621 #define UTMI_EYE_SETTING_2E (0x30) 622 #define UTMI_EYE_SETTING_2F (0x81) 623 #elif 0 624 // for 40nm after Agate, use 55nm setting4 625 #define UTMI_EYE_SETTING_2C (0x90) 626 #define UTMI_EYE_SETTING_2D (0x03) 627 #define UTMI_EYE_SETTING_2E (0x00) 628 #define UTMI_EYE_SETTING_2F (0x81) 629 #elif 0 630 // for 40nm after Agate, use 55nm setting3 631 #define UTMI_EYE_SETTING_2C (0x10) 632 #define UTMI_EYE_SETTING_2D (0x03) 633 #define UTMI_EYE_SETTING_2E (0x00) 634 #define UTMI_EYE_SETTING_2F (0x81) 635 #elif defined(CHIP_KENYA) || \ 636 defined(CHIP_KAISER) || \ 637 defined(CHIP_KELTIC) 638 #if defined(CHIP_KENYA) 639 // for 40nm after Agate, use 55nm special setting2 640 // STB chips only to deal with bad Dev 641 // - Manufacturer:"HP" Product:"v220w" 642 // - VID:0x3f0 PID:0x5a07 643 #define UTMI_EYE_SETTING_2C (0x90) 644 #define UTMI_EYE_SETTING_2D (0x02) 645 #define UTMI_EYE_SETTING_2E (0x00) 646 #define UTMI_EYE_SETTING_2F (0x01) 647 #else 648 // for 40nm after Agate, use 55nm setting2 649 #define UTMI_EYE_SETTING_2C (0x90) 650 #define UTMI_EYE_SETTING_2D (0x02) 651 #define UTMI_EYE_SETTING_2E (0x00) 652 #define UTMI_EYE_SETTING_2F (0x81) 653 #endif 654 #else 655 #if defined(CHIP_KERES) || \ 656 defined(CHIP_KIRIN) || \ 657 defined(CHIP_KRIS) || \ 658 defined(CHIP_KAYLA) || \ 659 defined(CHIP_KIWI) || \ 660 defined(CHIP_K5TN) 661 // for 40nm after Agate, use 55nm special setting1 662 // STB chips only to deal with bad Dev 663 // - Manufacturer:"HP" Product:"v220w" 664 // - VID:0x3f0 PID:0x5a07 665 #define UTMI_EYE_SETTING_2C (0x10) 666 #define UTMI_EYE_SETTING_2D (0x02) 667 #define UTMI_EYE_SETTING_2E (0x00) 668 #define UTMI_EYE_SETTING_2F (0x01) 669 #else 670 // for 40nm after Agate, use 55nm setting1, the default 671 #define UTMI_EYE_SETTING_2C (0x10) 672 #define UTMI_EYE_SETTING_2D (0x02) 673 #define UTMI_EYE_SETTING_2E (0x00) 674 #define UTMI_EYE_SETTING_2F (0x81) 675 #endif 676 #endif 677 678 #endif 679 680