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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regUART.h 98 // Description: UART Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_UART_H_ 103 #define _REG_UART_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Global Definition 107 //-------------------------------------------------------------------------------------------------- 108 109 //-------------------------------------------------------------------------------------------------- 110 // Compliation Option 111 //-------------------------------------------------------------------------------------------------- 112 113 //------------------------------------------------------------------------------------------------- 114 // Hardware Capability 115 //------------------------------------------------------------------------------------------------- 116 #if defined(MCU_AEON) 117 #define PIU_UART_VER 1 118 #endif 119 120 #if defined(__mips__) 121 #define PIU_UART_VER 2 122 #endif 123 124 #if defined(__arm__) || defined(__aarch64__) 125 #define PIU_UART_VER 2 126 #endif 127 128 #define UART_AEON_NUM 3 129 #define UART_PIU_NUM 3 130 131 #define UART_AEON_ADDR 0x90000000 132 #define UART_AEON_IRQ E_INT_IRQ_UART0 133 134 #define UART0_PIU_ADDR 0x1300 135 #define UART0_PIU_IRQ E_INT_IRQ_UART0 136 137 #define UART1_PIU_ADDR 0x20C00 138 #define UART1_PIU_IRQ E_INT_IRQ_UART1 139 140 #define UART2_PIU_ADDR 0x20C80 141 #define UART2_PIU_IRQ E_INT_IRQ_UART2 142 143 #define FUART_PIU_ADDR 0x20D00 144 #define FUART_PIU_IRQ E_INT_IRQ_UART2MCU 145 146 #if defined(MCU_AEON) 147 #define UART_CLK_FREQ 172800000 148 #endif 149 150 #if defined(__mips__) 151 #define UART_CLK_FREQ 123000000 152 #endif 153 154 #if defined(__arm__) || defined(__aarch64__) 155 #ifdef CONFIG_FPGA 156 #define UART_CLK_FREQ 12000000 157 #else 158 #define UART_CLK_FREQ 123000000 159 #endif 160 #endif 161 //------------------------------------------------------------------------------------------------- 162 // Type and Structure 163 //------------------------------------------------------------------------------------------------- 164 165 // 166 // UART Register List 167 // 168 169 #if (PIU_UART_VER == 1) 170 #define UART_RX 0 // In: Receive buffer (DLAB=0) 171 #define UART_TX 0 // Out: Transmit buffer (DLAB=0) 172 #define UART_DLL 0 // Out: Divisor Latch Low (DLAB=1) 173 #define UART_DLM 1 // Out: Divisor Latch High (DLAB=1) 174 #define UART_IER 1 // Out: Interrupt Enable Register 175 #define UART_IIR 2 // In: Interrupt ID Register 176 #define UART_FCR 2 // Out: FIFO Control Register 177 #define UART_LCR 3 // Out: Line Control Register 178 #define UART_MCR 4 // Out: Modem Control Register 179 #define UART_LSR 5 // In: Line Status Register 180 #define UART_USR 7 181 #endif 182 183 #if (PIU_UART_VER == 2) 184 #define UART_RX (0 * 2) // In: Receive buffer (DLAB=0) 185 #define UART_TX (0 * 2) // Out: Transmit buffer (DLAB=0) 186 #define UART_DLL (0 * 2) // Out: Divisor Latch Low (DLAB=1) 187 #define UART_DLM (1 * 2) // Out: Divisor Latch High (DLAB=1) 188 #define UART_IER (1 * 2) // Out: Interrupt Enable Register 189 #define UART_IIR (2 * 2) // In: Interrupt ID Register 190 #define UART_FCR (2 * 2) // Out: FIFO Control Register 191 #define UART_LCR (3 * 2) // Out: Line Control Register 192 #define UART_MCR (4 * 2) // Out: Modem Control Register 193 #define UART_LSR (5 * 2) // In: Line Status Register 194 #define UART_MSR (6 * 2) // In: Modem Status Register 195 #define UART_USR (7 * 2) // Out: USER Status Register 196 #endif 197 198 #define UART_FIFO 1 // Divisor Latch Low 199 #define UART_EFR 2 // I/O: Extended Features Register 200 #define UART_RB 3 // optional: set rf_pop delay for memack ; [3:0] rf_pop_delay; [6] rf_pop_mode_sel ; [7] reg_rb_read_ack 201 // (DLAB=1, 16C660 only) 202 #define UART_SCR 7 // I/O: Scratch Register 203 #define UART_SCCR 8 // Smartcard Control Register 204 #define UART_SCSR 9 // Smartcard Status Register 205 #define UART_SCFC 10 // Smartcard Fifo Count Register 206 #define UART_SCFI 11 // Smartcard Fifo Index Register 207 #define UART_SCFR 12 // Smartcard Fifo Read Delay Register 208 #define UART_SCMR 13 // Smartcard Mode Register 209 #define UART_DL 0 // Divisor Latch 210 #define UART_DL1_LSB 0 // Divisor Latch Low 211 #define UART_DL2_MSB 0 // Divisor Latch High 212 213 // 214 // UART_FCR(2) 215 // FIFO Control Register (16650 only) 216 // 217 #define UART_FCR_ENABLE_FIFO 0x01 // Enable the FIFO 218 #define UART_FCR_CLEAR_RCVR 0x02 // Clear the RCVR FIFO 219 #define UART_FCR_CLEAR_XMIT 0x04 // Clear the XMIT FIFO 220 #define UART_FCR_DMA_SELECT 0x08 // For DMA applications 221 #define UART_FCR_TRIGGER_MASK 0xC0 // Mask for the FIFO trigger range 222 //#define UART_FCR_TRIGGER_1 0x00 // Mask for trigger set at 1 223 //#define UART_FCR_TRIGGER_4 0x40 // Mask for trigger set at 4 224 #define UART_FCR_TRIGGER_8 0x80 // Mask for trigger set at 8 225 #define UART_FCR_TRIGGER_14 0xC0 // Mask for trigger set at 14 226 227 // 228 // UART_LCR(3) 229 // Line Control Register 230 // Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 231 // UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. 232 // 233 #define UART_LCR_WLEN5 0x00 // Wordlength: 5 bits 234 #define UART_LCR_WLEN6 0x01 // Wordlength: 6 bits 235 #define UART_LCR_WLEN7 0x02 // Wordlength: 7 bits 236 #define UART_LCR_WLEN8 0x03 // Wordlength: 8 bits 237 #define UART_LCR_STOP1 0x00 // Stop bits: 0=1 stop bit, 1= 2 stop bits 238 #define UART_LCR_STOP2 0x04 // Stop bits: 0=1 stop bit, 1= 2 stop bits 239 #define UART_LCR_PARITY 0x08 // Parity Enable 240 #define UART_LCR_EPAR 0x10 // Even parity select 241 #define UART_LCR_SPAR 0x20 // Stick parity (?) 242 #define UART_LCR_SBC 0x40 // Set break control 243 #define UART_LCR_DLAB 0x80 // Divisor latch access bit 244 245 // UART_FCR(4) 246 // FIFO Control Register (16650 only) 247 #define UART_FCR_MASK 0x00FF 248 #define UART_FCR_RXFIFO_CLR 0x0001 249 #define UART_FCR_TXFIFO_CLR 0x0002 250 #define UART_FCR_TRIGGER_0 0x0000 251 #define UART_FCR_TRIGGER_1 0x0010 252 #define UART_FCR_TRIGGER_2 0x0020 253 #define UART_FCR_TRIGGER_3 0x0030 254 #define UART_FCR_TRIGGER_4 0x0040 255 #define UART_FCR_TRIGGER_5 0x0050 256 #define UART_FCR_TRIGGER_6 0x0060 257 #define UART_FCR_TRIGGER_7 0x0070 258 259 // 260 // UART_LSR(5) 261 // Line Status Register 262 // 263 #define UART_LSR_DR 0x01 // Receiver data ready 264 #define UART_LSR_OE 0x02 // Overrun error indicator 265 #define UART_LSR_PE 0x04 // Parity error indicator 266 #define UART_LSR_FE 0x08 // Frame error indicator 267 #define UART_LSR_BI 0x10 // Break interrupt indicator 268 #define UART_LSR_THRE 0x20 // Transmit-hold-register empty 269 #define UART_LSR_TEMT 0x40 // Transmitter empty 270 271 // UART_LSR(6) 272 // Line Status Register 273 #define UART_LSR_TXFIFO_FULL 0x0080 // 274 275 // 276 // UART_IIR(2) 277 // Interrupt Identification Register 278 // 279 280 #define UART_IIR_MSI 0x00 // Modem status interrupt 281 #define UART_IIR_NO_INT 0x01 // No interrupts pending 282 #define UART_IIR_THRI 0x02 // Transmitter holding register empty 283 #define UART_IIR_TOI 0x0c // Receive time out interrupt 284 #define UART_IIR_RDI 0x04 // Receiver data interrupt 285 #define UART_IIR_RLSI 0x06 // Receiver line status interrupt 286 #define UART_IIR_ID 0x06 // Mask for the interrupt ID 287 288 // 289 // UART_IER(1) 290 // Interrupt Enable Register 291 // 292 #define UART_IER_RDI 0x01 // Enable receiver data available interrupt 293 #define UART_IER_THRI 0x02 // Enable Transmitter holding reg empty int 294 #define UART_IER_RLSI 0x04 // Enable receiver line status interrupt 295 #define UART_IER_MSI 0x08 // Enable Modem status interrupt 296 297 // UART_IER(3) 298 // Interrupt Enable Register 299 #define UART_IER_MASK 0xFF00 300 #define UART_IER_RDA 0x0100 // Enable receiver data available interrupt 301 #define UART_IER_THRE 0x0200 // Enable Transmitter holding reg empty int 302 303 // 304 // UART_MCR(4) 305 // Modem Control Register 306 // 307 #define UART_MCR_DTR 0x01 // DTR complement 308 #define UART_MCR_RTS 0x02 // RTS complement 309 #define UART_MCR_OUT1 0x04 // Out1 complement 310 #define UART_MCR_OUT2 0x08 // Out2 complement 311 #define UART_MCR_LOOP 0x10 // Enable loopback test mode 312 313 #define UART_MCR_FAST 0x20 // Slow / Fast baud rate mode 314 315 // UART_LCR(5) //2008/07/09 Nick 316 #define UART_LCR_MASK 0xFF00 317 #define UART_LCR_CHAR_BITS_5 0x0000 // Wordlength: 5 bits 318 #define UART_LCR_CHAR_BITS_6 0x0100 // Wordlength: 6 bits 319 #define UART_LCR_CHAR_BITS_7 0x0200 // Wordlength: 7 bits 320 #define UART_LCR_CHAR_BITS_8 0x0300 // Wordlength: 8 bits 321 #define UART_LCR_STOP_BITS_1 0x0000 // 1 bit 322 #define UART_LCR_STOP_BITS_2 0x0400 // 1.5, 2 bit 323 #define UART_LCR_PARITY_EN 0x0800 // Parity Enable 324 #define UART_LCR_EVEN_PARITY_SEL 0x1000 // Even parity select 325 #define UART_LCR_DIVISOR_EN 0x8000 // Divisor latch access bit 326 327 // 328 // UART_MSR(6) 329 // Modem Status Register 330 // 331 #define UART_MSR_ANY_DELTA 0x0F // Any of the delta bits! 332 #define UART_MSR_DCTS 0x01 // Delta CTS 333 #define UART_MSR_DDSR 0x02 // Delta DSR 334 #define UART_MSR_TERI 0x04 // Trailing edge ring indicator 335 #define UART_MSR_DDCD 0x08 // Delta DCD 336 #define UART_MSR_CTS 0x10 // Clear to Send 337 #define UART_MSR_DSR 0x20 // Data Set Ready 338 #define UART_MSR_RI 0x40 // Ring Indicator 339 #define UART_MSR_DCD 0x80 // Data Carrier Detect 340 341 // 342 // UART_EFR(2, UART_LCR_DLAB) 343 // These are the definitions for the Extended Features Register 344 // (StarTech 16C660 only, when DLAB=1) 345 // 346 #define UART_EFR_ENI 0x10 // Enhanced Interrupt 347 #define UART_EFR_SCD 0x20 // Special character detect 348 #define UART_EFR_RTS 0x40 // RTS flow control 349 #define UART_EFR_CTS 0x80 // CTS flow control 350 351 // 352 // UART_SCCR(8) 353 // SmartCard Control Register 354 // 355 #define UART_SCCR_MASK_CARDIN 0x01 // Smartcard card in interrupt mask 356 #define UART_SCCR_MASK_CARDOUT 0x02 // Smartcard card out interrupt mask 357 #define UART_SCCR_TX_BINV 0x04 // Smartcard Tx bit invert 358 #define UART_SCCR_TX_BSWAP 0x08 // Smartcard Tx bit swap 359 #define UART_SCCR_RST 0x10 // Smartcard reset 0->1, UART Rx enable 1 360 #define UART_SCCR_RX_BINV 0x20 // Smartcard Rx bit inverse 361 #define UART_SCCR_RX_BSWAP 0x40 // Smartcard Rx bit swap 362 363 // 364 // UART_SCSR(9) 365 // Smartcard Status Register 366 // 367 #define UART_SCSR_CLK 0x01 // Smartcard clock out 368 #define UART_SCSR_INT_CARDIN 0x02 // Smartcard card in interrupt 369 #define UART_SCSR_INT_CARDOUT 0x04 // Smartcard card out interrupt 370 #define UART_SCSR_DETECT 0x08 // Smartcard detection status 371 372 // 373 // UART_SCFC(10), UART_SCFI(11), UART_SCFR(12) 374 // Smartcard Fifo Register 375 // 376 #define UART_SCFC_MASK 0x07 377 #define UART_SCFI_MASK 0x0F 378 #define UART_SCFR_MASK 0x07 379 380 381 // 382 // UART_SCFR(12) 383 // Smartcard Fifo Read Delay Register 384 #define UART_SCFR_DELAY_MASK 0x03 385 #define UART_SCFR_V_HIGH 0x04 386 #define UART_SCFR_V_ENABLE 0x08 // Vcc = (Vcc_high ^ (Vcc_en & UART_SCSR_INT_CARDOUT)) 387 388 // 389 // UART_SCMR(13) 390 // SMart Mode Register 391 // 392 #define UART_SCMR_RETRY_MASK 0x1F 393 #define UART_SCMR_SMARTCARD 0x20 394 #define UART_SCMR_2STOP_BIT 0x40 395 396 //both Transmitter empty / Transmit-hold-register empty 397 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 398 399 // UART_SEL_TYPE 400 #define UART_SEL_HK_R2 0x00 401 #define UART_SEL_VD_MHEG5 0x02 402 #define UART_SEL_TSP 0x03 403 #define UART_SEL_PIU_UART0 0x04 404 #define UART_SEL_PIU_UART1 0x05 405 #define UART_SEL_PIU_UART2 0x06 406 #define UART_SEL_PIU_FAST_UART 0x07 407 #define UART_SEL_DMD_MCU51_TXD0 0x08 408 #define UART_SEL_DMD_MCU51_TXD1 0x09 409 #define UART_SEL_VD_MCU51_TXD0 0x0A 410 #define UART_SEL_VD_MCU51_TXD1 0x0B 411 #define UART_SEL_AUDIO_R2 0x0C 412 #define UART_SEL_SECURE_R2 0x0D 413 #define UART_SEL_OFF 0x0F 414 415 #define BIT0 (0x0001) 416 #define BIT1 (0x0002) 417 #define BIT2 (0x0004) 418 #define BIT3 (0x0008) 419 #define BIT4 (0x0010) 420 #define BIT5 (0x0020) 421 #define BIT6 (0x0040) 422 #define BIT7 (0x0080) 423 #define BIT8 (0x0100) 424 #define BIT9 (0x0200) 425 #define BIT10 (0x0400) 426 #define BIT11 (0x0800) 427 #define BIT12 (0x1000) 428 #define BIT13 (0x2000) 429 #define BIT14 (0x4000) 430 #define BIT15 (0x8000) 431 432 // 433 // PM_SLEEP 434 // for UART RX enable and switch MCU & PM51 435 // 436 #define REG_PM_SLEEP 0x0E00 437 #define REG_PM_UART_CTRL (REG_PM_SLEEP + (0x09*2) + 1) 438 #define _uart_rx_enable BIT3 439 #define _reg_hk51_uart0_en BIT4 440 441 // 442 // CHIP_TOP 443 // for UART PAD Select 444 // 445 #define CHIP_REG_BASE 0x1E00 446 #define CHIP_REG_FastUART (CHIP_REG_BASE+ (0x02*2)) 447 #define CHIP_FastUART_PAD_1 (BIT4) 448 #define CHIP_FastUART_PAD_2 (BIT5) 449 #define CHIP_FastUART_PAD_3 (BIT4|BIT5) 450 #define CHIP_FastUART_PAD_MASK (BIT4|BIT5) 451 #define CHIP_REG_FourthUART (CHIP_REG_BASE+ (0x02*2)) 452 #define CHIP_FourthUART_PAD_1 (BIT6) 453 #define CHIP_FourthUART_PAD_2 (BIT7) 454 #define CHIP_FourthUART_PAD_3 (BIT6|BIT7) 455 #define CHIP_FourthUART_PAD_MASK (BIT6|BIT7) 456 #define CHIP_REG_SecondUART (CHIP_REG_BASE+ (0x02*2) + 1) 457 #define CHIP_SecondUART_PAD_1 (BIT0) 458 #define CHIP_SecondUART_PAD_2 (BIT1) 459 #define CHIP_SecondUART_PAD_3 (BIT0|BIT1) 460 #define CHIP_SecondUART_PAD_MASK (BIT0|BIT1) 461 #define CHIP_REG_ThirdUART (CHIP_REG_BASE+ (0x02*2) + 1) 462 #define CHIP_ThirdUART_PAD_1 (BIT2) 463 #define CHIP_ThirdUART_PAD_2 (BIT3) 464 #define CHIP_ThirdUART_PAD_3 (BIT2|BIT3) 465 #define CHIP_ThirdUART_PAD_MASK (BIT2|BIT3) 466 467 //------------------------------------------------------------------------------------------------- 468 // Type and Structure 469 //------------------------------------------------------------------------------------------------- 470 471 #endif // _REG_UART_H_ 472