1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
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10 // permission has been granted by MStar.
11 //
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14 // comply with all applicable laws and regulations:
15 //
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17 // Software and any modification/derivatives thereof.
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19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
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32 //
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47 //
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55 //
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74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // ("MStar Confidential Information") by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 #include "MsCommon.h"
100 #include "regCHIP.h"
101 #include "halCHIP.h"
102 #include "drvSYS.h"
103 #include "halSYS.h"
104 #include "drvMMIO.h"
105 #include "drvSYS_priv.h"
106
107 #ifdef CONFIG_MSTAR_DVFS_KERNEL_SUPPORT
108 #include "halSYS_DVFS.h"
109 #include <fcntl.h>
110 #include <pthread.h>
111 #include <unistd.h>
112 #endif
113
114 //-------------------------------------------------------------------------------------------------
115 // Driver Compiler Options
116 //-------------------------------------------------------------------------------------------------
117 #define REG_EFUSE_OUTC_15_00 0x202CUL
118 #define REG_EFUSE_OUTC_31_16 0x202EUL
119 #define REG_EFUSE_OUTC_47_32 0x2030UL
120 #define REG_EFUSE_OUTC_63_48 0x2032UL
121 #define REG_EFUSE_OUTD_15_00 0x2034UL
122 #define REG_EFUSE_OUTD_31_16 0x2036UL
123 #define REG_EFUSE_OUTD_47_32 0x2038UL
124 #define REG_EFUSE_OUTD_63_48 0x203AUL
125
126 //-------------------------------------------------------------------------------------------------
127 // Local Defines
128 //-------------------------------------------------------------------------------------------------
129
130 #define BIT0 (0x0001UL)
131 #define BIT1 (0x0002UL)
132 #define BIT2 (0x0004UL)
133 #define BIT3 (0x0008UL)
134 #define BIT4 (0x0010UL)
135 #define BIT5 (0x0020UL)
136 #define BIT6 (0x0040UL)
137 #define BIT7 (0x0080UL)
138 #define BIT8 (0x0100UL)
139 #define BIT9 (0x0200UL)
140 #define BIT10 (0x0400UL)
141 #define BIT11 (0x0800UL)
142 #define BIT12 (0x1000UL)
143 #define BIT13 (0x2000UL)
144 #define BIT14 (0x4000UL)
145 #define BIT15 (0x8000UL)
146
147 //-------------------------------------------------------------------------------------------------
148 // Local Structures
149 //-------------------------------------------------------------------------------------------------
150
151 //-------------------------------------------------------------------------------------------------
152 // Global Variables
153 //-------------------------------------------------------------------------------------------------
154 static MS_VIRT _gMIO_efuse_MapBase = 0;
155
156 //-------------------------------------------------------------------------------------------------
157 // Local Variables
158 //-------------------------------------------------------------------------------------------------
159 static SYS_Info sysInfo;
160
161 static MS_VIRT u32hal_sys_baseaddr=0;
162
163 extern MS_U32 g_bDvfsInitFlag;
164 extern SYS_IO_PROC g_SysIoProc;
165 //-------------------------------------------------------------------------------------------------
166 // Debug Functions
167 //-------------------------------------------------------------------------------------------------
168
169
170 //-------------------------------------------------------------------------------------------------
171 // Local Functions
172 //-------------------------------------------------------------------------------------------------
HAL_SYS_Read2Byte(MS_U32 u32RegAddr)173 MS_U16 HAL_SYS_Read2Byte(MS_U32 u32RegAddr)
174 {
175 MS_U16 u16Val=0;
176
177 if ((u32RegAddr == 0) || (u32hal_sys_baseaddr == 0))
178 {
179 printf("drvSYS access RIU register error!!\r\n");
180 }
181 else
182 {
183 u16Val = ((volatile MS_U16*)(u32hal_sys_baseaddr))[u32RegAddr];
184 }
185 return u16Val;
186 }
187
HAL_SYS_Write2Byte(MS_U32 u32RegAddr,MS_U16 u16Val)188 void HAL_SYS_Write2Byte(MS_U32 u32RegAddr, MS_U16 u16Val)
189 {
190 if ((u32RegAddr == 0) || (u32hal_sys_baseaddr == 0))
191 {
192 printf("drvSYS access RIU register error!!\r\n");
193 }
194 else
195 {
196 ((volatile MS_U16*)(u32hal_sys_baseaddr))[u32RegAddr] = u16Val;
197 }
198 }
199
XIU_TimeOutINTHandler(InterruptNum eIntNum)200 void XIU_TimeOutINTHandler(InterruptNum eIntNum)
201 {
202 MsOS_DisableInterrupt(eIntNum);
203 printf("XIU Time Out Occurred!\n");
204 printf("Address is 0x%x%x\n",HAL_SYS_Read2Byte(0x100113),HAL_SYS_Read2Byte(0x100112));
205 printf("Address is 0x%x%x\n",HAL_SYS_Read2Byte(0x101276),HAL_SYS_Read2Byte(0x101274));
206 MsOS_EnableInterrupt(eIntNum);
207 }
208 //-------------------------------------------------------------------------------------------------
209 // Global Functions
210 //-------------------------------------------------------------------------------------------------
SYS_Init(MS_PHY phy64baseaddr)211 void SYS_Init(MS_PHY phy64baseaddr)
212 {
213 u32hal_sys_baseaddr=phy64baseaddr;
214
215 sysInfo.Chip.DeviceId = HAL_SYS_Read2Byte(0x001E00);
216 sysInfo.Chip.Version = (HAL_SYS_Read2Byte(0x001E02) & CHIP_VERSION_MASK) >> CHIP_VERSION_SHFT;
217 sysInfo.Chip.Revision = (HAL_SYS_Read2Byte(0x001E02) & CHIP_REVISION_MASK) >> CHIP_REVISION_SHFT;
218 sysInfo.Chip.MIU1Base = HAL_MIU1_BASE;
219 sysInfo.Chip.MIU1BusBase = HAL_MIU1_BUS_BASE;
220
221 //HAL_SYS_SetTSOutClockPhase(0);
222
223 // Enable XIU timeout
224 HAL_SYS_Write2Byte(0x100100, 0x0001);
225 HAL_SYS_Write2Byte(0x100128, 0xFFFF);
226 HAL_SYS_Write2Byte(0x10012A, 0xFFFF);
227 #if defined(CONFIG_FRC)
228 MsOS_AttachInterrupt(E_FRCINT_IRQ_FRC_XIU_TIMEOUT, (InterruptCb)XIU_TimeOutINTHandler);
229 MsOS_EnableInterrupt(E_FRCINT_IRQ_FRC_XIU_TIMEOUT);
230 #else
231 MsOS_AttachInterrupt(E_INT_FIQ_XIU_TIMEOUT, (InterruptCb)XIU_TimeOutINTHandler);
232 MsOS_EnableInterrupt(E_INT_FIQ_XIU_TIMEOUT);
233 #endif
234
235 // 40nm MCP demod issue
236 HAL_SYS_Write2Byte(0x11280E, (HAL_SYS_Read2Byte(0x11280E) | (BIT4)));
237
238 #ifdef CONFIG_MSTAR_DVFS_KERNEL_SUPPORT
239 if(g_bDvfsInitFlag == 0)
240 {
241 SysDvfsProc();
242 g_bDvfsInitFlag = 1;
243 }
244 #endif
245
246 }
247
248
SYS_GetChipRev(void)249 MS_U8 SYS_GetChipRev(void)
250 {
251 return sysInfo.Chip.Revision;
252 }
253
SYS_GetChipID(void)254 MS_U16 SYS_GetChipID(void)
255 {
256 return sysInfo.Chip.DeviceId;
257 }
258
SYS_GetInfo(void)259 const SYS_Info* SYS_GetInfo(void)
260 {
261 return (const SYS_Info*)&sysInfo;
262 }
263
264
SYS_ResetCPU(void)265 void SYS_ResetCPU(void)
266 {
267 /*
268 // Switch CPU to XTAL clk
269 TOP_REG(REG_TOP_MCU_USB_STC0) = (TOP_REG(REG_TOP_MCU_USB_STC0) & ~(TOP_MCU_CLK_MASK)) | TOP_MCU_CLK_DFT;
270
271 // Reset CPU
272 TOP_REG(REG_TOP_RESET_CPU0) = 0x029F;
273 TOP_REG(REG_TOP_RESET_CPU0) = 0x029F | TOP_RESET_CPU0;
274 */
275 }
276
HAL_SYS_RFAGC_Tristate(MS_BOOL bEnable)277 void HAL_SYS_RFAGC_Tristate(MS_BOOL bEnable)
278 {
279 MS_BOOL bDmdAccessPreEnabled = TRUE;
280 MS_U16 wReadRegisterData = 0;
281
282 wReadRegisterData = HAL_SYS_Read2Byte(0x101E38);
283
284 if((wReadRegisterData & (BIT9 | BIT8)) != 0)
285 {
286 HAL_SYS_Write2Byte(0x101E38, (wReadRegisterData & ~(BIT9 | BIT8)));
287 bDmdAccessPreEnabled = FALSE;
288 }
289
290 if (bEnable)
291 {
292 HAL_SYS_Write2Byte(0x11286C, (HAL_SYS_Read2Byte(0x11286C) & ~(BIT0)));
293 }
294 else
295 {
296 HAL_SYS_Write2Byte(0x11286C, (HAL_SYS_Read2Byte(0x11286C) | (BIT0)));
297 }
298
299 if(bDmdAccessPreEnabled == FALSE)
300 {
301 HAL_SYS_Write2Byte(0x101E38, wReadRegisterData);
302 }
303 }
304
HAL_SYS_IFAGC_Tristate(MS_BOOL bEnable)305 void HAL_SYS_IFAGC_Tristate(MS_BOOL bEnable)
306 {
307 MS_BOOL bDmdAccessPreEnabled = TRUE;
308 MS_U16 wReadRegisterData = 0;
309
310 wReadRegisterData = HAL_SYS_Read2Byte(0x101E38);
311
312 if((wReadRegisterData & (BIT9 | BIT8)) != 0)
313 {
314 HAL_SYS_Write2Byte(0x101E38, (wReadRegisterData & ~(BIT9 | BIT8)));
315 bDmdAccessPreEnabled = FALSE;
316 }
317
318 if (bEnable)
319 {
320 HAL_SYS_Write2Byte(0x11286C, (HAL_SYS_Read2Byte(0x11286C) & ~(BIT4)));
321 }
322 else
323 {
324 HAL_SYS_Write2Byte(0x11286C, (HAL_SYS_Read2Byte(0x11286C) | (BIT4)));
325 }
326
327 if(bDmdAccessPreEnabled == FALSE)
328 {
329 HAL_SYS_Write2Byte(0x101E38, wReadRegisterData);
330 }
331 }
332
HAL_SYS_SetAGCPadMux(SYS_AGC_PAD_SET eAgcPadMux)333 void HAL_SYS_SetAGCPadMux(SYS_AGC_PAD_SET eAgcPadMux)
334 {
335 MS_BOOL bDmdAccessPreEnabled = TRUE;
336 MS_U16 wReadRegisterData = 0;
337
338 wReadRegisterData = HAL_SYS_Read2Byte(0x101E38);
339
340 if((wReadRegisterData & (BIT9 | BIT8)) != 0)
341 {
342 HAL_SYS_Write2Byte(0x101E38, (wReadRegisterData & ~(BIT9 | BIT8)));
343 bDmdAccessPreEnabled = FALSE;
344 }
345
346 if(eAgcPadMux == E_SYS_ATV_AGC_PAD_SET) // ATV Mode
347 {
348 HAL_SYS_RFAGC_Tristate(TRUE);
349 HAL_SYS_IFAGC_Tristate(TRUE);
350 }
351 else if(eAgcPadMux == E_SYS_DTV_AGC_PAD_SET) // DTV Mode
352 {
353 HAL_SYS_RFAGC_Tristate(TRUE);
354 HAL_SYS_IFAGC_Tristate(FALSE);
355 }
356 else if(eAgcPadMux == E_SYS_DTV_AGC_PAD_SET_ALL_OFF) // DTV Mode
357 {
358 HAL_SYS_RFAGC_Tristate(TRUE);
359 HAL_SYS_IFAGC_Tristate(TRUE);
360 }
361 else
362 {
363 printf("[ERROR] HAL_SYS_SetAGCPadMux: Invalid AGC Pad Selection\r\n");
364 }
365
366 if(bDmdAccessPreEnabled == FALSE)
367 {
368 HAL_SYS_Write2Byte(0x101E38, wReadRegisterData);
369 }
370
371 }
372
HAL_SYS_SetPCMCardDetectMode(SYS_PCM_CD_MODE ePCMCDMode)373 MS_BOOL HAL_SYS_SetPCMCardDetectMode(SYS_PCM_CD_MODE ePCMCDMode)
374 {
375 MS_BOOL ret = TRUE;
376
377 if(ePCMCDMode >= E_PCM_CD_MAX)
378 {
379 ret = FALSE;
380 return ret;
381 }
382
383 if(ePCMCDMode == E_PCM_CD_SINGLE)
384 {
385 HAL_SYS_Write2Byte(0x102A04, (HAL_SYS_Read2Byte(0x102A04) & ~(BIT13)));
386 }
387 else if(ePCMCDMode == E_PCM_CD_OR)
388 {
389 HAL_SYS_Write2Byte(0x102A04, (HAL_SYS_Read2Byte(0x102A04) | BIT13));
390 }
391 else
392 {
393 ret = FALSE;
394 }
395
396 return ret;
397 }
398
HAL_SYS_DisableDebugPort(void)399 MS_BOOL HAL_SYS_DisableDebugPort(void)
400 {
401 return FALSE;
402 }
403
HAL_SYS_EnableDebugPort(void)404 MS_BOOL HAL_SYS_EnableDebugPort(void)
405 {
406 return FALSE;
407 }
408
409
HAL_SYS_SetPadMux(SYS_PAD_MUX_SET ePadMuxType,SYS_PAD_SEL ePadSel)410 MS_BOOL HAL_SYS_SetPadMux(SYS_PAD_MUX_SET ePadMuxType,SYS_PAD_SEL ePadSel)
411 {
412 MS_BOOL ret = TRUE;
413 MS_U16 u16data=0, u16data1 = 0;
414
415 if((ePadMuxType >= E_PAD_SET_MAX) || (ePadSel >= E_PAD_SEL_MAX))
416 {
417 ret = FALSE;
418 return ret;
419 }
420
421 if(ePadMuxType == E_TS0_PAD_SET)
422 {
423 u16data = HAL_SYS_Read2Byte(0x101EAE) & ~(BIT10|BIT9|BIT8);
424
425 if(ePadSel == E_PARALLEL_IN)
426 {
427 u16data |= BIT8;
428 HAL_SYS_Write2Byte(0x101EAE, u16data);
429 }
430 else if(ePadSel == E_SERIAL_IN)
431 {
432 u16data |= BIT9;
433 HAL_SYS_Write2Byte(0x101EAE, u16data);
434 }
435 else if(ePadSel == E_SERIAL_IN_3_WIRE)
436 {
437 u16data |= BIT10;
438 HAL_SYS_Write2Byte(0x101EAE, u16data);
439 }
440 else if(ePadSel == E_PARALLEL_IN_2nd_PORT) // PARALLEL_2nd_PORT
441 {
442 ret = FALSE;
443 }
444 else
445 {
446 ret = FALSE;
447 }
448 }
449 else if(ePadMuxType == E_TS1_PAD_SET)
450 {
451 u16data = HAL_SYS_Read2Byte(0x101EAE) & ~(BIT13|BIT12|BIT11);
452 u16data1 = HAL_SYS_Read2Byte(0x101E80) & ~(BIT6|BIT5|BIT4);
453
454 switch(ePadSel)
455 {
456 case E_PARALLEL_IN:
457 u16data |= BIT11;
458 break;
459 case E_PARALLEL_OUT:
460 case E_PARALLEL_OUT_INTDMD:
461 u16data |= BIT12;
462 break;
463 case E_SERIAL_IN:
464 u16data |= (BIT11|BIT12);
465 break;
466 case E_PARALLEL_OUT_TSO:
467 u16data1 |= (BIT4|BIT5);
468 break;
469 case E_PARALLEL_OUT_SER2PAR:
470 u16data1 |= BIT6;
471 break;
472 case E_PARALLEL_OUT_SER2PAR1:
473 u16data1 |= (BIT4|BIT6);
474 break;
475 case E_SERIAL_IN_3_WIRE:
476 u16data |= BIT13;
477 break;
478 default:
479 return FALSE;
480 }
481 HAL_SYS_Write2Byte(0x101EAE, u16data);
482 HAL_SYS_Write2Byte(0x101E80, u16data1);
483 }
484 else if(ePadMuxType == E_TS2_PAD_SET)
485 {
486 u16data = HAL_SYS_Read2Byte(0x101EAE) & ~(BIT14|BIT15);
487
488 if(ePadSel == E_SERIAL_IN)
489 {
490 HAL_SYS_Write2Byte(0x101EAE, u16data|BIT14);
491 }
492 else if(ePadSel == E_PARALLEL_IN)
493 {
494 HAL_SYS_Write2Byte(0x101EAE, u16data|BIT15);
495 }
496 else
497 {
498 ret = FALSE;
499 }
500 }
501 else if(ePadMuxType == E_TS3_PAD_SET)
502 {
503 u16data = HAL_SYS_Read2Byte(0x101ECE) & ~(BIT12|BIT13|BIT14|BIT15);
504 u16data1 = HAL_SYS_Read2Byte(0x101E20) & ~(BIT9|BIT10);
505
506 switch(ePadSel)
507 {
508 case E_PARALLEL_IN:
509 u16data |= BIT13;
510 break;
511 case E_PARALLEL_OUT:
512 case E_PARALLEL_OUT_INTDMD:
513 u16data |= (BIT12|BIT14);
514 break;
515 case E_SERIAL_IN:
516 u16data |= BIT12;
517 break;
518 case E_PARALLEL_OUT_TSO:
519 u16data1 |= BIT10;
520 break;
521 case E_PARALLEL_OUT_SER2PAR:
522 u16data |= (BIT12|BIT13|BIT14);
523 break;
524 case E_PARALLEL_OUT_SER2PAR1:
525 u16data |= BIT15;
526 break;
527 case E_SERIAL_IN_3_WIRE:
528 u16data |= (BIT13|BIT14);
529 break;
530 default:
531 return FALSE;
532 }
533 HAL_SYS_Write2Byte(0x101ECE, u16data);
534 HAL_SYS_Write2Byte(0x101E20, u16data1);
535 }
536 else if(ePadMuxType == E_TS4_PAD_SET)
537 {
538 u16data = HAL_SYS_Read2Byte(0x101E80) & ~(BIT10|BIT11);
539 if(ePadSel == E_PARALLEL_IN)
540 {
541 HAL_SYS_Write2Byte(0x101E80, u16data|BIT11);
542 }
543 else if(ePadSel == E_SERIAL_IN)
544 {
545 HAL_SYS_Write2Byte(0x101E80, u16data|BIT10);
546 }
547 else
548 {
549 return FALSE;
550 }
551 }
552 else if(ePadMuxType == E_TS5_PAD_SET)
553 {
554 u16data = HAL_SYS_Read2Byte(0x101E80) & ~BIT12;
555 if(ePadSel == E_SERIAL_IN)
556 {
557 HAL_SYS_Write2Byte(0x101E80, u16data|BIT12);
558 }
559 else
560 {
561 return FALSE;
562 }
563 }
564 else if(ePadMuxType == E_CA_CI_PAD_SET)
565 {
566 if(ePadSel == E_CA_CI_PAD_CI)
567 {
568 HAL_SYS_Write2Byte(0x101ec8, (HAL_SYS_Read2Byte(0x101ec8) | BIT5));
569 }
570 else if(ePadSel == E_CA_CI_PAD_NONE)
571 {
572 HAL_SYS_Write2Byte(0x101ec8, (HAL_SYS_Read2Byte(0x101ec8) & ~BIT5));
573 }
574 }
575 else if(ePadMuxType == E_SC_PAD_SET)
576 {
577 u16data = HAL_SYS_Read2Byte(0x101EDC) & ~(BIT5|BIT4);
578
579 if(ePadSel == E_SC_PAD_PCM)
580 {
581 u16data |= BIT4;
582 HAL_SYS_Write2Byte(0x101EDC, u16data);
583 HAL_SYS_Write2Byte(0x101EC8, (HAL_SYS_Read2Byte(0x101EC8) & ~BIT5));
584 }
585 else if(ePadSel == E_SC_PAD_TS1)
586 {
587 u16data |= BIT5;
588 HAL_SYS_Write2Byte(0x101EDC, u16data);
589 HAL_SYS_Write2Byte(0x101E0C, (HAL_SYS_Read2Byte(0x101E0C) | (BIT3|BIT6)));
590 HAL_SYS_Write2Byte(0x101E24, (HAL_SYS_Read2Byte(0x101E24) & ~(BIT0|BIT1|BIT2)));
591 HAL_SYS_Write2Byte(0x101EAE, (HAL_SYS_Read2Byte(0x101EAE) & ~(BIT11|BIT12|BIT13)));
592 }
593 }
594 else if(ePadMuxType == E_MSPI_PAD_SET)
595 {
596 if(ePadSel == E_MSPI_PAD_ON)
597 {
598 u16data |= BIT2;
599 HAL_SYS_Write2Byte(0x101EB4, u16data);
600 }
601 else if(ePadSel == E_MSPI_PAD_GPIO)
602 {
603 u16data = HAL_SYS_Read2Byte(0x101EB4) & ~(BIT10|BIT1|BIT2|BIT3);
604 HAL_SYS_Write2Byte(0x101EB4, u16data);
605 }
606 }
607 else
608 {
609 ret = FALSE;
610 }
611
612 return ret;
613 }
614
HAL_SYS_SetTSOutClockPhase(MS_U16 u16Val)615 MS_BOOL HAL_SYS_SetTSOutClockPhase(MS_U16 u16Val)
616 {
617 if(u16Val > 32)
618 {
619 return FALSE;
620 }
621
622 if(u32hal_sys_baseaddr == 0)
623 {
624 return FALSE;
625 }
626
627 HAL_SYS_Write2Byte(0x103300, HAL_SYS_Read2Byte(0x103300) | BIT12);
628 HAL_SYS_Write2Byte(0x10330a, HAL_SYS_Read2Byte(0x10330a) & ~(BIT12|BIT11|BIT10|BIT9|BIT8));
629 HAL_SYS_Write2Byte(0x10330a, HAL_SYS_Read2Byte(0x10330a) | (u16Val*0x100));
630
631 return TRUE;
632 }
633
SYS_VIF_ReadByteByVDMbox(MS_U32 u32Reg)634 MS_U8 SYS_VIF_ReadByteByVDMbox(MS_U32 u32Reg)
635 {
636 printf("%s(0x%08X) not support!!!\n", __FUNCTION__, (MS_U32)u32Reg);
637 return 0;
638 }
639
SYS_VIF_WriteByteByVDMbox(MS_U32 u32Reg,MS_U8 u8Val)640 void SYS_VIF_WriteByteByVDMbox(MS_U32 u32Reg, MS_U8 u8Val)
641 {
642 printf("%s(0x%08X, 0x%02X) not support!!!\n", __FUNCTION__, (MS_U32)u32Reg, u8Val);
643 }
644
SYS_VIF_WriteByteMaskByVDMbox(MS_U32 u32Reg,MS_U8 u8Val,MS_U8 u8Mask)645 void SYS_VIF_WriteByteMaskByVDMbox(MS_U32 u32Reg, MS_U8 u8Val, MS_U8 u8Mask)
646 {
647 printf("%s(0x%08X, 0x%02X, 0x%02X) not support!!!\n", __FUNCTION__, (MS_U32)u32Reg, u8Val, u8Mask);
648 }
649
SYS_VIF_WriteRegBitByVDMbox(MS_U32 u32Reg,MS_U8 bEnable,MS_U8 u8Mask)650 void SYS_VIF_WriteRegBitByVDMbox(MS_U32 u32Reg, MS_U8 bEnable, MS_U8 u8Mask)
651 {
652 printf("%s(0x%08X, 0x%02X, 0x%02X) not support!!!\n", __FUNCTION__, (MS_U32)u32Reg, bEnable, u8Mask);
653 }
654
SYS_VIF_Read2ByteByVDMbox(MS_U32 u32Reg)655 MS_U16 SYS_VIF_Read2ByteByVDMbox(MS_U32 u32Reg)
656 {
657 printf("%s(0x%08X) not support!!!\n", __FUNCTION__, (MS_U32)u32Reg);
658 return 0;
659 }
660
HAL_SYS_SetEfuseIOMapBase(MS_VIRT u32Base)661 void HAL_SYS_SetEfuseIOMapBase(MS_VIRT u32Base)
662 {
663 _gMIO_efuse_MapBase = u32Base;
664 }
665
HAL_SYS_EfuseRead2Byte(MS_U32 u32RegAddr)666 MS_U16 HAL_SYS_EfuseRead2Byte(MS_U32 u32RegAddr)
667 {
668 return ((volatile MS_U16*)(_gMIO_efuse_MapBase))[u32RegAddr];
669 }
670
HAL_SYS_EfuseWrite2Byte(MS_U32 u32RegAddr,MS_U16 u16Val)671 MS_U16 HAL_SYS_EfuseWrite2Byte(MS_U32 u32RegAddr, MS_U16 u16Val)
672 {
673 return ((volatile MS_U16*)(_gMIO_efuse_MapBase))[u32RegAddr] = u16Val;
674 }
675
HAL_SYS_SetOtpIOMapBase(MS_VIRT u32Base)676 void HAL_SYS_SetOtpIOMapBase(MS_VIRT u32Base)
677 {
678 // Not Implemented
679 }
680
HAL_SYS_Query(E_SYS_QUERY id)681 MS_BOOL HAL_SYS_Query(E_SYS_QUERY id)
682 {
683 MS_BOOL bRet = FALSE;
684
685 //
686 // get efuse settings
687 //
688 #ifndef CONFIG_MBOOT //Add For GPL (content protection)
689 if(_gMIO_efuse_MapBase == 0)
690 {
691 MS_VIRT dwEfuseIoBaseAddress = 0;
692 MS_PHY dwEfuseIoBaseSize = 0;
693
694 if(MDrv_MMIO_GetBASE(&dwEfuseIoBaseAddress, &dwEfuseIoBaseSize, MS_MODULE_PM) == FALSE)
695 {
696 printf("[ERROR][SYS] Get IO Base Address Failed\n");
697 MS_ASSERT(0);
698 return FALSE;
699 }
700
701 HAL_SYS_SetEfuseIOMapBase(dwEfuseIoBaseAddress);
702 }
703
704 //
705 // determine
706 //
707 switch (id)
708 {
709 case E_SYS_QUERY_TTS_SUPPORTED:
710 {
711 //=============================
712 // xxxx-xxxx-xxxx-vmmm
713 // Valid0 : reg_efuse_128x32_6a[3]
714 // Mode0 : reg_efuse_128x32_6a[2~0]
715 // xxxx-xxxx-vmmm-xxxx
716 // Valid1 : reg_efuse_128x32_6a[7]
717 // Mode1 : reg_efuse_128x32_6a[6~4]
718 //=============================
719 MS_U16 u16_efs128x32_rdata_lo = 0;
720 MS_U16 u16_efs128x32_rdata_hi = 0;
721 MS_U32 u32timeout_count = 0;
722 MS_BOOL bTTSValid0=0, bTTSValid1=0;
723 MS_U8 u8TTSMode0=0, u8TTSMode1=0;
724
725 //====================
726 //trigger to read efuse data
727 //from 128x32 sub-bank 6a
728 //====================
729 HAL_SYS_EfuseWrite2Byte(REG_RESERVED4_15_0, (0x6A*0x04) | 0x2000 );
730 while ((HAL_SYS_EfuseRead2Byte(REG_RESERVED4_15_0) & FLAG_EFUSE_DATA_BUSY) != 0)
731 {
732 if (u32timeout_count++ > MAX_TIMEOUT_COUNT)
733 {
734 printf ("[Error] %s(%d) Read time out!!\n", __FUNCTION__, __LINE__);
735 return 0;
736 }
737 MsOS_DelayTaskUs(10);
738 }
739
740 //====================
741 //read efuse data
742 //====================
743 u16_efs128x32_rdata_lo = HAL_SYS_EfuseRead2Byte(REG_EFUSE_128_RD_15_0);
744 u16_efs128x32_rdata_hi = HAL_SYS_EfuseRead2Byte(REG_EFUSE_128_RD_31_16);
745
746 //====================
747 //judge TTS Support mode
748 //====================
749 bTTSValid0 = (((u16_efs128x32_rdata_lo>>0) & 0x08)!=0) ? TRUE : FALSE;
750 u8TTSMode0 = (u16_efs128x32_rdata_lo>>0) & 0x07;
751 bTTSValid1 = (((u16_efs128x32_rdata_lo>>4) & 0x08)!=0) ? TRUE : FALSE;
752 u8TTSMode1 = (u16_efs128x32_rdata_lo>>4) & 0x07;
753 bRet =(MS_BOOL)((bTTSValid1) ? u8TTSMode1 : ((bTTSValid0)? u8TTSMode0 : 0));
754 }
755 break;
756
757 default:
758 printf("[SYS] Unknown query!\n");
759 return TRUE;
760 }
761 #endif //End of GPL contect protection
762 return bRet;
763 }
764
HAL_SYS_ReadRSAKey(MS_U16 u16ReadAddr)765 MS_U32 HAL_SYS_ReadRSAKey(MS_U16 u16ReadAddr)
766 {
767 //not implement yet
768 return FALSE;
769 }
770
HAL_SYS_SetTSClockPhase(SYS_PAD_MUX_SET ePadMuxType,MS_U16 u16Val)771 MS_BOOL HAL_SYS_SetTSClockPhase(SYS_PAD_MUX_SET ePadMuxType,MS_U16 u16Val)
772 {
773 if(ePadMuxType >= E_PAD_SET_MAX)
774 {
775 return FALSE;
776 }
777
778 if(u16Val > 31)
779 {
780 return FALSE;
781 }
782
783 if(u32hal_sys_baseaddr == 0)
784 {
785 return FALSE;
786 }
787
788 MS_U16 wReadRegisterData = 0;
789 if(ePadMuxType == E_TS0_PAD_SET)
790 {
791 wReadRegisterData = HAL_SYS_Read2Byte(0x101EAE) & (BIT10|BIT9|BIT8);
792 if((wReadRegisterData) == BIT9){
793 HAL_SYS_Write2Byte(0x110A00, (u16Val & 0x1F) & ~(BIT5|BIT6));
794 }else{
795 HAL_SYS_Write2Byte(0x110A00, (u16Val & 0x1F) | BIT5);
796 }
797 }
798 else if(ePadMuxType == E_TS1_PAD_SET)
799 {
800 wReadRegisterData = HAL_SYS_Read2Byte(0x101EAE) & (BIT13|BIT12|BIT11);
801 if(wReadRegisterData == (BIT11|BIT12)){
802 HAL_SYS_Write2Byte(0x110A02, (u16Val & 0x1F) & ~(BIT5|BIT6));
803 }else{
804 HAL_SYS_Write2Byte(0x110A02, (u16Val & 0x1F) | BIT5);
805 }
806 }
807 else if(ePadMuxType == E_TS2_PAD_SET)
808 {
809 wReadRegisterData = HAL_SYS_Read2Byte(0x101EAE) & (BIT14|BIT15);
810 if(wReadRegisterData == BIT14){
811 HAL_SYS_Write2Byte(0x110A04, (u16Val & 0x1F) & ~(BIT5|BIT6));
812 }else{
813 HAL_SYS_Write2Byte(0x110A04, (u16Val & 0x1F) | BIT5);
814 }
815 }
816 else if(ePadMuxType == E_TS3_PAD_SET)
817 {
818 wReadRegisterData = HAL_SYS_Read2Byte(0x101ECE) & (BIT12|BIT13|BIT14|BIT15);
819 if(wReadRegisterData == BIT12){
820 HAL_SYS_Write2Byte(0x110A06, (u16Val & 0x1F) & ~(BIT5|BIT6));
821 }else{
822 HAL_SYS_Write2Byte(0x110A06, (u16Val & 0x1F) | BIT5);
823 }
824 }
825 else if(ePadMuxType == E_TS4_PAD_SET)
826 {
827 wReadRegisterData = HAL_SYS_Read2Byte(0x101E80) & (BIT10|BIT11);
828 if(wReadRegisterData == BIT10){
829 HAL_SYS_Write2Byte(0x110A08, (u16Val & 0x1F) & ~(BIT5|BIT6));
830 }else{
831 HAL_SYS_Write2Byte(0x110A08, (u16Val & 0x1F) | BIT5);
832 }
833 }
834 else if(ePadMuxType == E_TS5_PAD_SET)
835 {
836 wReadRegisterData = HAL_SYS_Read2Byte(0x101E80) & (BIT12|BIT13);
837 if(wReadRegisterData == BIT12){
838 HAL_SYS_Write2Byte(0x110A0A, (u16Val & 0x1F) & ~(BIT5|BIT6));
839 }else{
840 HAL_SYS_Write2Byte(0x110A0A, (u16Val & 0x1F) | BIT5);
841 }
842 }
843 else
844 {
845 return FALSE;
846 }
847
848 return TRUE;
849 }
850
HAL_SYS_QueryDolbyHashInfo(E_SYS_DOLBY_HASH_INFO index)851 MS_U32 HAL_SYS_QueryDolbyHashInfo(E_SYS_DOLBY_HASH_INFO index)
852 {
853
854 MS_U16 hash_rdata_lo = 0;
855 MS_U16 hash_rdata_hi = 0;
856 MS_U32 u32Ret = 0;
857 MS_U32 u32timeout_count = 0;
858
859 #ifndef CONFIG_MBOOT //Add For GPL (content protection)
860 if(_gMIO_efuse_MapBase == 0)
861 {
862 MS_VIRT dwEfuseIoBaseAddress = 0;
863 MS_PHY dwEfuseIoBaseSize = 0;
864
865 if(MDrv_MMIO_GetBASE(&dwEfuseIoBaseAddress, &dwEfuseIoBaseSize, MS_MODULE_PM) == FALSE)
866 {
867 printf("[ERROR][SYS] Get IO Base Address Failed\n");
868 MS_ASSERT(0);
869 return 0;
870 }
871
872 HAL_SYS_SetEfuseIOMapBase(dwEfuseIoBaseAddress);
873 }
874
875 //Bank 2, 0x29 = 2008
876 HAL_SYS_EfuseWrite2Byte(REG_RESERVED4_31_16, (0X4*2) | 0x2000UL );
877
878 while ((HAL_SYS_EfuseRead2Byte(REG_RESERVED4_31_16) & FLAG_EFUSE_DATA_BUSY) != 0)
879 {
880 if (u32timeout_count++ > MAX_TIMEOUT_COUNT)
881 {
882 printf ("[Error] %s(%d) Read time out!!\n", __FUNCTION__, __LINE__);
883 return 0;
884 }
885 MsOS_DelayTaskUs(10);
886 }
887
888 hash_rdata_lo = HAL_SYS_EfuseRead2Byte(REG_EFUSE_32_RD_15_0);
889 hash_rdata_hi = HAL_SYS_EfuseRead2Byte(REG_EFUSE_32_RD_31_16);
890
891 switch(index)
892 {
893 case E_SYS_DOLBY_VERSION:
894 //Bank 2 [12:10], [3:0],
895 u32Ret = (MS_U32)(((hash_rdata_lo >> 10) & (0x7)) << 0x4);
896 u32Ret = u32Ret | (MS_U32)(((hash_rdata_lo)& 0xF));
897 break;
898
899 case E_SYS_DOLBY_CONTROL_BIT:
900 //Bank 2 [13]
901 u32Ret = (MS_U32)((hash_rdata_lo >> 13) & (0x01)); //Bank 2 [13]
902 break;
903
904 case E_SYS_DOLBY_REVERSE_BIT:
905 //Bank 2 [14]
906 u32Ret = (MS_U32)((hash_rdata_lo >> 14) & (0x01)); // Bank 2 [14]
907 break;
908
909 default:
910 printf ("[Error] %s(%d) Unknown Cmd: 0x%x\n", __FUNCTION__, __LINE__, index);
911 break;
912 }
913 #endif //End of GPL contect protection
914 return u32Ret;
915 }
916
917 #ifndef CONFIG_MBOOT //Add For GPL (content protection)
918 static volatile MS_U8 u8gDolbyKeyCustomer[24] =
919 {'H','K','C','S',
920 0x44,0x10,0x91,0x68,0xff,0x0e,0x4c,0x28,0x77,0x0e,0xf5,0x57,0xe0,0x20,0x02,0xdf
921 ,'H','K','C','E'};
922 #endif //End of GPL contect protection
923
HAL_SYS_GetDolbyKeyCustomer(MS_U8 * u8pkey)924 void HAL_SYS_GetDolbyKeyCustomer(MS_U8 * u8pkey)
925 {
926 #ifndef CONFIG_MBOOT //Add For GPL (content protection)
927 MS_U8 u8index;
928
929 for(u8index =4; u8index <(16+4); u8index ++)
930 {
931
932 u8pkey[u8index-4] = u8gDolbyKeyCustomer [u8index];
933
934 }
935 #endif //End of GPL contect protection
936 }
937
HAL_SYS_SetChipType(E_SYS_CHIP_TYPE Type)938 void HAL_SYS_SetChipType(E_SYS_CHIP_TYPE Type)
939 {
940
941 }
942
943
HAL_SYS_GetChipType(void)944 E_SYS_CHIP_TYPE HAL_SYS_GetChipType(void)
945 {
946 MS_U16 hash_rdata_lo = 0;
947 MS_U16 hash_rdata_hi = 0;
948 MS_U32 u32timeout_count = 0;
949 #ifndef CONFIG_MBOOT //Add For GPL (content protection)
950 if(_gMIO_efuse_MapBase == 0)
951 {
952 MS_VIRT dwEfuseIoBaseAddress = 0;
953 MS_PHY dwEfuseIoBaseSize = 0;
954
955 if(MDrv_MMIO_GetBASE(&dwEfuseIoBaseAddress, &dwEfuseIoBaseSize, MS_MODULE_PM) == FALSE)
956 {
957 printf("[ERROR][SYS] Get IO Base Address Failed\n");
958 MS_ASSERT(0);
959 return 0;
960 }
961
962 HAL_SYS_SetEfuseIOMapBase(dwEfuseIoBaseAddress);
963 }
964
965 //Bank 0, 0x29 = 2000
966 HAL_SYS_EfuseWrite2Byte(REG_RESERVED4_31_16, (0X4*0) | 0x2000 );
967
968 while ((HAL_SYS_EfuseRead2Byte(REG_RESERVED4_31_16) & FLAG_EFUSE_DATA_BUSY) != 0)
969 {
970 if (u32timeout_count++ > MAX_TIMEOUT_COUNT)
971 {
972 printf ("[Error] %s(%d) Read time out!!\n", __FUNCTION__, __LINE__);
973 return 0;
974 }
975 MsOS_DelayTaskUs(10);
976 }
977
978 hash_rdata_lo = HAL_SYS_EfuseRead2Byte(REG_EFUSE_32_RD_15_0);
979 hash_rdata_hi = HAL_SYS_EfuseRead2Byte(REG_EFUSE_32_RD_31_16);
980 #endif //End of GPL contect protection
981 if(((hash_rdata_lo >> 11)& 0x01) == 0x01) ////Bank 0 [11]
982 {
983 return E_SYS_CHIP_STB;
984 }
985 else
986 {
987 return E_SYS_CHIP_TV;
988 }
989 }
990
991 //RTC0 Bank 0x12 : h0010 dummy register
992 // merge the setting from monaco, confirm with yenfu and acem ok
HAL_SYS_ReadBrickTerminatorStatus(void)993 MS_U16 HAL_SYS_ReadBrickTerminatorStatus(void)
994 {
995 MS_U16 u16Status = 0;
996
997 u16Status = HAL_SYS_Read2Byte(0x001220);
998
999 return u16Status;
1000 }
1001
HAL_SYS_WriteBrickTerminatorStatus(MS_U16 u16Status)1002 void HAL_SYS_WriteBrickTerminatorStatus(MS_U16 u16Status)
1003 {
1004 HAL_SYS_Write2Byte(0x001220, u16Status);
1005 }
1006
HAL_SYS_GetEfuseDid(MS_U16 * u16efuse_did)1007 void HAL_SYS_GetEfuseDid(MS_U16 *u16efuse_did)
1008 {
1009 u16efuse_did[0] = HAL_SYS_Read2Byte(0x003800);
1010 u16efuse_did[1] = HAL_SYS_Read2Byte(0x003802);
1011 u16efuse_did[2] = HAL_SYS_Read2Byte(0x003804);
1012 u16efuse_did[3] = HAL_SYS_Read2Byte(0x003806);
1013 }
1014
HAL_SYS_ReadEfuseHDCPKey(MS_U16 u16ReadAddr,MS_U32 * u32HDCPKey)1015 MS_BOOL HAL_SYS_ReadEfuseHDCPKey(MS_U16 u16ReadAddr, MS_U32 *u32HDCPKey)
1016 {
1017 MS_U16 hdcp_rdata_lo = 0;
1018 MS_U16 hdcp_rdata_hi = 0;
1019 MS_U32 u32timeout_count = 0;
1020
1021 #ifndef CONFIG_MBOOT //Add For GPL (content protection)
1022 if(_gMIO_efuse_MapBase == 0)
1023 {
1024 MS_VIRT dwEfuseIoBaseAddress = 0;
1025 MS_PHY dwEfuseIoBaseSize = 0;
1026
1027 if(MDrv_MMIO_GetBASE(&dwEfuseIoBaseAddress, &dwEfuseIoBaseSize, MS_MODULE_PM) == FALSE)
1028 {
1029 printf("[ERROR][SYS] Get IO Base Address Failed\n");
1030 MS_ASSERT(0);
1031 return FALSE;
1032 }
1033
1034 HAL_SYS_SetEfuseIOMapBase(dwEfuseIoBaseAddress);
1035 }
1036
1037 if(u16ReadAddr > 75)
1038 {
1039 printf("[ERROR][SYS] Read Address overflow\n");
1040 MS_ASSERT(0);
1041 return FALSE;
1042 }
1043
1044
1045 HAL_SYS_EfuseWrite2Byte(REG_RESERVED4_15_0, (0X4*u16ReadAddr) | 0x2000 );
1046
1047 while ((HAL_SYS_EfuseRead2Byte(REG_RESERVED4_15_0) & FLAG_EFUSE_DATA_BUSY) != 0)
1048 {
1049 if (u32timeout_count++ > MAX_TIMEOUT_COUNT)
1050 {
1051 printf ("[Error] %s(%d) Read time out!!\n", __FUNCTION__, __LINE__);
1052 return 0;
1053 }
1054 MsOS_DelayTaskUs(10);
1055 }
1056
1057 hdcp_rdata_lo = HAL_SYS_EfuseRead2Byte(REG_EFUSE_128_RD_15_0);
1058 hdcp_rdata_hi = HAL_SYS_EfuseRead2Byte(REG_EFUSE_128_RD_31_16);
1059 #endif //End of GPL contect protection
1060 *u32HDCPKey = (MS_U32)((hdcp_rdata_hi<<16)|hdcp_rdata_lo);
1061 return TRUE;
1062 }
1063
1064 //=================================================================================================
1065 #ifdef CONFIG_MSTAR_DVFS_KERNEL_SUPPORT
1066 static MS_S32 _s32SAR_Dvfs_Mutex;
1067 static MSTAR_DVFS_INFO hMstarDvfsInfo =
1068 {
1069 .bDvfsInitOk = 0,
1070 .dwVidSetting = 0,
1071 .dwPowerChipId = CONFIG_DVFS_CHIP_ID_UNKNOWN,
1072 .dwSWI2CBusId = 0,
1073 };
1074
1075 //#if (CONFIG_DVFS_CPU_POWER_I2C_ENABLE | CONFIG_DVFS_CORE_POWER_I2C_ENABLE)
1076 //extern MS_BOOL MApi_SWI2C_ReadBytes(MS_U16 u16BusNumSlaveID, MS_U8 u8AddrNum, MS_U8* paddr, MS_U16 u16size, MS_U8* pu8data);
1077 //extern MS_BOOL MApi_SWI2C_WriteBytes(MS_U16 u16BusNumSlaveID, MS_U8 u8addrcount, MS_U8* pu8addr, MS_U16 u16size, MS_U8* pu8data);
1078 //#endif
1079
1080 ////////////////////////////////////////////////////////////////////////////////
1081 /// @brief \b Function \b Name: SysDvfsProc
1082 /// @brief \b Function \b Description: Read T-Sensor to Handle DVFS Flow
1083 /// @param <IN> \b None:
1084 /// @param <OUT> \b None:
1085 /// @param <RET> \b None:
1086 /// @param <GLOBAL> \b None:
1087 ////////////////////////////////////////////////////////////////////////////////
1088
1089 static pthread_t hDvfsThread;
SysDvfsThreadProc(void * pThreadInfo)1090 static void *SysDvfsThreadProc(void *pThreadInfo)
1091 {
1092 int hFileHandle;
1093 int dwDataLength = 0;
1094 unsigned int dwLoopCounter = 0;
1095 char sFileName[48] = "/proc/on_demand_ctl\0";
1096 MSTAR_DVFS_READ_INFO hMstarDvfsReadInfo;
1097 MSTAR_DVFS_WRITE_INFO hMstarDvfsWriteInfo;
1098
1099 while(1)
1100 {
1101 if((g_SysIoProc.SysSwI2CReadBytes != 0) && (g_SysIoProc.SysSwI2CWriteBytes != 0))
1102 {
1103 hFileHandle = open(sFileName, (O_RDWR | O_EXCL));
1104 if(hFileHandle == -1)
1105 {
1106 DVFS_DEBUG("\033[35m[ERROR] Cannot Open File: %s\033[m\n", sFileName);
1107 }
1108 else
1109 {
1110 while(1)
1111 {
1112 if(hMstarDvfsInfo.bDvfsInitOk == 0)
1113 {
1114 SysDvfsInit();
1115 hMstarDvfsInfo.bDvfsInitOk = 1;
1116 }
1117
1118 dwDataLength = read(hFileHandle, (void *) &hMstarDvfsReadInfo, sizeof(hMstarDvfsReadInfo));
1119
1120 DVFS_DEBUG("\033[35m[INFO] Read Data Length: %d\033[m\n", dwDataLength);
1121 DVFS_DEBUG("\033[35m[INFO] Voltage: %d0 mV\033[m\n", hMstarDvfsReadInfo.dwVoltage);
1122 if(hMstarDvfsReadInfo.dwVoltageType == 0)
1123 {
1124 DVFS_DEBUG("\033[35m[INFO] Voltage Type: CPU Power\033[m\n");
1125 }
1126 else if(hMstarDvfsReadInfo.dwVoltageType == 1)
1127 {
1128 DVFS_DEBUG("\033[35m[INFO] Voltage Type: Core Power\033[m\n");
1129 }
1130 else
1131 {
1132 DVFS_DEBUG("\033[35m[INFO] Voltage Type: Unknown\033[m\n");
1133 }
1134 DVFS_DEBUG("\033[35m[INFO] Data Exchange Count (Read): %d\033[m\n", hMstarDvfsReadInfo.dwDataExchangeCount);
1135
1136 if(hMstarDvfsReadInfo.dwVoltageType == CONFIG_DVFS_CPU_POWER)
1137 {
1138 SysDvfsCpuPowerAdjustment(hMstarDvfsReadInfo.dwVoltage);
1139 }
1140 else if(hMstarDvfsReadInfo.dwVoltageType == CONFIG_DVFS_CORE_POWER)
1141 {
1142 SysDvfsCorePowerAdjustment(hMstarDvfsReadInfo.dwVoltage);
1143 }
1144 else if(hMstarDvfsReadInfo.dwVoltageType == CONFIG_DVFS_STR_INIT)
1145 {
1146 SysDvfsInit();
1147 }
1148
1149 hMstarDvfsWriteInfo.dwDataExchangeCount = hMstarDvfsReadInfo.dwDataExchangeCount;
1150 hMstarDvfsWriteInfo.dwDataExchangeResult = 0;
1151 dwDataLength = write(hFileHandle, (void *)&hMstarDvfsWriteInfo, sizeof(hMstarDvfsWriteInfo));
1152
1153 DVFS_DEBUG("\033[35m[INFO] Write Data Length: %d\033[m\n", dwDataLength);
1154 DVFS_DEBUG("\033[35m[INFO] Data Exchange Count (Write): %d\033[m\n", hMstarDvfsWriteInfo.dwDataExchangeCount);
1155 DVFS_DEBUG("\033[35m[INFO] Data Exchange Result: %d\033[m\n", hMstarDvfsWriteInfo.dwDataExchangeResult);
1156 }
1157
1158 close(hFileHandle);
1159 }
1160 }
1161
1162 dwLoopCounter ++;
1163 if(dwLoopCounter > 50)
1164 {
1165 pthread_exit(NULL);
1166 break;
1167 }
1168
1169 MsOS_DelayTaskUs(100000);
1170 }
1171
1172 return NULL;
1173 }
1174
SysDvfsProc(void)1175 void SysDvfsProc(void)
1176 {
1177 if(*(volatile MS_U16 *)(u32hal_sys_baseaddr + (0x100500 << 1)) == CONFIG_DVFS_ENABLE_PATTERN)
1178 {
1179 if(hMstarDvfsInfo.bDvfsInitOk == 0)
1180 {
1181 int dwErrorCode = 0;
1182 char sDvfsThreadName[20] = "MstarDvfsThread\0";
1183 pthread_attr_t attr;
1184
1185 _s32SAR_Dvfs_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, "Mutex SAR_DVFS", MSOS_PROCESS_SHARED);
1186 MS_ASSERT(_s32SAR_Dvfs_Mutex >= 0);
1187
1188 if (FALSE == MsOS_ObtainMutex(_s32SAR_Dvfs_Mutex, CONFIG_DVFS_MUTEX_WAIT_TIME))
1189 {
1190 DVFS_INFO("\033[37m[DVFS] Mutex Lock Fail\033[m\n");
1191 MsOS_ReleaseMutex(_s32SAR_Dvfs_Mutex);
1192 return;
1193 }
1194
1195 //SysDvfsInit();
1196
1197 pthread_attr_init(&attr);
1198 pthread_attr_setdetachstate(&attr, PTHREAD_CREATE_DETACHED);
1199
1200 dwErrorCode = pthread_create(
1201 &hDvfsThread,
1202 &attr,
1203 SysDvfsThreadProc,
1204 (void *) sDvfsThreadName);
1205
1206 if(dwErrorCode)
1207 {
1208 DVFS_DEBUG("\033[33m[ERROR] Create DVFS Thread Failed\033[m\n");
1209 MsOS_ReleaseMutex(_s32SAR_Dvfs_Mutex);
1210 return;
1211 }
1212
1213 MsOS_ReleaseMutex(_s32SAR_Dvfs_Mutex);
1214 }
1215 }
1216 }
1217
1218 ////////////////////////////////////////////////////////////////////////////////
1219 /// @brief \b Function \b Name: SysDvfsInit
1220 /// @brief \b Function \b Description: Read T-Sensor to Handle DVFS Flow
1221 /// @param <IN> \b None:
1222 /// @param <OUT> \b None:
1223 /// @param <RET> \b None:
1224 /// @param <GLOBAL> \b None:
1225 ////////////////////////////////////////////////////////////////////////////////
SysDvfsInit(void)1226 void SysDvfsInit(void)
1227 {
1228 SysDvfsCpuPowerInit();
1229 SysDvfsCorePowerInit();
1230
1231 hMstarDvfsInfo.bDvfsInitOk = 1;
1232 }
1233
1234 ////////////////////////////////////////////////////////////////////////////////
1235 /// @brief \b Function \b Name: SysDvfsCpuPowerAdjustment
1236 /// @brief \b Function \b Description: Update Output Voltage Level in External Power Chip
1237 /// @param <IN> \b None:
1238 /// @param <OUT> \b None:
1239 /// @param <RET> \b None:
1240 /// @param <GLOBAL> \b None:
1241 ////////////////////////////////////////////////////////////////////////////////
SysDvfsCpuPowerAdjustment(MS_U32 dwCpuPowerVoltage)1242 void SysDvfsCpuPowerAdjustment(MS_U32 dwCpuPowerVoltage)
1243 {
1244 #if CONFIG_DVFS_CPU_POWER_I2C_ENABLE
1245 MS_U32 dwRegisterValue = 0;
1246 MS_U32 dwOriginalCpuPowerVoltage = 0;
1247 MS_U32 dwSourceRegisterSetting = 0;
1248 MS_U32 dwTargetRegisterSetting = 0;
1249
1250 MS_U8 byTargetRegAddress[5] =
1251 {
1252 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
1253 };
1254 MS_U8 byTargetData[5] =
1255 {
1256 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
1257 };
1258
1259 if(dwCpuPowerVoltage > CONFIG_DVFS_CPU_POWER_MAX || dwCpuPowerVoltage < CONFIG_DVFS_CPU_POWER_MIN)
1260 {
1261 DVFS_DEBUG("\033[37m[ERROR] Get error CpuPowerVoltage!\033[m\n");
1262 return;
1263 }
1264
1265 if(hMstarDvfsInfo.dwPowerChipId == CONFIG_DVFS_CHIP_ID_PRADO)
1266 {
1267 byTargetRegAddress[0] = 0x10;
1268 byTargetRegAddress[1] = (0x06 << 1);
1269 if(g_SysIoProc.SysSwI2CReadBytes(CONFIG_DVFS_POWER_SWI2C_ADDR_CPU(hMstarDvfsInfo.dwSWI2CBusId), 2, byTargetRegAddress, 2, byTargetData) == TRUE)
1270 {
1271 dwOriginalCpuPowerVoltage = (unsigned int) byTargetData[1] + CONFIG_DVFS_CPU_POWER_SHIFT_PRADO;
1272 DVFS_DEBUG("\033[33m[INFO] Orginal CPU Power: %d0 mV\033[m\n", (unsigned int) dwOriginalCpuPowerVoltage);
1273 }
1274
1275 dwSourceRegisterSetting = (dwOriginalCpuPowerVoltage - CONFIG_DVFS_CPU_POWER_SHIFT_PRADO);
1276 dwTargetRegisterSetting = (dwCpuPowerVoltage - CONFIG_DVFS_CPU_POWER_SHIFT_PRADO);
1277
1278 if(hMstarDvfsInfo.bDvfsInitOk == 1)
1279 {
1280 if(dwCpuPowerVoltage > dwOriginalCpuPowerVoltage)
1281 {
1282 for(;dwSourceRegisterSetting <= dwTargetRegisterSetting; dwSourceRegisterSetting += CONFIG_DVFS_CPU_POWER_STEP)
1283 {
1284 //Set CPU Voltage
1285 dwRegisterValue = dwSourceRegisterSetting;
1286 byTargetRegAddress[0] = 0x10;
1287 byTargetRegAddress[1] = (0x06 << 1);
1288 byTargetRegAddress[2] = 0x10;
1289 byTargetRegAddress[3] = dwRegisterValue;
1290 if(g_SysIoProc.SysSwI2CWriteBytes(CONFIG_DVFS_POWER_SWI2C_ADDR_CPU(hMstarDvfsInfo.dwSWI2CBusId), 4, byTargetRegAddress, 0, byTargetData) == TRUE)
1291 {
1292 DVFS_DEBUG("\033[37m[INFO] Change to Voltage: %d0 mV (0x%X)\033[m\n", (unsigned int) dwCpuPowerVoltage, (unsigned int) dwRegisterValue);
1293 }
1294 else
1295 {
1296 DVFS_DEBUG("\033[37m[ERROR] Software I2C Write Failed\033[m\n");
1297 }
1298 }
1299 }
1300 else if(dwCpuPowerVoltage < dwOriginalCpuPowerVoltage)
1301 {
1302 for(;dwSourceRegisterSetting >= dwTargetRegisterSetting; dwSourceRegisterSetting -= CONFIG_DVFS_CPU_POWER_STEP)
1303 {
1304 //Set CPU Voltage
1305 dwRegisterValue = dwSourceRegisterSetting;
1306 byTargetRegAddress[0] = 0x10;
1307 byTargetRegAddress[1] = (0x06 << 1);
1308 byTargetRegAddress[2] = 0x10;
1309 byTargetRegAddress[3] = dwRegisterValue;
1310 if(g_SysIoProc.SysSwI2CWriteBytes(CONFIG_DVFS_POWER_SWI2C_ADDR_CPU(hMstarDvfsInfo.dwSWI2CBusId), 4, byTargetRegAddress, 0, byTargetData) == TRUE)
1311 {
1312 DVFS_DEBUG("\033[37m[INFO] Change to Voltage: %d0 mV (0x%X)\033[m\n", (unsigned int) dwCpuPowerVoltage, (unsigned int) dwRegisterValue);
1313 }
1314 else
1315 {
1316 DVFS_DEBUG("\033[37m[ERROR] Software I2C Write Failed\033[m\n");
1317 }
1318 }
1319 }
1320 else
1321 {
1322 DVFS_DEBUG("\033[37m[INFO] No Need to Change CPU Power\033[m\n");
1323 return;
1324 }
1325 }
1326
1327 if(dwSourceRegisterSetting != dwTargetRegisterSetting)
1328 {
1329 //Set CPU Voltage
1330 dwRegisterValue = (dwCpuPowerVoltage - CONFIG_DVFS_CPU_POWER_SHIFT_PRADO);
1331 byTargetRegAddress[0] = 0x10;
1332 byTargetRegAddress[1] = (0x06 << 1);
1333 byTargetRegAddress[2] = 0x10;
1334 byTargetRegAddress[3] = dwRegisterValue;
1335 if(g_SysIoProc.SysSwI2CWriteBytes(CONFIG_DVFS_POWER_SWI2C_ADDR_CPU(hMstarDvfsInfo.dwSWI2CBusId), 4, byTargetRegAddress, 0, byTargetData) == TRUE)
1336 {
1337 DVFS_INFO("\033[37m[INFO] Change to Voltage: %d0 mV (0x%X)\033[m\n", (unsigned int) dwCpuPowerVoltage, (unsigned int) dwRegisterValue);
1338 }
1339 else
1340 {
1341 DVFS_DEBUG("\033[37m[ERROR] Software I2C Write Failed\033[m\n");
1342 }
1343 }
1344 else
1345 {
1346 DVFS_INFO("\033[37m[INFO] Change to Voltage: %d0 mV (0x%X)\033[m\n", (unsigned int) dwCpuPowerVoltage, (unsigned int) dwRegisterValue);
1347 }
1348 }
1349 #endif
1350 }
1351
1352 ////////////////////////////////////////////////////////////////////////////////
1353 /// @brief \b Function \b Name: SysDvfsCorePowerAdjustment
1354 /// @brief \b Function \b Description: Update Output Voltage Level in External Power Chip
1355 /// @param <IN> \b None:
1356 /// @param <OUT> \b None:
1357 /// @param <RET> \b None:
1358 /// @param <GLOBAL> \b None:
1359 ////////////////////////////////////////////////////////////////////////////////
SysDvfsCorePowerAdjustment(MS_U32 dwCorePowerVoltage)1360 void SysDvfsCorePowerAdjustment(MS_U32 dwCorePowerVoltage)
1361 {
1362 #if CONFIG_DVFS_CORE_POWER_I2C_ENABLE
1363 #error "No Support Core Power Adjustment by I2C in Messi Platform"
1364 #endif
1365 #if CONFIG_DVFS_CORE_POWER_GPIO_ENABLE
1366 MS_U32 dwRegisterValue = 0;
1367
1368 dwRegisterValue = *(volatile MS_U16 *)(u32hal_sys_baseaddr + (0x000f14 << 1));
1369
1370 if(dwCorePowerVoltage < CONFIG_DVFS_CORE_POWER_DEFAULT)
1371 {
1372 //VID = 2'b10 = Core Power is 0.95V
1373 dwRegisterValue &= ~(0x01 << 1);
1374 }
1375 else
1376 {
1377 //VID = 2'b11 = Core Power is 1V
1378 dwRegisterValue |= (0x01 << 1);
1379 }
1380
1381 *(volatile MS_U16 *)(u32hal_sys_baseaddr + (0x000f14 << 1)) = dwRegisterValue;
1382 *(volatile MS_U16 *)(u32hal_sys_baseaddr + (0x100512 << 1)) = CONFIG_DVFS_DYNAMIC_POWER_ADJUST_INIT;
1383 #endif
1384 }
1385
1386 ////////////////////////////////////////////////////////////////////////////////
1387 /// @brief \b Function \b Name: SysDvfsCpuPowerInit
1388 /// @brief \b Function \b Description: The Init Flow of External Power Chip
1389 /// @param <IN> \b None:
1390 /// @param <OUT> \b None:
1391 /// @param <RET> \b None:
1392 /// @param <GLOBAL> \b None:
1393 ////////////////////////////////////////////////////////////////////////////////
SysDvfsCpuPowerInit(void)1394 void SysDvfsCpuPowerInit(void)
1395 {
1396 #if CONFIG_DVFS_CPU_POWER_I2C_ENABLE
1397 MS_U8 byTargetRegAddress[5] =
1398 {
1399 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
1400 };
1401 MS_U8 byTargetData[5] =
1402 {
1403 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
1404 };
1405 MS_U8 SWI2C_Bus_idx = 0;
1406
1407 for(SWI2C_Bus_idx = 0; SWI2C_Bus_idx < CONFIG_DVFS_POWER_SWI2C_BUS_NUM; SWI2C_Bus_idx++)
1408 {
1409 byTargetRegAddress[0] = 0x53;
1410 byTargetRegAddress[1] = 0x45;
1411 byTargetRegAddress[2] = 0x52;
1412 byTargetRegAddress[3] = 0x44;
1413 byTargetRegAddress[4] = 0x42;
1414 if(g_SysIoProc.SysSwI2CWriteBytes(CONFIG_DVFS_POWER_SWI2C_ADDR_CPU(SWI2C_Bus_idx), 5, byTargetRegAddress, 0, byTargetData) != TRUE)
1415 {
1416 DVFS_DEBUG("\033[33m[ERROR] I2C_Enter_I2C Failed\033[m\n");
1417 }
1418
1419 byTargetRegAddress[0] = 0x7F;
1420 if(g_SysIoProc.SysSwI2CWriteBytes(CONFIG_DVFS_POWER_SWI2C_ADDR_CPU(SWI2C_Bus_idx), 1, byTargetRegAddress, 0, byTargetData) != TRUE)
1421 {
1422 DVFS_DEBUG("\033[33m[ERROR] I2C_USE_CFG Failed\033[m\n");
1423 }
1424
1425 byTargetRegAddress[0] = 0x7D;
1426 if(g_SysIoProc.SysSwI2CWriteBytes(CONFIG_DVFS_POWER_SWI2C_ADDR_CPU(SWI2C_Bus_idx), 1, byTargetRegAddress, 0, byTargetData) != TRUE)
1427 {
1428 DVFS_DEBUG("\033[33m[ERROR] I2C_OUT_NO_DELAY Failed\033[m\n");
1429 }
1430
1431 byTargetRegAddress[0] = 0x50;
1432 if(g_SysIoProc.SysSwI2CWriteBytes(CONFIG_DVFS_POWER_SWI2C_ADDR_CPU(SWI2C_Bus_idx), 1, byTargetRegAddress, 0, byTargetData) != TRUE)
1433 {
1434 DVFS_DEBUG("\033[33m[ERROR] I2C_AD_BYTE_EN0 Failed\033[m\n");
1435 }
1436
1437 byTargetRegAddress[0] = 0x55;
1438 if(g_SysIoProc.SysSwI2CWriteBytes(CONFIG_DVFS_POWER_SWI2C_ADDR_CPU(SWI2C_Bus_idx), 1, byTargetRegAddress, 0, byTargetData) != TRUE)
1439 {
1440 DVFS_DEBUG("\033[33m[ERROR] I2C_DA_BYTE_EN1 Failed\033[m\n");
1441 }
1442
1443 byTargetRegAddress[0] = 0x35;
1444 if(g_SysIoProc.SysSwI2CWriteBytes(CONFIG_DVFS_POWER_SWI2C_ADDR_CPU(SWI2C_Bus_idx), 1, byTargetRegAddress, 0, byTargetData) != TRUE)
1445 {
1446 DVFS_DEBUG("\033[33m[ERROR] I2C_USE Failed\033[m\n");
1447 }
1448
1449 byTargetRegAddress[0] = 0x10;
1450 byTargetRegAddress[1] = 0xc0;
1451 if(g_SysIoProc.SysSwI2CReadBytes(CONFIG_DVFS_POWER_SWI2C_ADDR_CPU(SWI2C_Bus_idx), 2, byTargetRegAddress, 2, byTargetData) == TRUE)
1452 {
1453 DVFS_DEBUG("\033[33m[INFO] MStar Power IC Chip ID: %x%x\033[m\n", (unsigned int) byTargetData[0], (unsigned int) byTargetData[1]);
1454 hMstarDvfsInfo.dwPowerChipId = (unsigned int) byTargetData[1];
1455 hMstarDvfsInfo.dwSWI2CBusId = SWI2C_Bus_idx;
1456 }
1457 else
1458 {
1459 DVFS_DEBUG("\033[33m[ERROR] I2C_IDENTIFY_PMIC Failed\033[m\n");
1460 continue;
1461 }
1462
1463 SysDvfsCpuPowerAdjustment(CONFIG_DVFS_CPU_POWER_DEFAULT);
1464
1465 if(hMstarDvfsInfo.dwPowerChipId == CONFIG_DVFS_CHIP_ID_PRADO)
1466 {
1467 //Set OTP Level
1468 byTargetRegAddress[0] = 0x10;
1469 byTargetRegAddress[1] = (0x05 << 1);
1470 byTargetRegAddress[2] = 0x40;
1471 byTargetRegAddress[3] = 0x00;
1472 if(g_SysIoProc.SysSwI2CWriteBytes(CONFIG_DVFS_POWER_SWI2C_ADDR_CPU(SWI2C_Bus_idx), 4, byTargetRegAddress, 0, byTargetData) != TRUE)
1473 {
1474 DVFS_INFO("\033[37m[ERROR] Software I2C Write Failed\033[m\n");
1475 }
1476
1477 //Set Password
1478 byTargetRegAddress[0] = 0x10;
1479 byTargetRegAddress[1] = (0x0C << 1);
1480 byTargetRegAddress[2] = 0xbe;
1481 byTargetRegAddress[3] = 0xaf;
1482 if(g_SysIoProc.SysSwI2CWriteBytes(CONFIG_DVFS_POWER_SWI2C_ADDR_CPU(SWI2C_Bus_idx), 4, byTargetRegAddress, 0, byTargetData) != TRUE)
1483 {
1484 DVFS_INFO("\033[37m[ERROR] Software I2C Write Failed\033[m\n");
1485 }
1486 }
1487
1488 //SysDvfsCpuPowerAdjustment(CONFIG_DVFS_CPU_POWER_DEFAULT);
1489
1490 *(volatile MS_U16 *)(u32hal_sys_baseaddr + (0x100510 << 1)) = CONFIG_DVFS_DYNAMIC_POWER_ADJUST_INIT;
1491 }
1492 #endif
1493 #if CONFIG_DVFS_CPU_POWER_GPIO_ENABLE
1494 #error "No Support CPU Power Adjustment by GPIO in Messi Platform"
1495 #endif
1496 }
1497
1498 ////////////////////////////////////////////////////////////////////////////////
1499 /// @brief \b Function \b Name: SysDvfsCorePowerInit
1500 /// @brief \b Function \b Description: The Init Flow of External Power Chip
1501 /// @param <IN> \b None:
1502 /// @param <OUT> \b None:
1503 /// @param <RET> \b None:
1504 /// @param <GLOBAL> \b None:
1505 ////////////////////////////////////////////////////////////////////////////////
SysDvfsCorePowerInit(void)1506 void SysDvfsCorePowerInit(void)
1507 {
1508 #if CONFIG_DVFS_CORE_POWER_I2C_ENABLE
1509 #error "No Support Core Power Init by I2C in Messi Platform"
1510 #endif
1511 #if CONFIG_DVFS_CORE_POWER_GPIO_ENABLE
1512 MS_U32 dwRegisterValue;
1513
1514 dwRegisterValue = *(volatile MS_U16 *)(u32hal_sys_baseaddr + (0x000f14 << 1));
1515 dwRegisterValue |= 0x03;
1516 *(volatile MS_U16 *)(u32hal_sys_baseaddr + (0x000f14 << 1)) = dwRegisterValue;
1517 dwRegisterValue = *(volatile MS_U16 *)(u32hal_sys_baseaddr + (0x000f14 << 1));
1518 dwRegisterValue &= 0x01;
1519 *(volatile MS_U16 *)(u32hal_sys_baseaddr + (0x000f14 << 1)) = dwRegisterValue;
1520
1521 *(volatile MS_U16 *)(u32hal_sys_baseaddr + (0x000e38 << 1)) &= ~(0x01 << 10);
1522 *(volatile MS_U16 *)(u32hal_sys_baseaddr + (0x100512 << 1)) = CONFIG_DVFS_DYNAMIC_POWER_ADJUST_INIT;
1523 #endif
1524 }
1525
1526 #endif
1527
1528 ////////////////////////////////////////////////////////////////////////////////
1529 /// @brief \b Function \b Name: HAL_SYS_GetMemcConfg
1530 /// @brief \b Function \b Description: Query the result of config MEMC
1531 /// @param <IN> \b eSource:
1532 /// @param <IN> \b eTiming:
1533 /// @param <OUT> \b retEnMemc:
1534 /// @param <RET> \b E_SYS_ReturnValue:
1535 /// @param <GLOBAL> \b None:
1536 ////////////////////////////////////////////////////////////////////////////////
HAL_SYS_GetMemcConfg(MS_U32 eSource,MS_U32 eTiming,MS_BOOL * retEnMemc)1537 MS_U32 HAL_SYS_GetMemcConfg(MS_U32 eSource, MS_U32 eTiming, MS_BOOL *retEnMemc)
1538 {
1539 return E_SYS_NOT_SUPPORT;
1540 }
1541
1542 ////////////////////////////////////////////////////////////////////////////////
1543 /// @brief \b Function \b Name: HAL_SYS_GetXcByPartConfg
1544 /// @brief \b Function \b Description: Query the result of config Bypart XC
1545 /// @param <IN> \b eSource:
1546 /// @param <IN> \b eInputTiming:
1547 /// @param <IN> \b eOutputTiming:
1548 /// @param <OUT> \b retEn:
1549 /// @param <RET> \b E_SYS_ReturnValue:
1550 /// @param <GLOBAL> \b None:
1551 ////////////////////////////////////////////////////////////////////////////////
HAL_SYS_GetXcByPartConfg(MS_U32 eSource,MS_U32 eInputTiming,MS_U32 eOutputTiming,MS_BOOL * retEn)1552 MS_U32 HAL_SYS_GetXcByPartConfg (MS_U32 eSource, MS_U32 eInputTiming, MS_U32 eOutputTiming, MS_BOOL *retEn)
1553 {
1554 return E_SYS_NOT_SUPPORT;
1555 }
1556