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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regAESDMA.h 98 // Description: AESDMA Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _AESDMA_REG_MCU_H_ 103 #define _AESDMA_REG_MCU_H_ 104 105 106 //-------------------------------------------------------------------------------------------------- 107 // Abbreviation 108 //-------------------------------------------------------------------------------------------------- 109 // Addr Address 110 // Buf Buffer 111 // Clr Clear 112 // CmdQ Command queue 113 // Cnt Count 114 // Ctrl Control 115 // Flt Filter 116 // Hw Hardware 117 // Int Interrupt 118 // Len Length 119 // Ovfw Overflow 120 // Pkt Packet 121 // Rec Record 122 // Recv Receive 123 // Rmn Remain 124 // Reg Register 125 // Req Request 126 // Rst Reset 127 // Scmb Scramble 128 // Sec Section 129 // Stat Status 130 // Sw Software 131 // Ts Transport Stream 132 133 134 //-------------------------------------------------------------------------------------------------- 135 // Global Definition 136 //-------------------------------------------------------------------------------------------------- 137 138 139 //-------------------------------------------------------------------------------------------------- 140 // Compliation Option 141 //-------------------------------------------------------------------------------------------------- 142 143 144 //------------------------------------------------------------------------------------------------- 145 // Harware Capability 146 //------------------------------------------------------------------------------------------------- 147 148 149 //------------------------------------------------------------------------------------------------- 150 // Type and Structure 151 //------------------------------------------------------------------------------------------------- 152 #define REG_AESDMACTRL_BASE 0x47940 //(0x23C00/2 + 0x50) * 4 153 #define REG_SHARNGCTRL_BASE 0x47800 //(0x23C00/2 + 0x0) * 4 154 #define REG_DMASECURE_CTRL_BASE 0x27A00 //(0x13D00/2 + 0x00) * 4 155 #define REG_DMASECURE_BASE 0x27B40 //(0x13D00/2 + 0x50) * 4 156 #define REG_AESDMACLK_BASE 0x06660 //(0x03300/2 + 0x18) * 4 157 //#define REG_AESDMAMBX_BASE 0x17F8 //(0x0B00/2 + 0x7F) * 4 158 #define REG_AESDMAMBX_BASE 0x7B84 //(0x3D00/2 + 0x61) * 4 159 #define REG_PARSERCTRL_BASE 0x45800 //(0x22C00/2 + 0x00) * 4 160 #define REG_CIPHERCTRL_BASE 0x45840 //(0x22C00/2 + 0x10) * 4 161 #define REG_AESDMAEXT_BASE 0x45980 //(0x22C00/2 + 0x60) * 4 162 #define RSA_E_BASE_ADDR (0x00) 163 #define RSA_N_BASE_ADDR (0x40) 164 #define RSA_A_BASE_ADDR (0x80) 165 #define RSA_Z_BASE_ADDR (0xC0) 166 #define REG_HDCP22_BASE 0xC5400 //(0x62A00/2 + 0x00) * 4 //P0: Bank 0x162A_h��00~07 167 #define REG_HDCP22_SEK 0xC5438 //(0x62A00/2 + 0x0E) * 4 168 169 typedef struct _REG32 170 { 171 volatile MS_U16 L; 172 volatile MS_U16 empty_L; 173 volatile MS_U16 H; 174 volatile MS_U16 empty_H; 175 } REG32; 176 177 typedef struct _REG_CipherKey 178 { 179 REG32 Key_L; 180 REG32 Key_H; 181 } REG_CipherKey; 182 183 typedef struct _REG_InitVector 184 { 185 REG32 IV_L; 186 REG32 IV_H; 187 } REG_InitVector; 188 189 typedef struct _REG_AESDMACtrl 190 { 191 REG32 Dma_Ctrl; //0x50 192 #define AESDMA_CTRL_FILEIN_START 0x00000100 193 #define AESDMA_CTRL_FILEOUT_START 0x00000001 194 #define AESDMA_CTRL_SW_RST 0x00000080 195 196 #define AESDMA_ENG_PS_RELEASE 0x00010000 197 #define AESDMA_ENG_PS_IN_EN 0x00100000 198 #define AESDMA_ENG_PS_OUT_EN 0x00200000 199 #define AESDMA_ENG_AES_EN 0x01000000 200 #define AESDMA_ENG_DES_EN 0x00040000 201 #define AESDMA_ENG_TDES_EN 0x00080000 202 #define AESDMA_ENG_DESCRYPT 0x02000000 // 0:encrypt, 1:decrypt 203 #define AESDMA_ENG_CTR_MODE 0x10000000 204 #define AESDMA_ENG_CBC_MODE 0x20000000 205 #define AESDMA_ENG_CTS_CBC_MODE 0x40000000 206 #define AESDMA_ENG_CTS_ECB_MODE 0x00000002 207 #define AESDMA_ECO_FIX_LAST_BYTE 0x80000000 // when (output address + length)/8=1 the last byte maybe no output 208 209 REG32 Dma_Filein_Addr; //0x52 210 REG32 Dma_Filein_Num; //0x54 211 REG32 Dma_Fileout_SAddr; //0x56 212 REG32 Dma_Fileout_EAddr; //0x58 213 REG32 Dma_PS_Pattern; //0x5a 214 REG32 Dma_PS_Pattern_Mask; //0x5c 215 REG32 Dma_Ctrl2; //0x5e 216 #define AESDMA_DMA_USE_TDES_EN 0x00000100 // DES/TDES path switch 217 #define AESDMA_CTRL_BANK_R_H 0x00002000 218 #define AESDMA_CTRL_BANK_W_H 0x00004000 219 #define AESDMA_CTRL_BANK_R 0x00000010 220 #define AESDMA_CTRL_BANK_W 0x00000020 221 #define AESDMA_INT_EN 0x00000080 222 #define AESDMA_USE_SECRET_KEY 0x00001000 223 #define AESDMA_WADR_ERR_CLR 0x00000001 224 225 REG_CipherKey Dma_CipherKey_L; //0x60 226 REG_CipherKey Dma_CipherKey_H; //0x64 227 REG_InitVector Dma_InitVector_L; //0x68 228 REG_InitVector Dma_InitVector_H; //0x6C 229 REG32 Dma_Matched_Btyecnt; //0x70 230 REG32 Dma_Matched_Pat; //0x72 231 REG32 Dma_Err_Wadr; //0x74 232 REG32 _xbf808fd8[4]; //0x76~0x7c 233 REG32 Dma_PVR_Status; //0x7e 234 #define AESDMA_IS_FINISHED 0x00010000 235 /* 236 #define AESDMA_PS_DONE 0x00000001 237 #define AESDMA_PS_STOP 0x00000002 238 #define AESDMA_DMA_DONE 0x00010000 239 #define AESDMA_DMA_PAUSE 0x00020000 240 #define AESDMA_STATES_GROUP (AESDMA_PS_DONE | \ 241 AESDMA_PS_STOP | \ 242 AESDMA_DMA_DONE | \ 243 AESDMA_DMA_PAUSE ) 244 */ 245 }REG_AESDMACtrl; 246 247 #define DmaCtrlSet (AESDMA_ENG_AES_EN | \ 248 AESDMA_ENG_DES_EN | \ 249 AESDMA_ENG_TDES_EN | \ 250 AESDMA_ENG_DESCRYPT | \ 251 AESDMA_ENG_CTR_MODE | \ 252 AESDMA_ENG_CBC_MODE | \ 253 AESDMA_ENG_CTS_CBC_MODE | \ 254 AESDMA_ENG_CTS_ECB_MODE) 255 256 typedef struct _REG_SHARNGCtrl 257 { 258 REG32 Rng_Ctrl; //0x00 259 #define SHARNG_CTRL_RNG_SW_RST 0x00000080 260 #define MOBF_IN_MIU_READ_EN 0x00010000 261 #define MOBF_IN_MIU_WRITE_EN 0x00020000 262 #define MOBF_ONEWAY_EN 0x01000000 263 264 #define SECRET_KEY_IN_NORMAL_BANK 0x08000000 265 266 267 REG32 Rng_Out; //0x02 268 REG32 MOBF_KeyR; //0x04 269 REG32 MOBF_KeyW; //0x06 270 REG32 Sha_Ctrl; //0x08 271 #define SHARNG_CTRL_SHA_FIRE_ONCE 0x00000001 272 #define SHARNG_CTRL_SHA_CLR 0x00000040 273 #define SHARNG_CTRL_SHA_RST 0x00000080 274 #define SHARNG_CTRL_SHA_INT 0x00000100 275 #define SHARNG_CTRL_SHA_SEL_SHA256 0x00000200 276 #define SHARNG_CTRL_SHA_BYPASS_TABLE_EN 0x00000800 277 #define SHARNG_CTRL_SHA_INITIAL_HASH_EN 0x00002000 278 #define SHARNG_CTRL_SHA_WORKMODE_MANUAL_EN 0x00004000 279 #define SHARNG_CTRL_SHA_MSG_INVERSE 0x00040000 280 #define SHARNG_CTRL_SHA_MSG_BLOCK_NUM 0x00010000 /* Always be 1 */ 281 #define SHARNG_CTRL_SPEED_MODE_N 0x00000010 282 283 REG32 Sha_Start; //0x0a 284 REG32 Sha_Length; //0x0c 285 REG32 Sha_Status; //0x0e 286 #define SHARNG_CTRL_SHA_BUSY 0x00020000 287 #define SHARNG_CTRL_SHA_READY 0x00010000 288 289 REG32 Sha_Out[8]; //0x10~0x1E 290 REG32 Rsa_Ind32_Start; //0x20 291 #define RSA_INDIRECT_START 0x00000001 292 #define RSA_IND32_CTRL_DIRECTION_WRITE 0x00020000 293 #define RSA_IND32_CTRL_ADDR_AUTO_INC 0x00040000 294 #define RSA_IND32_CTRL_ACCESS_AUTO_START 0x00080000 295 REG32 Rsa_Ind32_Addr; //0x22 296 #define RSA_ADDRESS_MASK 0x0000FFFF 297 #define RSA_WDATA_MASK_L 0xFFFF0000 298 REG32 Rsa_Ind32_WData; //0x24 299 #define RSA_WDATA_MASK_H 0x0000FFFF 300 #define RSA_RDATA_MASK_L 0xFFFF0000 301 REG32 Rsa_Ind32_RData; //0x26 302 #define RSA_RDATA_MASK_H 0x0000FFFF 303 #define RSA_EXP_START 0x00010000 304 #define RSA_INT_CLR 0x00020000 305 REG32 Rsa_Ctrl; //0x28 306 #define RSA_CTRL_RSA_RST 0x00000001 307 #define RSA_CTRL_SEL_HW_KEY 0x00000002 308 #define RSA_CTRL_SEL_PUBLIC_KEY 0x00000004 309 #define RSA_CTRL_KEY_LENGTH_MASK 0x00003F00 310 #define RSA_STATUS_RSA_BUSY 0x00010000 311 #define RSA_STATUS_MASK 0x00FF0000 312 }REG_SHARNGCtrl; 313 314 typedef struct _REG_DMASECURECtrl 315 { 316 REG32 Secure_file_st; //0x50 317 REG32 reserved52; //0x52 318 REG32 reserved54; //0x54 319 REG32 reserved56; //0x56 320 REG32 reserved58; //0x58 321 REG32 reserved5a; //0x5a 322 REG32 reserved5c; //0x5c 323 REG32 reserved5e; //0x5e 324 REG_CipherKey Secure_CipherKey_L; //0x60 325 REG_CipherKey Secure_CipherKey_H; //0x64 326 REG_InitVector Secure_InitVector_L; //0x68 327 REG_InitVector Secure_InitVector_H; //0x6C 328 REG32 reserved70; //0x70 329 REG32 reserved72; //0x72 330 REG32 reserved74; //0x74 331 REG32 reserved76; //0x76 332 REG32 Secure_dma3_ctrl; //0x78 333 #define AESDMA_SECURE_PROTECT_S 0x00010000 334 #define AESDMA_USE_SECRET_KEY0 0x00200000 335 #define AESDMA_USE_SECRET_KEY1 0x00400000 336 REG32 reserved7a; //0x7a 337 REG32 reserved7c; //0x7c 338 REG32 Secure_dma3_status; //0x7e 339 }REG_DMASECURECtrl; 340 341 typedef struct _REG_CKG_AESDMA 342 { 343 REG32 Reg_Gate_Clk_AESDMA; //0x18 344 #define AESDMA_CLK_GATED 0x80000000 345 REG32 Reg_AESDMAClk; //0x1A 346 #define AESDMA_CLK_DISABLE 0x00000001 347 }REG_AESDMAClk; 348 349 typedef struct _REG_MBX_AESDMA 350 { 351 REG32 Reg_Et_Rpd; //0x61 352 #define AESDMA_SEM_USED 0x00000100 353 #define AESDMA_CLK_USED 0x00000200 354 #define TSP_CLK_USED 0x00000400 355 }REG_AESDMAMbx; 356 357 358 typedef struct _REG_PARSERCtrl 359 { 360 REG32 Parser_Ctrl; //0x00 361 #define HDCP20_MODE 0x00000001 362 #define PKT192_MODE 0x00000002 363 #define AUTO_MODE 0x00000004 364 #define TRIGGER_MODE 0x00000008 365 #define INIT_TRUST 0x00000010 366 #define CLEAR_MODE 0x00000020 367 #define REMOVE_SCRMB 0x00000040 368 #define INSERT_SCRMB 0x00000080 369 #define SCRMB_PATTERN10 0x00000400 370 #define SCRMB_PATTERN11 0x00000600 371 #define SCRMB_INITVALUE 0x00000600 372 #define HW_PARSER_MODE 0x00000100 373 #define TS_SCRMB_MASK 0x00000800 374 #define TS_MODE 0x00008000 375 #define PARSER_PID0_MASK 0x1FFF0000 376 REG32 Parser_Pid1; //0x02 377 #define PARSER_PID1_MASK 0x00001FFF 378 #define BYPASS_PID 0x00080000 379 #define SCRMB_PATTERN10_ADD 0x00200000 380 #define SCRMB_PATTERN11_ADD 0x00300000 381 #define SCRMB_INITVALUE_ADD 0x00300000 382 #define SCRMB_ENABLE_TWO_KEY 0x00400000 383 REG32 Parser_Status; //0x04 384 385 }REG_PARSERCtrl; 386 387 typedef struct _REG_CIPHERCtrl 388 { 389 REG32 Cipher_Ctrl; //0x00 390 #define CC_CTRL_BY_ACPU 0x00000080 391 REG32 Cipher_len; //0x02 392 REG32 Parser_Status; //0x04 393 394 }REG_CIPHERCtrl; 395 396 #define ParserCtrlSet (HDCP20_MODE | \ 397 PKT192_MODE | \ 398 AUTO_MODE | \ 399 TRIGGER_MODE | \ 400 INIT_TRUST | \ 401 CLEAR_MODE | \ 402 HW_PARSER_MODE | \ 403 TS_MODE ) 404 405 typedef struct _REG_AESDMACtrlEx 406 { 407 REG_CipherKey Dma_CipherKey_L; //0x60 408 REG_CipherKey Dma_CipherKey_H; //0x64 409 REG_InitVector Dma_InitVector_L; //0x68 410 REG_InitVector Dma_InitVector_H; //0x6C 411 }REG_AESDMACtrlEx; 412 413 typedef struct _REG_HDCP22Data 414 { 415 REG32 Hdcp22_ContentKey[4]; 416 REG32 Hdcp22_Riv[2]; 417 }REG_HDCP22Data; 418 419 typedef struct _REG_HDCP22SEKCtrl 420 { 421 REG32 SEK; //0x9C 422 #define HDCP_SEK_BIT0 0x00000001 423 }REG_HDCP22SEKCtrl; 424 425 typedef struct _REG_GENERAL_STRUCT 426 { 427 REG32 Reg0001; //0x00 428 REG32 Reg0203; //0x02 429 REG32 Reg0405; //0x04 430 REG32 Reg0607; //0x06 431 REG32 Reg0809; //0x08 432 }REG_GENERAL_STRUCT; 433 434 typedef REG_GENERAL_STRUCT REG_TZPCCtrl; //BANK: 0x1239 435 #define REG_TZPC2NONPM_RNG_SOURCE_EN 0x000F0000UL //0x03[3:0] 436 437 typedef REG_GENERAL_STRUCT REG_SECUREBASECtrl; //BANK: 0x113D 438 #define REG_RNG_EN 0x00000080UL //0x00[7] 439 440 441 #endif // #ifndef _AESDMA_REG_MCU_H_ 442