xref: /utopia/UTPA2-700.0.x/modules/security/hal/maldives/aesdma/halAESDMA.c (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
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94 
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file   halAESDMA.c
97 // @brief  AESDMA HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100 
101 #include "MsCommon.h"
102 #include "regAESDMA.h"
103 #include "halAESDMA.h"
104 #include "halCHIP.h"
105 
106 
107 //--------------------------------------------------------------------------------------------------
108 //  Driver Compiler Option
109 //--------------------------------------------------------------------------------------------------
110 
111 
112 //--------------------------------------------------------------------------------------------------
113 //  TSP Hardware Abstraction Layer
114 //--------------------------------------------------------------------------------------------------
115 static MS_U32                _u32RegBase = NULL;
116 static MS_U32                _u32PmRegBase = NULL;
117 static MS_U32                SECUREBASECtrl_Buffer;
118 static REG_AESDMACtrl        *_AESDMACtrl = (REG_AESDMACtrl*)REG_AESDMACTRL_BASE;
119 static REG_SHARNGCtrl        *_SHARNGCtrl = (REG_SHARNGCtrl*)REG_SHARNGCTRL_BASE;
120 static REG_AESDMAClk         *_AESDMAClk  = (REG_AESDMAClk*)REG_AESDMACLK_BASE;
121 static REG_AESDMAMbx         *_AESDMAMbx  = (REG_AESDMAMbx*)REG_AESDMAMBX_BASE;
122 static REG_PARSERCtrl        *_PARSERCtrl = (REG_PARSERCtrl*)REG_PARSERCTRL_BASE;
123 static REG_CIPHERCtrl        *_CIPHERCtrl = (REG_CIPHERCtrl*)REG_CIPHERCTRL_BASE;
124 static REG_DMASECURECtrl     *_DMASECURECtrl = (REG_DMASECURECtrl*)REG_DMASECURE_BASE;
125 static REG_SECUREBASECtrl    *_SECUREBASECtrl = (REG_SECUREBASECtrl*)REG_DMASECURE_CTRL_BASE;
126 static REG_AESDMACtrlEx      *_AESDMACtrlEx = (REG_AESDMACtrlEx*)REG_AESDMAEXT_BASE;
127 static REG_HDCP22Data        *_HDCP22Data = (REG_HDCP22Data*)REG_HDCP22_BASE;
128 static REG_HDCP22SEKCtrl     *_HDCP22SekCtrl = (REG_HDCP22SEKCtrl*)REG_HDCP22_SEK;
129 #define REG32_W(reg, value)     do {    \
130                                     (reg)->H = ((value) >> 16); \
131                                     (reg)->L = ((value) & 0x0000FFFF);  \
132                                 } while(0)
133 
134 //--------------------------------------------------------------------------------------------------
135 //  Macro of bit operations
136 //--------------------------------------------------------------------------------------------------
137 
_AESDMA_REG32_R(REG32 * reg)138 MS_U32 _AESDMA_REG32_R(REG32 *reg)
139 {
140     MS_U32     value;
141 
142     value = (reg)->H << 16;
143     value |= (reg)->L;
144 
145     return value;
146 }
147 
148 //--------------------------------------------------------------------------------------------------
149 //  Inline Function
150 //--------------------------------------------------------------------------------------------------
HAL_AESDMA_SetBank(MS_U32 u32NonPmBankAddr,MS_U32 u32PmBankAddr)151 void HAL_AESDMA_SetBank(MS_U32 u32NonPmBankAddr, MS_U32 u32PmBankAddr)
152 {
153     _u32RegBase = u32NonPmBankAddr;
154     _u32PmRegBase = u32PmBankAddr;
155     _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_AESDMACTRL_BASE);
156     _SHARNGCtrl = (REG_SHARNGCtrl*)(_u32RegBase + REG_SHARNGCTRL_BASE);
157     _AESDMAClk = (REG_AESDMAClk*)(_u32RegBase + REG_AESDMACLK_BASE);
158     _AESDMAMbx = (REG_AESDMAMbx*)(_u32PmRegBase + REG_AESDMAMBX_BASE);
159     _PARSERCtrl = (REG_PARSERCtrl*)(_u32RegBase + REG_PARSERCTRL_BASE);
160     _CIPHERCtrl = (REG_CIPHERCtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE);
161     _DMASECURECtrl = (REG_DMASECURECtrl*)(_u32RegBase + REG_DMASECURE_BASE);
162     _SECUREBASECtrl = (REG_SECUREBASECtrl*)(_u32RegBase + REG_DMASECURE_CTRL_BASE);
163     _AESDMACtrlEx = (REG_AESDMACtrlEx*)(_u32RegBase + REG_AESDMAEXT_BASE);
164     _HDCP22Data = (REG_HDCP22Data*)(_u32RegBase + REG_HDCP22_BASE);
165     _HDCP22SekCtrl = (REG_HDCP22SEKCtrl*)(_u32RegBase + REG_HDCP22_SEK);
166 }
167 
AESDMA_GetMIU1Base(void)168 MS_U32 AESDMA_GetMIU1Base(void)
169 {
170     return HAL_MIU1_BASE;
171 }
172 
AESDMA_GetMIU2Base(void)173 MS_U32 AESDMA_GetMIU2Base(void)
174 {
175     //not support
176     return FALSE;
177 }
178 
AESDMA_Reset(void)179 void AESDMA_Reset(void)
180 {
181     MS_U32 Reg_AESDMA;
182     int i = 0;
183     Reg_AESDMA = (MS_U32)(&_AESDMACtrl[0].Dma_Ctrl);
184 
185     REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register
186     REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(AESDMA_CTRL_SW_RST)); // sw rst
187     REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_SW_RST));
188 
189     // reset all AESdma register
190     for (i = 0 ; i < 19 ; i++)
191     {
192         REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000);
193     }
194     // reset secure_dma3_ctrl register
195     REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000);
196 
197     // reset hw_parser_ctrl register
198     REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x01000000);
199     REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000);
200 }
201 
AESDMA_Set_CipherKey(MS_U32 * cipherkey)202 void AESDMA_Set_CipherKey(MS_U32 *cipherkey)
203 {
204     REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_L) , cipherkey[0]);
205     REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_H) , cipherkey[1]);
206     REG32_W((&_AESDMACtrl[0].Dma_CipherKey_H.Key_L) , cipherkey[2]);
207     REG32_W((&_AESDMACtrl[0].Dma_CipherKey_H.Key_H) , cipherkey[3]);
208 }
209 
AESDMA_Set_InitVector(MS_U32 * pInitVector)210 void AESDMA_Set_InitVector(MS_U32 *pInitVector)
211 {
212     REG32_W((&_AESDMACtrl[0].Dma_InitVector_L.IV_L), pInitVector[0]);
213     REG32_W((&_AESDMACtrl[0].Dma_InitVector_L.IV_H), pInitVector[1]);
214     REG32_W((&_AESDMACtrl[0].Dma_InitVector_H.IV_L), pInitVector[2]);
215     REG32_W((&_AESDMACtrl[0].Dma_InitVector_H.IV_H), pInitVector[3]);
216 }
217 
AESDMA_Sel_Key(MS_BOOL keysel)218 void AESDMA_Sel_Key(MS_BOOL keysel)
219 {
220 }
221 
AESDMA_Sel_SecureKey(void)222 void AESDMA_Sel_SecureKey(void)
223 {
224     MS_U32 u32Ctrl = _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2);
225     u32Ctrl |= AESDMA_USE_SECRET_KEY;
226     REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), u32Ctrl);
227 }
228 
AESDMA_Set_FileinDesc(MS_U32 FileinAddr,MS_U32 FileinNum)229 void AESDMA_Set_FileinDesc(MS_U32 FileinAddr , MS_U32 FileinNum)
230 {
231     REG32_W((&_AESDMACtrl[0].Dma_Filein_Addr), FileinAddr);
232     REG32_W((&_AESDMACtrl[0].Dma_Filein_Num), FileinNum);
233 }
234 
AESDMA_Set_FileoutDesc(MS_U32 FileoutSAddr,MS_U32 FileoutEAddr)235 void AESDMA_Set_FileoutDesc(MS_U32 FileoutSAddr , MS_U32 FileoutEAddr)
236 {
237     REG32_W((&_AESDMACtrl[0].Dma_Fileout_SAddr), FileoutSAddr);
238     REG32_W((&_AESDMACtrl[0].Dma_Fileout_EAddr), FileoutEAddr);
239 }
240 
AESDMA_Start(MS_BOOL AESDMAStart)241 void AESDMA_Start(MS_BOOL AESDMAStart)
242 {
243     if (AESDMAStart)
244     {
245         REG32_W((&_AESDMACtrl[0].Dma_Ctrl), (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) &~ AESDMA_CTRL_FILEOUT_START &~ AESDMA_CTRL_FILEIN_START));
246         REG32_W((&_AESDMACtrl[0].Dma_Ctrl), (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) | AESDMA_CTRL_FILEOUT_START | AESDMA_CTRL_FILEIN_START));
247     }
248     else
249     {
250         REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_FILEOUT_START|AESDMA_CTRL_FILEIN_START));
251     }
252 }
253 
AESDMA_Set_PS_PTN(MS_U32 MatchPTN)254 void AESDMA_Set_PS_PTN(MS_U32 MatchPTN)
255 {
256     REG32_W((&_AESDMACtrl[0].Dma_PS_Pattern) , MatchPTN);
257 }
258 
AESDMA_Set_PS_Mask(MS_U32 MatchMask)259 void AESDMA_Set_PS_Mask(MS_U32 MatchMask)
260 {
261     REG32_W((&_AESDMACtrl[0].Dma_PS_Pattern_Mask) , MatchMask);
262 }
263 
AESDMA_Set_PS_ENG(MS_BOOL PSin_en,MS_BOOL PSout_en)264 void AESDMA_Set_PS_ENG(MS_BOOL PSin_en, MS_BOOL PSout_en)
265 {
266     MS_U32 u32PSin, u32PSout;
267 
268     u32PSin  = AESDMA_ENG_PS_IN_EN & (PSin_en<<20);
269     u32PSout = AESDMA_ENG_PS_OUT_EN & (PSout_en<<21);
270 
271     REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(u32PSin|u32PSout));
272 }
273 
AESDMA_Get_PS_MatchedBytecnt(void)274 MS_U32 AESDMA_Get_PS_MatchedBytecnt(void)
275 {
276     return _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Matched_Btyecnt);
277 }
278 
AESDMA_Get_PS_MatchedPTN(void)279 MS_U32 AESDMA_Get_PS_MatchedPTN(void)
280 {
281     return _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Matched_Pat);
282 }
283 
AESDMA_Set_PS_Release(void)284 void AESDMA_Set_PS_Release(void)
285 {
286     REG32_W((&_AESDMACtrl[0].Dma_Ctrl), _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|AESDMA_ENG_PS_RELEASE);
287     REG32_W((&_AESDMACtrl[0].Dma_Ctrl), _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) & ~AESDMA_ENG_PS_RELEASE);
288 }
289 
AESDMA_Get_AESDMA_Status(void)290 MS_U32 AESDMA_Get_AESDMA_Status(void)
291 {
292     return _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_PVR_Status);
293 }
294 
AESDMA_Get_AESDMA_IsFinished(void)295 MS_U32 AESDMA_Get_AESDMA_IsFinished(void)
296 {
297     return (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_PVR_Status) & AESDMA_IS_FINISHED);
298 }
299 
AESDMA_Set_CIPHER_ENG(AESDMA_CipherMode eMode,MS_BOOL Descrypt)300 void AESDMA_Set_CIPHER_ENG(AESDMA_CipherMode eMode, MS_BOOL Descrypt)
301 {
302     MS_U32 u32Cmd = 0;
303 
304     switch (eMode)
305     {
306     case E_AESDMA_CIPHER_ECB:
307         u32Cmd |= AESDMA_ENG_AES_EN;
308         break;
309 
310     case E_AESDMA_CIPHER_CTR:
311         u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CTR_MODE);
312         break;
313 
314     case E_AESDMA_CIPHER_CBC:
315         u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CBC_MODE);
316         break;
317 
318     case E_AESDMA_CIPHER_DES_ECB:
319         u32Cmd |= AESDMA_ENG_DES_EN;
320         break;
321 
322     case E_AESDMA_CIPHER_DES_CTR:
323         u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CTR_MODE);
324         break;
325 
326     case E_AESDMA_CIPHER_DES_CBC:
327         u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CBC_MODE);
328         break;
329 
330     case E_AESDMA_CIPHER_TDES_ECB:
331         u32Cmd |= AESDMA_ENG_TDES_EN;
332         break;
333 
334     case E_AESDMA_CIPHER_TDES_CTR:
335         u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CTR_MODE);
336         break;
337 
338     case E_AESDMA_CIPHER_TDES_CBC:
339         u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CBC_MODE);
340         break;
341 
342     case E_AESDMA_CIPHER_CTS_CBC:
343         u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CTS_CBC_MODE);
344         break;
345 
346     case E_AESDMA_CIPHER_CTS_ECB:
347         u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CTS_ECB_MODE);
348         break;
349 
350     case E_AESDMA_CIPHER_DES_CTS_CBC:
351         u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CTS_CBC_MODE);
352         break;
353 
354     case E_AESDMA_CIPHER_DES_CTS_ECB:
355         u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CTS_ECB_MODE);
356         break;
357 
358     case E_AESDMA_CIPHER_TDES_CTS_CBC:
359         u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CTS_CBC_MODE);
360         break;
361 
362     case E_AESDMA_CIPHER_TDES_CTS_ECB:
363         u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CTS_ECB_MODE);
364         break;
365     default:
366         return;
367     }
368 
369 	if( eMode >= E_AESDMA_CIPHER_DES_ECB )
370 		REG32_W((&_AESDMACtrl[0].Dma_Ctrl2),_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2) | AESDMA_DMA_USE_TDES_EN);
371 
372     u32Cmd |= AESDMA_ENG_DESCRYPT & (Descrypt<<25);
373     REG32_W((&_AESDMACtrl[0].Dma_Ctrl),(( _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) & (~DmaCtrlSet)) | u32Cmd ) );
374 }
375 
AESDMA_QueryCipherMode(AESDMA_CipherMode eMode)376 MS_U32 AESDMA_QueryCipherMode(AESDMA_CipherMode eMode)
377 {
378     MS_U32 u32Result = 1;
379 
380     switch (eMode)
381     {
382     case E_AESDMA_CIPHER_ECB:
383     case E_AESDMA_CIPHER_CTR:
384     case E_AESDMA_CIPHER_CBC:
385     case E_AESDMA_CIPHER_DES_ECB:
386     case E_AESDMA_CIPHER_DES_CTR:
387     case E_AESDMA_CIPHER_DES_CBC:
388     case E_AESDMA_CIPHER_TDES_ECB:
389     case E_AESDMA_CIPHER_TDES_CTR:
390     case E_AESDMA_CIPHER_TDES_CBC:
391     case E_AESDMA_CIPHER_CTS_CBC:
392     case E_AESDMA_CIPHER_CTS_ECB:
393     case E_AESDMA_CIPHER_DES_CTS_CBC:
394     case E_AESDMA_CIPHER_DES_CTS_ECB:
395     case E_AESDMA_CIPHER_TDES_CTS_CBC:
396     case E_AESDMA_CIPHER_TDES_CTS_ECB:
397         u32Result = 0;
398         break;
399     default:
400         break;
401     }
402     return u32Result;
403 
404 }
405 
AESDMA_Set_MIU_Path(MS_BOOL MIU_R,MS_BOOL MIU_W)406 void AESDMA_Set_MIU_Path(MS_BOOL MIU_R, MS_BOOL MIU_W)
407 {
408     REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), RESET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), AESDMA_CTRL_BANK_R));
409     REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), RESET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), AESDMA_CTRL_BANK_W));
410 
411     REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), SET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), (AESDMA_CTRL_BANK_R & ((MS_U32)MIU_R << 4))));
412     REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), SET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), (AESDMA_CTRL_BANK_W & ((MS_U32)MIU_W << 5))));
413 }
414 
AESDMA_Set_MIU2_Path(MS_BOOL MIU_R,MS_BOOL MIU_W)415 void AESDMA_Set_MIU2_Path(MS_BOOL MIU_R, MS_BOOL MIU_W)
416 {
417     // Not support
418 }
419 
AESDMA_Enable_Int(void)420 void AESDMA_Enable_Int(void)
421 {
422 #ifndef CONFIG_MBOOT
423     REG32_W((&_AESDMACtrl[0].Dma_Ctrl2) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2)|AESDMA_INT_EN);
424 #endif
425 }
426 
AESDMA_Disable_Int(void)427 void AESDMA_Disable_Int(void)
428 {
429     REG32_W((&_AESDMACtrl[0].Dma_Ctrl2) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2)&~AESDMA_INT_EN);
430 }
431 
AESDMA_Clear_Int(void)432 void AESDMA_Clear_Int(void)
433 {
434     REG32_W((&_AESDMACtrl[0].Dma_Ctrl2) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2)|AESDMA_WADR_ERR_CLR);
435     REG32_W((&_AESDMACtrl[0].Dma_Ctrl2) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2)&~AESDMA_WADR_ERR_CLR);
436 }
437 
AESDMA_HW_Patch(void)438 void AESDMA_HW_Patch(void)
439 {
440     REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|AESDMA_ECO_FIX_LAST_BYTE);
441 }
442 
AESDMA_Enable_Clk(void)443 void AESDMA_Enable_Clk(void)
444 {
445     MS_U32 u32Val;
446 
447     //1. clk_aesdma
448     u32Val = _AESDMA_REG32_R(&_AESDMAClk[0].Reg_Gate_Clk_AESDMA);
449     u32Val &= ~0xF0000; //Set Clk to 172M, Enable Clk
450     REG32_W((&_AESDMAClk[0].Reg_Gate_Clk_AESDMA) , u32Val);
451 
452     //
453     // Due to the security concern
454     // Set this CLK at SBOOT
455     //
456 
457     //2. clk_rc
458     //Enable 0x1239_0x03[3:0] = 4b'1111
459 
460     //3. Enable Rng
461     u32Val = _AESDMA_REG32_R(&_SECUREBASECtrl[0].Reg0001);
462     u32Val |= REG_RNG_EN;
463     REG32_W((&_SECUREBASECtrl[0].Reg0001) , u32Val);
464 
465 }
466 
AESDMA_Disable_Clk(void)467 void AESDMA_Disable_Clk(void)
468 {
469     REG32_W((&_AESDMAClk[0].Reg_Gate_Clk_AESDMA) , _AESDMA_REG32_R(&_AESDMAClk[0].Reg_Gate_Clk_AESDMA) | AESDMA_CLK_DISABLE);
470 }
471 
AESDMA_Rand(void)472 MS_U8 AESDMA_Rand(void)
473 {
474    MS_U8 u8RN = 0x00;
475    u8RN = (MS_U8)_AESDMA_REG32_R(&_SECUREBASECtrl[0].Reg0203)&0xFF;
476 
477    return u8RN;
478 }
479 
SHA_Reset(void)480 void SHA_Reset(void)
481 {
482     MS_U32 Reg_SHARNG;
483     int i = 0;
484     Reg_SHARNG = (MS_U32)(&_SHARNGCtrl[0].Sha_Ctrl);
485     REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , SHARNG_CTRL_SHA_RST); // 0->1
486 	REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , (_AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&(~SHARNG_CTRL_SHA_RST))); // 1->0
487 
488 	// reset all SHA & RNG register
489     for (i = 0 ; i < 7 ; i++)
490     {
491         REG32_W((REG32 *)(Reg_SHARNG+(i*8)), 0x00000000);
492     }
493 }
494 
SHA_Get_Status(void)495 MS_U32 SHA_Get_Status(void)
496 {
497     return _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Status);
498 }
499 
SHA_SelMode(AESDMA_SHAMode eMode)500 void SHA_SelMode(AESDMA_SHAMode eMode)
501 {
502     MS_U32 u32Cmd = 0;
503 
504     switch (eMode)
505     {
506     case E_AESDMA_SHA1:
507         u32Cmd |= (SHARNG_CTRL_SHA_MSG_BLOCK_NUM);
508         break;
509 
510     case E_AESDMA_SHA256:
511         u32Cmd |= (SHARNG_CTRL_SHA_SEL_SHA256 | SHARNG_CTRL_SHA_MSG_BLOCK_NUM);
512         break;
513 
514     default:
515         return;
516     }
517 
518     //Turn off speedup mode
519     //u32Cmd |= SHARNG_CTRL_SPEED_MODE_N;
520 
521     REG32_W((&_SHARNGCtrl[0].Sha_Ctrl), _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl) | u32Cmd);
522 }
523 
SHA_SetAddress(MS_U32 u32Addr)524 void SHA_SetAddress(MS_U32 u32Addr)
525 {
526     REG32_W((&_SHARNGCtrl[0].Sha_Start), u32Addr);
527 }
528 
SHA_SetLength(MS_U32 u32Size)529 void SHA_SetLength(MS_U32 u32Size)
530 {
531     REG32_W((&_SHARNGCtrl[0].Sha_Length), u32Size);
532 }
533 
SHA_Start(MS_BOOL SHAStart)534 void SHA_Start(MS_BOOL SHAStart)
535 {
536 	if(SHAStart)
537 	{
538 		REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&~(SHARNG_CTRL_SHA_FIRE_ONCE));
539 		REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)|(SHARNG_CTRL_SHA_FIRE_ONCE));
540 	}
541 	else
542 	{
543 		REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&~(SHARNG_CTRL_SHA_FIRE_ONCE));
544 	}
545 }
546 
SHA_Out(MS_U32 u32Buf)547 void SHA_Out(MS_U32 u32Buf)
548 {
549 	MS_U32 Index, u32Size, u32offset;
550 	MS_U32 eMode = _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&SHARNG_CTRL_SHA_SEL_SHA256;
551 
552 	if(eMode == SHARNG_CTRL_SHA_SEL_SHA256)
553 	{
554 		u32Size = DIGEST_SIZE_SHA256;
555         u32offset = 0;
556 	}
557 	else
558 	{
559 		u32Size = DIGEST_SIZE_SHA1;
560         u32offset = 3;
561 	}
562 
563 	for( Index = 0; Index < u32Size; Index++ )
564 	{
565 		*((MS_U32 *)u32Buf + Index) = _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Out[Index + u32offset]);
566 	}
567 	//Set "1" to idle state after reg_read_sha_ready = 1
568 	REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)|(SHARNG_CTRL_SHA_CLR));
569 }
570 
SHA_SetByPassTable(MS_BOOL bEnable)571 void SHA_SetByPassTable(MS_BOOL bEnable)
572 {
573     if (bEnable == TRUE)
574     {
575         REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)|SHARNG_CTRL_SHA_BYPASS_TABLE_EN);
576     }
577     else
578     {
579         REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&~(SHARNG_CTRL_SHA_BYPASS_TABLE_EN));
580     }
581 }
582 
SHA_SetInitialHashEn(MS_BOOL bEnable)583 void SHA_SetInitialHashEn(MS_BOOL bEnable)
584 {
585     if (bEnable == TRUE)
586     {
587         REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)|SHARNG_CTRL_SHA_INITIAL_HASH_EN);
588     }
589     else
590     {
591         REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&~(SHARNG_CTRL_SHA_INITIAL_HASH_EN));
592     }
593 }
594 
SHA_SetShaManualMode(MS_BOOL bEnable)595 void SHA_SetShaManualMode(MS_BOOL bEnable)
596 {
597     if (bEnable == TRUE)
598     {
599         REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)|SHARNG_CTRL_SHA_WORKMODE_MANUAL_EN);
600     }
601     else
602     {
603         REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&~(SHARNG_CTRL_SHA_WORKMODE_MANUAL_EN));
604     }
605 }
606 
SHA_SetInitialSha(MS_U32 u32Buf)607 void SHA_SetInitialSha(MS_U32 u32Buf)
608 {
609     MS_U32 Index, u32Size, u32offset;
610     MS_U32 eMode = _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&SHARNG_CTRL_SHA_SEL_SHA256;
611 
612     if(eMode == SHARNG_CTRL_SHA_SEL_SHA256)
613     {
614         u32Size = DIGEST_SIZE_SHA256;
615         u32offset = 0;
616     }
617     else
618     {
619         u32Size = DIGEST_SIZE_SHA1;
620         u32offset = 3;
621     }
622 
623     for( Index = 0; Index < u32Size; Index++ )
624     {
625         REG32_W((&_SHARNGCtrl[0].Sha_Out[Index + u32offset]), *((MS_U32 *)u32Buf + Index));
626     }
627 }
628 
629 //-------------------------------------------------------------------------------------------------
630 /// Enable mobf one way function
631 /// @param  NULL
632 
633 /// @note : disable read mobf key, and could not enable read mobf key anymore
634 //-------------------------------------------------------------------------------------------------
MOBF_OneWay(void)635 void MOBF_OneWay(void)
636 {
637 	REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)|(MOBF_ONEWAY_EN));
638 }
639 
640 //-------------------------------------------------------------------------------------------------
641 /// Set MOBF encrypt key
642 /// @param  u32WriteKey                \b IN: Encrypt Key
643 
644 /// @note
645 //-------------------------------------------------------------------------------------------------
MOBF_WriteKey(MS_U32 u32WriteKey)646 void MOBF_WriteKey(MS_U32 u32WriteKey)
647 {
648 	REG32_W((&_SHARNGCtrl[0].MOBF_KeyW) , u32WriteKey);
649 }
650 
651 //-------------------------------------------------------------------------------------------------
652 /// Set MOBF decrypt key
653 /// @param  u32ReadKey                \b IN: Decrypt Key
654 
655 /// @note
656 //-------------------------------------------------------------------------------------------------
MOBF_ReadKey(MS_U32 u32ReadKey)657 void MOBF_ReadKey(MS_U32 u32ReadKey)
658 {
659 	REG32_W((&_SHARNGCtrl[0].MOBF_KeyR) , u32ReadKey);
660 }
661 
662 //-------------------------------------------------------------------------------------------------
663 /// Enable MOBF in MIU write port
664 /// @param  bEnable                \b IN: Enable/Disable
665 
666 /// @note : MOBF Encrypt
667 //-------------------------------------------------------------------------------------------------
MOBF_WriteEnable(MS_BOOL bEnable)668 void MOBF_WriteEnable(MS_BOOL bEnable)
669 {
670 	if(bEnable)
671 	{
672 		REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_WRITE_EN));
673 	}
674 	else
675 	{
676 		REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_WRITE_EN));
677         REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)|(MOBF_IN_MIU_WRITE_EN));
678 	}
679 }
680 
681 //-------------------------------------------------------------------------------------------------
682 /// Enable MOBF in MIU read port
683 /// @param  bEnable                \b IN: Enable/Disable
684 
685 /// @note : MOBF Decrypt
686 //-------------------------------------------------------------------------------------------------
MOBF_ReadEnable(MS_BOOL bEnable)687 void MOBF_ReadEnable(MS_BOOL bEnable)
688 {
689 	if(bEnable)
690 	{
691 		REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_READ_EN));
692 	}
693 	else
694 	{
695 		REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_READ_EN));
696         REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)|(MOBF_IN_MIU_READ_EN));
697 	}
698 }
699 
700 //-------------------------------------------------------------------------------------------------
701 /// Disable TDES
702 ///
703 
704 /// @note : MOBF Decrypt
705 //-------------------------------------------------------------------------------------------------
MOBF_DisableTDES(void)706 void MOBF_DisableTDES(void)
707 {
708 	REG32_W((&_AESDMACtrl[0].Dma_Ctrl2),_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2) & (~AESDMA_DMA_USE_TDES_EN));
709 }
710 
AESDMA_Parser_Set_Mode(AESDMA_ParserMode eMode)711 void AESDMA_Parser_Set_Mode(AESDMA_ParserMode eMode)
712 {
713     MS_U32 u32Cmd = 0;
714 
715     switch (eMode)
716     {
717     case E_AESDMA_PARSER_TS_PKT192:
718         u32Cmd |= (TS_MODE | PKT192_MODE);
719         break;
720 
721     case E_AESDMA_PARSER_TS_PKT192_CLEAR:
722         u32Cmd |= (TS_MODE | PKT192_MODE | CLEAR_MODE);
723         break;
724 
725     case E_AESDMA_PARSER_TS_PKT188:
726         u32Cmd |= (TS_MODE);
727         u32Cmd &= (~PKT192_MODE);
728         break;
729 
730     case E_AESDMA_PARSER_TS_PKT188_CLEAR:
731         u32Cmd |= (TS_MODE | CLEAR_MODE);
732         u32Cmd &= (~PKT192_MODE);
733         break;
734 
735     case E_AESDMA_PARSER_HDCP20_PKT192:
736         u32Cmd |= (HDCP20_MODE | PKT192_MODE);
737         break;
738 
739     case E_AESDMA_PARSER_HDCP20_PKT192_CLEAR:
740         u32Cmd |= (HDCP20_MODE | PKT192_MODE | CLEAR_MODE);
741         break;
742 
743     case E_AESDMA_PARSER_HDCP20_PKT188:
744         u32Cmd |= (HDCP20_MODE);
745         u32Cmd &= (~PKT192_MODE);
746         break;
747 
748     case E_AESDMA_PARSER_HDCP20_PKT188_CLEAR:
749         u32Cmd |= (HDCP20_MODE | CLEAR_MODE);
750         u32Cmd &= (~PKT192_MODE);
751         break;
752 
753     default:
754         return;
755     }
756 
757     u32Cmd |= (AUTO_MODE | INIT_TRUST);
758     REG32_W((&_PARSERCtrl[0].Parser_Ctrl),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~ParserCtrlSet)) | u32Cmd ) );
759 }
760 
761 
AESDMA_Parser_Insert_Scrmb(MS_BOOL bEnable)762 void AESDMA_Parser_Insert_Scrmb(MS_BOOL bEnable)
763 {
764     if(bEnable)
765 	{
766 	    REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~INSERT_SCRMB)) );
767         REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (INSERT_SCRMB)) );
768     }
769     else
770     {
771         REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~INSERT_SCRMB)) );
772     }
773 }
774 
AESDMA_Parser_Remove_Scrmb(MS_BOOL bEnable)775 void AESDMA_Parser_Remove_Scrmb(MS_BOOL bEnable)
776 {
777     if(bEnable)
778     {
779         REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~REMOVE_SCRMB)) );
780         REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (REMOVE_SCRMB)) );
781     }
782     else
783     {
784         REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~REMOVE_SCRMB)) );
785     }
786 }
787 
AESDMA_Parser_Mask_Scrmb(MS_BOOL bEnable)788 void AESDMA_Parser_Mask_Scrmb(MS_BOOL bEnable)
789 {
790     if(bEnable)
791     {
792         REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~TS_SCRMB_MASK)) );
793         REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (TS_SCRMB_MASK)) );
794     }
795     else
796     {
797         REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~TS_SCRMB_MASK)) );
798     }
799 }
800 
AESDMA_Parser_Bypass_Pid(MS_BOOL bEnable)801 void AESDMA_Parser_Bypass_Pid(MS_BOOL bEnable)
802 {
803     if(bEnable)
804     {
805         REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~BYPASS_PID)) );
806         REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) | (BYPASS_PID)) );
807     }
808     else
809     {
810         REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~BYPASS_PID)) );
811     }
812 }
813 
AESDMA_Parser_Set_ScrmbPattern(AESDMA_ScrmbPattern ePattern)814 void AESDMA_Parser_Set_ScrmbPattern(AESDMA_ScrmbPattern ePattern)
815 {
816     MS_U32 u32Cmd = 0;
817 
818     switch (ePattern)
819     {
820     case E_AESDMA_PARSER_SCRMB_10:
821         u32Cmd |= (SCRMB_PATTERN10);
822         break;
823 
824     case E_AESDMA_PARSER_SCRMB_11:
825         u32Cmd |= (SCRMB_PATTERN11);
826         break;
827 
828     default:
829         u32Cmd &= ~(SCRMB_PATTERN11);
830         break;
831     }
832 
833     REG32_W((&_PARSERCtrl[0].Parser_Ctrl),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~SCRMB_INITVALUE)) | u32Cmd ) );
834 
835 }
836 
AESDMA_Parser_Set_AddedScrmbPattern(AESDMA_ScrmbPattern ePattern)837 void AESDMA_Parser_Set_AddedScrmbPattern(AESDMA_ScrmbPattern ePattern)
838 {
839     MS_U32 u32Cmd = 0;
840 
841     switch (ePattern)
842     {
843     case E_AESDMA_PARSER_SCRMB_10:
844         u32Cmd |= (SCRMB_PATTERN10_ADD);
845         break;
846 
847     case E_AESDMA_PARSER_SCRMB_11:
848         u32Cmd |= (SCRMB_PATTERN11_ADD);
849         break;
850 
851     default:
852         return;
853     }
854 
855     REG32_W((&_PARSERCtrl[0].Parser_Pid1),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~SCRMB_INITVALUE_ADD)) | u32Cmd ) );
856 
857 }
858 
AESDMA_Parser_Set_Pid(MS_U8 u8Index,MS_U16 u16Pid)859 void AESDMA_Parser_Set_Pid(MS_U8 u8Index, MS_U16 u16Pid)
860 {
861     if(u8Index==0)
862     {
863         REG32_W((&_PARSERCtrl[0].Parser_Ctrl),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~PARSER_PID0_MASK)) | (u16Pid<<16) ) );
864     }
865     else if(u8Index==1)
866     {
867         REG32_W((&_PARSERCtrl[0].Parser_Pid1),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~PARSER_PID1_MASK)) | u16Pid ) );
868     }
869     else
870     {
871         printf("Edison do not support other PID\n");
872     }
873 }
874 
AESDMA_Parser_Query_PidCount(void)875 MS_U8 AESDMA_Parser_Query_PidCount(void)
876 {
877     return PARSER_PID_COUNT;
878 }
879 
AESDMA_Parser_Enable_HWParser(MS_BOOL bEnable)880 void AESDMA_Parser_Enable_HWParser(MS_BOOL bEnable)
881 {
882     if(bEnable)
883     {
884         REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~HW_PARSER_MODE))  );
885         REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (HW_PARSER_MODE))  );
886     }
887     else
888     {
889         REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~HW_PARSER_MODE))  );
890     }
891 
892     //make sure CC_CTRL_BY_ACPU is set 0
893     REG32_W((&_CIPHERCtrl[0].Cipher_Ctrl),( _AESDMA_REG32_R(&_CIPHERCtrl[0].Cipher_Ctrl) & (~CC_CTRL_BY_ACPU)) );
894 }
895 
RSA_ClearInt(void)896 void RSA_ClearInt(void)
897 {
898     //RSA interrupt clear
899     REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_RData) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_RData)|(RSA_INT_CLR));
900 }
901 
RSA_Reset(void)902 void RSA_Reset(void)
903 {
904     //RSA Rst
905     REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)|(RSA_CTRL_RSA_RST));
906     REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_RSA_RST));
907 
908     //add polling RSA status before load data to SRAM
909     while (( RSA_GetStatus() & RSA_STATUS_RSA_BUSY ) != 0);
910 }
911 
RSA_Ind32Ctrl(MS_U8 u8dirction)912 void RSA_Ind32Ctrl(MS_U8 u8dirction)
913 {
914     //[1] reg_ind32_direction 0: Read. 1: Write
915     if(u8dirction==1)
916     {
917         REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_IND32_CTRL_DIRECTION_WRITE));
918     }
919     else
920     {
921         REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)&(~RSA_IND32_CTRL_DIRECTION_WRITE));
922     }
923 
924     REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_IND32_CTRL_ADDR_AUTO_INC|RSA_IND32_CTRL_ACCESS_AUTO_START));
925 
926 }
927 
RSA_LoadSram(MS_U32 * u32Buf,RSA_IND32Address eMode)928 void RSA_LoadSram(MS_U32 *u32Buf, RSA_IND32Address eMode)
929 {
930     MS_U32 u32Cmd = 0;
931     MS_U32 i = 0;
932     MS_U32 WData_H = 0;
933     MS_U32 WData_L = 0;
934 
935     switch (eMode)
936     {
937     case E_RSA_ADDRESS_E:
938         u32Cmd |= (RSA_E_BASE_ADDR);
939         break;
940 
941     case E_RSA_ADDRESS_N:
942         u32Cmd |= (RSA_N_BASE_ADDR);
943         break;
944 
945     case E_RSA_ADDRESS_A:
946         u32Cmd |= (RSA_A_BASE_ADDR);
947         break;
948 
949     default:
950         return;
951     }
952 
953     REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Addr) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Addr)&(~RSA_ADDRESS_MASK))|u32Cmd));
954     REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_INDIRECT_START));
955 
956     for( i = 0; i < 64; i++ )
957     {
958         if( eMode == E_RSA_ADDRESS_E )
959         {
960             WData_L = (((*(u32Buf+i))>>8)&0xFF00)|(((*(u32Buf+i))>>24)&0xFF);
961             WData_H = (((*(u32Buf+i))>>8)&0xFF)|(((*(u32Buf+i))<<8)&0xFF00);
962         }
963         else
964         {
965             WData_L = (((*(u32Buf-i))>>8)&0xFF00)|(((*(u32Buf-i))>>24)&0xFF);
966             WData_H = (((*(u32Buf-i))>>8)&0xFF)|(((*(u32Buf-i))<<8)&0xFF00);
967         }
968 
969         REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Addr) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Addr)&(~RSA_WDATA_MASK_L))|(WData_L<<16)));
970         REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_WData) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_WData)&(~RSA_WDATA_MASK_H))|WData_H));
971     }
972 
973 }
974 
RSA_SetKeyLength(MS_U32 u32keylen)975 void RSA_SetKeyLength(MS_U32 u32keylen)
976 {
977     //[13:8] n_len_e: key length
978     REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_KEY_LENGTH_MASK))|(u32keylen<<8));
979 }
980 
RSA_SetKeyType(MS_U8 u8hwkey,MS_U8 u8pubkey)981 void RSA_SetKeyType(MS_U8 u8hwkey, MS_U8 u8pubkey)
982 {
983     //[1] hw_key_e : 0 : software key, 1: hardware key
984     //[2] e_pub_e : 0: pvivate key, 1: public key
985     if(u8hwkey==1)
986     {
987         REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)|(RSA_CTRL_SEL_HW_KEY));
988     }
989     else
990     {
991         REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_SEL_HW_KEY));
992     }
993 
994     if(u8pubkey==1)
995     {
996         REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)|(RSA_CTRL_SEL_PUBLIC_KEY));
997     }
998     else
999     {
1000         REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_SEL_PUBLIC_KEY));
1001     }
1002 
1003 }
1004 
RSA_ExponetialStart(void)1005 void RSA_ExponetialStart(void)
1006 {
1007     //RSA exp start
1008     REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_RData) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_RData)|(RSA_EXP_START));
1009 }
1010 
RSA_GetStatus(void)1011 MS_U32 RSA_GetStatus(void)
1012 {
1013     return _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl) & RSA_STATUS_MASK;
1014 }
1015 
RSA_FileOutStart(void)1016 void RSA_FileOutStart(void)
1017 {
1018     //RSA ind32_start
1019     REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_INDIRECT_START));
1020 }
1021 
RSA_SetFileOutAddr(MS_U32 u32offset)1022 void RSA_SetFileOutAddr(MS_U32 u32offset)
1023 {
1024     MS_U32 u32Addr = 0;
1025     u32Addr = RSA_Z_BASE_ADDR + u32offset;
1026 
1027     REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Addr) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Addr)&(~RSA_ADDRESS_MASK))|u32Addr));
1028 }
1029 
RSA_FileOut(void)1030 MS_U32 RSA_FileOut(void)
1031 {
1032     MS_U32 u32out_L = 0;
1033     MS_U32 u32out_H = 0;
1034 
1035     u32out_L = (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_WData)&RSA_RDATA_MASK_L)>>16;
1036     u32out_H = (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_RData)&RSA_RDATA_MASK_H)<<16;
1037 
1038     return (u32out_H|u32out_L);
1039 }
1040 
RSA_Get_RSA_IsFinished(void)1041 MS_U32 RSA_Get_RSA_IsFinished(void)
1042 {
1043     return (RSA_GetStatus()&RSA_STATUS_RSA_BUSY);
1044 }
1045 
1046 //-------------------------------------------------------------------------------------------------
1047 /// Get status of Secret Key in Normal bank
1048 /// @param  N/A
1049 /// @note : Get Status
1050 //-------------------------------------------------------------------------------------------------
AESDMA_IsSecretKeyInNormalBank(void)1051 MS_U32 AESDMA_IsSecretKeyInNormalBank(void)
1052 {
1053     return (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl) & (SECRET_KEY_IN_NORMAL_BANK));
1054 }
1055 
1056 //-------------------------------------------------------------------------------------------------
1057 /// Enable Two keys (Odd/Even) in using HW auto select key.
1058 /// @param  bEnable                \b IN: Enable/Disable
1059 
1060 /// @note : Hardware Parser Decrypt
1061 //-------------------------------------------------------------------------------------------------
AESDMA_Parser_Enable_Two_Keys(MS_BOOL bEnable)1062 void AESDMA_Parser_Enable_Two_Keys(MS_BOOL bEnable)
1063 {
1064     if(bEnable)
1065     {
1066         REG32_W((&_PARSERCtrl[0].Parser_Pid1), _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) | (SCRMB_ENABLE_TWO_KEY) );
1067     }
1068     else
1069     {
1070         REG32_W((&_PARSERCtrl[0].Parser_Pid1), _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~SCRMB_ENABLE_TWO_KEY) );
1071     }
1072 }
1073 
1074 //-------------------------------------------------------------------------------------------------
1075 /// Set Odd keys in using HW auto select key.
1076 /// @param  cipherkey
1077 /// @note : Hardware Parser Decrypt
1078 //-------------------------------------------------------------------------------------------------
AESDMA_Set_CipherOddKey(MS_U32 * cipherkey)1079 void AESDMA_Set_CipherOddKey(MS_U32 *cipherkey)
1080 {
1081     REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_L.Key_L) , cipherkey[0]);
1082     REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_L.Key_H) , cipherkey[1]);
1083     REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_H.Key_L) , cipherkey[2]);
1084     REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_H.Key_H) , cipherkey[3]);
1085 }
1086 
1087 //-------------------------------------------------------------------------------------------------
1088 /// Set Odd IVs in using HW auto select key.
1089 /// @param  cipherkey
1090 /// @note : Hardware Parser Decrypt
1091 //-------------------------------------------------------------------------------------------------
AESDMA_Set_OddInitVector(MS_U32 * pInitVector)1092 void AESDMA_Set_OddInitVector(MS_U32 *pInitVector)
1093 {
1094     REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_L.IV_L), pInitVector[0]);
1095     REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_L.IV_H), pInitVector[1]);
1096     REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_H.IV_L), pInitVector[2]);
1097     REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_H.IV_H), pInitVector[3]);
1098 }
1099 
1100 //-------------------------------------------------------------------------------------------------
1101 /// Set Even keys in using HW auto select key.
1102 /// @param  cipherkey
1103 /// @note : Hardware Parser Decrypt
1104 //-------------------------------------------------------------------------------------------------
AESDMA_Set_CipherEvenKey(MS_U32 * cipherkey)1105 void AESDMA_Set_CipherEvenKey(MS_U32 *cipherkey)
1106 {
1107     AESDMA_Set_CipherKey(cipherkey);
1108 }
1109 
1110 //-------------------------------------------------------------------------------------------------
1111 /// Set Even IVs in using HW auto select key.
1112 /// @param  cipherkey
1113 /// @note : Hardware Parser Decrypt
1114 //-------------------------------------------------------------------------------------------------
AESDMA_Set_EvenInitVector(MS_U32 * pInitVector)1115 void AESDMA_Set_EvenInitVector(MS_U32 *pInitVector)
1116 {
1117     AESDMA_Set_InitVector(pInitVector);
1118 }
1119 
1120 //-------------------------------------------------------------------------------------------------
1121 /// Set HDCP Data
1122 /// @param  u8Idx                \b IN: Index
1123 /// @param  pu8Data              \b IN: Data array
1124 /// @param  pu8privData          \b IN: Private data array
1125 /// @note : Set HDCP2.2
1126 //-------------------------------------------------------------------------------------------------
HDCP_ProcessCipher(MS_U8 u8Idx,MS_U8 * pu8Data,MS_U8 * pu8privData)1127 void HDCP_ProcessCipher (MS_U8 u8Idx, MS_U8 *pu8Data, MS_U8* pu8privData)
1128 {
1129     //
1130     //Ks^LC128:
1131     //P0: Bank 0x162A_h��00~07
1132     //P1: Bank 0x162B_h��00~07
1133     //P2: Bank 0x162C_h��00~07
1134     //P3: Bank 0x162D_h��00~07
1135     //Riv:
1136     //P0: Bank 0x162A_h��08~0B
1137     //P1: Bank 0x162B_h��08~0B
1138     //P2: Bank 0x162C_h��08~0B
1139     //P3: Bank 0x162D_h��08~0B
1140     //
1141 
1142     REG_HDCP22Data *pData = NULL;
1143     REG_HDCP22SEKCtrl *pCtrl = NULL;
1144     MS_U32 offset = 0;
1145     MS_U32 BKOffset = 0;
1146 
1147     if (u8Idx >= MAX_HDMI_PORT_MUN)
1148     {
1149         printf ("[Error] %s (%d), Wrong HDMI Port\n", __FUNCTION__, __LINE__);
1150         return;
1151     }
1152 
1153     MS_U32 *cipherkey = (MS_U32 *)((void *)pu8Data);
1154     MS_U32 *riv = (MS_U32 *)((void *)pu8privData);
1155 
1156     offset = u8Idx * 0x200;
1157     BKOffset = u8Idx * 0x200;
1158 
1159     pData = (REG_HDCP22Data*)((MS_U32)_HDCP22Data + offset);
1160     pCtrl = (REG_HDCP22SEKCtrl*)((MS_U32)_HDCP22SekCtrl + BKOffset);
1161 
1162     //Content Keys
1163     REG32_W((&pData[0].Hdcp22_ContentKey[0]) , cipherkey[0]);
1164     REG32_W((&pData[0].Hdcp22_ContentKey[1]) , cipherkey[1]);
1165     REG32_W((&pData[0].Hdcp22_ContentKey[2]) , cipherkey[2]);
1166     REG32_W((&pData[0].Hdcp22_ContentKey[3]) , cipherkey[3]);
1167 
1168     //RIV
1169     REG32_W((&pData[0].Hdcp22_Riv[0]) , riv[0]);
1170     REG32_W((&pData[0].Hdcp22_Riv[1]) , riv[1]);
1171 
1172     //Set SKE successful
1173     REG32_W((&pCtrl[0].SEK), (_AESDMA_REG32_R(&pCtrl[0].SEK) | HDCP_SEK_BIT0));
1174 }
1175 
1176 //-------------------------------------------------------------------------------------------------
1177 /// Get the status of HW supports HDCP2.2
1178 /// @param  N/A
1179 /// @note : Support HDCP2.2
1180 //-------------------------------------------------------------------------------------------------
HDCP_GetHdcpCipherState(MS_U8 u8Idx,MS_U8 * pu8State)1181 void HDCP_GetHdcpCipherState(MS_U8 u8Idx, MS_U8 *pu8State)
1182 {
1183     //
1184     // Set SKE successful:
1185     // P0: Bank 0x162A_h��0E[0]
1186     // P1: Bank 0x162B_h��0E[0]
1187     // P2: Bank 0x162C_h��0E[0]
1188     // P3: Bank 0x162D_h��0E[0]
1189     //
1190 
1191 #define HDCP_SUPPORT_EN 0x00000001
1192     REG_HDCP22SEKCtrl *pCtrl = NULL;
1193     MS_U16 BKOffset = 0;
1194 
1195     if (u8Idx >= MAX_HDMI_PORT_MUN)
1196     {
1197         printf ("[Error] %s (%d), Wrong HDMI Port\n", __FUNCTION__, __LINE__);
1198         return;
1199     }
1200 
1201     BKOffset = u8Idx * 0x200;
1202     pCtrl = (REG_HDCP22SEKCtrl*)((MS_U32)_HDCP22SekCtrl + BKOffset);
1203     *pu8State = (MS_U8)(_AESDMA_REG32_R(&pCtrl[0].SEK) & HDCP_SUPPORT_EN);
1204 }
1205 
1206 //-------------------------------------------------------------------------------------------------
1207 /// Reset AESDMA
1208 /// @param  N/A
1209 /// @note : Clear Registers, not to do sw reset
1210 //-------------------------------------------------------------------------------------------------
AESDMA_NormalReset(void)1211 void AESDMA_NormalReset(void)
1212 {
1213     MS_U32 Reg_AESDMA;
1214     int i = 0;
1215     Reg_AESDMA = (MS_U32)(&_AESDMACtrl[0].Dma_Ctrl);
1216 
1217     REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register
1218 
1219     // reset all AESdma register
1220     for (i = 0 ; i < 19 ; i++)
1221     {
1222         REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000);
1223     }
1224     // reset secure_dma3_ctrl register
1225     REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000);
1226 
1227     // reset hw_parser_ctrl register
1228     REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x00000000);
1229     REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000);
1230 }
1231 
AESDMA_POWER_SUSPEND(void)1232 MS_BOOL AESDMA_POWER_SUSPEND(void)
1233 {
1234     SECUREBASECtrl_Buffer =  _AESDMA_REG32_R(&_SECUREBASECtrl[0].Reg0001);
1235     return TRUE;
1236 }
1237 
AESDMA_POWER_RESUME(void)1238 MS_BOOL AESDMA_POWER_RESUME(void)
1239 {
1240     REG32_W((&_SECUREBASECtrl[0].Reg0001), SECUREBASECtrl_Buffer);
1241     return TRUE;
1242 }
1243 
1244