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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regAESDMA.h 98 // Description: AESDMA Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _AESDMA_REG_MCU_H_ 103 #define _AESDMA_REG_MCU_H_ 104 105 106 //-------------------------------------------------------------------------------------------------- 107 // Abbreviation 108 //-------------------------------------------------------------------------------------------------- 109 // Addr Address 110 // Buf Buffer 111 // Clr Clear 112 // CmdQ Command queue 113 // Cnt Count 114 // Ctrl Control 115 // Flt Filter 116 // Hw Hardware 117 // Int Interrupt 118 // Len Length 119 // Ovfw Overflow 120 // Pkt Packet 121 // Rec Record 122 // Recv Receive 123 // Rmn Remain 124 // Reg Register 125 // Req Request 126 // Rst Reset 127 // Scmb Scramble 128 // Sec Section 129 // Stat Status 130 // Sw Software 131 // Ts Transport Stream 132 133 134 //-------------------------------------------------------------------------------------------------- 135 // Global Definition 136 //-------------------------------------------------------------------------------------------------- 137 138 139 //-------------------------------------------------------------------------------------------------- 140 // Compliation Option 141 //-------------------------------------------------------------------------------------------------- 142 143 144 //------------------------------------------------------------------------------------------------- 145 // Harware Capability 146 //------------------------------------------------------------------------------------------------- 147 148 149 //------------------------------------------------------------------------------------------------- 150 // Type and Structure 151 //------------------------------------------------------------------------------------------------- 152 #define REG_AESDMACTRL_BASE 0x47940UL //(0x23C00/2 + 0x50) * 4 153 #define REG_SHARNGCTRL_BASE 0x47800UL //(0x23C00/2 + 0x0) * 4 154 #define REG_DMASECURE_CTRL_BASE 0x27A00UL //(0x13D00/2 + 0x00) * 4 155 #define REG_DMASECURE_BASE 0x27B40UL //(0x13D00/2 + 0x50) * 4 156 #define REG_AESDMACLK_BASE 0x1460UL //(0x0A00/2 + 0x18) * 4 157 //#define REG_AESDMAMBX_BASE 0x17F8 //(0x0B00/2 + 0x7F) * 4 158 #define REG_AESDMAMBX_BASE 0x7B84UL //(0x3D00/2 + 0x61) * 4 159 #define REG_PARSERCTRL_BASE 0x45800UL //(0x22C00/2 + 0x00) * 4 160 #define REG_CIPHERCTRL_BASE 0x45840UL //(0x22C00/2 + 0x10) * 4 161 #define REG_AESDMAEXT_BASE 0x45980UL //(0x22C00/2 + 0x60) * 4 162 #define REG_TZPC_NONPM_BASE 0x47200UL //(0x23900/2 + 0x00) * 4 163 #define REG_AES_DSCMB6_BASE 0xE7A00UL //(0x73D00/2 + 0x00) * 4 164 #define REG_AES_DSCMB7_BASE 0xE7B00UL //(0x73D00/2 + 0x40) * 4 165 166 167 //Used for Random Number Gen, Manhattan only 168 #define REG_ANA_MISC_BASE 0x21840UL //(0x10C00/2 + 0x10) * 4 169 170 #define RSA_E_BASE_ADDR (0x00UL) 171 #define RSA_N_BASE_ADDR (0x40UL) 172 #define RSA_A_BASE_ADDR (0x80UL) 173 #define RSA_Z_BASE_ADDR (0xC0UL) 174 #define REG_HDCP22_BASE 0xE74C0UL //(0x73A00/2 + 0x30) * 4 175 #define REG_HDCP22_SEK 0xE2538UL //(0x71200/2 + 0x4E) * 4 176 177 typedef struct _REG32 178 { 179 volatile MS_U16 L; 180 volatile MS_U16 empty_L; 181 volatile MS_U16 H; 182 volatile MS_U16 empty_H; 183 } REG32; 184 185 typedef struct _REG_CipherKey 186 { 187 REG32 Key_L; 188 REG32 Key_H; 189 } REG_CipherKey; 190 191 typedef struct _REG_InitVector 192 { 193 REG32 IV_L; 194 REG32 IV_H; 195 } REG_InitVector; 196 197 typedef struct _REG_AESDMACtrl 198 { 199 REG32 Dma_Ctrl; //0x50 200 #define AESDMA_CTRL_FILEIN_START 0x00000100UL 201 #define AESDMA_CTRL_FILEOUT_START 0x00000001UL 202 #define AESDMA_CTRL_SW_RST 0x00000080UL 203 #define AESDMA_CTRL_BURST_LENGTH 0x00001000UL 204 205 #define AESDMA_ENG_PS_RELEASE 0x00010000UL 206 #define AESDMA_ENG_PS_IN_EN 0x00100000UL 207 #define AESDMA_ENG_PS_OUT_EN 0x00200000UL 208 #define AESDMA_ENG_AES_EN 0x01000000UL 209 #define AESDMA_ENG_DES_EN 0x00040000UL 210 #define AESDMA_ENG_TDES_EN 0x00080000UL 211 #define AESDMA_ENG_DESCRYPT 0x02000000UL // 0:encrypt, 1:decrypt 212 #define AESDMA_ENG_CTR_MODE 0x10000000UL 213 #define AESDMA_ENG_CBC_MODE 0x20000000UL 214 #define AESDMA_ENG_CTS_CBC_MODE 0x40000000UL 215 #define AESDMA_ENG_CTS_ECB_MODE 0x00000002UL 216 #define AESDMA_ECO_FIX_LAST_BYTE 0x80000000UL // when (output address + length)/8=1 the last byte maybe no output 217 218 REG32 Dma_Filein_Addr; //0x52 219 REG32 Dma_Filein_Num; //0x54 220 REG32 Dma_Fileout_SAddr; //0x56 221 REG32 Dma_Fileout_EAddr; //0x58 222 REG32 Dma_PS_Pattern; //0x5a 223 REG32 Dma_PS_Pattern_Mask; //0x5c 224 REG32 Dma_Ctrl2; //0x5e 225 #define AESDMA_DMA_USE_TDES_EN 0x00000100UL // DES/TDES path switch 226 #define AESDMA_CTRL_BANK_R_H 0x00002000UL 227 #define AESDMA_CTRL_BANK_W_H 0x00004000UL 228 #define AESDMA_CTRL_BANK_R 0x00000010UL 229 #define AESDMA_CTRL_BANK_W 0x00000020UL 230 #define AESDMA_INT_EN 0x00000080UL 231 #define AESDMA_USE_SECRET_KEY 0x00001000UL 232 #define AESDMA_WADR_ERR_CLR 0x00000001UL 233 234 REG_CipherKey Dma_CipherKey_L; //0x60 235 REG_CipherKey Dma_CipherKey_H; //0x64 236 REG_InitVector Dma_InitVector_L; //0x68 237 REG_InitVector Dma_InitVector_H; //0x6C 238 REG32 Dma_Matched_Btyecnt; //0x70 239 REG32 Dma_Matched_Pat; //0x72 240 REG32 Dma_Err_Wadr; //0x74 241 REG32 Dma_Eng3_Ctrl; //0x76 242 #define AESDMA_ENG_SPEEDUP 0x03BF0000UL 243 REG32 _xbf808fd8[3]; //0x78~0x7c 244 REG32 Dma_PVR_Status; //0x7e 245 #define AESDMA_IS_FINISHED 0x00010000UL 246 /* 247 #define AESDMA_PS_DONE 0x00000001 248 #define AESDMA_PS_STOP 0x00000002 249 #define AESDMA_DMA_DONE 0x00010000 250 #define AESDMA_DMA_PAUSE 0x00020000 251 #define AESDMA_STATES_GROUP (AESDMA_PS_DONE | \ 252 AESDMA_PS_STOP | \ 253 AESDMA_DMA_DONE | \ 254 AESDMA_DMA_PAUSE ) 255 */ 256 }REG_AESDMACtrl; 257 258 #define DmaCtrlSet (AESDMA_ENG_AES_EN | \ 259 AESDMA_ENG_DES_EN | \ 260 AESDMA_ENG_TDES_EN | \ 261 AESDMA_ENG_DESCRYPT | \ 262 AESDMA_ENG_CTR_MODE | \ 263 AESDMA_ENG_CBC_MODE | \ 264 AESDMA_ENG_CTS_CBC_MODE | \ 265 AESDMA_ENG_CTS_ECB_MODE) 266 267 typedef struct _REG_SHARNGCtrl 268 { 269 REG32 Rng_Ctrl; //0x00 270 #define SHARNG_CTRL_RNG_SW_RST 0x00000080UL 271 #define MOBF_IN_MIU_READ_EN 0x00010000UL 272 #define MOBF_IN_MIU_WRITE_EN 0x00020000UL 273 #define AES_FILE_IN_MIU_NS 0x00100000UL 274 #define AES_FILE_OUT_MIU_NS 0x00200000UL 275 #define MOBF_ONEWAY_EN 0x01000000UL 276 277 #define SECRET_KEY_IN_NORMAL_BANK 0x08000000UL 278 279 280 REG32 Rng_Out; //0x02 281 REG32 MOBF_KeyR; //0x04 282 REG32 MOBF_KeyW; //0x06 283 REG32 Sha_Ctrl; //0x08 284 #define SHARNG_CTRL_SHA_FIRE_ONCE 0x00000001UL 285 #define SHARNG_CTRL_SHA_CLR 0x00000040UL 286 #define SHARNG_CTRL_SHA_RST 0x00000080UL 287 #define SHARNG_CTRL_SHA_INT 0x00000100UL 288 #define SHARNG_CTRL_SHA_SEL_SHA256 0x00000200UL 289 #define SHARNG_CTRL_SHA_MSG_INVERSE 0x00040000UL 290 #define SHARNG_CTRL_SHA_MSG_BLOCK_NUM 0x00010000UL /* Always be 1 */ 291 #define SHARNG_CTRL_SPEED_MODE_N 0x00000010UL 292 #define SHARNG_CTRL_REMOVE_SCATTER_GATHER 0x00000800UL 293 294 REG32 Sha_Start; //0x0a 295 REG32 Sha_Length; //0x0c 296 REG32 Sha_Status; //0x0e 297 #define SHARNG_CTRL_SHA_BUSY 0x00020000UL 298 #define SHARNG_CTRL_SHA_READY 0x00010000UL 299 300 REG32 Sha_Out[8]; //0x10~0x1E 301 REG32 Rsa_Ind32_Start; //0x20 302 #define RSA_INDIRECT_START 0x00000001UL 303 #define RSA_IND32_CTRL_DIRECTION_WRITE 0x00020000UL 304 #define RSA_IND32_CTRL_ADDR_AUTO_INC 0x00040000UL 305 #define RSA_IND32_CTRL_ACCESS_AUTO_START 0x00080000UL 306 REG32 Rsa_Ind32_Addr; //0x22 307 #define RSA_ADDRESS_MASK 0x0000FFFFUL 308 #define RSA_WDATA_MASK_L 0xFFFF0000UL 309 REG32 Rsa_Ind32_WData; //0x24 310 #define RSA_WDATA_MASK_H 0x0000FFFFUL 311 #define RSA_RDATA_MASK_L 0xFFFF0000UL 312 REG32 Rsa_Ind32_RData; //0x26 313 #define RSA_RDATA_MASK_H 0x0000FFFFUL 314 #define RSA_EXP_START 0x00010000UL 315 #define RSA_INT_CLR 0x00020000UL 316 REG32 Rsa_Ctrl; //0x28 317 #define RSA_CTRL_RSA_RST 0x00000001UL 318 #define RSA_CTRL_SEL_HW_KEY 0x00000002UL 319 #define RSA_CTRL_SEL_PUBLIC_KEY 0x00000004UL 320 #define RSA_CTRL_KEY_LENGTH_MASK 0x00003F00UL 321 #define RSA_STATUS_RSA_BUSY 0x00010000UL 322 #define RSA_STATUS_MASK 0x00FF0000UL 323 }REG_SHARNGCtrl; 324 325 typedef struct _REG_DMASECURECtrl 326 { 327 REG32 Secure_file_st; //0x50 328 //#define AESDMA_SECURE_FILEIN_START 0x00000001 329 REG32 reserved52; //0x52 330 REG32 reserved54; //0x54 331 REG32 reserved56; //0x56 332 REG32 reserved58; //0x58 333 REG32 reserved5a; //0x5a 334 REG32 reserved5c; //0x5c 335 REG32 reserved5e; //0x5e 336 REG_CipherKey Secure_CipherKey_L; //0x60 337 REG_CipherKey Secure_CipherKey_H; //0x64 338 REG_InitVector Secure_InitVector_L; //0x68 339 REG_InitVector Secure_InitVector_H; //0x6C 340 REG32 reserved70; //0x70 341 REG32 reserved72; //0x72 342 REG32 reserved74; //0x74 343 REG32 reserved76; //0x76 344 REG32 Secure_dma3_ctrl; //0x78 345 #define AESDMA_SECURE_PROTECT_S 0x00010000UL 346 #define AESDMA_SECURE_PROTECT_SHA_S 0x00020000UL 347 #define AESDMA_SECURE_PROTECT_RSA_S 0x00040000UL 348 #define AESDMA_USE_SECRET_KEY0 0x00200000UL 349 #define AESDMA_USE_SECRET_KEY1 0x00400000UL 350 REG32 reserved7a; //0x7a 351 REG32 reserved7c; //0x7c 352 REG32 Secure_dma3_status; //0x7e 353 //#define AESDMA_DONE_S 0x00010000 354 }REG_DMASECURECtrl; 355 356 typedef struct _REG_CKG_AESDMA 357 { 358 REG32 Reg_Gate_Clk_AESDMA; //0x18 359 #define AESDMA_CLK_OFF_EN 0x00010000UL //0x19[0] 360 #define AESDMA_CLK_INV 0x00020000UL //0x19[1] 361 #define AESDMA_CLK_172M 0x00000000UL //0x19[3:2] 362 #define AESDMA_CLK_144M 0x00040000UL //0x19[3:2] 363 #define AESDMA_CLK_108M 0x00080000UL //0x19[3:2] 364 #define AESDMA_CLK_XTAL 0x000C0000UL //0x19[3:2] 365 366 }REG_AESDMAClk; 367 368 typedef struct _REG_MBX_AESDMA 369 { 370 REG32 Reg_Et_Rpd; //0x61 371 #define AESDMA_SEM_USED 0x00000100UL 372 #define AESDMA_CLK_USED 0x00000200UL 373 #define TSP_CLK_USED 0x00000400UL 374 }REG_AESDMAMbx; 375 376 377 typedef struct _REG_PARSERCtrl 378 { 379 REG32 Parser_Ctrl; //0x00 380 #define HDCP20_MODE 0x00000001UL 381 #define PKT192_MODE 0x00000002UL 382 #define AUTO_MODE 0x00000004UL 383 #define TRIGGER_MODE 0x00000008UL 384 #define INIT_TRUST 0x00000010UL 385 #define CLEAR_MODE 0x00000020UL 386 #define REMOVE_SCRMB 0x00000040UL 387 #define INSERT_SCRMB 0x00000080UL 388 #define SCRMB_PATTERN10 0x00000400UL 389 #define SCRMB_PATTERN11 0x00000600UL 390 #define SCRMB_INITVALUE 0x00000600UL 391 #define HW_PARSER_MODE 0x00000100UL 392 #define TS_SCRMB_MASK 0x00000800UL 393 #define TS_MODE 0x00008000UL 394 #define PARSER_PID0_MASK 0x1FFF0000UL 395 REG32 Parser_Pid1; //0x02 396 #define PARSER_PID1_MASK 0x00001FFFUL 397 #define BYPASS_PID 0x00080000UL 398 #define SCRMB_PATTERN10_ADD 0x00200000UL 399 #define SCRMB_PATTERN11_ADD 0x00300000UL 400 #define SCRMB_INITVALUE_ADD 0x00300000UL 401 #define SCRMB_ENABLE_TWO_KEY 0x00400000UL 402 #define ENABLE_LG_PATCH 0x01000000UL 403 REG32 Parser_Status; //0x04 404 405 }REG_PARSERCtrl; 406 407 typedef struct _REG_CIPHERCtrl 408 { 409 REG32 Cipher_Ctrl; //0x00 410 #define CC_CTRL_BY_ACPU 0x00000080UL 411 REG32 Cipher_len; //0x02 412 REG32 Parser_Status; //0x04 413 414 }REG_CIPHERCtrl; 415 416 #define ParserCtrlSet (HDCP20_MODE | \ 417 PKT192_MODE | \ 418 AUTO_MODE | \ 419 TRIGGER_MODE | \ 420 INIT_TRUST | \ 421 CLEAR_MODE | \ 422 HW_PARSER_MODE | \ 423 TS_MODE ) 424 425 typedef struct _REG_AESDMACtrlEx 426 { 427 REG_CipherKey Dma_CipherKey_L; //0x60 428 REG_CipherKey Dma_CipherKey_H; //0x64 429 REG_InitVector Dma_InitVector_L; //0x68 430 REG_InitVector Dma_InitVector_H; //0x6C 431 }REG_AESDMACtrlEx; 432 433 typedef struct _REG_HDCP22Data 434 { 435 REG32 Hdcp22_ContentKey[4]; 436 REG32 Hdcp22_Riv[2]; 437 }REG_HDCP22Data; 438 439 typedef struct _REG_HDCP22SEKCtrl 440 { 441 REG32 SEK; //0x9C 442 #define HDCP_SEK_BIT0 0x00000001 443 }REG_HDCP22SEKCtrl; 444 445 typedef struct _REG_GENERAL_STRUCT 446 { 447 REG32 Reg0001; //0x00 448 REG32 Reg0203; //0x02 449 REG32 Reg0405; //0x04 450 REG32 Reg0607; //0x06 451 REG32 Reg0809; //0x08 452 }REG_GENERAL_STRUCT; 453 454 typedef REG_GENERAL_STRUCT REG_TZPCCtrl; //BANK: 0x1239 455 #define REG_TZPC2NONPM_RNG_SOURCE_EN 0x000F0000UL //0x03[3:0] 456 457 typedef REG_GENERAL_STRUCT REG_SECUREBASECtrl; //BANK: 0x113D 458 #define REG_RNG_EN 0x00000080UL //0x00[7] 459 #define REG_RNG_READY 0x00010000UL 460 461 typedef REG_GENERAL_STRUCT REG_ANAMISCBASECtrl; //BANK: 0x110C_10 462 #define REG_MIPSPLL_OCCCLK2_EN 0x02000000UL //0x11[9] 463 464 typedef REG_GENERAL_STRUCT REG_AES_DSCMB6Ctrl; //BANK: 0x173D_0 465 typedef REG_GENERAL_STRUCT REG_AES_DSCMB7Ctrl; //BANK: 0x173D_40 466 #define AESDMA_ISR_CLR 0x00010000UL //0x01[0] 467 468 #endif // #ifndef _AESDMA_REG_MCU_H_ 469