1 //////////////////////////////////////////////////////////////////////////////// 2 // 3 // Copyright (c) 2006-2009 MStar Semiconductor, Inc. 4 // All rights reserved. 5 // 6 // Unless otherwise stipulated in writing, any and all information contained 7 // herein regardless in any format shall remain the sole proprietary of 8 // MStar Semiconductor Inc. and be kept in strict confidence 9 // ("MStar Confidential Information") by the recipient. 10 // Any unauthorized act including without limitation unauthorized disclosure, 11 // copying, use, reproduction, sale, distribution, modification, disassembling, 12 // reverse engineering and compiling of the contents of MStar Confidential 13 // Information is unlawful and strictly prohibited. MStar hereby reserves the 14 // rights to any and all damages, losses, costs and expenses resulting therefrom. 15 // 16 //////////////////////////////////////////////////////////////////////////////// 17 18 //////////////////////////////////////////////////////////////////////////////////////////////////// 19 // file halCIPHER.h 20 // @brief CIPHER HAL 21 // @author MStar Semiconductor,Inc. 22 //////////////////////////////////////////////////////////////////////////////////////////////////// 23 #ifndef __HAL_CIPHER_H__ 24 #define __HAL_CIPHER_H__ 25 26 #include "regCIPHER.h" 27 #include "drvCIPHER.h" 28 29 //-------------------------------------------------------------------------------------------------- 30 // Driver Compiler Option 31 //-------------------------------------------------------------------------------------------------- 32 33 //-------------------------------------------------------------------------------------------------- 34 // CIPHER Software Define 35 //-------------------------------------------------------------------------------------------------- 36 #define HAL_CIPHER_RESETKEY_TIMEOUT_VALUE (1000UL) 37 38 //-------------------------------------------------------------------------------------------------- 39 // CIPHER Hardware Abstraction Layer 40 //-------------------------------------------------------------------------------------------------- 41 42 #define HAL_CRYPTODMA_KEYLEN_MAX 16UL 43 #define HAL_CRYPTODMA_DIRDATA_MAX 16UL 44 #define HAL_CRYPTODMA_OTPHASH_UNIT 16UL 45 #define HAL_CRYPTODMA_OTPHASH_SIZE_MIN 32UL 46 #define HAL_CRYPTODMA_THREAD_ID_MAX 0xFFFFUL 47 #define HAL_CRYPTODMA_DMA_KEY_SLOT 4UL 48 #define HAL_CRYPTODMA_OTP_SCK_NUM 4UL 49 #define HAL_CRYPTODMA_CAVID_MAX 0x1FUL 50 //-------------------------------------------------------------------------------------------------- 51 // Macro of bit operations 52 //-------------------------------------------------------------------------------------------------- 53 #define HAS_FLAG(flag, bit) ((flag) & (bit)) 54 #define SET_FLAG(flag, bit) ((flag)|= (bit)) 55 #define RESET_FLAG(flag, bit) ((flag)&= (~(bit))) 56 #define SET_FLAG1(flag, bit) ((flag)| (bit)) 57 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) 58 59 //////////////////////////////////////////////////////////////////////////////////////////////// 60 // QMEM base address 61 //////////////////////////////////////////////////////////////////////////////////////////////// 62 #define HAL_CIPHER_BASE_IQMEM 0x00000000UL 63 #define HAL_CIPHER_BASE_DQMEM 0x80000000UL 64 #define HAL_CIPHER_BASE_LUT 0x00000010 65 #define HAL_CIPHER_SIZE_LUT 256 66 #define HAL_CIPHER_BASE_M 0x00000110 67 #define HAL_CIPHER_SIZE_M 128 68 #define HAL_CIPHER_BASE_BC 0x00000190 69 #define HAL_CIPHER_SIZE_BC 16 70 71 //////////////////////////////////////////////////////////////////////////////////////////////// 72 // IRQ 73 //////////////////////////////////////////////////////////////////////////////////////////////// 74 #define CRYPTODMA_IRQ E_INT_FIQ_CA_CRYPTO_DMA //halIRQTBL.h CryptoDMA FIQ 56 75 76 //////////////////////////////////////////////////////////////////////////////////////////////// 77 // Except 78 //////////////////////////////////////////////////////////////////////////////////////////////// 79 #define HAL_CIPHER_EXCEPT_CAVID 0x0001UL 80 #define HAL_CIPHER_EXCEPT_DATA 0x0002UL 81 #define HAL_CIPHER_EXCEPT_ALGO 0x0004UL 82 #define HAL_CIPHER_EXCEPT_DMA_KEY 0x0008UL 83 #define HAL_CIPHER_EXCEPT_HMAC_KEY 0x0010UL 84 85 //////////////////////////////////////////////////////////////////////////////////////////////// 86 // AESDMA Compatible 87 //////////////////////////////////////////////////////////////////////////////////////////////// 88 #define HAL_CIPHER_KEYSLOT_BASE 0x10UL 89 90 typedef enum 91 { 92 E_CIPHER_CAVID1 = 0x0001, 93 E_CIPHER_CAVID2 = 0x0002, 94 E_CIPHER_CAVID3 = 0x0003, 95 E_CIPHER_CAVID4 = 0x0004, 96 E_CIPHER_CAVID5 = 0x0005, 97 E_CIPHER_CAVID6 = 0x0006, 98 }HAL_CIPHER_CAVID; 99 100 /// SHA Mode 101 typedef enum 102 { 103 E_HASH_SHA1 = 0, 104 E_HASH_SHA256, 105 E_HASH_MD5, 106 }HAL_CIPHER_HASHMODE; 107 108 typedef enum 109 { 110 E_DMA_ALGO_NONE = 0, 111 E_DMA_ALGO_AES = 1, 112 E_DMA_ALGO_DES = 2, 113 E_DMA_ALGO_TDES = 3, 114 E_DMA_ALGO_M6_S56_CCBC = 4 , 115 E_DMA_ALGO_M6_S56 =5 , 116 E_DMA_ALGO_M6_KE56 = 7 , 117 E_DMA_ALGO_RC4 = 8, 118 }HAL_CIPHER_ALGO; 119 120 typedef enum 121 { 122 E_DMA_MODE_NONE = 0, 123 E_DMA_MODE_ECB = 0, 124 E_DMA_MODE_CBC, 125 E_DMA_MODE_CTR, 126 E_DMA_MODE_CBC_MAC, 127 E_DMA_MODE_CTR_64, 128 E_DMA_MODE_CMAC_Key, 129 E_DMA_MODE_CMAC_Algo, 130 E_DMA_MODE_PCBC_ADD, 131 E_DMA_MODE_PCBC_XOR, 132 E_DMA_MODE_OTPHASH, 133 E_DMA_MODE_NUM, 134 135 }HAL_CIPHER_MODE; 136 137 typedef enum 138 { 139 // From KL 140 E_DMA_KSEL_SK0 = 0 , 141 E_DMA_KSEL_SK1 = 1 , 142 E_DMA_KSEL_SK2 = 2 , 143 E_DMA_KSEL_SK3 = 3 , 144 145 // From OTP 146 E_DMA_KSEL_MK0 = 4 , 147 E_DMA_KSEL_MK1 = 5 , 148 E_DMA_KSEL_CCCK = 6 , 149 E_DMA_KSEL_STRN = 7 , 150 151 // From CPU 152 E_DMA_KSEL_REGKEY, 153 154 //From NSK 155 E_DMA_KSEL_CAIP, 156 157 }HAL_CIPHER_KEYSRC; 158 159 typedef enum 160 { 161 E_DMA_SRC_DIRECT = 0 , 162 E_DMA_SRC_DRAM = 1 , 163 E_DMA_SRC_IQMEM = 2 , 164 E_DMA_SRC_DQMEM = 2 , 165 E_DMA_SRC_HW_INPUT = 3 166 }HAL_CIPHER_DATASRC; 167 168 typedef enum 169 { 170 E_DMA_DST_DRAM = 0 , 171 E_DMA_DST_REGFILE = 1 , 172 E_DMA_DST_IQMEM = 1 , 173 E_DMA_DST_DQMEM = 1 , 174 }HAL_CIPHER_DATADST; 175 176 typedef enum 177 { 178 E_DMA_RESIDUE_NONE = 0 , 179 E_DMA_RESIDUE_CLR = 0 , 180 E_DMA_RESIDUE_CTS = 1 , 181 E_DMA_RESIDUE_SCTE52 = 2 , 182 E_DMA_RESIDUE_NUM , 183 184 }HAL_CIPHER_RESIDUE; 185 186 typedef enum 187 { 188 E_DMA_SB_NONE = 0 , 189 E_DMA_SB_CLR = 0 , 190 E_DMA_SB_IV1 , 191 E_DMA_SB_IV2 , 192 E_DMA_SB_NUM , 193 194 }HAL_CIPHER_SHORTBLOCK; 195 196 typedef enum 197 { 198 E_DMA_INT_NONE = 0 , 199 E_DMA_INT_ENABLE = 1 , 200 E_DMA_INT_EN_WAIT = 2 , 201 202 }HAL_CIPHER_INTMODE; 203 204 typedef enum 205 { 206 E_CIPHER_HASH_IWC_PRV = 0, 207 E_CIPHER_HASH_IWC_MANUAL, 208 }HAL_CIPHER_IWCTYPE; 209 210 typedef enum 211 { 212 E_CIPHER_TYPE_DMA = 0 , 213 E_CIPHER_TYPE_SHA , 214 E_CIPHER_TYPE_OTPHASH , 215 216 }HAL_CIPHER_CMDTYPE; 217 218 typedef enum 219 { 220 E_PARSER_HDCPMODE_NONE = 0, 221 E_PARSER_HDCPMODE_HDCP20, 222 223 }HAL_CIPHER_PARSER_HDCPMODE; 224 225 typedef enum 226 { 227 E_PARSER_TSMODE_PES = 0, 228 E_PARSER_TSMODE_TS, 229 230 }HAL_CIPHER_PARSER_TSMODE; 231 232 typedef enum 233 { 234 E_PARSER_PKTMODE_188 = 0, 235 E_PARSER_PKTMODE_192, 236 237 }HAL_CIPHER_PARSER_PKTMODE; 238 239 typedef enum 240 { 241 E_PARSER_AUTOMODE_NONE = 0, 242 E_PARSER_AUTOMODE_EN, 243 244 }HAL_CIPHER_PARSER_AUTOMODE; 245 246 typedef enum 247 { 248 E_PARSER_ITMODE_NONE = 0, 249 E_PARSER_ITMODE_EN, 250 251 }HAL_CIPHER_PARSER_ITMODE; //Init trust 252 253 typedef enum 254 { 255 E_PARSER_CLEARMODE_NONE = 0, 256 E_PARSER_CLEARMODE_EN, 257 258 }HAL_CIPHER_PARSER_CLEARMODE; 259 260 //Tmp area, open to drv level latter 261 typedef struct 262 { 263 MS_U32 u32ObfIdxR; 264 MS_U32 u32ObfIdxW; 265 }DRV_CIPHER_OBF; 266 267 typedef enum 268 { 269 E_CIPHER_PARSER_TS_PKT192 = 0, 270 E_CIPHER_PARSER_TS_PKT192_CLEAR, 271 E_CIPHER_PARSER_TS_PKT188, 272 E_CIPHER_PARSER_TS_PKT188_CLEAR, 273 E_CIPHER_PARSER_HDCP20_PKT192, 274 E_CIPHER_PARSER_HDCP20_PKT192_CLEAR, 275 E_CIPHER_PARSER_HDCP20_PKT188, 276 E_CIPHER_PARSER_HDCP20_PKT188_CLEAR, 277 } CIPHER_PARSER_MODE; 278 279 typedef struct 280 { 281 MS_U8 *pu8PID0; 282 MS_U8 *pu8PID1; 283 }CIPHER_PARSER_PID; 284 285 typedef enum 286 { 287 E_CIPHER_PARSER_SCB_NONE = 0, 288 E_CIPHER_PARSER_SCB_10, 289 E_CIPHER_PARSER_SCB_11, 290 } CIPHER_PARSER_SCB; 291 292 typedef struct 293 { 294 CIPHER_PARSER_SCB eSCB; //Transport Stream Scramble Pattern, decide 10 or 11 or 1x need to scrambled (TS layer) 295 CIPHER_PARSER_SCB eFSCB; 296 MS_BOOL bTsScrbMask; //Transport Stream Mask 297 MS_BOOL bRmvScrb; //Remove Scramble 298 MS_BOOL bInScrb; //Insert Scramble 299 } CIPHER_PARSER_TSCFG; 300 301 302 typedef struct 303 { 304 DRV_CIPHER_ALGO stAlgo; 305 DRV_CIPHER_KEY stKey; 306 DRV_CIPHER_DATA stInput; 307 DRV_CIPHER_DATA stOutput; 308 MS_BOOL bDecrypt; 309 CIPHER_PARSER_MODE eParserMode; 310 CIPHER_PARSER_TSCFG stTSCfg; 311 CIPHER_PARSER_PID stPID; 312 DRV_CIPHER_KEY stKey2; 313 MS_U32 u32CAVid; 314 MS_BOOL bClearHead; 315 P_DrvCIPHER_EvtCallback pfCallback; 316 }CIPHER_PARSERCFG; 317 318 //////////////////////////////////////////////// 319 // HAL API 320 //////////////////////////////////////////////// 321 void HAL_CIPHER_SetBank(MS_VIRT u32BankAddr) ; 322 void HAL_CIPHER_ResetStatus(MS_BOOL RstDma , MS_BOOL RstSha); 323 void HAL_CIPHER_ResetException(void); 324 MS_BOOL HAL_CIPHER_ResetKey(MS_U32 u32KeyIdx); 325 void HAL_CIPHER_SetDbgLevel(CIPHER_DBGMSG_LEVEL eDBGMsgLevel); 326 327 void HAL_CIPHER_SWReset(void); 328 329 void HAL_CIPHER_DMA_Set_InputSrcFrom(CIPHER_MEM_TYPE InputSrcFrom, MS_U8* pu8Data, MS_U32 u32Size); 330 MS_BOOL HAL_CIPHER_DMA_Set_OutputDstTo(CIPHER_MEM_TYPE OutputDstTo, MS_U8* pu8Data, MS_U32 u32Size); 331 void HAL_CIPHER_DMA_Set_OutputDstKL(MS_BOOL bDstKL); 332 333 334 void HAL_CIPHER_DMA_Set_FileinDesc(MS_PHY FileinAddr, MS_U32 u32FileinNum); 335 void HAL_CIPHER_DMA_Set_FileoutDesc(MS_PHY FileoutSAddr, MS_PHY phyFileoutEAddr); 336 void HAL_CIPHER_OTPHash_Set_FileinDesc(MS_PHY u32FileinAddr, MS_U32 u32FileinNum, MS_U32 u32CurrentRound, CIPHER_MEM_TYPE eInputSrcFrom); 337 338 MS_BOOL HAL_CIPHER_DMA_Set_Key(DRV_CIPHER_KEY stKey); 339 void HAL_CIPHER_DMA_Set_IV(MS_U8* pu8IV, MS_U32 u32Size); 340 341 MS_BOOL HAL_CIPHER_DMA_Set_Data(MS_U8* pu8Data, MS_U32 u32Size); 342 void HAL_CIPHER_DMA_Set_Config(MS_BOOL OutputReg); 343 void HAL_CIPHER_DMA_Set_ReportMode(MS_BOOL RptInDram, MS_PHY u32DramAddr); 344 345 void HAL_CIPHER_DMA_Set_DataSwap(MS_BOOL InDataSwap , MS_BOOL OutDataSwap, 346 MS_BOOL DInByteSwap, MS_BOOL DOutByteSwap ); 347 348 void HAL_CIPHER_DMA_Set_Algo(DRV_CIPHER_ALGO stAlgo); 349 350 void HAL_CIPHER_DMA_Set_OTPHash(MS_U32 u32CurrentRound, MS_U32 u32OTPHashRound); 351 352 MS_BOOL HAL_CIPHER_DMA_Start(MS_BOOL Decrypt , HAL_CIPHER_INTMODE IntMode , MS_BOOL bWaitCmdQ, MS_U16 u16CmdID); 353 MS_BOOL HAL_CIPHER_OTPHash_Start(HAL_CIPHER_INTMODE IntMode , MS_BOOL bWaitCmdQ, MS_U16 u16CmdID); 354 MS_BOOL HAL_CIPHER_DMA_CmdDone(MS_U32 u32CmdID, MS_U32 *u32Ret); 355 356 void HAL_CIPHER_DMA_WriteCMDQ(MS_U32 u32Cmd); 357 358 MS_BOOL HAL_CIPHER_DMA_Set_CaVid(MS_U32 u32CAVid); 359 360 void HAL_CIPHER_DMA_GetRpt(MS_U32 *DmaRpt); 361 void HAL_CIPHER_DMA_GetData(MS_U8 *u8Data) ; 362 void HAL_CIPHER_DMA_AlgoTable_Init(void); 363 MS_BOOL HAL_CIPHER_DMA_CheckAlgo(HAL_CIPHER_ALGO eAlgo, HAL_CIPHER_MODE eMode, HAL_CIPHER_RESIDUE eRes, HAL_CIPHER_SHORTBLOCK eSB); 364 void HAL_CIPHER_Hash_SetMsgLength( MS_U32 u32Size ); 365 MS_BOOL HAL_CIPHER_Hash_SetMsg(MS_PHY u32MsgPAddr, MS_U32 u32Size ,MS_U32 u32SrcSel ); 366 void HAL_CIPHER_Hash_SetHOS(MS_BOOL bHos); 367 MS_BOOL HAL_CIPHER_Hash_Start(HAL_CIPHER_INTMODE IntMode , MS_BOOL bWaitCmdQ , MS_BOOL bRst, MS_U16 u16CmdID); 368 MS_BOOL HAL_CIPHER_Hash_Set_OuputAddr(MS_PHY u32OutputPAddr, MS_U32 u32DstSel); 369 MS_BOOL HAL_CIPHER_Hash_Set_InitWordCnt(HAL_CIPHER_IWCTYPE eIWCType, MS_U32 u32StartBytes); 370 MS_BOOL HAL_CIPHER_Hash_Set_IV(MS_U8* pu8IV, MS_U32 u32IVSize ,MS_U32 u32IVSel); 371 MS_BOOL HAL_CIPHER_Hash_Set_CaVid(MS_U32 u32CAVid); 372 void HAL_CIPHER_Hash_Set_Config(CIPHER_HASH_ALGO algo , MS_BOOL bAutoPad , MS_BOOL bInv16); 373 void HAL_CIPHER_Hash_GetRpt(MS_U32 *HashRpt, MS_U32 u32Size); 374 MS_BOOL HAL_CIPHER_Hash_SetHMACKey(DRV_CIPHER_HMAC_KEY stHMACKey, CIPHER_HMAC_KPAD eKpad, MS_BOOL bClear); 375 MS_BOOL HAL_CIPHER_Hash_CmdDone(MS_U32 u32CmdID, MS_U32 *u32Ret); 376 MS_BOOL HAL_CIPHER_Hash_Set_MsgSrcFrom(CIPHER_MEM_TYPE eMemType, MS_U32 *u32HashSrc); 377 MS_BOOL HAL_CIPHER_Hash_Set_OutputDstTo(CIPHER_MEM_TYPE eMemType, MS_U32 *u32HashDst); 378 void HAL_CIPHER_Hash_Set_ReportMode(MS_BOOL RptInDram, MS_U32 u32DramAddr); 379 void HAL_CIPHER_Hash_ExceptFilter(MS_U32 *pu32Exception, CIPHER_KEY_SRC eKeySrc, MS_U8 u8KeyIdx); 380 381 MS_U32 HAL_CIPHER_ReadException(MS_U32 u32ExcTmp); 382 void HAL_CIPHER_GetException(MS_U32 *pu32ExcFlag); 383 384 void HAL_CIPHER_IntEnable(void); 385 void HAL_CIPHER_IntClear(void); 386 387 //=============PARSER================================= 388 void HAL_CIPHER_PARSER_Set_Mode(CIPHER_PARSER_MODE eMode); 389 void HAL_CIPHER_PARSER_Set_PID(CIPHER_PARSER_PID stPID); 390 void HAL_CIPHER_PARSER_Set_SCB(CIPHER_PARSER_SCB eSCB); 391 void HAL_CIPHER_PARSER_Set_ForceSCB(MS_BOOL bInsert, CIPHER_PARSER_SCB eSCB); 392 MS_BOOL HAL_CIPHER_PARSER_Set_IV2(MS_U8 *pu8IV2, MS_U8 u8IVLen); 393 MS_BOOL HAL_CIPHER_PARSER_Set_Key2(DRV_CIPHER_KEY stKey); 394 void HAL_CIPHER_PARSER_Set_MaskSCB(MS_BOOL bEnable); 395 void HAL_CIPHER_PARSER_Rmv_SCB(MS_BOOL bRemove); 396 void HAL_CIPHER_PARSER_BypassPid(MS_BOOL bEnable); 397 void HAL_CIPHER_PARSER_Set_ClearStartMode(MS_BOOL bEnable); 398 //MISC Function 399 MS_BOOL HAL_CIPHER_Misc_Random(MS_U8 *pu8Buf, MS_U32 u32Size); 400 MS_BOOL HAL_CIPHER_Set_OBFIdx(MS_BOOL bDMA, MS_U8 u8ReadIdx, MS_U8 u8WriteIdx); 401 402 #endif // #ifndef __HAL_CIPHER_H__ 403 404