1 ////////////////////////////////////////////////////////////////////////////////
2 //
3 // Copyright (c) 2006-2013 MStar Semiconductor, Inc.
4 // All rights reserved.
5 //
6 // Unless otherwise stipulated in writing, any and all information contained
7 // herein regardless in any format shall remain the sole proprietary of
8 // MStar Semiconductor Inc. and be kept in strict confidence
9 // ("MStar Confidential Information") by the recipient.
10 // Any unauthorized act including without limitation unauthorized disclosure,
11 // copying, use, reproduction, sale, distribution, modification, disassembling,
12 // reverse engineering and compiling of the contents of MStar Confidential
13 // Information is unlawful and strictly prohibited. MStar hereby reserves the
14 // rights to any and all damages, losses, costs and expenses resulting therefrom.
15 //
16 ////////////////////////////////////////////////////////////////////////////////
17
18 ////////////////////////////////////////////////////////////////////////////////////////////////////
19 // file halCIPHER.c
20 // @brief CIPHER HAL
21 // @author MStar Semiconductor,Inc.
22 ////////////////////////////////////////////////////////////////////////////////////////////////////
23 #ifdef MSOS_TYPE_LINUX_KERNEL
24 #include <linux/string.h>
25 #include <linux/uaccess.h>
26 #include <linux/compat.h>
27 #else
28 #include <stdio.h>
29 #include <string.h>
30 #endif
31
32
33 #include "MsCommon.h"
34 #include "regCIPHER.h"
35 #include "halCIPHER.h"
36 #include "drvCIPHER.h"
37 #include "halCHIP.h"
38
39 #ifndef MSOS_TYPE_LINUX_KERNEL
40 extern void * memset ( void * ptr, int value, size_t num );
41 extern void * memcpy ( void * destination, const void * source, size_t num );
42 extern int printf ( const char * format, ... );
43 #endif
44 //--------------------------------------------------------------------------------------------------
45 // Driver Compiler Option
46 //--------------------------------------------------------------------------------------------------
47
48 //--------------------------------------------------------------------------------------------------
49 // Macro of bit operations
50 //--------------------------------------------------------------------------------------------------
51 #define DELAY_WAITING 1UL
52 #define DELAY_RESCHEDULE 10UL
53 #define COMQ_AVALIABLE 0x10UL
54 #define CIPHER_KEY_SIZE 16UL
55 #define CRYPTODMA_DEBUG_SIZE 32UL
56 #define HASH_MANUAL_BLOCK_SIZE 64UL
57 #define PID_SIZE 2UL
58 #define MIU_SELECT_BIT 0x80000000UL
59
60 //--------------------------------------------------------------------------------------------------
61 // TSP Hardware Abstraction Layer
62 //--------------------------------------------------------------------------------------------------
63 static MS_VIRT _u32RegBase = 0;
64 static REG_AESDMACtrl *_AESDMACtrl = 0 ;
65 static CIPHER_DBGMSG_LEVEL _HAL_CIPHERDBGLevel = CIPHER_DBG_ERR;
66
67 // Algorithm Table for AES/TDES/DES
68 static MS_BOOL _CryptodMA_AlgoTable[4][E_DMA_MODE_NUM][E_DMA_RESIDUE_NUM][E_DMA_SB_NUM];
69
70
71 #define REG32_W(reg, value) do { \
72 (reg)->H = ((value) >> 16); \
73 (reg)->L = ((value) & 0x0000FFFF); \
74 } while(0)
75
76 #define REG32(addr) (*(volatile MS_U32 *) (addr))
77 #define REG16(add) *((volatile MS_U16 *)(add))
78
79 #ifdef CIPHER_NO_PRINTF
80 #define HAL_DEBUG_CIPHER(debug_level, x)
81 #else
82 #define HAL_DEBUG_CIPHER(debug_level, x) do { if (_HAL_CIPHERDBGLevel >= (debug_level)) (x); } while(0)
83 #endif
84 //--------------------------------------------------------------------------------------------------
85 // Local Variable
86 //--------------------------------------------------------------------------------------------------
87
88 MS_PHY _u32DmaInAddr;
89 MS_U32 _u32DmaInNum;
90 MS_PHY _u32DmaOut_StartAddr;
91 MS_PHY _u32DmaOut_EndAddr;
92 MS_PHY _u32ReportAddr;
93 MS_U32 _u32OTPHashLengthPadding;
94
95 MS_U8 _pu8CipherKey[CIPHER_KEY_SIZE];
96 MS_U8 _pu8CipherKey2[CIPHER_KEY_SIZE];
97 MS_U8 _pu8IV[CIPHER_KEY_SIZE];
98 MS_U8 _pu8IV2[CIPHER_KEY_SIZE];
99 MS_U8 _pu8Data[CIPHER_KEY_SIZE];
100 MS_U8 _pu8PID0[PID_SIZE];
101 MS_U8 _pu8PID1[PID_SIZE];
102
103 MS_U32 _u32CmdLen = 0 ;
104
105 // [NOTE] Solve Strict-Aliasing //
106 union {
107 CMD_DmaFormat0 DmaCtrl0;
108 MS_U32 u32DmaCtrl0;
109 }_uDmaCtrl0;
110
111 union{
112 CMD_DmaFormat1 DmaCtrl1;
113 MS_U32 u32DmaCtrl1;
114 }_uDmaCtrl1;
115
116 union{
117 CMD_DmaFormat2 DmaCtrl2;
118 MS_U32 u32DmaCtrl2;
119 }_uDmaCtrl2;
120
121 union{
122 CMD_DmaFormat3 DmaCtrl3;
123 MS_U32 u32DmaCtrl3;
124 }_uDmaCtrl3;
125
126 union{
127 Hash_DmaFormat0 HashCtrl0;
128 MS_U32 u32HashCtrl0;
129 }_uHashCtrl0;
130
131 union{
132 Hash_DmaFormat1 HashCtrl1;
133 MS_U32 u32HashCtrl1;
134 }_uHashCtrl1;
135
136 union{
137 CMD_HashFormat2 HashCtrl2;
138 MS_U32 u32HashCtrl2;
139 }_uHashCtrl2;
140
141 MS_PHY _u32HashSrcAddr;
142 MS_PHY _u32HashDestAddr;
143 MS_U32 _u32InitWordCnt;
144 MS_U32 _u32HashMsgLen;
145
146 MS_U8 _pu8HashIV[HASH_CMD_IV_SIZE];
147 MS_U8 _pu8HashMsg[HASH_CMD_MSG_SIZE];
148 MS_U8 _pu8HashHMACHostKey[HASH_CMD_HMAC_HOSTKEY_SIZE];
149
150 static MS_U32 _CIPHER_CAVid = 0x0F;
151
152 //--------------------------------------------------------------------------------------------------
153 // Inline Function
154 //--------------------------------------------------------------------------------------------------
WRITE_CMDQ(MS_U32 u32Value)155 void WRITE_CMDQ(MS_U32 u32Value)
156 {
157 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s] = 0x%08X \n",__func__, (unsigned int)(u32Value)));
158 REG32(&_AESDMACtrl->Cmd_Queue) = (u32Value) ;
159 }
160
_HAL_CIPHER_TransMIUAddr(MS_PHY * phyAddr)161 MS_BOOL _HAL_CIPHER_TransMIUAddr(MS_PHY* phyAddr)
162 {
163 CHIP_MIU_ID eMIUSel;
164 MS_PHY phyOffset;
165
166 if(NULL == phyAddr)
167 {
168 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]NULL Address!\n",__func__, __LINE__));
169 return FALSE;
170 }
171
172 _phy_to_miu_offset(eMIUSel,phyOffset,*phyAddr);
173
174 if(E_CHIP_MIU_0 == eMIUSel)
175 {
176 *phyAddr = phyOffset;
177 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]Physical address trans to MIU0\n",__func__, __LINE__));
178 }
179 else
180 {
181 *phyAddr = (phyOffset | MIU_SELECT_BIT);
182 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]Physical address trans to MIU1\n",__func__, __LINE__));
183 }
184
185 return TRUE;
186 }
187
_HAL_CIPHER_GetCmdLen(HAL_CIPHER_CMDTYPE CmdType)188 MS_U32 _HAL_CIPHER_GetCmdLen(HAL_CIPHER_CMDTYPE CmdType)
189 {
190
191 MS_U32 u32CmdLen = 0 ;
192
193
194 if ( E_CIPHER_TYPE_DMA == CmdType )
195 {
196 u32CmdLen = 7;
197
198 if ( _uDmaCtrl1.DmaCtrl1.RR == TRUE )
199 {
200 u32CmdLen += 1 ;
201 }
202 if ( _uDmaCtrl0.DmaCtrl0.DIV == TRUE )
203 {
204 u32CmdLen += 4 ;
205 }
206 if ( _uDmaCtrl1.DmaCtrl1.SD == E_DMA_SRC_DIRECT )
207 {
208 u32CmdLen += 4 ;
209 }
210 if ( _uDmaCtrl0.DmaCtrl0.DK == TRUE )
211 {
212 u32CmdLen += 4 ;
213 }
214 if ( _uDmaCtrl2.DmaCtrl2.HP == TRUE )
215 {
216 u32CmdLen += 1 ;
217 }
218 if ( _uDmaCtrl3.DmaCtrl3.DK2 == TRUE )
219 {
220 u32CmdLen += 4 ;
221 }
222 if ( _uDmaCtrl3.DmaCtrl3.DIV2 == TRUE )
223 {
224 u32CmdLen += 4 ;
225 }
226
227 return u32CmdLen ;
228 }
229
230
231 if ( E_CIPHER_TYPE_SHA == CmdType )
232 {
233
234 u32CmdLen = 3 ;
235
236 if (_uHashCtrl0.HashCtrl0.CMD == CMD_HASH_START_RR )
237 {
238 u32CmdLen += 1 ;
239 }
240
241 if (_uHashCtrl0.HashCtrl0.Src != CMD_HASH_SRC_REG )
242 {
243 u32CmdLen += 1 ;
244 }
245
246 if(_uHashCtrl2.HashCtrl2.RR == TRUE)
247 {
248 u32CmdLen += 1 ;
249 }
250
251 if (_uHashCtrl0.HashCtrl0.IWC_Sel == CMD_HASH_IWC_CMDQ )
252 {
253 u32CmdLen += 1 ;
254 }
255
256 if ((_uHashCtrl0.HashCtrl0.Dest == CMD_HASH_OUTPUT_DRAM ) || (_uHashCtrl0.HashCtrl0.Dest == CMD_HASH_OUTPUT_R2 ))
257 {
258 u32CmdLen += 1 ;
259 }
260
261 if (_uHashCtrl0.HashCtrl0.InitHashSel == CMD_HASH_IV_CMD )
262 {
263 u32CmdLen += 8 ;
264 }
265
266 if (_uHashCtrl0.HashCtrl0.Src == CMD_HASH_SRC_REG )
267 {
268 u32CmdLen += 16 ;
269 }
270
271 if((_uHashCtrl0.HashCtrl0.HMAC_KeySel == CMD_HMAC_KSEL_HK) && (_uHashCtrl0.HashCtrl0.DK == CMD_HMAC_KSEL_DIR_HK))
272 {
273 u32CmdLen += 4 ;
274 }
275
276 return u32CmdLen ;
277
278 }
279
280 if ( E_CIPHER_TYPE_OTPHASH == CmdType )
281 {
282 u32CmdLen = 7 ;
283
284 if ( _uDmaCtrl1.DmaCtrl1.NL == TRUE )
285 {
286 u32CmdLen += 1 ;
287 }
288 if ( _uDmaCtrl1.DmaCtrl1.RR == TRUE )
289 {
290 u32CmdLen += 1 ;
291 }
292 if ( _uDmaCtrl3.DmaCtrl3.AP == TRUE && _uDmaCtrl3.DmaCtrl3.IK == FALSE)
293 {
294 u32CmdLen += 1 ;
295 }
296
297 return u32CmdLen ;
298 }
299
300
301 return 0 ;
302
303 }
304
_HAL_CIPHER_TransKey(CIPHER_KEY_SRC src,MS_U32 idx)305 HAL_CIPHER_KEYSRC _HAL_CIPHER_TransKey(CIPHER_KEY_SRC src, MS_U32 idx)
306 {
307 HAL_CIPHER_KEYSRC KeySrc = E_DMA_KSEL_REGKEY;
308
309 if(src == E_CIPHER_KSRC_KL)
310 {
311 KeySrc = E_DMA_KSEL_SK0 + idx;
312 }
313 else if(src == E_CIPHER_KSRC_OTP)
314 {
315 KeySrc = E_DMA_KSEL_MK0 + idx;
316 }
317 else if(src == E_CIPHER_KSRC_CPU)
318 {
319 KeySrc = E_DMA_KSEL_REGKEY;
320 }
321 else if(src == E_CIPHER_KSRC_CAIP)
322 {
323 KeySrc = E_DMA_KSEL_CAIP;
324 }
325
326 return KeySrc;
327 }
328
_HAL_CIPHER_TransMainAlgo(CIPHER_MAIN_ALGO algo)329 HAL_CIPHER_ALGO _HAL_CIPHER_TransMainAlgo(CIPHER_MAIN_ALGO algo)
330 {
331 HAL_CIPHER_ALGO hal_algo;
332 switch(algo)
333 {
334 case E_CIPHER_MAIN_AES:
335 hal_algo = E_DMA_ALGO_AES;
336 break;
337 case E_CIPHER_MAIN_DES:
338 hal_algo = E_DMA_ALGO_DES;
339 break;
340 case E_CIPHER_MAIN_TDES:
341 hal_algo = E_DMA_ALGO_TDES;
342 break;
343 case E_CIPHER_MAIN_M6_S56_CCBC:
344 hal_algo = E_DMA_ALGO_M6_S56_CCBC;
345 break;
346 case E_CIPHER_MAIN_M6_S56:
347 hal_algo = E_DMA_ALGO_M6_S56;
348 break;
349 case E_CIPHER_MAIN_M6_KE56:
350 hal_algo = E_DMA_ALGO_M6_KE56;
351 break;
352 case E_CIPHER_MAIN_RC4:
353 hal_algo = E_DMA_ALGO_RC4;
354 break;
355 case E_CIPHER_MAIN_RC4_128:
356 hal_algo = E_DMA_ALGO_RC4_128;
357 break;
358 default:
359 hal_algo = E_DMA_ALGO_NONE;
360 }
361
362 return hal_algo;
363 }
364
_HAL_CIPHER_TransSubAlgo(CIPHER_SUB_ALGO algo)365 HAL_CIPHER_MODE _HAL_CIPHER_TransSubAlgo(CIPHER_SUB_ALGO algo)
366 {
367 HAL_CIPHER_MODE hal_algo;
368 switch(algo)
369 {
370 case E_CIPHER_SUB_ECB:
371 hal_algo = E_DMA_MODE_ECB;
372 break;
373 case E_CIPHER_SUB_CBC:
374 hal_algo = E_DMA_MODE_CBC;
375 break;
376 case E_CIPHER_SUB_CTR:
377 hal_algo = E_DMA_MODE_CTR;
378 break;
379 case E_CIPHER_SUB_CBC_MAC:
380 hal_algo = E_DMA_MODE_CBC_MAC;
381 break;
382 case E_CIPHER_SUB_CTR_64:
383 hal_algo = E_DMA_MODE_CTR_64;
384 break;
385 case E_CIPHER_SUB_CMAC_Key:
386 hal_algo = E_DMA_MODE_CMAC_Key;
387 break;
388 case E_CIPHER_SUB_CMAC_Algo:
389 hal_algo = E_DMA_MODE_CMAC_Algo;
390 break;
391 case E_CIPHER_SUB_PCBC_ADD:
392 hal_algo = E_DMA_MODE_PCBC_ADD;
393 break;
394 case E_CIPHER_SUB_PCBC_XOR:
395 hal_algo = E_DMA_MODE_PCBC_XOR;
396 break;
397 case E_CIPHER_SUB_OTPHASH:
398 hal_algo = E_DMA_MODE_OTPHASH;
399 break;
400 default:
401 hal_algo = E_DMA_MODE_NONE;
402 }
403
404 return hal_algo;
405
406 }
407
_HAL_CIPHER_TransResAlgo(CIPHER_RES_ALGO algo)408 HAL_CIPHER_RESIDUE _HAL_CIPHER_TransResAlgo(CIPHER_RES_ALGO algo)
409 {
410 HAL_CIPHER_RESIDUE hal_algo;
411 switch(algo)
412 {
413 case E_CIPHER_RES_CLR:
414 hal_algo = E_DMA_RESIDUE_CLR;
415 break;
416 case E_CIPHER_RES_CTS:
417 hal_algo = E_DMA_RESIDUE_CTS;
418 break;
419 case E_CIPHER_RES_SCTE52:
420 hal_algo = E_DMA_RESIDUE_SCTE52;
421 break;
422 default:
423 hal_algo = E_DMA_RESIDUE_NONE;
424 }
425
426 return hal_algo;
427 }
428
_HAL_CIPHER_TransSBAlgo(CIPHER_SB_ALGO algo)429 HAL_CIPHER_SHORTBLOCK _HAL_CIPHER_TransSBAlgo(CIPHER_SB_ALGO algo)
430 {
431 HAL_CIPHER_SHORTBLOCK hal_algo;
432 switch(algo)
433 {
434 case E_CIPHER_SB_CLR:
435 hal_algo = E_DMA_SB_CLR;
436 break;
437 case E_CIPHER_SB_IV1:
438 hal_algo = E_DMA_SB_IV1;
439 break;
440 case E_CIPHER_SB_IV2:
441 hal_algo = E_DMA_SB_IV2;
442 break;
443 default:
444 hal_algo = E_DMA_SB_NONE;
445 }
446
447 return hal_algo;
448
449 }
450
_HAL_CIPHER_TransHASHAlgo(CIPHER_HASH_ALGO algo)451 HAL_CIPHER_HASHMODE _HAL_CIPHER_TransHASHAlgo(CIPHER_HASH_ALGO algo)
452 {
453 HAL_CIPHER_HASHMODE hal_algo;
454 switch(algo)
455 {
456 case E_CIPHER_HASH_ALGO_SHA1:
457 hal_algo = E_HASH_SHA1;
458 break;
459 case E_CIPHER_HASH_ALGO_SHA256:
460 hal_algo = E_HASH_SHA256;
461 break;
462 case E_CIPHER_HASH_ALGO_MD5:
463 hal_algo = E_HASH_MD5;
464 break;
465 default:
466 hal_algo = E_HASH_SHA256;
467 }
468
469 return hal_algo;
470 }
471
HAL_CIPHER_DMA_AlgoTable_Init(void)472 void HAL_CIPHER_DMA_AlgoTable_Init(void)
473 {
474
475 memset(_CryptodMA_AlgoTable , 0x0 , sizeof(_CryptodMA_AlgoTable));
476
477 // AES algorithms //
478 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
479 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
480 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
481 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
482 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_IV1] = TRUE ;
483 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_IV1] = TRUE ;
484 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_CLR] = TRUE ;
485 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC_MAC][E_DMA_RESIDUE_CLR][E_DMA_RESIDUE_CLR] = TRUE ;
486 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CTR][E_DMA_RESIDUE_NONE][E_DMA_SB_NONE] = TRUE ; // residue & sb don't care
487
488 // DES Algorithms //
489 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
490 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
491 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
492 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
493 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_IV1] = TRUE ;
494 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_IV1] = TRUE ;
495 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_IV2] = TRUE ;
496 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_CLR] = TRUE ;
497 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CTR][E_DMA_RESIDUE_NONE][E_DMA_SB_NONE] = TRUE ; // residue & sb don't care
498
499 // TDES Algorithm //
500 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
501 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
502 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CTR][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
503 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
504 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_IV1] = TRUE ;
505 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
506 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_IV1] = TRUE ;
507 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_IV2] = TRUE ;
508 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_CLR] = TRUE ;
509
510 }
511
512
HAL_CIPHER_DMA_CheckAlgo(HAL_CIPHER_ALGO eAlgo,HAL_CIPHER_MODE eMode,HAL_CIPHER_RESIDUE eRes,HAL_CIPHER_SHORTBLOCK eSB)513 MS_BOOL HAL_CIPHER_DMA_CheckAlgo(HAL_CIPHER_ALGO eAlgo, HAL_CIPHER_MODE eMode, HAL_CIPHER_RESIDUE eRes, HAL_CIPHER_SHORTBLOCK eSB)
514 {
515 // Special Cases //
516 if (eAlgo > E_DMA_ALGO_TDES )
517 {
518 if ((E_DMA_ALGO_RC4==eAlgo)&&(E_DMA_RESIDUE_NONE==eRes)&&(E_DMA_SB_CLR == eSB)&&(E_DMA_MODE_NONE==eMode))
519 { //RC4/none/none/none
520 return TRUE ;
521 }
522 if ((E_DMA_ALGO_M6_KE56==eAlgo)&&(E_DMA_MODE_ECB==eMode)&&(E_DMA_RESIDUE_NONE==eRes)&&(E_DMA_SB_CLR==eSB))
523 { //M6_KE56/ecb/none/clr
524 return TRUE;
525 }
526 if ((E_DMA_ALGO_M6_S56==eAlgo)&&(E_DMA_MODE_ECB==eMode)&&(E_DMA_RESIDUE_NONE==eRes)&&(E_DMA_SB_CLR==eSB))
527 { //M6_S56/ecb/none/clr
528 return TRUE;
529 }
530 if ((E_DMA_ALGO_M6_S56_CCBC==eAlgo)&&(E_DMA_MODE_NONE==eMode)&&(E_DMA_RESIDUE_NONE==eRes)&&(E_DMA_SB_CLR==eSB))
531 { //M6_S56_CCBC/none/none/clr
532 return TRUE;
533 }
534 return FALSE ;
535 }
536
537 // Reference table for Algorithm AES/TDES/DES //
538 return _CryptodMA_AlgoTable[eAlgo][eMode][eRes][eSB] ;
539 }
540
HAL_CIPHER_SetBank(MS_VIRT u32BankAddr)541 void HAL_CIPHER_SetBank(MS_VIRT u32BankAddr)
542 {
543 _u32RegBase = u32BankAddr;
544 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE);
545
546 }
547
HAL_CIPHER_SetDbgLevel(CIPHER_DBGMSG_LEVEL eDBGMsgLevel)548 void HAL_CIPHER_SetDbgLevel(CIPHER_DBGMSG_LEVEL eDBGMsgLevel)
549 {
550 _HAL_CIPHERDBGLevel = eDBGMsgLevel;
551 }
552
HAL_CIPHER_ResetStatus(MS_BOOL RstDma,MS_BOOL RstHash)553 void HAL_CIPHER_ResetStatus(MS_BOOL RstDma , MS_BOOL RstHash)
554 {
555 if (RstDma)
556 {
557 _uDmaCtrl0.u32DmaCtrl0 = 0 ;
558 _uDmaCtrl1.u32DmaCtrl1 = 0 ;
559 _uDmaCtrl2.u32DmaCtrl2 = 0 ;
560 _uDmaCtrl3.u32DmaCtrl3 = 0 ;
561
562 _u32DmaInAddr = 0;
563 _u32DmaInNum = 0 ;
564 _u32OTPHashLengthPadding = 0;
565 _u32DmaOut_StartAddr = 0;
566 _u32DmaOut_EndAddr = 0;
567 _u32ReportAddr = 0 ;
568 memset(&_pu8CipherKey , 0x0, CIPHER_KEY_SIZE );
569 memset(&_pu8IV , 0x0, CIPHER_KEY_SIZE );
570 memset(&_pu8CipherKey2 , 0x0, CIPHER_KEY_SIZE );
571 memset(&_pu8IV2 , 0x0, CIPHER_KEY_SIZE );
572 memset(&_pu8Data , 0x0, CIPHER_KEY_SIZE );
573 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Reset DMA value\n", __FUNCTION__, __LINE__));
574
575 }
576
577 if (RstHash)
578 {
579 (_uHashCtrl0.u32HashCtrl0) = 0 ;
580 (_uHashCtrl1.u32HashCtrl1) = 0 ;
581 (_uHashCtrl2.u32HashCtrl2) = 0 ;
582
583 _u32HashSrcAddr = 0 ;
584 _u32InitWordCnt = 0 ;
585 _u32HashDestAddr = 0 ;
586 _u32HashMsgLen = 0 ;
587
588 memset(_pu8HashIV, 0x0 ,HASH_CMD_IV_SIZE);
589 memset(_pu8HashMsg, 0x0 , HASH_CMD_MSG_SIZE);
590 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Reset HASH value\n", __FUNCTION__, __LINE__));
591 }
592
593 }
594
HAL_CIPHER_ResetException(void)595 void HAL_CIPHER_ResetException(void)
596 {
597 MS_U32 u32DMACtrl = REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]);
598 REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = u32DMACtrl | REG_EXCEPT_FLAG_CLEAR; //clear all except flag
599 REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = u32DMACtrl & ~REG_EXCEPT_FLAG_CLEAR; //enable acpu except flag
600 }
601
HAL_CIPHER_ResetKey(MS_U32 u32KeyIdx)602 MS_BOOL HAL_CIPHER_ResetKey(MS_U32 u32KeyIdx)
603 {
604 HAL_CIPHER_KEYSRC KeySrc;
605
606 //Check Key Index
607 if(u32KeyIdx > HAL_CRYPTODMA_DMA_KEY_SLOT-1)
608 {
609 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Invalid Key Index[%u]\n",
610 __func__, __LINE__, u32KeyIdx));
611 return FALSE;
612 }
613
614 KeySrc = _HAL_CIPHER_TransKey(E_CIPHER_KSRC_KL, u32KeyIdx);
615
616 _uDmaCtrl0.DmaCtrl0.DK = FALSE;
617 _uDmaCtrl0.DmaCtrl0.KeySel = KeySrc|CMD_DMA_KSEL_CLR_SK;
618
619 return TRUE;
620
621 }
HAL_CIPHER_SWReset(void)622 void HAL_CIPHER_SWReset(void)
623 {
624 MS_U32 DMA_CTRL = REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]);
625 REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = DMA_CTRL | REG_DMA_SW_RESET; //reset CryptoDMA
626 REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = DMA_CTRL & ~REG_DMA_SW_RESET; //enable CryptoDMA
627
628 }
629
HAL_CIPHER_Set_OBFIdx(MS_BOOL bDMA,MS_U8 u8ReadIdx,MS_U8 u8WriteIdx)630 MS_BOOL HAL_CIPHER_Set_OBFIdx(MS_BOOL bDMA, MS_U8 u8ReadIdx, MS_U8 u8WriteIdx)
631 {
632 if(bDMA)
633 {
634 _uDmaCtrl2.DmaCtrl2.OBF_IDX_READ = u8ReadIdx;
635 _uDmaCtrl2.DmaCtrl2.OBF_IDX_WRITE = u8WriteIdx;
636 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Set DMA Obf Index Read:[%u], Write:[%u]\n",
637 __func__, __LINE__, u8ReadIdx, u8WriteIdx));
638 }
639 else
640 {
641 _uHashCtrl1.HashCtrl1.OBF_IDX_READ = u8ReadIdx;
642 _uHashCtrl1.HashCtrl1.OBF_IDX_WRITE = u8WriteIdx;
643 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Set HASH Obf Index Read:[%u], Write:[%u]\n",
644 __func__, __LINE__, u8ReadIdx, u8WriteIdx));
645 }
646
647 return TRUE;
648 }
649
HAL_CIPHER_DMA_Set_InputSrcFrom(CIPHER_MEM_TYPE InputSrcFrom,MS_U8 * pu8Data,MS_U32 u32Size)650 void HAL_CIPHER_DMA_Set_InputSrcFrom(CIPHER_MEM_TYPE InputSrcFrom, MS_U8* pu8Data, MS_U32 u32Size)
651 {
652 HAL_CIPHER_DATASRC src = E_DMA_SRC_DRAM;
653
654 switch(InputSrcFrom)
655 {
656 case E_CIPHER_DRAM:
657 _u32DmaInAddr = 0;
658 src = E_DMA_SRC_DRAM;
659 break;
660
661 case E_CIPHER_DQMEM://only for R2
662 _u32DmaInAddr = HAL_CIPHER_BASE_DQMEM;
663 src = E_DMA_SRC_DQMEM;
664 break;
665
666 case E_CIPHER_IQMEM://only for R2
667 _u32DmaInAddr = HAL_CIPHER_BASE_IQMEM;
668 src = E_DMA_SRC_IQMEM;
669 break;
670
671 // TODO: future work, DIRECT data from pu8Data
672 #if 0
673 case E_CIPHER_DIRECT:
674 HAL_CIPHER_DMA_Set_Data(pu8Data, u32Size);
675 src = E_DMA_SRC_DIRECT;
676 break;
677 #endif
678
679 case E_CIPHER_OTP: //only for OTPHASH
680 _u32DmaInAddr = 0;
681 src = E_DMA_SRC_HW_INPUT;
682 break;
683
684 default:
685 _u32DmaInAddr = 0;
686 src = E_DMA_SRC_DRAM;
687 break;
688 }
689
690 _uDmaCtrl1.DmaCtrl1.SD = (MS_U32)src;
691
692 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set input source from [%d]\n", __func__, __LINE__, src));
693 }
694
HAL_CIPHER_DMA_Set_OutputDstTo(CIPHER_MEM_TYPE OutputDstTo,MS_U8 * pu8Data,MS_U32 u32Size)695 MS_BOOL HAL_CIPHER_DMA_Set_OutputDstTo(CIPHER_MEM_TYPE OutputDstTo, MS_U8* pu8Data, MS_U32 u32Size)
696 {
697 HAL_CIPHER_DATADST dst = E_DMA_DST_DRAM;
698 MS_BOOL bDstKL = FALSE;
699
700 switch(OutputDstTo)
701 {
702 case E_CIPHER_DRAM:
703 _u32DmaOut_StartAddr = 0;
704 _u32DmaOut_EndAddr = 0;
705 dst = E_DMA_DST_DRAM;
706 break;
707
708 case E_CIPHER_DQMEM: //only for R2
709 _u32DmaOut_StartAddr = HAL_CIPHER_BASE_DQMEM;
710 _u32DmaOut_EndAddr = HAL_CIPHER_BASE_DQMEM;
711 dst = E_DMA_DST_DQMEM;
712 break;
713
714 case E_CIPHER_IQMEM: //only for R2
715 _u32DmaOut_StartAddr = HAL_CIPHER_BASE_IQMEM;
716 _u32DmaOut_EndAddr = HAL_CIPHER_BASE_IQMEM;
717 dst = E_DMA_DST_IQMEM;
718 break;
719
720 case E_CIPHER_DIRECT: //for ACPU, OTPHASH
721 dst = E_DMA_DST_REGFILE;
722 break;
723
724 case E_CIPHER_KL_LUT: //for KL transform algorithm
725 _u32DmaOut_StartAddr = HAL_CIPHER_BASE_LUT;
726 _u32DmaOut_EndAddr = HAL_CIPHER_BASE_LUT;
727 dst = E_DMA_DST_DRAM;
728 bDstKL = TRUE;
729 break;
730
731 case E_CIPHER_KL_M: //for KL transform algorithm
732 _u32DmaOut_StartAddr = HAL_CIPHER_BASE_M;
733 _u32DmaOut_EndAddr = HAL_CIPHER_BASE_M;
734 dst = E_DMA_DST_DRAM;
735 bDstKL = TRUE;
736 break;
737
738 case E_CIPHER_KL_BC: //for KL transform algorithm
739 _u32DmaOut_StartAddr = HAL_CIPHER_BASE_BC;
740 _u32DmaOut_EndAddr = HAL_CIPHER_BASE_BC;
741 dst = E_DMA_DST_DRAM;
742 bDstKL = TRUE;
743 break;
744
745 default:
746 _u32DmaOut_StartAddr = 0;
747 _u32DmaOut_EndAddr = 0;
748 dst = E_DMA_DST_DRAM;
749 break;
750 }
751
752 _uDmaCtrl1.DmaCtrl1.Dest= (MS_U32)dst;
753
754 if(bDstKL)
755 {
756 HAL_CIPHER_DMA_Set_OutputDstKL(TRUE);
757 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set output destination to KL [0x%4x]\n", __func__, __LINE__, (unsigned int)_u32DmaOut_StartAddr));
758 }
759 else
760 {
761 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set output destination to [%d]\n", __func__, __LINE__, dst));
762 }
763
764 return TRUE;
765 }
766
HAL_CIPHER_DMA_Set_OutputDstKL(MS_BOOL bDstKL)767 void HAL_CIPHER_DMA_Set_OutputDstKL(MS_BOOL bDstKL)
768 {
769 if(bDstKL)
770 {
771 _uDmaCtrl1.DmaCtrl1.DestKL = CMD_DMA_OUTPUT_SRAM_KL;
772 _uDmaCtrl0.DmaCtrl0.DK = TRUE;
773 }
774 else
775 {
776 _uDmaCtrl1.DmaCtrl1.DestKL = CMD_DMA_OUTPUT_DEST;
777 }
778 }
779
HAL_CIPHER_DMA_Set_FileinDesc(MS_PHY u32FileinAddr,MS_U32 u32FileinNum)780 void HAL_CIPHER_DMA_Set_FileinDesc(MS_PHY u32FileinAddr, MS_U32 u32FileinNum)
781 {
782
783 _u32DmaInAddr += u32FileinAddr;
784 _u32DmaInNum = u32FileinNum ;
785 }
786
HAL_CIPHER_DMA_Set_FileoutDesc(MS_PHY u32FileoutSAddr,MS_PHY u32phyFileoutEAddr)787 void HAL_CIPHER_DMA_Set_FileoutDesc(MS_PHY u32FileoutSAddr, MS_PHY u32phyFileoutEAddr)
788 {
789 _u32DmaOut_StartAddr += u32FileoutSAddr;
790 _u32DmaOut_EndAddr += u32phyFileoutEAddr;
791
792 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d] _u32DmaOut_StartAddr = %x _u32DmaOut_EndAddr = %x\n", __func__, __LINE__, (unsigned int)_u32DmaOut_StartAddr, (unsigned int)_u32DmaOut_EndAddr));
793 }
794
HAL_CIPHER_OTPHash_Set_FileinDesc(MS_PHY u32FileinAddr,MS_U32 u32FileinNum,MS_U32 u32CurrentRound,CIPHER_MEM_TYPE eInputSrcFrom)795 void HAL_CIPHER_OTPHash_Set_FileinDesc(MS_PHY u32FileinAddr, MS_U32 u32FileinNum, MS_U32 u32CurrentRound, CIPHER_MEM_TYPE eInputSrcFrom)
796 {
797 if(E_CIPHER_OTP == eInputSrcFrom)
798 {
799 _u32DmaInAddr = u32CurrentRound;
800 }
801 else
802 {
803 _u32DmaInAddr = u32FileinAddr + u32CurrentRound*HAL_CRYPTODMA_OTPHASH_UNIT;
804 }
805
806 _u32OTPHashLengthPadding = u32FileinNum;
807 if((u32FileinNum - u32CurrentRound*HAL_CRYPTODMA_OTPHASH_UNIT) >= HAL_CRYPTODMA_OTPHASH_UNIT)
808 {
809 _u32DmaInNum = HAL_CRYPTODMA_OTPHASH_UNIT;
810 }
811 else
812 {
813 _u32DmaInNum = u32FileinNum - u32CurrentRound*HAL_CRYPTODMA_OTPHASH_UNIT;
814 }
815
816 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d] _u32DmaInAddr = %x _u32DmaInNum = %x _u32OTPHashLengthPadding = %x\n", __func__, __LINE__, (unsigned int)_u32DmaInAddr, (unsigned int)_u32DmaInNum, (unsigned int)_u32OTPHashLengthPadding));
817 }
818
HAL_CIPHER_DMA_Set_Key(DRV_CIPHER_KEY stKey)819 MS_BOOL HAL_CIPHER_DMA_Set_Key(DRV_CIPHER_KEY stKey)
820 {
821 HAL_CIPHER_KEYSRC KeySrc = 0;
822 HAL_CIPHER_ALGO algo = 0;
823 MS_BOOL bDK = FALSE;
824
825 algo = _uDmaCtrl0.DmaCtrl0.Algo;
826
827 if(E_DMA_ALGO_NONE == algo)
828 {
829 //No key
830 bDK = TRUE;
831 memset(_pu8CipherKey, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX);
832 goto SET_KEY_DONE;
833 }
834 //Check Key Source, Index
835 if(((E_CIPHER_KSRC_KL == stKey.eKeySrc) && (stKey.u8KeyIdx > HAL_CRYPTODMA_DMA_KEY_SLOT-1)) ||
836 ((E_CIPHER_KSRC_OTP == stKey.eKeySrc) && (stKey.u8KeyIdx > HAL_CRYPTODMA_OTP_SCK_NUM-1)))
837 {
838 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Invalid KeySrc[%d], Index[%d]\n",
839 __func__, __LINE__, stKey.eKeySrc, stKey.u8KeyIdx));
840 return FALSE;
841 }
842
843 //DRV to HAL Type transfer
844 KeySrc = _HAL_CIPHER_TransKey(stKey.eKeySrc, stKey.u8KeyIdx);
845
846 // key from CPU
847 if(E_DMA_KSEL_REGKEY == KeySrc)
848 {
849 if ((NULL != stKey.pu8KeyData) && (stKey.u8KeyLen != 0) && (stKey.u8KeyLen <= HAL_CRYPTODMA_KEYLEN_MAX) )
850 {
851 memset(_pu8CipherKey, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX );
852 memcpy(_pu8CipherKey, (MS_U8 *)stKey.pu8KeyData , stKey.u8KeyLen);
853 bDK = TRUE ;
854 KeySrc = 0;
855 }
856 else
857 {
858 return FALSE ;
859 }
860
861 }
862 else if(E_DMA_KSEL_CAIP == KeySrc)
863 {
864 bDK = FALSE ;
865 KeySrc = 0 ;
866 }
867 else// key from KL or OTP
868 {
869 bDK = FALSE;
870 }
871
872 SET_KEY_DONE:
873
874 _uDmaCtrl0.DmaCtrl0.DK = bDK;
875 _uDmaCtrl0.DmaCtrl0.KeySel = KeySrc;
876
877 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set DK[%d], KeySel[%d]\n",
878 __func__, __LINE__, bDK, KeySrc));
879
880 return TRUE ;
881 }
882
HAL_CIPHER_DMA_Set_IV(MS_U8 * pu8IV,MS_U32 u32Size)883 void HAL_CIPHER_DMA_Set_IV(MS_U8* pu8IV, MS_U32 u32Size)
884 {
885 MS_BOOL bDIV = FALSE;
886
887 if ((NULL != pu8IV) && (u32Size != 0) && (u32Size <= HAL_CRYPTODMA_KEYLEN_MAX) )
888 {
889 memset(_pu8IV, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX);
890 memcpy(_pu8IV, (MS_U8 *)pu8IV, u32Size);
891 bDIV = TRUE;
892 }
893 else // Data from Dram
894 {
895 memset(_pu8IV, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX);
896 bDIV = FALSE;
897 }
898
899 _uDmaCtrl0.DmaCtrl0.DIV = bDIV ;
900
901 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set DIV[%d]\n",
902 __func__, __LINE__, bDIV));
903 }
904
905
906 // Set Direct Data to Register Input, if Dram input, set pu8Data = NULL ;
HAL_CIPHER_DMA_Set_Data(MS_U8 * pu8Data,MS_U32 u32Size)907 MS_BOOL HAL_CIPHER_DMA_Set_Data(MS_U8* pu8Data, MS_U32 u32Size)
908 {
909 HAL_CIPHER_DATASRC eDataSrc = E_DMA_SRC_DRAM;
910
911 // Data size can't be zero //
912 if (( 0 == u32Size ) && (NULL != pu8Data ))
913 {
914 return FALSE ;
915 }
916
917 if (NULL != pu8Data ) // Data from CMDQ
918 {
919 _u32DmaInNum = u32Size ;
920 memset(_pu8Data, 0x0, HAL_CRYPTODMA_DIRDATA_MAX);
921 memcpy(_pu8Data, (MS_U8 *)pu8Data, u32Size);
922 eDataSrc = E_DMA_SRC_DIRECT ;
923 }
924 else // Data from Dram
925 {
926 memset(_pu8Data, 0x0 , HAL_CRYPTODMA_DIRDATA_MAX );
927 eDataSrc = E_DMA_SRC_DRAM ;
928 }
929
930 _uDmaCtrl1.DmaCtrl1.SD = (MS_U32)eDataSrc ;
931
932 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set SD[%d]\n",
933 __func__, __LINE__, eDataSrc));
934
935 return TRUE ;
936 }
937
HAL_CIPHER_DMA_Set_CaVid(MS_U32 u32CAVid)938 MS_BOOL HAL_CIPHER_DMA_Set_CaVid(MS_U32 u32CAVid)
939 {
940 MS_U32 u32Tmp = u32CAVid;
941
942 if(u32Tmp > HAL_CRYPTODMA_CAVID_MAX)
943 {
944 return FALSE;
945 }
946
947 if(u32Tmp == 0)
948 {
949 u32Tmp = _CIPHER_CAVid ;
950 }
951 else
952 {
953 u32Tmp = u32CAVid ;
954 }
955
956 _uDmaCtrl1.DmaCtrl1.CaVid = u32Tmp ;
957
958 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set CAVid [0x%x]\n",
959 __func__, __LINE__, (unsigned int)u32Tmp));
960
961 return TRUE;
962 }
963
HAL_CIPHER_DMA_Set_Config(MS_BOOL OutputReg)964 void HAL_CIPHER_DMA_Set_Config(MS_BOOL OutputReg)
965 {
966 _uDmaCtrl1.DmaCtrl1.Dest= OutputReg ;
967 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set dest[%d]\n",
968 __func__, __LINE__, OutputReg));
969 }
970
971
HAL_CIPHER_DMA_Set_ReportMode(MS_BOOL RptInDram,MS_PHY u32DramAddr)972 void HAL_CIPHER_DMA_Set_ReportMode(MS_BOOL RptInDram, MS_PHY u32DramAddr)
973 {
974 MS_BOOL bRR = FALSE;
975
976 if (RptInDram)
977 {
978 bRR = TRUE ;
979 _u32ReportAddr = u32DramAddr;
980
981 }
982 else
983 {
984 bRR = FALSE ;
985 _u32ReportAddr = 0;
986
987 }
988
989 _uDmaCtrl1.DmaCtrl1.RR = bRR;
990
991 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set report mode[%d], report address[0x%08x]\n",
992 __func__, __LINE__, bRR, (unsigned int)_u32ReportAddr));
993 }
994
995 // [NOTE] HW Bug, the DMA can't support DRAM Data Swap, Data Error for input and output
HAL_CIPHER_DMA_Set_DataSwap(MS_BOOL InDataSwap,MS_BOOL OutDataSwap,MS_BOOL DInByteSwap,MS_BOOL DOutByteSwap)996 void HAL_CIPHER_DMA_Set_DataSwap(MS_BOOL InDataSwap , MS_BOOL OutDataSwap,
997 MS_BOOL DInByteSwap, MS_BOOL DOutByteSwap )
998 {
999 _uDmaCtrl1.DmaCtrl1.CIS = InDataSwap ;
1000 _uDmaCtrl1.DmaCtrl1.COS = OutDataSwap ;
1001 //_uDmaCtrl1.DmaCtrl1.DODS = DOutBitSwap ;
1002 _uDmaCtrl1.DmaCtrl1.DOBS = DOutByteSwap ;
1003 _uDmaCtrl1.DmaCtrl1.DIBS = DInByteSwap;
1004
1005 }
1006
1007
1008 //void HAL_CIPHER_DMA_Set_Algo(CipherAlgo algo , CipherMode subalgo , Cipher_Residue eRes , Cipher_ShortBlock eSB )
HAL_CIPHER_DMA_Set_Algo(DRV_CIPHER_ALGO stAlgo)1009 void HAL_CIPHER_DMA_Set_Algo(DRV_CIPHER_ALGO stAlgo)
1010 {
1011 HAL_CIPHER_ALGO algo;
1012 HAL_CIPHER_MODE subalgo;
1013 HAL_CIPHER_RESIDUE eRes;
1014 HAL_CIPHER_SHORTBLOCK eSB;
1015
1016 if(_uDmaCtrl1.DmaCtrl1.CaVid == E_CIPHER_CAVID1)
1017 {
1018 algo = (HAL_CIPHER_ALGO)stAlgo.eMainAlgo;
1019 subalgo = (HAL_CIPHER_MODE)stAlgo.eSubAlgo;
1020
1021 // For OTPHASH in E_CIPHER_CAVID1
1022 if(stAlgo.eSubAlgo == E_CIPHER_SUB_OTPHASH)
1023 subalgo = E_DMA_MODE_OTPHASH;
1024 }
1025 else
1026 {
1027 algo = _HAL_CIPHER_TransMainAlgo(stAlgo.eMainAlgo);
1028 subalgo = _HAL_CIPHER_TransSubAlgo(stAlgo.eSubAlgo);
1029 }
1030
1031 eRes = _HAL_CIPHER_TransResAlgo(stAlgo.eResAlgo);
1032 eSB = _HAL_CIPHER_TransSBAlgo(stAlgo.eSBAlgo);
1033
1034 _uDmaCtrl0.DmaCtrl0.Algo= algo ;
1035 _uDmaCtrl0.DmaCtrl0.SubAlgo= subalgo ;
1036 _uDmaCtrl0.DmaCtrl0.Residue = eRes ;
1037 _uDmaCtrl0.DmaCtrl0.SB = eSB ;
1038
1039 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set algorithm, MAIN[%d], SUB[%d], RES[%d], SB[%d]\n",
1040 __func__, __LINE__, algo, subalgo, eRes, eSB));
1041 }
1042
HAL_CIPHER_DMA_Set_OTPHash(MS_U32 u32CurrentRound,MS_U32 u32OTPHashRound)1043 void HAL_CIPHER_DMA_Set_OTPHash(MS_U32 u32CurrentRound, MS_U32 u32OTPHashRound)
1044 {
1045 _uDmaCtrl3.DmaCtrl3.AP = 0;
1046 _uDmaCtrl3.DmaCtrl3.IK = 0;
1047 // First OTPHASH enable IK, other disable IK
1048 if(u32CurrentRound == 0)
1049 {
1050 _uDmaCtrl3.DmaCtrl3.IK = 1;
1051 }
1052 // Final OTPHASH enable AP, other disable AP
1053 if(u32CurrentRound == u32OTPHashRound)
1054 {
1055 _uDmaCtrl3.DmaCtrl3.AP = 1;
1056 }
1057
1058 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set OTPHASH, AP[%d], IK[%d]\n",
1059 __func__, __LINE__, _uDmaCtrl3.DmaCtrl3.AP, _uDmaCtrl3.DmaCtrl3.IK));
1060 }
1061
HAL_CIPHER_DMA_WriteCMDQ(MS_U32 u32Cmd)1062 void HAL_CIPHER_DMA_WriteCMDQ(MS_U32 u32Cmd)
1063 {
1064 WRITE_CMDQ(u32Cmd) ;
1065 }
1066
HAL_CIPHER_DMA_GetData(MS_U8 * u8Data)1067 void HAL_CIPHER_DMA_GetData(MS_U8 *u8Data)
1068 {
1069
1070 MS_U32 tmp ;
1071
1072 // [Note] for u8Data is not always 4 bytes alignment.
1073 tmp = REG32(&_AESDMACtrl->Dma_Out[0]);
1074 u8Data[0] = (tmp >> 0) & 0xFF ;
1075 u8Data[1] = (tmp >> 8) & 0xFF ;
1076 u8Data[2] = (tmp >> 16) & 0xFF ;
1077 u8Data[3] = (tmp >> 24) & 0xFF ;
1078
1079 tmp = REG32(&_AESDMACtrl->Dma_Out[1]);
1080 u8Data[4] = (tmp >> 0) & 0xFF ;
1081 u8Data[5] = (tmp >> 8) & 0xFF ;
1082 u8Data[6] = (tmp >> 16) & 0xFF ;
1083 u8Data[7] = (tmp >> 24) & 0xFF ;
1084
1085 tmp = REG32(&_AESDMACtrl->Dma_Out[2]);
1086 u8Data[8] = (tmp >> 0) & 0xFF ;
1087 u8Data[9] = (tmp >> 8) & 0xFF ;
1088 u8Data[10] = (tmp >> 16) & 0xFF ;
1089 u8Data[11] = (tmp >> 24) & 0xFF ;
1090
1091 tmp = REG32(&_AESDMACtrl->Dma_Out[3]);
1092 u8Data[12] = (tmp >> 0) & 0xFF ;
1093 u8Data[13] = (tmp >> 8) & 0xFF ;
1094 u8Data[14] = (tmp >> 16) & 0xFF ;
1095 u8Data[15] = (tmp >> 24) & 0xFF ;
1096
1097 }
1098
HAL_CIPHER_DMA_GetRpt(MS_U32 * DmaRpt)1099 void HAL_CIPHER_DMA_GetRpt(MS_U32 *DmaRpt)
1100 {
1101 MS_U32 i ;
1102
1103 for (i = 0 ; i < DMA_RPT_REG_SIZE ; i++)
1104 {
1105 DmaRpt[i] = REG32(&_AESDMACtrl->Dma_Reportp[i]);
1106 }
1107 }
1108
HAL_CIPHER_DMA_Start(MS_BOOL Decrypt,HAL_CIPHER_INTMODE IntMode,MS_BOOL bWaitCmdQ,MS_U16 u16CmdID)1109 MS_BOOL HAL_CIPHER_DMA_Start(MS_BOOL Decrypt, HAL_CIPHER_INTMODE IntMode, MS_BOOL bWaitCmdQ, MS_U16 u16CmdID)
1110 {
1111 MS_U32 u32SpareCnt = 0 , CmdLen = 0 ;
1112
1113 _uDmaCtrl0.DmaCtrl0.OVT = FALSE ;
1114
1115 //Set Thread Id
1116 _uDmaCtrl1.DmaCtrl1.TID = u16CmdID ;
1117
1118 _uDmaCtrl1.DmaCtrl1.IntM = IntMode ;
1119
1120 CmdLen = _HAL_CIPHER_GetCmdLen(E_CIPHER_TYPE_DMA);
1121
1122 _uDmaCtrl0.DmaCtrl0.CL = CmdLen & CMD_LEN_MASK ;
1123 _uDmaCtrl0.DmaCtrl0.CMD = ((Decrypt?0x3:0x2) & 0xF);
1124
1125 _uDmaCtrl2.DmaCtrl2.NS = 0;
1126 _uDmaCtrl1.DmaCtrl1.NL = CMD_NEW_LINE;
1127
1128 //Parser patch
1129 if(TRUE == _uDmaCtrl2.DmaCtrl2.HP)
1130 {
1131 MS_U32 u32Tmp = 0;
1132 u32Tmp = _AESDMACtrl->Dma_Ctrl[1];
1133 u32Tmp |= REG_PARSER_LG_PATH_EN;
1134 _AESDMACtrl->Dma_Ctrl[1] = u32Tmp;
1135 }
1136
1137 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613
1138 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar
1139
1140
1141 if(_uDmaCtrl1.DmaCtrl1.SD == CMD_DMA_DATA_DRAM)
1142 {
1143 if(_HAL_CIPHER_TransMIUAddr(&_u32DmaInAddr) == FALSE)
1144 {
1145 return FALSE;
1146 }
1147 }
1148
1149 if(_uDmaCtrl1.DmaCtrl1.Dest == CMD_DMA_OUTPUT_DRAM)
1150 {
1151 if(_HAL_CIPHER_TransMIUAddr(&_u32DmaOut_StartAddr) == FALSE)
1152 {
1153 return FALSE;
1154 }
1155 if(_HAL_CIPHER_TransMIUAddr(&_u32DmaOut_EndAddr) == FALSE)
1156 {
1157 return FALSE;
1158 }
1159 }
1160
1161 DMA_RETRY:
1162 // [HW] Hardware will check Current spare count first, and others read spare count will be zero!
1163 u32SpareCnt = REG32(&_AESDMACtrl->SpareCnt) ;
1164
1165 if (u32SpareCnt > CmdLen)
1166 {
1167 u32SpareCnt -= CmdLen ;
1168
1169 WRITE_CMDQ( (_uDmaCtrl0.u32DmaCtrl0)) ;
1170 WRITE_CMDQ( (_uDmaCtrl1.u32DmaCtrl1)) ;
1171 WRITE_CMDQ( (_uDmaCtrl2.u32DmaCtrl2)) ;
1172 WRITE_CMDQ( (_uDmaCtrl3.u32DmaCtrl3)) ;
1173
1174 WRITE_CMDQ((MS_U32)_u32DmaInAddr) ;
1175 WRITE_CMDQ(_u32DmaInNum) ;
1176 WRITE_CMDQ((MS_U32)_u32DmaOut_StartAddr);
1177 WRITE_CMDQ((MS_U32)_u32DmaOut_EndAddr);
1178
1179 if (_uDmaCtrl1.DmaCtrl1.RR == TRUE )
1180 {
1181 WRITE_CMDQ((MS_U32)_u32ReportAddr);
1182 }
1183
1184 // DMA Initial Vector from CmdQ
1185 if (_uDmaCtrl0.DmaCtrl0.DIV == TRUE )
1186 {
1187 #if 0
1188 WRITE_CMDQ(_pu8IV[15]<<24 |_pu8IV[14]<<16 | _pu8IV[13]<<8 | _pu8IV[12]);
1189 WRITE_CMDQ(_pu8IV[11]<<24 |_pu8IV[10]<<16 | _pu8IV[ 9]<<8 | _pu8IV[ 8]);
1190 WRITE_CMDQ(_pu8IV[ 3]<<24 |_pu8IV[ 2]<<16 | _pu8IV[ 1]<<8 | _pu8IV[ 0]);
1191 WRITE_CMDQ(_pu8IV[ 7]<<24 |_pu8IV[ 6]<<16 | _pu8IV[ 5]<<8 | _pu8IV[ 4]);
1192 #else
1193 WRITE_CMDQ(_pu8IV[ 0]<<24 |_pu8IV[ 1]<<16 | _pu8IV[ 2]<<8 | _pu8IV[ 3]);
1194 WRITE_CMDQ(_pu8IV[ 4]<<24 |_pu8IV[ 5]<<16 | _pu8IV[ 6]<<8 | _pu8IV[ 7]);
1195 WRITE_CMDQ(_pu8IV[ 8]<<24 |_pu8IV[ 9]<<16 | _pu8IV[10]<<8 | _pu8IV[11]);
1196 WRITE_CMDQ(_pu8IV[12]<<24 |_pu8IV[13]<<16 | _pu8IV[14]<<8 | _pu8IV[15]);
1197 #endif
1198 }
1199
1200 // DMA Data from CmdQ
1201 if (_uDmaCtrl1.DmaCtrl1.SD == CMD_DMA_DATA_REG )
1202 {
1203 #if 0
1204 WRITE_CMDQ(_pu8Data[15]<<24 |_pu8Data[14]<<16 | _pu8Data[13]<<8 | _pu8Data[12]);
1205 WRITE_CMDQ(_pu8Data[11]<<24 |_pu8Data[10]<<16 | _pu8Data[ 9]<<8 | _pu8Data[ 8]);
1206 WRITE_CMDQ(_pu8Data[ 7]<<24 |_pu8Data[ 6]<<16 | _pu8Data[ 5]<<8 | _pu8Data[ 4]);
1207 WRITE_CMDQ(_pu8Data[ 3]<<24 |_pu8Data[ 2]<<16 | _pu8Data[ 1]<<8 | _pu8Data[ 0]);
1208 #else
1209 WRITE_CMDQ(_pu8Data[ 0]<<24 |_pu8Data[ 1]<<16 | _pu8Data[ 2]<<8 | _pu8Data[ 3]);
1210 WRITE_CMDQ(_pu8Data[ 4]<<24 |_pu8Data[ 5]<<16 | _pu8Data[ 6]<<8 | _pu8Data[ 7]);
1211 WRITE_CMDQ(_pu8Data[ 8]<<24 |_pu8Data[ 9]<<16 | _pu8Data[10]<<8 | _pu8Data[11]);
1212 WRITE_CMDQ(_pu8Data[12]<<24 |_pu8Data[13]<<16 | _pu8Data[14]<<8 | _pu8Data[15]);
1213 #endif
1214 }
1215
1216 // DMA Key from CmdQ
1217 if (_uDmaCtrl0.DmaCtrl0.DK == TRUE )
1218 {
1219 #if 0
1220 WRITE_CMDQ(_pu8CipherKey[15]<<24 |_pu8CipherKey[14]<<16 | _pu8CipherKey[13]<<8 | _pu8CipherKey[12]);
1221 WRITE_CMDQ(_pu8CipherKey[11]<<24 |_pu8CipherKey[10]<<16 | _pu8CipherKey[ 9]<<8 | _pu8CipherKey[ 8]);
1222 WRITE_CMDQ(_pu8CipherKey[ 7]<<24 |_pu8CipherKey[ 6]<<16 | _pu8CipherKey[ 5]<<8 | _pu8CipherKey[ 4]);
1223 WRITE_CMDQ(_pu8CipherKey[ 3]<<24 |_pu8CipherKey[ 2]<<16 | _pu8CipherKey[ 1]<<8 | _pu8CipherKey[ 0]);
1224 #else
1225 WRITE_CMDQ(_pu8CipherKey[ 0]<<24 |_pu8CipherKey[ 1]<<16 | _pu8CipherKey[ 2]<<8 | _pu8CipherKey[ 3]);
1226 WRITE_CMDQ(_pu8CipherKey[ 4]<<24 |_pu8CipherKey[ 5]<<16 | _pu8CipherKey[ 6]<<8 | _pu8CipherKey[ 7]);
1227 WRITE_CMDQ(_pu8CipherKey[ 8]<<24 |_pu8CipherKey[ 9]<<16 | _pu8CipherKey[10]<<8 | _pu8CipherKey[11]);
1228 WRITE_CMDQ(_pu8CipherKey[12]<<24 |_pu8CipherKey[13]<<16 | _pu8CipherKey[14]<<8 | _pu8CipherKey[15]);
1229 #endif
1230 }
1231
1232 // PID for HW parser
1233 if (_uDmaCtrl2.DmaCtrl2.HP == TRUE )
1234 {
1235 WRITE_CMDQ(_pu8PID0[ 0]<<27 |_pu8PID0[ 1]<<19 | _pu8PID1[ 0]<<14 | _pu8PID1[ 1]<<6);
1236
1237 }
1238
1239 if (_uDmaCtrl3.DmaCtrl3.DIV2 == TRUE )
1240 {
1241 WRITE_CMDQ(_pu8IV2[ 0]<<24 |_pu8IV2[ 1]<<16 | _pu8IV2[ 2]<<8 | _pu8IV2[ 3]);
1242 WRITE_CMDQ(_pu8IV2[ 4]<<24 |_pu8IV2[ 5]<<16 | _pu8IV2[ 6]<<8 | _pu8IV2[ 7]);
1243 WRITE_CMDQ(_pu8IV2[ 8]<<24 |_pu8IV2[ 9]<<16 | _pu8IV2[10]<<8 | _pu8IV2[11]);
1244 WRITE_CMDQ(_pu8IV2[12]<<24 |_pu8IV2[13]<<16 | _pu8IV2[14]<<8 | _pu8IV2[15]);
1245 }
1246
1247 if (_uDmaCtrl3.DmaCtrl3.DK2 == TRUE )
1248 {
1249 WRITE_CMDQ(_pu8CipherKey2[ 0]<<24 |_pu8CipherKey2[ 1]<<16 | _pu8CipherKey2[ 2]<<8 | _pu8CipherKey2[ 3]);
1250 WRITE_CMDQ(_pu8CipherKey2[ 4]<<24 |_pu8CipherKey2[ 5]<<16 | _pu8CipherKey2[ 6]<<8 | _pu8CipherKey2[ 7]);
1251 WRITE_CMDQ(_pu8CipherKey2[ 8]<<24 |_pu8CipherKey2[ 9]<<16 | _pu8CipherKey2[10]<<8 | _pu8CipherKey2[11]);
1252 WRITE_CMDQ(_pu8CipherKey2[12]<<24 |_pu8CipherKey2[13]<<16 | _pu8CipherKey2[14]<<8 | _pu8CipherKey2[15]);
1253 }
1254
1255 // [HW] Hardware will check Current spare count != Write back Spare count to start operation.
1256 REG32(&_AESDMACtrl->SpareCnt) = u32SpareCnt ;
1257 return TRUE ;
1258
1259 }
1260 else
1261 {
1262 // [HW] Check Current spare count == Write back Spare count to start wait cmd
1263 REG32(&_AESDMACtrl->SpareCnt) = u32SpareCnt ;
1264 if (bWaitCmdQ)
1265 {
1266 // Retry until CMDQ avaliable
1267 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]DMA retry!\n",__func__, __LINE__));
1268 goto DMA_RETRY;
1269 }
1270 else
1271 {
1272 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]DMA Fail!\n",__func__, __LINE__));
1273 // Return Fail, Command abort
1274 return FALSE ;
1275 }
1276 }
1277 //DMA_FAIL:
1278
1279 }
1280
HAL_CIPHER_OTPHash_Start(HAL_CIPHER_INTMODE IntMode,MS_BOOL bWaitCmdQ,MS_U16 u16CmdID)1281 MS_BOOL HAL_CIPHER_OTPHash_Start(HAL_CIPHER_INTMODE IntMode, MS_BOOL bWaitCmdQ, MS_U16 u16CmdID)
1282 {
1283 MS_U32 u32SpareCnt = 0 , CmdLen = 0 ;
1284
1285 _uDmaCtrl0.DmaCtrl0.OVT = FALSE ;
1286
1287 //Set Thread Id
1288 _uDmaCtrl1.DmaCtrl1.TID = u16CmdID ;
1289
1290 _uDmaCtrl1.DmaCtrl1.IntM = IntMode ;
1291
1292 _uDmaCtrl1.DmaCtrl1.NL = CMD_NEW_LINE;
1293
1294 CmdLen = _HAL_CIPHER_GetCmdLen(E_CIPHER_TYPE_OTPHASH);
1295
1296 _uDmaCtrl0.DmaCtrl0.CL = CmdLen & CMD_LEN_MASK ;
1297 _uDmaCtrl0.DmaCtrl0.CMD = CMD_DMA_ENCRYPT;
1298
1299 _uDmaCtrl2.DmaCtrl2.NS = 0;
1300
1301 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613
1302 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar
1303
1304 DMA_RETRY:
1305 // [HW] Hardware will check Current spare count first, and others read spare count will be zero!
1306 u32SpareCnt = REG32(&_AESDMACtrl->SpareCnt) ;
1307
1308 if (u32SpareCnt > CmdLen)
1309 {
1310 u32SpareCnt -= CmdLen ;
1311
1312 WRITE_CMDQ( (_uDmaCtrl0.u32DmaCtrl0)) ;
1313 WRITE_CMDQ( (_uDmaCtrl1.u32DmaCtrl1)) ;
1314 WRITE_CMDQ( (_uDmaCtrl2.u32DmaCtrl2)) ;
1315 WRITE_CMDQ( (_uDmaCtrl3.u32DmaCtrl3)) ;
1316
1317 WRITE_CMDQ((MS_U32)_u32DmaInAddr) ;
1318 WRITE_CMDQ(_u32DmaInNum) ;
1319 WRITE_CMDQ((MS_U32)_u32DmaOut_StartAddr);
1320 WRITE_CMDQ((MS_U32)_u32DmaOut_EndAddr);
1321
1322 if(_uDmaCtrl3.DmaCtrl3.AP == TRUE && _uDmaCtrl3.DmaCtrl3.IK == FALSE)
1323 {
1324 WRITE_CMDQ(_u32OTPHashLengthPadding);
1325 }
1326
1327 if (_uDmaCtrl1.DmaCtrl1.RR == TRUE )
1328 {
1329 WRITE_CMDQ((MS_U32)_u32ReportAddr);
1330 }
1331
1332 // [HW] Hardware will check Current spare count != Write back Spare count to start operation.
1333 REG32(&_AESDMACtrl->SpareCnt) = u32SpareCnt ;
1334 return TRUE ;
1335 }
1336 else
1337 {
1338 // [HW] Check Current spare count == Write back Spare count to start wait cmd
1339 REG32(&_AESDMACtrl->SpareCnt) = u32SpareCnt ;
1340 if (bWaitCmdQ)
1341 {
1342 // Retry until CMDQ avaliable
1343 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]DMA retry!\n",__func__, __LINE__));
1344 goto DMA_RETRY;
1345 }
1346 else
1347 {
1348 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]DMA Fail!\n",__func__, __LINE__));
1349 // Return Fail, Command abort
1350 return FALSE ;
1351 }
1352 }
1353
1354 }
1355
HAL_CIPHER_DMA_CmdDone(MS_U32 u32CmdID,MS_U32 * u32Ret)1356 MS_BOOL HAL_CIPHER_DMA_CmdDone(MS_U32 u32CmdID, MS_U32 *u32Ret)
1357 {
1358 MS_U32 u32ExcTmp = 0;
1359 MS_U32 u32Rpt = REG32(&_AESDMACtrl->Dma_Reportp[0]) ;
1360 MS_U32 u32RptId = u32Rpt & REG_CIPHER_RPT_THREAD_MSK;
1361
1362 if(u32RptId == u32CmdID)
1363 {
1364 u32ExcTmp = (MS_U32) REG32(&_AESDMACtrl->Dma_Ctrl[REG_EXCEPT_FLAG]);
1365 *u32Ret = u32ExcTmp;
1366 }
1367 else
1368 {
1369 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]DMA Cmd[%u] Not done!ReportId[%u]\n",
1370 __func__, __LINE__, u32CmdID, u32RptId));
1371 return FALSE;
1372 }
1373
1374 return TRUE;
1375
1376 }
1377
HAL_CIPHER_GetException(MS_U32 * pu32ExcFlag)1378 void HAL_CIPHER_GetException(MS_U32 *pu32ExcFlag)
1379 {
1380 MS_U32 u32ExcTmp = (MS_U32) REG32(&_AESDMACtrl->Dma_Ctrl[REG_EXCEPT_FLAG]);
1381 *pu32ExcFlag = u32ExcTmp;
1382 }
1383
HAL_CIPHER_ReadException(MS_U32 u32ExcTmp)1384 MS_U32 HAL_CIPHER_ReadException(MS_U32 u32ExcTmp)
1385 {
1386 MS_U32 i = 0;
1387 MS_U32 u32ExcOut = 0;
1388
1389 for(i = 0;i<CRYPTODMA_DEBUG_SIZE;i++) //check each error flag
1390 {
1391 if((u32ExcTmp & (1 << i)) >> i)
1392 {
1393 switch(i)
1394 {
1395 case E_CIPHER_NDS_Region_fail:
1396 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_NDS_Region_fail\n", __func__, __LINE__));
1397 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1398 break;
1399 case E_CIPHER_NDS_keyoff:
1400 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_NDS_keyoff\n", __func__, __LINE__));
1401 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1402 break;
1403 case E_CIPHER_sha_write_scr:
1404 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_sha_write_scr\n", __func__, __LINE__));
1405 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1406 break;
1407 case E_CIPHER_sha_read_scr:
1408 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_sha_read_scr\n", __func__, __LINE__));
1409 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1410 break;
1411 case E_CIPHER_sha_error_flag:
1412 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_sha_error_flag\n", __func__, __LINE__));
1413 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1414 break;
1415 case E_CIPHER_except_read_scr:
1416 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_read_scr\n", __func__, __LINE__));
1417 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1418 break;
1419 case E_CIPHER_except_key:
1420 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_key\n", __func__, __LINE__));
1421 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1422 break;
1423 case E_CIPHER_except_CAVid:
1424 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_CAVid\n", __func__, __LINE__));
1425 u32ExcOut |= HAL_CIPHER_EXCEPT_CAVID;
1426 break;
1427 case E_CIPHER_except_des:
1428 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_des\n", __func__, __LINE__));
1429 u32ExcOut |= HAL_CIPHER_EXCEPT_ALGO;
1430 break;
1431 case E_CIPHER_except_NDS:
1432 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_NDS\n", __func__, __LINE__));
1433 u32ExcOut |= HAL_CIPHER_EXCEPT_ALGO;
1434 break;
1435 case E_CIPHER_except_chain:
1436 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_chain\n", __func__, __LINE__));
1437 u32ExcOut |= HAL_CIPHER_EXCEPT_ALGO;
1438 break;
1439 case E_CIPHER_except_algo:
1440 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_algo\n", __func__, __LINE__));
1441 u32ExcOut |= HAL_CIPHER_EXCEPT_ALGO;
1442 break;
1443 case E_CIPHER_except_key_HID:
1444 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_key_HID\n", __func__, __LINE__));
1445 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1446 break;
1447 case E_CIPHER_except_key_cbc_mac:
1448 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_key_cbc_mac\n", __func__, __LINE__));
1449 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1450 break;
1451 case E_CIPHER_except_file_dqmem:
1452 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_file_dqmem\n", __func__, __LINE__));
1453 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1454 break;
1455 case E_CIPHER_except_hash_dqmem:
1456 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_hash_dqmem\n", __func__, __LINE__));
1457 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1458 break;
1459 case E_CIPHER_disable_masterkey0:
1460 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_masterkey0\n", __func__, __LINE__));
1461 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1462 break;
1463 case E_CIPHER_disable_masterkey1:
1464 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_masterkey1\n", __func__, __LINE__));
1465 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1466 break;
1467 case E_CIPHER_disable_cck:
1468 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_cck\n", __func__, __LINE__));
1469 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1470 break;
1471 case E_CIPHER_disable_reg_key_0:
1472 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_reg_key_0\n", __func__, __LINE__));
1473 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1474 break;
1475 case E_CIPHER_disable_reg_key_1:
1476 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_reg_key_1\n", __func__, __LINE__));
1477 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1478 break;
1479 case E_CIPHER_disable_reg_key_2:
1480 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_reg_key_2\n", __func__, __LINE__));
1481 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1482 break;
1483 case E_CIPHER_disable_reg_key_3:
1484 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_reg_key_3\n", __func__, __LINE__));
1485 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1486 break;
1487 case E_CIPHER_dma_forbid_qmem2dram:
1488 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_dma_forbid_qmem2dram\n", __func__, __LINE__));
1489 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1490 break;
1491 case E_CIPHER_dma_forbid_cryptodma_keyslot_qmem:
1492 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_dma_forbid_cryptodma_keyslot_qmem\n", __func__, __LINE__));
1493 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1494 break;
1495 case E_CIPHER_sha_forbid_qmem2dram:
1496 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_sha_forbid_qmem2dram\n", __func__, __LINE__));
1497 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1498 break;
1499 case E_CIPHER_sha_forbid_cryptodma_keyslot_qmem:
1500 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_sha_forbid_cryptodma_keyslot_qmem\n", __func__, __LINE__));
1501 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1502 break;
1503 case E_CIPHER_tdes_key_error:
1504 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_tdes_key_error\n", __func__, __LINE__));
1505 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1506 break;
1507 case E_CIPHER_write_address_error:
1508 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_write_address_error\n", __func__, __LINE__));
1509 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1510 break;
1511 case E_CIPHER_except_str:
1512 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_str\n", __func__, __LINE__));
1513 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1514 break;
1515 case E_CIPHER_except_sha_str:
1516 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_sha_str\n", __func__, __LINE__));
1517 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1518 break;
1519 default:
1520 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] Unknown error \n", __func__, __LINE__));
1521 break;
1522
1523 }
1524
1525 }
1526
1527 }
1528
1529 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]Exception out [0x%08x]\n", __func__, __LINE__, (unsigned int)u32ExcOut));
1530
1531 return u32ExcOut;
1532
1533 }
1534
HAL_CIPHER_IntEnable(void)1535 void HAL_CIPHER_IntEnable(void)
1536 {
1537 MS_U16 u16MaskTmp = REG16(_u32RegBase + REG_HST0_FIQ_MASK_63_48);
1538 u16MaskTmp &= REG_HTS0_FIQ_MASK_CRYPTODMA; //FIQ 56 in reg_hst0_fiq_mask_63_48_
1539 REG16(_u32RegBase + REG_HST0_FIQ_MASK_63_48) = u16MaskTmp;
1540 }
1541
HAL_CIPHER_IntClear(void)1542 void HAL_CIPHER_IntClear(void)
1543 {
1544 REG16(_u32RegBase + REG_HST0_FIQ_STATUS_63_48) = REG_HTS0_FIQ_CRYPTODMA; //set 1 to clear interrupt
1545 }
1546
1547 //======================================================================
1548
HAL_CIPHER_Hash_GetRpt(MS_U32 * HashRpt,MS_U32 u32Size)1549 void HAL_CIPHER_Hash_GetRpt(MS_U32 *HashRpt, MS_U32 u32Size)
1550 {
1551 MS_U32 i , tmp;
1552
1553 if (u32Size < HASH_RPT_REG_SIZE )
1554 {
1555 tmp = u32Size ;
1556 }
1557 else
1558 {
1559 tmp = HASH_RPT_REG_SIZE ;
1560 }
1561
1562 for (i = 0 ; i < tmp ; i++)
1563 {
1564 HashRpt[i] = REG32(&_AESDMACtrl->Hash_Reportp[i]);
1565 }
1566 }
1567
HAL_CIPHER_Hash_Set_Config(CIPHER_HASH_ALGO algo,MS_BOOL bAutoPad,MS_BOOL bInv16)1568 void HAL_CIPHER_Hash_Set_Config(CIPHER_HASH_ALGO algo , MS_BOOL bAutoPad , MS_BOOL bInv16)
1569 {
1570 HAL_CIPHER_HASHMODE hash_mode = E_HASH_SHA1;
1571 hash_mode = _HAL_CIPHER_TransHASHAlgo(algo);
1572
1573 _uHashCtrl0.HashCtrl0.HashSel = hash_mode ;
1574 _uHashCtrl0.HashCtrl0.AutoPad = bAutoPad ;
1575 _uHashCtrl0.HashCtrl0.Inv16 = bInv16; //Inverse the byte order per 16 bytes
1576
1577 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH Mode[%d], AutoPad[%d], Inverse16[%d]!\n",
1578 __func__, __LINE__, hash_mode, bAutoPad, bInv16));
1579 }
1580
HAL_CIPHER_Hash_Set_ReportMode(MS_BOOL RptInDram,MS_U32 u32DramAddr)1581 void HAL_CIPHER_Hash_Set_ReportMode(MS_BOOL RptInDram, MS_U32 u32DramAddr)
1582 {
1583 if (RptInDram)
1584 {
1585 _u32ReportAddr = u32DramAddr;
1586
1587 }
1588 else
1589 {
1590 _u32ReportAddr = 0;
1591 }
1592
1593 _uHashCtrl2.HashCtrl2.RR = RptInDram ;
1594
1595 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set report mode[%d], report address[0x%08x]\n",
1596 __func__, __LINE__, RptInDram, (unsigned int)_u32ReportAddr));
1597 }
1598
HAL_CIPHER_Hash_SetHMACKey(DRV_CIPHER_HMAC_KEY stHMACKey,CIPHER_HMAC_KPAD eKpad,MS_BOOL bClear)1599 MS_BOOL HAL_CIPHER_Hash_SetHMACKey(DRV_CIPHER_HMAC_KEY stHMACKey, CIPHER_HMAC_KPAD eKpad, MS_BOOL bClear)
1600 {
1601 MS_BOOL bHMAC = TRUE;
1602 MS_U32 u32HMACKeySel = 0;
1603 MS_U32 u32Kpad = CMD_HASH_IKP;
1604 HAL_CIPHER_KEYSRC KeySrc;
1605
1606 //Check Key Source, Index
1607 if(((E_CIPHER_KSRC_KL == stHMACKey.eKeySrc) && (stHMACKey.u8KeyIdx > HAL_CRYPTODMA_DMA_KEY_SLOT-1)) ||
1608 ((E_CIPHER_KSRC_OTP == stHMACKey.eKeySrc) && (stHMACKey.u8KeyIdx > HAL_CRYPTODMA_OTP_SCK_NUM-1)))
1609 {
1610 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Invalid KeySrc[%d], Index[%d]\n",
1611 __func__, __LINE__, stHMACKey.eKeySrc, stHMACKey.u8KeyIdx));
1612 return FALSE;
1613 }
1614
1615 //DRV to HAL Type transfer
1616 KeySrc = _HAL_CIPHER_TransKey(stHMACKey.eKeySrc, stHMACKey.u8KeyIdx);
1617
1618 switch(KeySrc)
1619 {
1620 case E_DMA_KSEL_REGKEY:
1621 u32HMACKeySel = CMD_HMAC_KSEL_HK;
1622 break;
1623 case E_DMA_KSEL_STRN:
1624 u32HMACKeySel = CMD_HMAC_KSEL_STRN;
1625 break;
1626 case E_DMA_KSEL_MK0:
1627 u32HMACKeySel = CMD_HMAC_KSEL_MK0;
1628 break;
1629 case E_DMA_KSEL_MK1:
1630 u32HMACKeySel = CMD_HMAC_KSEL_MK1;
1631 break;
1632 case E_DMA_KSEL_CCCK:
1633 u32HMACKeySel = CMD_HMAC_KSEL_CCCK;
1634 break;
1635 case E_DMA_KSEL_SK0:
1636 u32HMACKeySel = CMD_HMAC_KSEL_SK0;
1637 break;
1638 case E_DMA_KSEL_SK1:
1639 u32HMACKeySel = CMD_HMAC_KSEL_SK1;
1640 break;
1641 case E_DMA_KSEL_SK2:
1642 u32HMACKeySel = CMD_HMAC_KSEL_SK2;
1643 break;
1644 case E_DMA_KSEL_SK3:
1645 u32HMACKeySel = CMD_HMAC_KSEL_SK3;
1646 break;
1647 default:
1648 u32HMACKeySel = 0;
1649 break;
1650 }
1651
1652 if(eKpad == E_CIPHER_HMAC_OKPAD)
1653 {
1654 u32Kpad = CMD_HASH_OKP;
1655 }
1656
1657 if(bClear)
1658 {
1659 u32HMACKeySel += (MS_U32)CMD_HMAC_KSEL_CLR_SK;
1660 }
1661
1662 if(KeySrc == E_DMA_KSEL_REGKEY)
1663 {
1664 //command mode
1665 if (0 != stHMACKey.pu8KeyData)
1666 {
1667 memset(_pu8HashHMACHostKey, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX );
1668 memcpy(_pu8HashHMACHostKey, (MS_U8 *)stHMACKey.pu8KeyData , stHMACKey.u8KeyLen);
1669 _uHashCtrl0.HashCtrl0.DK = CMD_HMAC_KSEL_DIR_HK;
1670 }
1671 else
1672 {
1673 memset(_pu8HashHMACHostKey, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX );
1674 bHMAC = FALSE;
1675 }
1676 }
1677
1678 _uHashCtrl0.HashCtrl0.HMAC = bHMAC;
1679 _uHashCtrl0.HashCtrl0.KPAD = u32Kpad;
1680 _uHashCtrl0.HashCtrl0.HMAC_KeySel = u32HMACKeySel;
1681
1682 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HMAC[%d], HMAC KPAD[%u] HMAC KeySel[%u]!\n",
1683 __func__, __LINE__, bHMAC, u32Kpad, u32HMACKeySel));
1684
1685 return TRUE;
1686 }
1687
HAL_CIPHER_Hash_Set_CaVid(MS_U32 u32CAVid)1688 MS_BOOL HAL_CIPHER_Hash_Set_CaVid(MS_U32 u32CAVid)
1689 {
1690 MS_U32 u32Tmp = u32CAVid;
1691
1692 if(u32Tmp > HAL_CRYPTODMA_CAVID_MAX)
1693 {
1694 return FALSE;
1695 }
1696
1697 if(u32Tmp == 0)
1698 {
1699 u32Tmp = _CIPHER_CAVid ;
1700 }
1701 else
1702 {
1703 u32Tmp = u32CAVid;
1704 }
1705
1706 _uHashCtrl1.HashCtrl1.CaVid = u32Tmp;
1707
1708 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set CAVid [0x%x]\n",
1709 __func__, __LINE__, (unsigned int)u32Tmp));
1710
1711 return TRUE;
1712 }
1713
HAL_CIPHER_Hash_Set_IV(MS_U8 * pu8IV,MS_U32 u32IVSize,MS_U32 u32IVSel)1714 MS_BOOL HAL_CIPHER_Hash_Set_IV(MS_U8* pu8IV, MS_U32 u32IVSize ,MS_U32 u32IVSel)
1715 {
1716 // 256 bits for sha256 , 160 bits for sha1
1717 _uHashCtrl0.HashCtrl0.InitHashSel = u32IVSel ;
1718
1719 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH IVSel [%u]\n",
1720 __func__, __LINE__, u32IVSel));
1721
1722 if(u32IVSel == CMD_HASH_IV_CMD)
1723 {
1724 if((pu8IV != NULL) && (u32IVSize > 0))
1725 {
1726 memset(_pu8HashIV, 0x0, HASH_CMD_IV_SIZE);
1727 memcpy(_pu8HashIV, (MS_U8 *)pu8IV , u32IVSize);
1728
1729 return TRUE;
1730 }
1731 else
1732 {
1733 return FALSE;
1734 }
1735 }
1736
1737 return TRUE;
1738 }
1739
1740
HAL_CIPHER_Hash_Set_InitWordCnt(HAL_CIPHER_IWCTYPE eIWCType,MS_U32 u32StartBytes)1741 MS_BOOL HAL_CIPHER_Hash_Set_InitWordCnt(HAL_CIPHER_IWCTYPE eIWCType, MS_U32 u32StartBytes)
1742 {
1743 MS_U32 u32IWCType = 0;
1744 MS_U32 u32IWC = 0;
1745 MS_U32 Rpt[2] = {0};
1746
1747 if(eIWCType == E_CIPHER_HASH_IWC_PRV) //Init Word Count from report
1748 {
1749 u32IWCType = CMD_HASH_IWC_RPT;
1750 HAL_CIPHER_Hash_GetRpt(Rpt, 2); //For debug
1751 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set IWC from report is [%u]\n",
1752 __func__, __LINE__, Rpt[1]>>2));
1753 }
1754 else
1755 {
1756 u32IWCType = CMD_HASH_IWC_CMDQ;
1757 if((u32StartBytes % HASH_MANUAL_BLOCK_SIZE) != 0)
1758 {
1759 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Error:Init word count is 64 bytes alignment!\n",
1760 __func__, __LINE__));
1761 return FALSE;
1762 }
1763
1764 if(u32StartBytes != 0)
1765 {
1766 u32IWC = u32StartBytes/4; //Init Word Count
1767 }
1768 else
1769 {
1770 u32IWC = 0;
1771 }
1772 }
1773
1774 _u32InitWordCnt = u32IWC;
1775 _uHashCtrl0.HashCtrl0.IWC_Sel = u32IWCType;
1776
1777 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set IWC type[%u], IWC[%u]\n",
1778 __func__, __LINE__, u32IWCType, _u32InitWordCnt));
1779
1780 return TRUE;
1781 }
1782
HAL_CIPHER_Hash_Set_MsgSrcFrom(CIPHER_MEM_TYPE eMemType,MS_U32 * u32HashSrc)1783 MS_BOOL HAL_CIPHER_Hash_Set_MsgSrcFrom(CIPHER_MEM_TYPE eMemType, MS_U32 *u32HashSrc)
1784 {
1785 MS_U32 u32SrcTmp = 0;
1786 switch(eMemType)
1787 {
1788 case E_CIPHER_DRAM:
1789 u32SrcTmp = CMD_HASH_SRC_DRAM;
1790 _u32HashSrcAddr = 0;
1791 break;
1792 case E_CIPHER_DQMEM:
1793 u32SrcTmp = CMD_HASH_SRC_R2;
1794 _u32HashSrcAddr = HAL_CIPHER_BASE_DQMEM;
1795 break;
1796 case E_CIPHER_IQMEM:
1797 u32SrcTmp = CMD_HASH_SRC_R2;
1798 _u32HashSrcAddr = HAL_CIPHER_BASE_IQMEM;
1799 break;
1800 case E_CIPHER_DIRECT:
1801 u32SrcTmp = CMD_HASH_SRC_REG;
1802 _u32HashSrcAddr = 0;
1803 break;
1804 default:
1805 u32SrcTmp = CMD_HASH_SRC_DRAM;
1806 _u32HashSrcAddr = 0;
1807 break;
1808 }
1809
1810 *u32HashSrc = u32SrcTmp;
1811
1812 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH source from [%u]\n",
1813 __func__, __LINE__, u32SrcTmp));
1814
1815 return TRUE;
1816 }
1817
HAL_CIPHER_Hash_Set_OutputDstTo(CIPHER_MEM_TYPE eMemType,MS_U32 * u32HashDst)1818 MS_BOOL HAL_CIPHER_Hash_Set_OutputDstTo(CIPHER_MEM_TYPE eMemType, MS_U32 *u32HashDst)
1819 {
1820 MS_U32 u32DstTmp = 0;
1821 switch(eMemType)
1822 {
1823 case E_CIPHER_DRAM:
1824 u32DstTmp = CMD_HASH_OUTPUT_DRAM;
1825 _u32HashDestAddr = 0;
1826 break;
1827 case E_CIPHER_DQMEM:
1828 u32DstTmp = CMD_HASH_OUTPUT_R2;
1829 _u32HashDestAddr = HAL_CIPHER_BASE_DQMEM;
1830 break;
1831 case E_CIPHER_IQMEM:
1832 u32DstTmp = CMD_HASH_OUTPUT_R2;
1833 _u32HashDestAddr = HAL_CIPHER_BASE_IQMEM;
1834 break;
1835 case E_CIPHER_DIRECT:
1836 u32DstTmp = CMD_HASH_OUTPUT_RPT;
1837 _u32HashDestAddr = 0;
1838 break;
1839 default:
1840 u32DstTmp = CMD_HASH_OUTPUT_RPT;
1841 _u32HashDestAddr = 0;
1842 break;
1843 }
1844
1845 *u32HashDst = u32DstTmp;
1846 _uHashCtrl0.HashCtrl0.Dest = u32DstTmp;
1847 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH destination[%u]\n",
1848 __func__, __LINE__, u32DstTmp));
1849
1850 return TRUE;
1851 }
1852
HAL_CIPHER_Hash_Set_OuputAddr(MS_PHY u32OutputPAddr,MS_U32 u32DstSel)1853 MS_BOOL HAL_CIPHER_Hash_Set_OuputAddr(MS_PHY u32OutputPAddr, MS_U32 u32DstSel)
1854 {
1855 if ((CMD_HASH_OUTPUT_DRAM == u32DstSel) || (CMD_HASH_OUTPUT_R2 == u32DstSel))
1856 {
1857 if (0 != u32OutputPAddr)
1858 {
1859 _u32HashDestAddr += u32OutputPAddr;
1860 }
1861 else
1862 {
1863 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Error:Hash output address is NULL\n",__func__, __LINE__));
1864 return FALSE;
1865 }
1866 }
1867 return TRUE;
1868 }
1869
HAL_CIPHER_Hash_SetMsgLength(MS_U32 u32Size)1870 void HAL_CIPHER_Hash_SetMsgLength( MS_U32 u32Size )
1871 {
1872 _u32HashMsgLen = u32Size;
1873
1874 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH message length[%u]\n",
1875 __func__, __LINE__, u32Size));
1876
1877 return ;
1878 }
1879
HAL_CIPHER_Hash_SetHOS(MS_BOOL bHos)1880 void HAL_CIPHER_Hash_SetHOS(MS_BOOL bHos)
1881 {
1882 _uHashCtrl0.HashCtrl0.HOS = bHos;
1883
1884 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HOS[%d]\n",
1885 __func__, __LINE__, bHos));
1886
1887 return ;
1888 }
1889
1890
HAL_CIPHER_Hash_SetMsg(MS_PHY u32MsgPAddr,MS_U32 u32Size,MS_U32 u32SrcSel)1891 MS_BOOL HAL_CIPHER_Hash_SetMsg(MS_PHY u32MsgPAddr, MS_U32 u32Size ,MS_U32 u32SrcSel )
1892 {
1893 _uHashCtrl0.HashCtrl0.Src = u32SrcSel;
1894 _u32HashMsgLen = u32Size;
1895
1896 if ((CMD_HASH_SRC_DRAM == u32SrcSel) || (CMD_HASH_SRC_R2 == u32SrcSel))
1897 {
1898 if (0 != u32MsgPAddr)
1899 {
1900 _u32HashSrcAddr += u32MsgPAddr;
1901 }
1902 else
1903 {
1904 return FALSE;
1905 }
1906 }
1907 else if (CMD_HASH_SRC_REG == u32SrcSel)
1908 {
1909 if((u32MsgPAddr == 0) || (u32Size > HASH_CMD_MSG_SIZE))
1910 {
1911 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Error:Set HASH direct message size[%u] over 64 bytes\n",
1912 __func__, __LINE__, u32Size));
1913 return FALSE;
1914 }
1915 _u32HashSrcAddr = 0;
1916 memset(_pu8HashMsg , 0x0 , HASH_CMD_MSG_SIZE);
1917 memcpy(_pu8HashMsg , (MS_U8 *)(MsOS_PA2KSEG1(u32MsgPAddr)) , u32Size);
1918 }
1919
1920 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH message source[%u], size[%u]\n",
1921 __func__, __LINE__, u32SrcSel, _u32HashMsgLen));
1922
1923 return TRUE;
1924
1925 }
1926
1927
HAL_CIPHER_Hash_Start(HAL_CIPHER_INTMODE IntMode,MS_BOOL bWaitCmdQ,MS_BOOL bRst,MS_U16 u16CmdID)1928 MS_BOOL HAL_CIPHER_Hash_Start(HAL_CIPHER_INTMODE IntMode , MS_BOOL bWaitCmdQ , MS_BOOL bRst, MS_U16 u16CmdID)
1929 {
1930 MS_U32 u32SpareCnt = 0 , CmdLen = 0 , i = 0 ;
1931 MS_U32 u32Tmp;
1932
1933 _uHashCtrl1.HashCtrl1.TID = u16CmdID;
1934 _uHashCtrl0.HashCtrl0.CMD = CMD_HASH_START_RR ;
1935
1936 _uHashCtrl0.HashCtrl0.OVT = FALSE ;
1937 _uHashCtrl0.HashCtrl0.IntM = IntMode ;
1938
1939 CmdLen = _HAL_CIPHER_GetCmdLen(E_CIPHER_TYPE_SHA);
1940
1941 _uHashCtrl0.HashCtrl0.CL = CmdLen & CMD_LEN_MASK ;
1942
1943 _uHashCtrl1.HashCtrl1.NS = 0;
1944
1945 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613
1946 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar
1947
1948
1949 SHA_RETRY:
1950 u32SpareCnt = REG32(&_AESDMACtrl->SpareCnt) ;
1951
1952 if (u32SpareCnt > CmdLen)
1953 {
1954 u32SpareCnt -= CmdLen ;
1955
1956 WRITE_CMDQ( (_uHashCtrl0.u32HashCtrl0)) ;
1957
1958 WRITE_CMDQ( (_uHashCtrl1.u32HashCtrl1)) ;
1959
1960 WRITE_CMDQ( (_uHashCtrl2.u32HashCtrl2)) ;
1961
1962 WRITE_CMDQ(_u32HashMsgLen) ;
1963
1964 //SRC
1965 if (_uHashCtrl0.HashCtrl0.Src != CMD_HASH_SRC_REG)
1966 {
1967 WRITE_CMDQ(_u32HashSrcAddr) ;
1968 }
1969
1970 //RR address
1971 if (_uHashCtrl2.HashCtrl2.RR == TRUE)
1972 {
1973 WRITE_CMDQ(_u32ReportAddr) ;
1974 }
1975
1976 // IWC
1977 if (CMD_HASH_IWC_CMDQ == _uHashCtrl0.HashCtrl0.IWC_Sel)
1978 {
1979 WRITE_CMDQ(_u32InitWordCnt);
1980 }
1981 else
1982 {
1983 REG32(&_AESDMACtrl->Hash_Reportp[1]) = _u32InitWordCnt;
1984 }
1985
1986 // DST
1987 if ((CMD_HASH_OUTPUT_DRAM == _uHashCtrl0.HashCtrl0.Dest) || (_uHashCtrl0.HashCtrl0.Dest == CMD_HASH_OUTPUT_R2 ))
1988 {
1989 WRITE_CMDQ(_u32HashDestAddr);
1990 }
1991
1992 // HASH Initial Vector from CmdQ
1993 if (CMD_HASH_IV_CMD == _uHashCtrl0.HashCtrl0.InitHashSel )
1994 {
1995 for ( i = 0 ; i < (HASH_CMD_IV_SIZE/4) ; i ++ )
1996 {
1997 u32Tmp = ((_pu8HashIV[4*i+0]<<24)|(_pu8HashIV[4*i+1]<<16)|(_pu8HashIV[4*i+2]<<8)|(_pu8HashIV[4*i+3]) );
1998
1999 WRITE_CMDQ(u32Tmp);
2000 }
2001 }
2002
2003 // HASH Data from CmdQ
2004 if ( CMD_HASH_SRC_REG == _uHashCtrl0.HashCtrl0.Src )
2005 {
2006 for ( i = 0 ; i < (HASH_CMD_MSG_SIZE/4) ; i ++ )
2007 {
2008 u32Tmp = ( (_pu8HashMsg[i*4+0]<<24)
2009 |(_pu8HashMsg[i*4+1]<<16)
2010 |(_pu8HashMsg[i*4+2]<<8)
2011 |(_pu8HashMsg[i*4+3]<<0)
2012 );
2013
2014 WRITE_CMDQ(u32Tmp);
2015 }
2016 }
2017
2018 if((CMD_HMAC_KSEL_HK == _uHashCtrl0.HashCtrl0.HMAC_KeySel) && (CMD_HMAC_KSEL_DIR_HK == _uHashCtrl0.HashCtrl0.DK))
2019 {
2020 for ( i = 0 ; i < (HASH_CMD_HMAC_HOSTKEY_SIZE/4) ; i ++ )
2021 {
2022 u32Tmp = ((_pu8HashHMACHostKey[4*i+0]<<24)|(_pu8HashHMACHostKey[4*i+1]<<16)|(_pu8HashHMACHostKey[4*i+2]<<8)|(_pu8HashHMACHostKey[4*i+3]) );
2023
2024 WRITE_CMDQ(u32Tmp);
2025 }
2026 }
2027 // [HW] Hardware will check Current spare count != Write back Spare count to start operation.
2028 REG32(&_AESDMACtrl->SpareCnt) = u32SpareCnt ;
2029 return TRUE ;
2030
2031 }
2032 else
2033 {
2034 // [HW] Check Current spare count == Write back Spare count to start wait cmd
2035 REG32(&_AESDMACtrl->SpareCnt) = u32SpareCnt ;
2036
2037 if (bWaitCmdQ)
2038 {
2039 // Retry until CMDQ avaliable
2040 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]HASH cmd retry!\n",
2041 __func__, __LINE__));
2042 goto SHA_RETRY;
2043 }
2044 else
2045 {
2046 // Return Fail, Command abort
2047 return FALSE ;
2048 }
2049 }
2050 }
2051
HAL_CIPHER_Hash_CmdDone(MS_U32 u32CmdID,MS_U32 * u32Ret)2052 MS_BOOL HAL_CIPHER_Hash_CmdDone(MS_U32 u32CmdID, MS_U32 *u32Ret)
2053 {
2054 MS_U32 u32ExcTmp = 0;
2055
2056 MS_U32 u32Tmp = REG32(&_AESDMACtrl->Hash_Reportp[0]) ;
2057 MS_U32 u32RptId = u32Tmp & REG_CIPHER_RPT_THREAD_MSK;
2058
2059 if(u32RptId == u32CmdID)
2060 {
2061 u32ExcTmp = (MS_U32)REG32(&_AESDMACtrl->Dma_Ctrl[REG_EXCEPT_FLAG]);
2062 *u32Ret = u32ExcTmp;
2063 }
2064 else
2065 {
2066 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]HASH Cmd[%u] Not done!ReportId[%u]\n",
2067 __func__, __LINE__, u32CmdID, u32RptId));
2068 return FALSE;
2069 }
2070
2071 return TRUE;
2072 }
2073
HAL_CIPHER_Hash_ExceptFilter(MS_U32 * pu32Exception,CIPHER_KEY_SRC eKeySrc,MS_U8 u8KeyIdx)2074 void HAL_CIPHER_Hash_ExceptFilter(MS_U32 *pu32Exception, CIPHER_KEY_SRC eKeySrc, MS_U8 u8KeyIdx)
2075 {
2076 //Because CryptoDMA will check every key slot usage for HMAC
2077 //We need to filter out the correct key exception
2078 MS_U32 u32ExcTmp = 0;
2079 HAL_CIPHER_KEYSRC KeySrc = 0;
2080 MS_U32 i = 0;
2081
2082 u32ExcTmp = *pu32Exception;
2083
2084 //DRV to HAL Type transfer
2085 KeySrc = _HAL_CIPHER_TransKey(eKeySrc, u8KeyIdx);
2086
2087 //Only check HMAC key exception
2088 for(i = E_CIPHER_disable_masterkey0;i<=E_CIPHER_disable_reg_key_3;i++) //check each error flag
2089 {
2090 if((u32ExcTmp & (1 << i)) >> i)
2091 {
2092 switch(i)
2093 {
2094 case E_CIPHER_disable_masterkey0:
2095 if(E_DMA_KSEL_MK0 != KeySrc)
2096 u32ExcTmp &= (~(1 << E_CIPHER_disable_masterkey0));
2097 break;
2098
2099 case E_CIPHER_disable_masterkey1:
2100 if(E_DMA_KSEL_MK1 != KeySrc)
2101 u32ExcTmp &= (~(1 << E_CIPHER_disable_masterkey1));
2102 break;
2103
2104 case E_CIPHER_disable_cck:
2105 if(E_DMA_KSEL_CCCK != KeySrc)
2106 u32ExcTmp &= (~(1 << E_CIPHER_disable_cck));
2107 break;
2108
2109 case E_CIPHER_disable_reg_key_0:
2110 if(E_DMA_KSEL_SK0 != KeySrc)
2111 u32ExcTmp &= (~(1 << E_CIPHER_disable_reg_key_0));
2112 break;
2113
2114 case E_CIPHER_disable_reg_key_1:
2115 if(E_DMA_KSEL_SK1 != KeySrc)
2116 u32ExcTmp &= (~(1 << E_CIPHER_disable_reg_key_1));
2117 break;
2118
2119 case E_CIPHER_disable_reg_key_2:
2120 if(E_DMA_KSEL_SK2 != KeySrc)
2121 u32ExcTmp &= (~(1 << E_CIPHER_disable_reg_key_2));
2122 break;
2123
2124 case E_CIPHER_disable_reg_key_3:
2125 if(E_DMA_KSEL_SK3 != KeySrc)
2126 u32ExcTmp &= (~(1 << E_CIPHER_disable_reg_key_3));
2127 break;
2128
2129 default:
2130 break;
2131 }
2132 }
2133 }
2134
2135 *pu32Exception = u32ExcTmp;
2136
2137 return;
2138
2139 }
2140 // =====================================
2141 // Parser function implementation
2142 // =====================================
HAL_CIPHER_PARSER_Set_Mode(CIPHER_PARSER_MODE eMode)2143 void HAL_CIPHER_PARSER_Set_Mode(CIPHER_PARSER_MODE eMode)
2144
2145 {
2146 HAL_CIPHER_PARSER_HDCPMODE eHDCPMode = 0;
2147 HAL_CIPHER_PARSER_TSMODE eTSMode = 0;
2148 HAL_CIPHER_PARSER_PKTMODE ePKTMode = 0;
2149 HAL_CIPHER_PARSER_AUTOMODE eAutoMode = 0;
2150 HAL_CIPHER_PARSER_ITMODE eITMode = 0;
2151 HAL_CIPHER_PARSER_CLEARMODE eClearMode = 0;
2152
2153 switch(eMode)
2154 {
2155 case E_CIPHER_PARSER_TS_PKT192:
2156 eHDCPMode = E_PARSER_HDCPMODE_NONE;
2157 eTSMode = E_PARSER_TSMODE_TS;
2158 ePKTMode = E_PARSER_PKTMODE_192;
2159 eAutoMode = E_PARSER_AUTOMODE_EN;
2160 eITMode = E_PARSER_ITMODE_EN;
2161 eClearMode = E_PARSER_CLEARMODE_NONE;
2162 break;
2163 case E_CIPHER_PARSER_TS_PKT192_CLEAR:
2164 eHDCPMode = E_PARSER_HDCPMODE_NONE;
2165 eTSMode = E_PARSER_TSMODE_TS;
2166 ePKTMode = E_PARSER_PKTMODE_192;
2167 eAutoMode = E_PARSER_AUTOMODE_EN;
2168 eITMode = E_PARSER_ITMODE_EN;
2169 eClearMode = E_PARSER_CLEARMODE_EN;
2170 break;
2171 case E_CIPHER_PARSER_TS_PKT188:
2172 eHDCPMode = E_PARSER_HDCPMODE_NONE;
2173 eTSMode = E_PARSER_TSMODE_TS;
2174 ePKTMode = E_PARSER_PKTMODE_188;
2175 eAutoMode = E_PARSER_AUTOMODE_EN;
2176 eITMode = E_PARSER_ITMODE_EN;
2177 eClearMode = E_PARSER_CLEARMODE_NONE;
2178 break;
2179 case E_CIPHER_PARSER_TS_PKT188_CLEAR:
2180 eHDCPMode = E_PARSER_HDCPMODE_NONE;
2181 eTSMode = E_PARSER_TSMODE_TS;
2182 ePKTMode = E_PARSER_PKTMODE_188;
2183 eAutoMode = E_PARSER_AUTOMODE_EN;
2184 eITMode = E_PARSER_ITMODE_EN;
2185 eClearMode = E_PARSER_CLEARMODE_EN;
2186 break;
2187 case E_CIPHER_PARSER_HDCP20_PKT192:
2188 eHDCPMode = E_PARSER_HDCPMODE_HDCP20;
2189 eTSMode = E_PARSER_TSMODE_PES;
2190 ePKTMode = E_PARSER_PKTMODE_192;
2191 eAutoMode = E_PARSER_AUTOMODE_EN;
2192 eITMode = E_PARSER_ITMODE_EN;
2193 eClearMode = E_PARSER_CLEARMODE_NONE;
2194 break;
2195 case E_CIPHER_PARSER_HDCP20_PKT192_CLEAR:
2196 eHDCPMode = E_PARSER_HDCPMODE_HDCP20;
2197 eTSMode = E_PARSER_TSMODE_PES;
2198 ePKTMode = E_PARSER_PKTMODE_192;
2199 eAutoMode = E_PARSER_AUTOMODE_EN;
2200 eITMode = E_PARSER_ITMODE_NONE;
2201 eClearMode = E_PARSER_CLEARMODE_EN;
2202 break;
2203 case E_CIPHER_PARSER_HDCP20_PKT188:
2204 eHDCPMode = E_PARSER_HDCPMODE_HDCP20;
2205 eTSMode = E_PARSER_TSMODE_PES;
2206 ePKTMode = E_PARSER_PKTMODE_188;
2207 eAutoMode = E_PARSER_AUTOMODE_EN;
2208 eITMode = E_PARSER_ITMODE_EN;
2209 eClearMode = E_PARSER_CLEARMODE_NONE;
2210 break;
2211 case E_CIPHER_PARSER_HDCP20_PKT188_CLEAR:
2212 eHDCPMode = E_PARSER_HDCPMODE_HDCP20;
2213 eTSMode = E_PARSER_TSMODE_PES;
2214 ePKTMode = E_PARSER_PKTMODE_188;
2215 eAutoMode = E_PARSER_AUTOMODE_EN;
2216 eITMode = E_PARSER_ITMODE_NONE;
2217 eClearMode = E_PARSER_CLEARMODE_EN;
2218 break;
2219 default:
2220 printf("Error: Not suport parser mode!\n");
2221 break;
2222 }
2223
2224 _uDmaCtrl2.DmaCtrl2.HP = TRUE;
2225 _uDmaCtrl2.DmaCtrl2.HDCP = eHDCPMode;
2226 _uDmaCtrl2.DmaCtrl2.TS = eTSMode;
2227 _uDmaCtrl2.DmaCtrl2.P192 = ePKTMode;
2228 _uDmaCtrl2.DmaCtrl2.AT = eAutoMode;
2229 _uDmaCtrl2.DmaCtrl2.IT = eITMode;
2230 _uDmaCtrl2.DmaCtrl2.CR = eClearMode;
2231
2232 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Parser config:HDCP[%d], TS[%d], P192[%d], AT[%d], IT[%d], ClearMode[%d]\n",
2233 __func__, __LINE__, eHDCPMode, eTSMode, ePKTMode, eAutoMode, eITMode, eClearMode));
2234
2235
2236 }
2237
HAL_CIPHER_PARSER_Set_MaskSCB(MS_BOOL bEnable)2238 void HAL_CIPHER_PARSER_Set_MaskSCB(MS_BOOL bEnable)
2239 {
2240 _uDmaCtrl2.DmaCtrl2.TsSbMk = bEnable;
2241 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Enable MaskSCB[%d]!\n",
2242 __func__, __LINE__, bEnable));
2243 }
2244
HAL_CIPHER_PARSER_Set_SCB(CIPHER_PARSER_SCB eSCB)2245 void HAL_CIPHER_PARSER_Set_SCB(CIPHER_PARSER_SCB eSCB)
2246 {
2247 MS_U8 u8SCB = 0;
2248
2249 if(eSCB == E_CIPHER_PARSER_SCB_10)
2250 {
2251 u8SCB = CMD_PARSER_SCB10;
2252 }
2253 else if(eSCB == E_CIPHER_PARSER_SCB_11)
2254 {
2255 u8SCB = CMD_PARSER_SCB11;
2256 }
2257 else
2258 {
2259 u8SCB = 0;
2260 }
2261 _uDmaCtrl2.DmaCtrl2.TsSbPn = u8SCB;
2262 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set SCB[%u]!\n",
2263 __func__, __LINE__, u8SCB));
2264 }
2265
HAL_CIPHER_PARSER_Set_ForceSCB(MS_BOOL bInsert,CIPHER_PARSER_SCB eSCB)2266 void HAL_CIPHER_PARSER_Set_ForceSCB(MS_BOOL bInsert, CIPHER_PARSER_SCB eSCB)
2267 {
2268 MS_U8 u8SCB = 0;
2269
2270 if(bInsert)
2271 {
2272 if(eSCB == E_CIPHER_PARSER_SCB_10)
2273 {
2274 u8SCB = CMD_PARSER_SCB10;
2275 }
2276 else if(eSCB == E_CIPHER_PARSER_SCB_11)
2277 {
2278 u8SCB = CMD_PARSER_SCB11;
2279 }
2280 else
2281 {
2282 u8SCB = 0;
2283 }
2284 }
2285
2286 _uDmaCtrl2.DmaCtrl2.InSb = bInsert;
2287 _uDmaCtrl2.DmaCtrl2.TsInSb = u8SCB;
2288
2289 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set Insert Enable[%d], SCB[%u]!\n",
2290 __func__, __LINE__, bInsert, u8SCB));
2291
2292 }
2293
HAL_CIPHER_PARSER_Rmv_SCB(MS_BOOL bRemove)2294 void HAL_CIPHER_PARSER_Rmv_SCB(MS_BOOL bRemove)
2295 {
2296 _uDmaCtrl2.DmaCtrl2.RmSb = bRemove;
2297 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Remove SCB[%d]!\n",
2298 __func__, __LINE__, bRemove));
2299 }
2300
HAL_CIPHER_PARSER_BypassPid(MS_BOOL bEnable)2301 void HAL_CIPHER_PARSER_BypassPid(MS_BOOL bEnable)
2302 {
2303 _uDmaCtrl2.DmaCtrl2.BPS = bEnable;
2304 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Bypass PID[%d]!\n",
2305 __func__, __LINE__, bEnable));
2306 }
2307
HAL_CIPHER_PARSER_Set_PID(CIPHER_PARSER_PID stPID)2308 void HAL_CIPHER_PARSER_Set_PID(CIPHER_PARSER_PID stPID)
2309 {
2310 if(stPID.pu8PID0 != NULL)
2311 {
2312 memset(_pu8PID0, 0x0 , PID_SIZE );
2313 memcpy(_pu8PID0, stPID.pu8PID0, PID_SIZE);
2314 }
2315 else
2316 {
2317 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set PID0 NULL!\n",
2318 __func__, __LINE__));
2319 }
2320
2321 if(stPID.pu8PID1 != NULL)
2322 {
2323 memset(_pu8PID1, 0x0 , PID_SIZE );
2324 memcpy(_pu8PID1, stPID.pu8PID1 , PID_SIZE);
2325 }
2326 else
2327 {
2328 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set PID1 NULL!\n",
2329 __func__, __LINE__));
2330 }
2331 }
2332
HAL_CIPHER_PARSER_Set_Key2(DRV_CIPHER_KEY stKey)2333 MS_BOOL HAL_CIPHER_PARSER_Set_Key2(DRV_CIPHER_KEY stKey)
2334 {
2335 HAL_CIPHER_KEYSRC KeySrc = 0;
2336 HAL_CIPHER_ALGO algo = 0;
2337 MS_BOOL bDK2 = FALSE;
2338 MS_BOOL bTwoKey = FALSE;
2339
2340 algo = _uDmaCtrl0.DmaCtrl0.Algo;
2341
2342 if(E_DMA_ALGO_NONE == algo)
2343 {
2344 //No key
2345 bDK2 = FALSE;
2346 bTwoKey = FALSE;
2347 memset(_pu8CipherKey2, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX);
2348 goto SET_KEY_DONE;
2349 }
2350
2351 //Check Key Source, Index
2352 if(((E_CIPHER_KSRC_KL == stKey.eKeySrc) && (stKey.u8KeyIdx > HAL_CRYPTODMA_DMA_KEY_SLOT-1)) ||
2353 ((E_CIPHER_KSRC_OTP == stKey.eKeySrc) && (stKey.u8KeyIdx > HAL_CRYPTODMA_OTP_SCK_NUM-1)))
2354 {
2355 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Invalid KeySrc[%d], Index[%d]\n",
2356 __func__, __LINE__, stKey.eKeySrc, stKey.u8KeyIdx));
2357 return FALSE;
2358 }
2359
2360 //DRV to HAL Type transfer
2361 KeySrc = _HAL_CIPHER_TransKey(stKey.eKeySrc, stKey.u8KeyIdx);
2362
2363 // key from CPU
2364 if(E_DMA_KSEL_REGKEY == KeySrc)
2365 {
2366 if ((0 != stKey.pu8KeyData) && (stKey.u8KeyLen != 0) && (stKey.u8KeyLen <= HAL_CRYPTODMA_KEYLEN_MAX) )
2367 {
2368 memset(_pu8CipherKey2, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX );
2369 memcpy(_pu8CipherKey2, (MS_U8 *)stKey.pu8KeyData , stKey.u8KeyLen);
2370 bDK2 = TRUE;
2371 KeySrc = 0;
2372 }
2373 else
2374 {
2375 return FALSE ;
2376 }
2377 }
2378 else if(E_DMA_KSEL_CAIP == KeySrc)
2379 {
2380 bDK2 = FALSE ;
2381 KeySrc = 0 ;
2382 }
2383 else// key from KL or OTP
2384 {
2385 bDK2 = FALSE;
2386 }
2387
2388 bTwoKey = TRUE;
2389
2390 SET_KEY_DONE:
2391
2392 _uDmaCtrl3.DmaCtrl3.DK2 = bDK2;
2393 _uDmaCtrl3.DmaCtrl3.KeySel2 = KeySrc;
2394 _uDmaCtrl2.DmaCtrl2.TK = bTwoKey;
2395
2396 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set DK2[%d], KeySel2[%d]\n",
2397 __func__, __LINE__, bDK2, KeySrc));
2398
2399 return TRUE ;
2400
2401 }
2402
HAL_CIPHER_PARSER_Set_IV2(MS_U8 * pu8IV2,MS_U8 u8IVLen)2403 MS_BOOL HAL_CIPHER_PARSER_Set_IV2(MS_U8 *pu8IV2, MS_U8 u8IVLen)
2404 {
2405 if((pu8IV2 != NULL) && (u8IVLen != 0))
2406 {
2407 memset(_pu8IV2, 0, CIPHER_KEY_SIZE);
2408 memcpy(_pu8IV2, pu8IV2, u8IVLen);
2409 _uDmaCtrl3.DmaCtrl3.DIV2 = TRUE;
2410
2411 return TRUE;
2412 }
2413 else
2414 {
2415 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set IV2 NULL!\n",
2416 __func__, __LINE__));
2417 return FALSE;
2418 }
2419
2420 }
2421
HAL_CIPHER_PARSER_Set_ClearStartMode(MS_BOOL bEnable)2422 void HAL_CIPHER_PARSER_Set_ClearStartMode(MS_BOOL bEnable)
2423 {
2424 _uDmaCtrl3.DmaCtrl3.CRS = bEnable;
2425 }
2426
2427 // =====================================
2428 // MISC function implementation
2429 // =====================================
HAL_CIPHER_Misc_Random(MS_U8 * pu8Buf,MS_U32 u32Size)2430 MS_BOOL HAL_CIPHER_Misc_Random(MS_U8 *pu8Buf, MS_U32 u32Size)
2431 {
2432 MS_U16 u16TRN = 0;
2433 MS_U16 u16PreTRN = 0;
2434 MS_U32 u32Count = 0;
2435
2436 if(NULL == pu8Buf || 0 == u32Size)
2437 return FALSE;
2438
2439 #if defined (MCU_AEON)
2440
2441 while(u32Count < u32Size)
2442 {
2443 do{
2444 do{
2445 //Toggle random number bit
2446 REG32(_u32RegBase+REG_RNG_TRNG_SCPU) ^= REG_RNG_TRNG_ACK_SCPU;
2447 }//Read random number valid
2448 while( !(REG32(_u32RegBase+REG_RNG_TRNG_SCPU) & REG_RNG_TRNG_VALID_SCPU_MASK) );
2449 }
2450 while( (u16TRN = (REG32(_u32RegBase+REG_RNG_TRNG_SCPU) & REG_RNG_TRNG_OUT_SCPU_MASK))==u16PreTRN );
2451 u16PreTRN = u16TRN;
2452
2453 if(0 == ((u32Size - u32Count)%2UL))
2454 {
2455 *(pu8Buf+u32Count) = u16TRN & 0xFFUL;
2456 *(pu8Buf+u32Count+1) = (u16TRN & 0xFF00UL) >> 8;
2457 u32Count += 2;
2458 }
2459 else
2460 {
2461 *(pu8Buf+u32Count) = u16TRN & 0xFFUL;
2462 u32Count += 1;
2463 }
2464 }
2465
2466 #else
2467
2468 while(u32Count < u32Size)
2469 {
2470 do{
2471 do{
2472 //Toggle random number bit
2473 REG32(_u32RegBase+REG_RNG_TRNG_ACPU) ^= REG_RNG_TRNG_ACK_ACPU;
2474 }//Read random number valid
2475 while( !(REG32(_u32RegBase+REG_RNG_TRNG_ACPU) & REG_RNG_TRNG_VALID_ACPU_MASK) );
2476 }
2477 while( (u16TRN = (REG32(_u32RegBase+REG_RNG_TRNG_ACPU) & REG_RNG_TRNG_OUT_ACPU_MASK))==u16PreTRN );
2478 u16PreTRN = u16TRN;
2479
2480 if(0 == ((u32Size - u32Count)%2UL))
2481 {
2482 *(pu8Buf+u32Count) = u16TRN & 0xFFUL;
2483 *(pu8Buf+u32Count+1) = (u16TRN & 0xFF00UL) >> 8;
2484 u32Count += 2;
2485 }
2486 else
2487 {
2488 *(pu8Buf+u32Count) = u16TRN & 0xFFUL;
2489 u32Count += 1;
2490 }
2491 }
2492 #endif
2493
2494 return TRUE;
2495 }
2496
2497
2498