1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2006-2008 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // (¡§MStar Confidential Information¡¨) by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 #include "MsCommon.h"
100 #include "MsTypes.h"
101 #include "regSEAL.h"
102 #include "halSEAL.h"
103 #include "drvSEAL.h"
104 #include "halCHIP.h"
105
106 //-------------------------------------------------------------------------------------------------
107 // Driver Compiler Options
108 //-------------------------------------------------------------------------------------------------
109
110
111 //-------------------------------------------------------------------------------------------------
112 // Local Defines
113 //-------------------------------------------------------------------------------------------------
114 #define HAL_SEAL_DBG(x) //x
115 #define HAL_SEAL_ERR(x, args...) {printf(x, ##args);}\
116
117 //Non PM IP group
118 #define SEAL_NON_PM_GROUP0 \
119 E_SEAL_RIU_DBG_PROT_NONPM, \
120 E_SEAL_FUART1_PROT_NONPM, \
121 E_SEAL_URDMA1_PROT_NONPM, \
122 E_SEAL_VD_MHEG5_PROT_NONPM, \
123 E_SEAL_MAU1_PROT_NONPM, \
124 E_SEAL_HIREG_PROT_NONPM, \
125 E_SEAL_POR_STATUS_PROT_NONPM, \
126 E_SEAL_INTR_CPUINT_PROT_NONPM, \
127 E_SEAL_MAILBOX_PQ_PROT_NONPM, \
128 E_SEAL_MIU2_PROT_NONPM, \
129 E_SEAL_USB0_PROT_NONPM, \
130 E_SEAL_USB1_PROT_NONPM, \
131 E_SEAL_UPLL0_PROT_NONPM, \
132 E_SEAL_BDMA_CH0_PROT_NONPM, \
133 E_SEAL_BDMA_CH1_PROT_NONPM, \
134 E_SEAL_UART0_PROT_NONPM
135
136 #define SEAL_NON_PM_GROUP1 \
137 E_SEAL_CLKGEN2_PROT_NONPM, \
138 E_SEAL_CLKGEN0_PROT_NONPM, \
139 E_SEAL_DSCRMB_PROT_NONPM, \
140 E_SEAL_UHC1_PROT_NONPM, \
141 E_SEAL_SPI_PRE_ARB_PROT_NONPM, \
142 E_SEAL_MVD_PROT_NONPM, \
143 E_SEAL_MIU_PROT_NONPM, \
144 E_SEAL_MVOPSUB_PROT_NONPM, \
145 E_SEAL_MVOP_PROT_NONPM, \
146 E_SEAL_TSP0_PROT_NONPM, \
147 E_SEAL_TSP1_PROT_NONPM, \
148 E_SEAL_SEMAPH_PROT_NONPM, \
149 E_SEAL_MAU0_PROT_NONPM, \
150 E_SEAL_L3_AXI_PROT_NONPM, \
151 E_SEAL_INTR_CTRL_CPU0_0_PROT_NONPM, \
152 E_SEAL_INTR_CTRL_CPU1_0_PROT_NONPM
153
154 #define SEAL_NON_PM_GROUP2 \
155 E_SEAL_INTR_CTRL_CPU2_0_PROT_NONPM, \
156 E_SEAL_INTR_CTRL_CPU3_0_PROT_NONPM, \
157 E_SEAL_HVD_PROT_NONPM, \
158 E_SEAL_TSP2_PROT_NONPM, \
159 E_SEAL_MCU_ARM_PROT_NONPM, \
160 E_SEAL_CHIP_PROT_NONPM, \
161 E_SEAL_GOP_PROT_NONPM, \
162 E_SEAL_EMAC0_PROT_NONPM, \
163 E_SEAL_EMAC1_PROT_NONPM, \
164 E_SEAL_EMAC2_PROT_NONPM, \
165 E_SEAL_EMAC3_PROT_NONPM, \
166 E_SEAL_UHC0_PROT_NONPM, \
167 E_SEAL_ADC_ATOP_PROT_NONPM, \
168 E_SEAL_ADC_DTOP_PROT_NONPM, \
169 E_SEAL_GE0_PROT_NONPM, \
170 E_SEAL_CHIPGPIO_PROT_NONPM
171
172 #define SEAL_NON_PM_GROUP3 \
173 E_SEAL_VP6_PROT_NONPM, \
174 E_SEAL_LDM_DMA0_PROT_NONPM, \
175 E_SEAL_LDM_DMA1_PROT_NONPM, \
176 E_SEAL_SC0_PROT_NONPM, \
177 E_SEAL_SC1_PROT_NONPM, \
178 E_SEAL_SC2_PROT_NONPM, \
179 E_SEAL_SC3_PROT_NONPM, \
180 E_SEAL_SC4_PROT_NONPM, \
181 E_SEAL_CLKGEN1_PROT_NONPM, \
182 E_SEAL_MAILBOX_PROT_NONPM, \
183 E_SEAL_MIIC_PROT_NONPM, \
184 E_SEAL_VDMCU51_IF_PROT_NONPM, \
185 E_SEAL_DMDMCU51_IF_PROT_NONPM, \
186 E_SEAL_VDMCU51_1_IF_PROT_NONPM, \
187 E_SEAL_URDMA_PROT_NONPM, \
188 E_SEAL_AFEC_PROT_NONPM
189
190 #define SEAL_NON_PM_GROUP4 \
191 E_SEAL_COMB_PROT_NONPM, \
192 E_SEAL_VBI_PROT_NONPM, \
193 E_SEAL_SCM_PROT_NONPM, \
194 E_SEAL_UTMI2_PROT_NONPM, \
195 E_SEAL_PATGEN_PROT_NONPM, \
196 E_SEAL_UTMI1_PROT_NONPM, \
197 E_SEAL_UTMI_PROT_NONPM, \
198 E_SEAL_VE_0_PROT_NONPM, \
199 E_SEAL_REG_PIU_NONPM_PROT_NONPM, \
200 E_SEAL_ADC_ATOPB_PROT_NONPM, \
201 E_SEAL_VE_1_PROT_NONPM, \
202 E_SEAL_VE_2_PROT_NONPM, \
203 E_SEAL_SC_GP1_NONPM, \
204 E_SEAL_CHIPGPIO1_NONPM, \
205 E_SEAL_MPIF_PROT_NONPM, \
206 E_SEAL_GPD_PROT_NONPM
207
208 #define SEAL_NON_PM_GROUP5 \
209 E_SEAL_UART1_PROT_NONPM, \
210 E_SEAL_FUART_PROT_NONPM, \
211 E_SEAL_GE1_PROT_NONPM, \
212 E_SEAL_GPU_NONPM, \
213 E_SEAL_GPU2MIU_MASK_PROT_NONPM, \
214 E_SEAL_TS_SAMPLE_NONPM, \
215 E_SEAL_NR_HSD_PROT_NONPM, \
216 E_SEAL_ANA_MISC2_NONPM, \
217 E_SEAL_ANA_MISC_PROT_NONPM, \
218 E_SEAL_ANA_MISC_GMAC_PROT_NONPM, \
219 E_SEAL_MIU_ATOP_PROT_NONPM, \
220 E_SEAL_NR_PROT_NONPM, \
221 E_SEAL_DI_PROT_NONPM, \
222 E_SEAL_MFE0_PROT_NONPM, \
223 E_SEAL_MFE1_PROT_NONPM, \
224 E_SEAL_ADC_DTOPB_PROT_NONPM
225
226 #define SEAL_NON_PM_GROUP6 \
227 E_SEAL_NFIE0_PROT_NONPM, \
228 E_SEAL_NFIE1_PROT_NONPM, \
229 E_SEAL_NFIE2_PROT_NONPM, \
230 E_SEAL_VIVALDIc_PROT_NONPM, \
231 E_SEAL_VIVALDId_PROT_NONPM, \
232 E_SEAL_MIIC0_PROT_NONPM, \
233 E_SEAL_MIIC1_PROT_NONPM, \
234 E_SEAL_MIIC2_PROT_NONPM, \
235 E_SEAL_MIIC3_PROT_NONPM, \
236 E_SEAL_MOD2_PROT_NONPM, \
237 E_SEAL_CLKGEN_DMD_PROT_NONPM, \
238 E_SEAL_DEMOD_0_PROT_NONPM, \
239 E_SEAL_DEMOD_1_PROT_NONPM, \
240 E_SEAL_DEMOD_2_PROT_NONPM, \
241 E_SEAL_DEMOD_3_PROT_NONPM, \
242 E_SEAL_DEMOD_4_PROT_NONPM
243
244 #define SEAL_NON_PM_GROUP7 \
245 E_SEAL_DEMOD_5_PROT_NONPM, \
246 E_SEAL_DEMOD_6_PROT_NONPM, \
247 E_SEAL_DEMOD_7_PROT_NONPM, \
248 E_SEAL_DMD_ANA_MISC_PROT_NONPM, \
249 E_SEAL_AUR20_PROT_NONPM, \
250 E_SEAL_VIVALDI0_PROT_NONPM, \
251 E_SEAL_VIVALDI1_PROT_NONPM, \
252 E_SEAL_VIVALDI2_PROT_NONPM, \
253 E_SEAL_VIVALDI3_PROT_NONPM, \
254 E_SEAL_VIVALDI4_PROT_NONPM, \
255 E_SEAL_VIVALDI5_PROT_NONPM, \
256 E_SEAL_AU_MAU_NONPM, \
257 E_SEAL_AU_GDMA_NONPM, \
258 E_SEAL_CLKGEN_SC_FE, \
259 E_SEAL_CLKGEN_SC_BE, \
260 E_SEAL_CLKGEN_SC_GP2
261
262 #define SEAL_NON_PM_GROUP8 \
263 E_SEAL_SC_GPLUS, \
264 E_SEAL_USB2_PROT_NONPM, \
265 E_SEAL_USB3_PROT_NONPM, \
266 E_SEAL_UHC2_PROT_NONPM, \
267 E_SEAL_TSO_PROT_NONPM, \
268 E_SEAL_DRM_SECURE_PROT_NONPM, \
269 E_SEAL_DSCRMB2_PROT_NONPM, \
270 E_SEAL_DSCRMB3_PROT_NONPM, \
271 E_SEAL_GPD0_PROT_NONPM, \
272 E_SEAL_GPD1_PROT_NONPM, \
273 E_SEAL_GOP0G_0_PROT_NONPM, \
274 E_SEAL_GOP0G_1_PROT_NONPM, \
275 E_SEAL_GOP0G_ST_PROT_NONPM, \
276 E_SEAL_GOP1G_0_PROT_NONPM, \
277 E_SEAL_GOP1G_1_PROT_NONPM, \
278 E_SEAL_GOP1G_ST_PROT_NONPM
279
280 #define SEAL_NON_PM_GROUP9 \
281 E_SEAL_GOP2G_0_PROT_NONPM, \
282 E_SEAL_GOP2G_1_PROT_NONPM, \
283 E_SEAL_GOP2G_ST_PROT_NONPM, \
284 E_SEAL_GOP3G_0_PROT_NONPM, \
285 E_SEAL_GOP3G_1_PROT_NONPM, \
286 E_SEAL_GOP3G_ST_PROT_NONPM, \
287 E_SEAL_GOPD_PROT_NONPM, \
288 E_SEAL_SDIO0_PROT_NONPM, \
289 E_SEAL_SPARE1_PROT_NONPM, \
290 E_SEAL_SRAM_LDO, \
291 E_SEAL_SPARE3_PROT_NONPM, \
292 E_SEAL_MIU_ARB256_PROT_NONPM, \
293 E_SEAL_OTG0_NONPM, \
294 E_SEAL_OTG1_NONPM, \
295 E_SEAL_OTG2_NONPM, \
296 E_SEAL_OTG3_NONPM
297
298 #define SEAL_NON_PM_GROUP10 \
299 E_SEAL_TZPC_NONPM2_NONPM, \
300 E_SEAL_GOP4G_0_PROT_NONPM, \
301 E_SEAL_MIIC4_PROT_NONPM, \
302 E_SEAL_MIIC5_PROT_NONPM, \
303 E_SEAL_GOP4G_1_PROT_NONPM, \
304 E_SEAL_GOP4G_ST_PROT_NONPM, \
305 E_SEAL_UHC3_PROT_NONPM, \
306 E_SEAL_SDIO1_PROT_NONPM, \
307 E_SEAL_SDIO2_PROT_NONPM, \
308 E_SEAL_SEC_R2_PROT_NONPM, \
309 E_SEAL_SEC_MAU0_PROT_NONPM, \
310 E_SEAL_DSCRMB4_PROT_NONPM, \
311 E_SEAL_MOBF_PROT_NONPM, \
312 E_SEAL_DC_SCL_PROT_NONPM, \
313 E_SEAL_JPD_PROT_NONPM, \
314 E_SEAL_MFDEC_PROT_NONPM
315
316 #define SEAL_NON_PM_GROUP11 \
317 E_SEAL_CMDQ_PROT_NONPM, \
318 E_SEAL_USBBC0_PROT_NONPM, \
319 E_SEAL_USBBC1_PROT_NONPM, \
320 E_SEAL_USBBC2_PROT_NONPM, \
321 E_SEAL_SECURERANGE0_PROT_NONPM, \
322 E_SEAL_SECURERANGE1_PROT_NONPM, \
323 E_SEAL_TZPC_NONPM_PROT_NONPM, \
324 E_SEAL_ONEWAY_PROT_NONPM, \
325 E_SEAL_NFIE3_PROT_NONPM, \
326 E_SEAL_DSCRMB5_PROT_NONPM, \
327 E_SEAL_TSO1_NONPM, \
328 E_SEAL_ZDEC_PROT_NONPM, \
329 E_SEAL_EMMC_PLL_PROT_NONPM, \
330 E_SEAL_MSC_PROT_NONPM, \
331 E_SEAL_MSC1_NONPM, \
332 E_SEAL_PATGEN_CODEC_PROT_NONPM
333
334 #define SEAL_NON_PM_GROUP12 \
335 E_SEAL_PATGEN_VIV_PROT_NONPM, \
336 E_SEAL_PATGEN_CPU_PROT_NONPM, \
337 E_SEAL_PATGEN_GPU_PROT_NONPM, \
338 E_SEAL_PATGEN_DEMOD_PROT_NONPM, \
339 E_SEAL_BAT_PROT_NONPM, \
340 E_SEAL_PATGEN_TSP_PROT_NONPM, \
341 E_SEAL_PATGEN_DVI_PROT_NONPM, \
342 E_SEAL_PATGEN_EVD_PROT_NONPM, \
343 E_SEAL_PATGEN_SC0_PROT_NONPM, \
344 E_SEAL_PATGEN_SC1_PROT_NONPM, \
345 E_SEAL_PATGEN_SC2_PROT_NONPM, \
346 E_SEAL_MIU_BWFLAG_PROT_NONPM, \
347 E_SEAL_MIU_BWFLAG2_PROT_NONPM, \
348 E_SEAL_PAD_MUX_NONPM, \
349 E_SEAL_ROM_CRC_NONPM, \
350 E_SEAL_MIU_ARBB_NONPM
351
352 #define SEAL_NON_PM_GROUP13 \
353 E_SEAL_MIU_ARBB2_NONPM, \
354 E_SEAL_COMB1_PROT_NONPM, \
355 E_SEAL_COMB2_PROT_NONPM, \
356 E_SEAL_COMB3_PROT_NONPM, \
357 E_SEAL_COMB4_PROT_NONPM, \
358 E_SEAL_COMB5_PROT_NONPM, \
359 E_SEAL_DEMOD_8_PROT_NONPM, \
360 E_SEAL_DEMOD_9_PROT_NONPM, \
361 E_SEAL_MIU_DIG_E_PROT_NONPM, \
362 E_SEAL_MIU_DIG_E2_PROT_NONPM, \
363 E_SEAL_MSPI0_PROT_NONPM, \
364 E_SEAL_MSPI1_PROT_NONPM, \
365 E_SEAL_MSPI_MCARD_PROT_NONPM, \
366 E_SEAL_DMD_MCU2_PROT_NONPM, \
367 E_SEAL_VIVALDI6_PROT_NONPM, \
368 E_SEAL_VIVALDI7_PROT_NONPM
369
370 #define SEAL_NON_PM_GROUP14 \
371 E_SEAL_TSP3_PROT_NONPM, \
372 E_SEAL_EVD_NONPM, \
373 E_SEAL_DYN_SCL_PROT_NONPM, \
374 E_SEAL_VP9_TOP_PROT_NONPM, \
375 E_SEAL_GPU_PLL_PROT_NONPM, \
376 E_SEAL_MIU_ARB_SC_NONPM, \
377 E_SEAL_MIU_ARB2_SC_NONPM, \
378 E_SEAL_CODEC_MRQ_PROT_NONPM, \
379 E_SEAL_MIU_ARB_NONPM, \
380 E_SEAL_MIU_ATOP2_PROT_NONPM, \
381 E_SEAL_MIU_ARB2_NONPM, \
382 E_SEAL_GE2_NONPM, \
383 E_SEAL_GE3_NONPM, \
384 E_SEAL_AU_R2_1_NONPM, \
385 E_SEAL_AU_MAU_1_NONPM, \
386 E_SEAL_AU_GDMA_1_NONPM
387
388 #define SEAL_NON_PM_GROUP15 \
389 E_SEAL_VD_EVD_R2_NONPM, \
390 E_SEAL_MAU_EVD_NONPM, \
391 E_SEAL_HIREG_EVD_PROT_NONPM, \
392 E_SEAL_MAU1_LV2_0_NONPM, \
393 E_SEAL_MAU1_LV2_1_NONPM, \
394 E_SEAL_MAU_EVD_LV2_0_NONPM, \
395 E_SEAL_MAU_EVD_LV2_1_NONPM, \
396 E_SEAL_SEC_MAU_LV2_0_NONPM, \
397 E_SEAL_SEC_MAU_LV2_1_NONPM, \
398 E_SEAL_TSP5_NONPM, \
399 E_SEAL_VIVALDI8_PROT_NONPM, \
400 E_SEAL_VIVALDI9_PROT_NONPM, \
401 E_SEAL_VIVALDIa_0_PROT_NONPM, \
402 E_SEAL_VIVALDIa_1_PROT_NONPM, \
403 E_SEAL_VIVALDIa_2_PROT_NONPM, \
404 E_SEAL_VIVALDIa_3_PROT_NONPM
405
406 #define SEAL_NON_PM_GROUP16 \
407 E_SEAL_VIVALDIb_0_PROT_NONPM, \
408 E_SEAL_VIVALDIb_1_PROT_NONPM, \
409 E_SEAL_VIVALDIb_2_PROT_NONPM, \
410 E_SEAL_VIVALDIb_3_PROT_NONPM, \
411 E_SEAL_COMBO_PHY0_P0_PROT_NONPM, \
412 E_SEAL_COMBO_PHY1_P0_PROT_NONPM, \
413 E_SEAL_COMBO_PHY0_P1_PROT_NONPM, \
414 E_SEAL_COMBO_PHY1_P1_PROT_NONPM, \
415 E_SEAL_COMBO_PHY0_P2_PROT_NONPM, \
416 E_SEAL_COMBO_PHY1_P2_PROT_NONPM, \
417 E_SEAL_DVI_DTOP_DUAL_P0_PROT_NONPM, \
418 E_SEAL_DVI_RSV_DUAL_P0_PROT_NONPM, \
419 E_SEAL_HDCP_DUAL_P0_PROT_NONPM, \
420 E_SEAL_DVI_DTOP_DUAL_P1_PROT_NONPM, \
421 E_SEAL_DVI_RSV_DUAL_P1_PROT_NONPM, \
422 E_SEAL_HDCP_DUAL_P1_PROT_NONPM
423
424 #define SEAL_NON_PM_GROUP17 \
425 E_SEAL_DVI_DTOP_DUAL_P2_PROT_NONPM, \
426 E_SEAL_DVI_RSV_DUAL_P2_PROT_NONPM, \
427 E_SEAL_HDCP_DUAL_P2_PROT_NONPM, \
428 E_SEAL_HDMI_DUAL_0_PROT_NONPM, \
429 E_SEAL_HDMI2_DUAL_0_PROT_NONPM, \
430 E_SEAL_HDMI3_DUAL_0_PROT_NONPM, \
431 E_SEAL_HDCPKEY_PROT_NONPM, \
432 E_SEAL_COMBO_GP_TOP_PROT_NONPM, \
433 E_SEAL_SECURE_TZPC_PROT_NONPM, \
434 E_SEAL_CBUS_AUDIO_PROT_NONPM, \
435 E_SEAL_X32_GPUAPB0_PROT_NONPM, \
436 E_SEAL_X32_GPUAPB1_PROT_NONPM, \
437 E_SEAL_X32_GPUAPB2_PROT_NONPM, \
438 E_SEAL_X32_EMAC0_NONPM, \
439 E_SEAL_X32_EMAC1_NONPM, \
440 E_SEAL_X32_EMAC2_NONPM
441
442 #define SEAL_NON_PM_GROUP18 \
443 E_SEAL_SC_EXT_PROT_NONPM, \
444 E_SEAL_MSC_EXT_PROT_NONPM, \
445 E_SEAL_DUMMY, \
446 E_SEAL_DUMMY, \
447 E_SEAL_DUMMY, \
448 E_SEAL_DUMMY, \
449 E_SEAL_DUMMY, \
450 E_SEAL_DUMMY, \
451 E_SEAL_DUMMY, \
452 E_SEAL_DUMMY, \
453 E_SEAL_DUMMY, \
454 E_SEAL_DUMMY, \
455 E_SEAL_DUMMY, \
456 E_SEAL_DUMMY, \
457 E_SEAL_DUMMY, \
458 E_SEAL_DUMMY
459
460 #define SEAL_NON_PM_GROUP19 \
461 E_SEAL_DUMMY, \
462 E_SEAL_DUMMY, \
463 E_SEAL_DUMMY, \
464 E_SEAL_DUMMY, \
465 E_SEAL_DUMMY, \
466 E_SEAL_DUMMY, \
467 E_SEAL_DUMMY, \
468 E_SEAL_DUMMY, \
469 E_SEAL_DUMMY, \
470 E_SEAL_DUMMY, \
471 E_SEAL_DUMMY, \
472 E_SEAL_DUMMY, \
473 E_SEAL_DUMMY, \
474 E_SEAL_DUMMY, \
475 E_SEAL_DUMMY, \
476 E_SEAL_DUMMY
477
478 #define SEAL_NON_PM_GROUP20 \
479 E_SEAL_DUMMY, \
480 E_SEAL_DUMMY, \
481 E_SEAL_DUMMY, \
482 E_SEAL_DUMMY, \
483 E_SEAL_DUMMY, \
484 E_SEAL_DUMMY, \
485 E_SEAL_DUMMY, \
486 E_SEAL_DUMMY, \
487 E_SEAL_DUMMY, \
488 E_SEAL_DUMMY, \
489 E_SEAL_DUMMY, \
490 E_SEAL_DUMMY, \
491 E_SEAL_DUMMY, \
492 E_SEAL_DUMMY, \
493 E_SEAL_DUMMY, \
494 E_SEAL_DUMMY
495
496 #define SEAL_NON_PM_GROUP21 \
497 E_SEAL_DUMMY, \
498 E_SEAL_DUMMY, \
499 E_SEAL_DUMMY, \
500 E_SEAL_DUMMY, \
501 E_SEAL_DUMMY, \
502 E_SEAL_DUMMY, \
503 E_SEAL_DUMMY, \
504 E_SEAL_DUMMY, \
505 E_SEAL_DUMMY, \
506 E_SEAL_DUMMY, \
507 E_SEAL_DUMMY, \
508 E_SEAL_DUMMY, \
509 E_SEAL_DUMMY, \
510 E_SEAL_DUMMY, \
511 E_SEAL_DUMMY, \
512 E_SEAL_DUMMY
513
514 #define SEAL_NON_PM_GROUP22 \
515 E_SEAL_DUMMY, \
516 E_SEAL_DUMMY, \
517 E_SEAL_DUMMY, \
518 E_SEAL_DUMMY, \
519 E_SEAL_DUMMY, \
520 E_SEAL_DUMMY, \
521 E_SEAL_DUMMY, \
522 E_SEAL_DUMMY, \
523 E_SEAL_DUMMY, \
524 E_SEAL_DUMMY, \
525 E_SEAL_DUMMY, \
526 E_SEAL_DUMMY, \
527 E_SEAL_DUMMY, \
528 E_SEAL_DUMMY, \
529 E_SEAL_DUMMY, \
530 E_SEAL_DUMMY
531
532 #define SEAL_NON_PM_GROUP23 \
533 E_SEAL_DUMMY, \
534 E_SEAL_DUMMY, \
535 E_SEAL_DUMMY, \
536 E_SEAL_DUMMY, \
537 E_SEAL_DUMMY, \
538 E_SEAL_DUMMY, \
539 E_SEAL_DUMMY, \
540 E_SEAL_DDI_1_PROT_NONPM, \
541 E_SEAL_DDI_0_PROT_NONPM, \
542 E_SEAL_DIP_1_PROT_NONPM, \
543 E_SEAL_DIP_0_PROT_NONPM, \
544 E_SEAL_PDW1_PROT_NONPM, \
545 E_SEAL_PDW0_PROT_NONPM, \
546 E_SEAL_DWIN1_PROT_NONPM, \
547 E_SEAL_DWIN0_PROT_NONPM, \
548 E_SEAL_DIP_PROT_NONPM
549
550 //PM IP group
551 #define SEAL_PM_GROUP0 \
552 E_SEAL_RIU_DBG_PROT_PM, \
553 E_SEAL_MENULOAD_PROT_PM, \
554 E_SEAL_GDMA_PROT_PM, \
555 E_SEAL_DDC_PROT_PM, \
556 E_SEAL_PM_PATGEN_PROT_PM, \
557 E_SEAL_PM_POR_PROT_PM, \
558 E_SEAL_ISP_PROT_PM, \
559 E_SEAL_FSP_PROT_PM, \
560 E_SEAL_QSPI_PROT_PM, \
561 E_SEAL_PM_SLEEP_PROT_PM, \
562 E_SEAL_PM_GPIO_PROT_PM, \
563 E_SEAL_MCU_PROT_PM, \
564 E_SEAL_PM_CEC_PROT_PM, \
565 E_SEAL_PM_RTC0_PROT_PM, \
566 E_SEAL_PM_RTC1_PROT_PM, \
567 E_SEAL_PM_SAR_PROT_PM
568
569 #define SEAL_PM_GROUP1 \
570 E_SEAL_PM_AV_LINK_PROT_PM, \
571 E_SEAL_PM_RTC2_PROT_PM, \
572 E_SEAL_PM_TOP_PROT_PM, \
573 E_SEAL_EFUSE_PROT_PM, \
574 E_SEAL_IRQ_PROT_PM, \
575 E_SEAL_CACHE_PROT_PM, \
576 E_SEAL_XDMIU_PROT_PM, \
577 E_SEAL_PM_MISC_PROT_PM, \
578 E_SEAL_WDT_PROT_PM, \
579 E_SEAL_TIMER0_PROT_PM, \
580 E_SEAL_TIMER1_PROT_PM, \
581 E_SEAL_TIMER2_PROT_PM, \
582 E_SEAL_WFIMON_PROT_PM, \
583 E_SEAL_ALBANY0_PROT_PM, \
584 E_SEAL_ALBANY1_PROT_PM, \
585 E_SEAL_ALBANY2_PROT_PM
586
587 #define SEAL_PM_GROUP2 \
588 E_SEAL_DID_KEY_PROT_PM, \
589 E_SEAL_TZPC_PROT_PM, \
590 E_SEAL_STR_PROT_PM, \
591 E_SEAL_ONEWAY_PROT_PM, \
592 E_SEAL_REG_PIU_MISC_0_PROT_PM, \
593 E_SEAL_IR_PROT_PM, \
594 E_SEAL_PM_SPARE0_PROT_PM, \
595 E_SEAL_PM_SPARE1_PROT_PM, \
596 E_SEAL_SCDC_0_PROT_PM, \
597 E_SEAL_SCDC_1_PROT_PM, \
598 E_SEAL_SCDC_2_PROT_PM, \
599 E_SEAL_SCDC_3_PROT_PM, \
600 E_SEAL_DUMMY, \
601 E_SEAL_DUMMY, \
602 E_SEAL_DUMMY, \
603 E_SEAL_DUMMY
604
605 //processor group
606 #define SEAL_PROCESSOR_GROUP0 \
607 E_SEAL_DBBUS, \
608 E_SEAL_MCU51, \
609 E_SEAL_CPU2, \
610 E_SEAL_VD_R2, \
611 E_SEAL_SECURE_R2, \
612 E_SEAL_SC, \
613 E_SEAL_CMDQ, \
614 E_SEAL_HEMCU ,\
615 E_SEAL_PROCESSOR_NUM
616
617 //lock group
618 #define SEAL_LOCK_GROUP_DUMMY \
619 E_SEAL_LOCK_DUMMY, \
620 E_SEAL_LOCK_DUMMY, \
621 E_SEAL_LOCK_DUMMY, \
622 E_SEAL_LOCK_DUMMY, \
623 E_SEAL_LOCK_DUMMY, \
624 E_SEAL_LOCK_DUMMY, \
625 E_SEAL_LOCK_DUMMY, \
626 E_SEAL_LOCK_DUMMY, \
627 E_SEAL_LOCK_DUMMY, \
628 E_SEAL_LOCK_DUMMY, \
629 E_SEAL_LOCK_DUMMY, \
630 E_SEAL_LOCK_DUMMY, \
631 E_SEAL_LOCK_DUMMY, \
632 E_SEAL_LOCK_DUMMY, \
633 E_SEAL_LOCK_DUMMY, \
634 E_SEAL_LOCK_DUMMY
635
636 #define SEAL_LOCK_GROUP0 \
637 E_SEAL_SC_WP_DIPW, \
638 E_SEAL_SC_RP_DIPW, \
639 E_SEAL_SC_WP_DIPR, \
640 E_SEAL_SC_RP_DIPR, \
641 E_SEAL_AUDIO_LCL_R2_WR_PROTN_0, \
642 E_SEAL_AUDIO_LCL_R2_WR_PROTN_1, \
643 E_SEAL_AUDIO_LCL_R2_WR_PROTN_2, \
644 E_SEAL_AUDIO_LCL_R2_WR_PROTN_3, \
645 E_SEAL_AUDIO_SCL_R2_WR_PROTN_0, \
646 E_SEAL_AUDIO_SCL_R2_WR_PROTN_1, \
647 E_SEAL_AUDIO_SCL_R2_WR_PROTN_2, \
648 E_SEAL_AUDIO_SCL_R2_WR_PROTN_3, \
649 E_SEAL_SECURE_R2_WR_PROTN_0, \
650 E_SEAL_SECURE_R2_WR_PROTN_1, \
651 E_SEAL_SECURE_R2_WR_PROTN_2, \
652 E_SEAL_SECURE_R2_WR_PROTN_3
653
654 #define SEAL_LOCK_GROUP1 \
655 E_SEAL_CIPHERENG_WP_SYSKEY, \
656 E_SEAL_CIPHERENG_RP_SYSKEY, \
657 E_SEAL_DSCRMB_WP_RIV0, \
658 E_SEAL_DSCRMB_RP_RIV0, \
659 E_SEAL_DSCRMB_WP_RIV1, \
660 E_SEAL_DSCRMB_RP_RIV1, \
661 E_SEAL_DSCRMB_WP_WDATA, \
662 E_SEAL_DSCRMB_RP_WDATA, \
663 E_SEAL_DSCRMB_WP_RIV2, \
664 E_SEAL_DSCRMB_RP_RIV2, \
665 E_SEAL_DSCRMB_WP_RIV3, \
666 E_SEAL_DSCRMB_RP_RIV3, \
667 E_SEAL_SC2_WP_SCM_M, \
668 E_SEAL_SC2_RP_SCM_M, \
669 E_SEAL_MVOP_WP_TLB, \
670 E_SEAL_AUDIO_PAS_PROTN
671
672 #define SEAL_LOCK_GROUP2 \
673 E_SEAL_DSCRMB_RP_RDATA, \
674 E_SEAL_LOCK_DUMMY, \
675 E_SEAL_LOCK_DUMMY, \
676 E_SEAL_LOCK_DUMMY, \
677 E_SEAL_RNG_PROTECT, \
678 E_SEAL_RSA_PROTECT, \
679 E_SEAL_SHA_PROTECT, \
680 E_SEAL_LOCK_DUMMY, \
681 E_SEAL_EVD_R2_WR_PROTN_0, \
682 E_SEAL_EVD_R2_WR_PROTN_1, \
683 E_SEAL_EVD_R2_WR_PROTN_2, \
684 E_SEAL_EVD_R2_WR_PROTN_3, \
685 E_SEAL_HVD_R2_WR_PROTN_0, \
686 E_SEAL_HVD_R2_WR_PROTN_1, \
687 E_SEAL_HVD_R2_WR_PROTN_2, \
688 E_SEAL_HVD_R2_WR_PROTN_3
689
690 #define SEAL_LOCK_GROUP3 \
691 E_SEAL_HVD_ES0_BUF, \
692 E_SEAL_HVD_ES1_BUF, \
693 E_SEAL_HVD_ES2_BUF, \
694 E_SEAL_LOCK_DUMMY, \
695 E_SEAL_MFE0_ES_BUF, \
696 E_SEAL_MVD_WR_PROTN_0, \
697 E_SEAL_MVD_WR_PROTN_1, \
698 E_SEAL_MVD_WR_PROTN_2, \
699 E_SEAL_EVD_0_WR_PROTN_0, \
700 E_SEAL_EVD_1_WR_PROTN_0, \
701 E_SEAL_MHEG5_WR_PROTN_0, \
702 E_SEAL_AUDIO_DSP_ES_PROTN, \
703 E_SEAL_AUDIO_DSP_CACHE_PROTN, \
704 E_SEAL_EVD_0_WR_PROTN_1, \
705 E_SEAL_EVD_1_WR_PROTN_1, \
706 E_SEAL_VP9_TOP
707
708 #define SEAL_LOCK_GROUP4 \
709 E_SEAL_TSO_WP_TSOFI, \
710 E_SEAL_TSO_RP_TSOFI, \
711 E_SEAL_MMFI_WP_MMFI0, \
712 E_SEAL_MMFI_RP_MMFI0, \
713 E_SEAL_MMFI_WP_MMFI1, \
714 E_SEAL_MMFI_RP_MMFI1, \
715 E_SEAL_TSP0_WP_PVR, \
716 E_SEAL_TSP0_RP_PVR, \
717 E_SEAL_TSP0_WP_PVR1, \
718 E_SEAL_TSP0_RP_PVR1, \
719 E_SEAL_TSP0_WP_FILEIN, \
720 E_SEAL_TSP0_RP_FILEIN, \
721 E_SEAL_TSP0_WP_QMEM, \
722 E_SEAL_TSP0_RP_QMEM, \
723 E_SEAL_TSP0_WP_FW, \
724 E_SEAL_TSP0_RP_FW
725
726 #define SEAL_LOCK_GROUP5 \
727 E_SEAL_VE_WP, \
728 E_SEAL_VE_RP, \
729 E_SEAL_SC_WP_OD, \
730 E_SEAL_SC_RP_OD, \
731 E_SEAL_SC_WP_SCM_M, \
732 E_SEAL_SC_RP_SCM_M, \
733 E_SEAL_SC_WP_SCM_S, \
734 E_SEAL_SC_RP_SCM_S, \
735 E_SEAL_SC_WP_PDW0, \
736 E_SEAL_SC_RP_PDW0, \
737 E_SEAL_SC_WP_PDW1, \
738 E_SEAL_SC_RP_PDW1, \
739 E_SEAL_SC_WP_OPW, \
740 E_SEAL_SC_RP_OPW, \
741 E_SEAL_GOPD_PROTN, \
742 E_SEAL_AUDIO_AL_PROTN
743
744 #define SEAL_LOCK_GROUP6 \
745 E_SEAL_GE0_SB_PROTN, \
746 E_SEAL_GE0_DB_PROTN, \
747 E_SEAL_GE1_SB_PROTN, \
748 E_SEAL_GE1_DB_PROTN, \
749 E_SEAL_LOCK_DUMMY, \
750 E_SEAL_LOCK_DUMMY, \
751 E_SEAL_LOCK_DUMMY, \
752 E_SEAL_LOCK_DUMMY, \
753 E_SEAL_LOCK_DUMMY, \
754 E_SEAL_LOCK_DUMMY, \
755 E_SEAL_LOCK_DUMMY, \
756 E_SEAL_LOCK_DUMMY, \
757 E_SEAL_LOCK_DUMMY, \
758 E_SEAL_LOCK_DUMMY, \
759 E_SEAL_LOCK_DUMMY, \
760 E_SEAL_LOCK_DUMMY
761
762 #define SEAL_LOCK_GROUP7 \
763 E_SEAL_LOCK_DUMMY, \
764 E_SEAL_LOCK_DUMMY, \
765 E_SEAL_LOCK_DUMMY, \
766 E_SEAL_LOCK_DUMMY, \
767 E_SEAL_LOCK_DUMMY, \
768 E_SEAL_LOCK_DUMMY, \
769 E_SEAL_LOCK_DUMMY, \
770 E_SEAL_LOCK_DUMMY, \
771 E_SEAL_LOCK_DUMMY, \
772 E_SEAL_LOCK_DUMMY, \
773 E_SEAL_LOCK_DUMMY, \
774 E_SEAL_LOCK_DUMMY, \
775 E_SEAL_LOCK_DUMMY, \
776 E_SEAL_LOCK_DUMMY, \
777 E_SEAL_LOCK_DUMMY, \
778 E_SEAL_LOCK_DUMMY
779
780 #define SEAL_LOCK_GROUP8 \
781 E_SEAL_LOCK_DUMMY, \
782 E_SEAL_LOCK_DUMMY, \
783 E_SEAL_LOCK_DUMMY, \
784 E_SEAL_LOCK_DUMMY, \
785 E_SEAL_LOCK_DUMMY, \
786 E_SEAL_LOCK_DUMMY, \
787 E_SEAL_LOCK_DUMMY, \
788 E_SEAL_LOCK_DUMMY, \
789 E_SEAL_LOCK_DUMMY, \
790 E_SEAL_LOCK_DUMMY, \
791 E_SEAL_LOCK_DUMMY, \
792 E_SEAL_LOCK_DUMMY, \
793 E_SEAL_LOCK_DUMMY, \
794 E_SEAL_LOCK_DUMMY, \
795 E_SEAL_LOCK_DUMMY, \
796 E_SEAL_LOCK_DUMMY
797
798 #define SEAL_LOCK_GROUP9 \
799 E_SEAL_LOCK_DUMMY, \
800 E_SEAL_LOCK_DUMMY, \
801 E_SEAL_LOCK_DUMMY, \
802 E_SEAL_LOCK_DUMMY, \
803 E_SEAL_LOCK_DUMMY, \
804 E_SEAL_LOCK_DUMMY, \
805 E_SEAL_LOCK_DUMMY, \
806 E_SEAL_LOCK_DUMMY, \
807 E_SEAL_LOCK_DUMMY, \
808 E_SEAL_LOCK_DUMMY, \
809 E_SEAL_LOCK_DUMMY, \
810 E_SEAL_LOCK_DUMMY, \
811 E_SEAL_LOCK_DUMMY, \
812 E_SEAL_LOCK_DUMMY, \
813 E_SEAL_LOCK_DUMMY, \
814 E_SEAL_LOCK_DUMMY
815
816 #define SEAL_LOCK_GROUP10 \
817 E_SEAL_FCIE_WR_PROT_ENABLE_0, \
818 E_SEAL_FCIE_WR_PROT_ENABLE_1, \
819 E_SEAL_FCIE_WR_PROT_ENABLE_2, \
820 E_SEAL_FCIE_WR_PROT_ENABLE_3, \
821 E_SEAL_HDCP_RIU_R_PROTN, \
822 E_SEAL_HDCP_XIU_R_PROTN, \
823 E_SEAL_HDCP_RIU_W_PROTN, \
824 E_SEAL_HDCP_XIU_W_PROTN, \
825 E_SEAL_FCIE_WR_PROT_0_LOCK, \
826 E_SEAL_FCIE_WR_PROT_1_LOCK, \
827 E_SEAL_FCIE_WR_PROT_2_LOCK, \
828 E_SEAL_FCIE_WR_PROT_3_LOCK, \
829 E_SEAL_LOCK_DUMMY, \
830 E_SEAL_LOCK_DUMMY, \
831 E_SEAL_LOCK_DUMMY, \
832 E_SEAL_LOCK_DUMMY
833
834
835 //-------------------------------------------------------------------------------------------------
836 // Local Structures
837 //-------------------------------------------------------------------------------------------------
838 const eSeal_IP NonPmIpTbl[SEAL_NONPM_TBL_IP_NUM] =
839 {
840 SEAL_NON_PM_GROUP0, SEAL_NON_PM_GROUP1, SEAL_NON_PM_GROUP2,
841 SEAL_NON_PM_GROUP3, SEAL_NON_PM_GROUP4, SEAL_NON_PM_GROUP5,
842 SEAL_NON_PM_GROUP6, SEAL_NON_PM_GROUP7, SEAL_NON_PM_GROUP8,
843 SEAL_NON_PM_GROUP9, SEAL_NON_PM_GROUP10, SEAL_NON_PM_GROUP11,
844 SEAL_NON_PM_GROUP12, SEAL_NON_PM_GROUP13, SEAL_NON_PM_GROUP14,
845 SEAL_NON_PM_GROUP15, SEAL_NON_PM_GROUP16, SEAL_NON_PM_GROUP17,
846 SEAL_NON_PM_GROUP18, SEAL_NON_PM_GROUP19, SEAL_NON_PM_GROUP20,
847 SEAL_NON_PM_GROUP21, SEAL_NON_PM_GROUP22, SEAL_NON_PM_GROUP23
848 };
849
850 const eSeal_IP PmIpTbl[SEAL_PM_TBL_IP_NUM] =
851 {
852 SEAL_PM_GROUP0, SEAL_PM_GROUP1, SEAL_PM_GROUP2
853 };
854
855 const eSeal_ProcessorId ProcessorTbl[SEAL_TBL_PROCESSOR_NUM] =
856 {
857 SEAL_PROCESSOR_GROUP0
858 };
859
860 const eSeal_Lock LockTbl[SEAL_TBL_LOCK_NUM] =
861 {
862 SEAL_LOCK_GROUP10, /*0x64*/
863 SEAL_LOCK_GROUP_DUMMY,
864 SEAL_LOCK_GROUP_DUMMY,
865 SEAL_LOCK_GROUP_DUMMY,
866 SEAL_LOCK_GROUP_DUMMY,
867 SEAL_LOCK_GROUP_DUMMY,
868 SEAL_LOCK_GROUP_DUMMY,
869 SEAL_LOCK_GROUP_DUMMY,
870 SEAL_LOCK_GROUP_DUMMY,
871 SEAL_LOCK_GROUP_DUMMY,
872 SEAL_LOCK_GROUP_DUMMY,
873 SEAL_LOCK_GROUP_DUMMY,
874 SEAL_LOCK_GROUP_DUMMY,
875 SEAL_LOCK_GROUP_DUMMY,
876 SEAL_LOCK_GROUP_DUMMY,
877 SEAL_LOCK_GROUP_DUMMY,
878 SEAL_LOCK_GROUP0, /*0x74*/
879 SEAL_LOCK_GROUP1,
880 SEAL_LOCK_GROUP2,
881 SEAL_LOCK_GROUP3,
882 SEAL_LOCK_GROUP4,
883 SEAL_LOCK_GROUP5,
884 SEAL_LOCK_GROUP6,
885 SEAL_LOCK_GROUP7,
886 SEAL_LOCK_GROUP8,
887 SEAL_LOCK_GROUP9
888 };
889 //-------------------------------------------------------------------------------------------------
890 // Global Variables
891 //-------------------------------------------------------------------------------------------------
892
893 //-------------------------------------------------------------------------------------------------
894 // Local Variables
895 //-------------------------------------------------------------------------------------------------
896 static MS_VIRT _gSEAL_NonPmMapBase = 0;
897 static MS_VIRT _gSEAL_PmMapBase = 0;
898
899 //-------------------------------------------------------------------------------------------------
900 // Debug Functions
901 //-------------------------------------------------------------------------------------------------
902
903 //-------------------------------------------------------------------------------------------------
904 // Local Functions
905 //-------------------------------------------------------------------------------------------------
906
907 ////////////////////////////////////////////////////////////////////////////////
908 /// @brief \b Function \b Name: HAL_SEAL_NonPmReadByte
909 /// @brief \b Function \b Description: read 1 Byte data
910 /// @param <IN> \b u32RegAddr: register address
911 /// @param <OUT> \b None :
912 /// @param <RET> \b MS_U8
913 /// @param <GLOBAL> \b None :
914 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_NonPmReadByte(MS_U32 u32RegAddr)915 MS_U8 HAL_SEAL_NonPmReadByte(MS_U32 u32RegAddr)
916 {
917 return ((volatile MS_U8*)(_gSEAL_NonPmMapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)];
918 }
919
920 ////////////////////////////////////////////////////////////////////////////////
921 /// @brief \b Function \b Name: HAL_SEAL_PmReadByte
922 /// @brief \b Function \b Description: read 1 Byte data
923 /// @param <IN> \b u32RegAddr: register address
924 /// @param <OUT> \b None :
925 /// @param <RET> \b MS_U8
926 /// @param <GLOBAL> \b None :
927 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_PmReadByte(MS_U32 u32RegAddr)928 MS_U8 HAL_SEAL_PmReadByte(MS_U32 u32RegAddr)
929 {
930 return ((volatile MS_U8*)(_gSEAL_PmMapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)];
931 }
932
933 ////////////////////////////////////////////////////////////////////////////////
934 /// @brief \b Function \b Name: HAL_SEAL_NonPmRead2Byte
935 /// @brief \b Function \b Description: read 2 Byte data
936 /// @param <IN> \b u32RegAddr: register address
937 /// @param <OUT> \b None :
938 /// @param <RET> \b MS_U16
939 /// @param <GLOBAL> \b None :
940 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_NonPmRead2Byte(MS_U32 u32RegAddr)941 MS_U16 HAL_SEAL_NonPmRead2Byte(MS_U32 u32RegAddr)
942 {
943 return ((volatile MS_U16*)(_gSEAL_NonPmMapBase))[u32RegAddr];
944 }
945
946 ////////////////////////////////////////////////////////////////////////////////
947 /// @brief \b Function \b Name: HAL_SEAL_PmRead2Byte
948 /// @brief \b Function \b Description: read 2 Byte data
949 /// @param <IN> \b u32RegAddr: register address
950 /// @param <OUT> \b None :
951 /// @param <RET> \b MS_U16
952 /// @param <GLOBAL> \b None :
953 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_PmRead2Byte(MS_U32 u32RegAddr)954 MS_U16 HAL_SEAL_PmRead2Byte(MS_U32 u32RegAddr)
955 {
956 return ((volatile MS_U16*)(_gSEAL_PmMapBase))[u32RegAddr];
957 }
958
959 ////////////////////////////////////////////////////////////////////////////////
960 /// @brief \b Function \b Name: HAL_SEAL_NonPmRead4Byte
961 /// @brief \b Function \b Description: read 4 Byte data
962 /// @param <IN> \b u32RegAddr: register address
963 /// @param <OUT> \b None :
964 /// @param <RET> \b MS_U32
965 /// @param <GLOBAL> \b None :
966 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_NonPmRead4Byte(MS_U32 u32RegAddr)967 MS_U32 HAL_SEAL_NonPmRead4Byte(MS_U32 u32RegAddr)
968 {
969 return (HAL_SEAL_NonPmRead2Byte(u32RegAddr) | HAL_SEAL_NonPmRead2Byte(u32RegAddr+2) << 16);
970 }
971
972 ////////////////////////////////////////////////////////////////////////////////
973 /// @brief \b Function \b Name: HAL_SEAL_NonPmRead6Byte
974 /// @brief \b Function \b Description: read 6 Byte data
975 /// @param <IN> \b u32RegAddr: register address
976 /// @param <OUT> \b None :
977 /// @param <RET> \b MS_U64
978 /// @param <GLOBAL> \b None :
979 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_NonPmRead6Byte(MS_U32 u32RegAddr)980 MS_U64 HAL_SEAL_NonPmRead6Byte(MS_U32 u32RegAddr)
981 {
982 MS_U64 u64HitAddr;
983
984 u64HitAddr = 0;
985 u64HitAddr |= (MS_U64)HAL_SEAL_NonPmRead2Byte(u32RegAddr);
986 u64HitAddr |= (MS_U64)HAL_SEAL_NonPmRead2Byte(u32RegAddr + 2) << 16;
987 u64HitAddr |= (MS_U64)(HAL_SEAL_NonPmRead2Byte(u32RegAddr + 4)) << 32;
988
989 return u64HitAddr;
990 }
991
992 ////////////////////////////////////////////////////////////////////////////////
993 /// @brief \b Function \b Name: HAL_SEAL_NonPmWriteByte
994 /// @brief \b Function \b Description: write 1 Byte data
995 /// @param <IN> \b u32RegAddr: register address
996 /// @param <IN> \b u8Val : 1 byte data
997 /// @param <OUT> \b None :
998 /// @param <RET> \b TRUE: Ok FALSE: Fail
999 /// @param <GLOBAL> \b None :
1000 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_NonPmWriteByte(MS_U32 u32RegAddr,MS_U8 u8Val)1001 MS_BOOL HAL_SEAL_NonPmWriteByte(MS_U32 u32RegAddr, MS_U8 u8Val)
1002 {
1003 if (!u32RegAddr)
1004 {
1005 HAL_SEAL_ERR("%s reg error!\n", __FUNCTION__);
1006 return FALSE;
1007 }
1008
1009 ((volatile MS_U8*)(_gSEAL_NonPmMapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)] = u8Val;
1010 return TRUE;
1011 }
1012
1013 ////////////////////////////////////////////////////////////////////////////////
1014 /// @brief \b Function \b Name: HAL_SEAL_PmWriteByte
1015 /// @brief \b Function \b Description: write 1 Byte data
1016 /// @param <IN> \b u32RegAddr: register address
1017 /// @param <IN> \b u8Val : 1 byte data
1018 /// @param <OUT> \b None :
1019 /// @param <RET> \b TRUE: Ok FALSE: Fail
1020 /// @param <GLOBAL> \b None :
1021 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_PmWriteByte(MS_U32 u32RegAddr,MS_U8 u8Val)1022 MS_BOOL HAL_SEAL_PmWriteByte(MS_U32 u32RegAddr, MS_U8 u8Val)
1023 {
1024 if (!u32RegAddr)
1025 {
1026 HAL_SEAL_ERR("%s reg error!\n", __FUNCTION__);
1027 return FALSE;
1028 }
1029
1030 ((volatile MS_U8*)(_gSEAL_PmMapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)] = u8Val;
1031 return TRUE;
1032 }
1033
1034 ////////////////////////////////////////////////////////////////////////////////
1035 /// @brief \b Function \b Name: HAL_SEAL_NonPmWrite2Byte
1036 /// @brief \b Function \b Description: write 2 Byte data
1037 /// @param <IN> \b u32RegAddr: register address
1038 /// @param <IN> \b u16Val : 2 byte data
1039 /// @param <OUT> \b None :
1040 /// @param <RET> \b TRUE: Ok FALSE: Fail
1041 /// @param <GLOBAL> \b None :
1042 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_NonPmWrite2Byte(MS_U32 u32RegAddr,MS_U16 u16Val)1043 MS_BOOL HAL_SEAL_NonPmWrite2Byte(MS_U32 u32RegAddr, MS_U16 u16Val)
1044 {
1045 if (!u32RegAddr)
1046 {
1047 HAL_SEAL_ERR("%s reg error!\n", __FUNCTION__);
1048 return FALSE;
1049 }
1050
1051 ((volatile MS_U16*)(_gSEAL_NonPmMapBase))[u32RegAddr] = u16Val;
1052 return TRUE;
1053 }
1054
1055 ////////////////////////////////////////////////////////////////////////////////
1056 /// @brief \b Function \b Name: HAL_SEAL_PmWrite2Byte
1057 /// @brief \b Function \b Description: write 2 Byte data
1058 /// @param <IN> \b u32RegAddr: register address
1059 /// @param <IN> \b u16Val : 2 byte data
1060 /// @param <OUT> \b None :
1061 /// @param <RET> \b TRUE: Ok FALSE: Fail
1062 /// @param <GLOBAL> \b None :
1063 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_PmWrite2Byte(MS_U32 u32RegAddr,MS_U16 u16Val)1064 MS_BOOL HAL_SEAL_PmWrite2Byte(MS_U32 u32RegAddr, MS_U16 u16Val)
1065 {
1066 if (!u32RegAddr)
1067 {
1068 HAL_SEAL_ERR("%s reg error!\n", __FUNCTION__);
1069 return FALSE;
1070 }
1071
1072 ((volatile MS_U16*)(_gSEAL_PmMapBase))[u32RegAddr] = u16Val;
1073 return TRUE;
1074 }
1075
1076 ////////////////////////////////////////////////////////////////////////////////
1077 /// @brief \b Function \b Name: HAL_SEAL_NonPmWrite4Byte
1078 /// @brief \b Function \b Description: write 4 Byte data
1079 /// @param <IN> \b u32RegAddr: register address
1080 /// @param <IN> \b u32Val : 4 byte data
1081 /// @param <OUT> \b None :
1082 /// @param <RET> \b TRUE: Ok FALSE: Fail
1083 /// @param <GLOBAL> \b None :
1084 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_NonPmWrite4Byte(MS_U32 u32RegAddr,MS_U32 u32Val)1085 MS_BOOL HAL_SEAL_NonPmWrite4Byte(MS_U32 u32RegAddr, MS_U32 u32Val)
1086 {
1087 if (!u32RegAddr)
1088 {
1089 HAL_SEAL_ERR("%s reg error!\n", __FUNCTION__);
1090 return FALSE;
1091 }
1092
1093 HAL_SEAL_NonPmWrite2Byte(u32RegAddr, u32Val & 0x0000FFFF);
1094 HAL_SEAL_NonPmWrite2Byte(u32RegAddr+2, u32Val >> 16);
1095 return TRUE;
1096 }
1097
1098 ////////////////////////////////////////////////////////////////////////////////
1099 /// @brief \b Function \b Name: HAL_SEAL_NonPmWrite6Byte
1100 /// @brief \b Function \b Description: write 6 Byte data
1101 /// @param <IN> \b u32RegAddr: register address
1102 /// @param <IN> \b u64Val : 4 byte data
1103 /// @param <OUT> \b None :
1104 /// @param <RET> \b TRUE: Ok FALSE: Fail
1105 /// @param <GLOBAL> \b None :
1106 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_NonPmWrite6Byte(MS_U32 u32RegAddr,MS_U64 u64Val)1107 MS_BOOL HAL_SEAL_NonPmWrite6Byte(MS_U32 u32RegAddr, MS_U64 u64Val)
1108 {
1109 HAL_SEAL_NonPmWrite2Byte(u32RegAddr, u64Val & 0xFFFF);
1110 HAL_SEAL_NonPmWrite2Byte(u32RegAddr + 2,(u64Val >> 16) & 0xFFFF);
1111 HAL_SEAL_NonPmWrite2Byte(u32RegAddr + 4,(u64Val >> 32) & 0xFFFF);
1112 return TRUE;
1113 }
1114
1115 ////////////////////////////////////////////////////////////////////////////////
1116 /// @brief \b Function \b Name: HAL_SEAL_NonPmWriteRegBit
1117 /// @brief \b Function \b Description: set or reset one bit in 1-byte data
1118 /// @param <IN> \b u32RegAddr: register address
1119 /// @param <IN> \b u8Mask: 1-byte mask
1120 /// @param <IN> \b bEnabl: decide if set or reset bits
1121 /// @param <RET> \b TRUE: Ok FALSE: Fail
1122 /// @param <GLOBAL> \b None :
1123 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_NonPmWriteRegBit(MS_U32 u32RegAddr,MS_U8 u8Mask,MS_BOOL bEnable)1124 MS_BOOL HAL_SEAL_NonPmWriteRegBit(MS_U32 u32RegAddr, MS_U8 u8Mask, MS_BOOL bEnable)
1125 {
1126 MS_U8 u8Val = HAL_SEAL_NonPmReadByte(u32RegAddr);
1127 if (!u32RegAddr)
1128 {
1129 HAL_SEAL_ERR("%s reg error!\n", __FUNCTION__);
1130 return FALSE;
1131 }
1132
1133 u8Val = HAL_SEAL_NonPmReadByte(u32RegAddr);
1134 u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask);
1135 HAL_SEAL_NonPmWriteByte(u32RegAddr, u8Val);
1136 return TRUE;
1137 }
1138
1139 ////////////////////////////////////////////////////////////////////////////////
1140 /// @brief \b Function \b Name: HAL_SEAL_NonPmWrite2BytesBit
1141 /// @brief \b Function \b Description: set or reset one bit in 2-byte data
1142 /// @param <IN> \b u32RegAddr: register address
1143 /// @param <IN> \b u8Mask: 2-byte mask
1144 /// @param <IN> \b bEnabl: decide if set or reset bits
1145 /// @param <RET> \b TRUE: Ok FALSE: Fail
1146 /// @param <GLOBAL> \b None :
1147 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_NonPmWrite2BytesBit(MS_U32 u32RegOffset,MS_BOOL bEnable,MS_U16 u16Mask)1148 void HAL_SEAL_NonPmWrite2BytesBit(MS_U32 u32RegOffset, MS_BOOL bEnable, MS_U16 u16Mask)
1149 {
1150 MS_U16 val = HAL_SEAL_NonPmRead2Byte(u32RegOffset);
1151 val = (bEnable) ? (val | u16Mask) : (val & ~u16Mask);
1152 HAL_SEAL_NonPmWrite2Byte(u32RegOffset, val);
1153 }
1154
1155 ////////////////////////////////////////////////////////////////////////////////
1156 /// @brief \b Function \b Name: HAL_SEAL_GetNonPmIpIdx
1157 /// @brief \b Function \b Description: Get the Non-PM IP index with respect to HW wired
1158 /// @param <IN> \b u32RegAddr: Non-PM IP index with respect to SW enum
1159 /// @param <OUT> \b None :
1160 /// @param <RET> \b MS_S32: Non-PM IP index with respect to HW wired
1161 /// @param <GLOBAL> \b None :
1162 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_GetNonPmIpIdx(eSeal_IP eNonPmIP)1163 MS_S32 HAL_SEAL_GetNonPmIpIdx(eSeal_IP eNonPmIP)
1164 {
1165 MS_S32 s32HwIdx;
1166
1167 for (s32HwIdx = 0; s32HwIdx < SEAL_NONPM_TBL_IP_NUM; s32HwIdx++)
1168 {
1169 if(eNonPmIP == NonPmIpTbl[s32HwIdx])
1170 {
1171 return s32HwIdx;
1172 }
1173 }
1174
1175 return (-1);
1176 }
1177
1178 ////////////////////////////////////////////////////////////////////////////////
1179 /// @brief \b Function \b Name: HAL_SEAL_GetPmIpIdx
1180 /// @brief \b Function \b Description: Get the PM IP index with respect to HW wired
1181 /// @param <IN> \b u32RegAddr: PM IP index with respect to SW enum
1182 /// @param <OUT> \b None :
1183 /// @param <RET> \b MS_S32: PM IP index with respect to HW wired
1184 /// @param <GLOBAL> \b None :
1185 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_GetPmIpIdx(eSeal_IP ePmIP)1186 MS_S32 HAL_SEAL_GetPmIpIdx(eSeal_IP ePmIP)
1187 {
1188 MS_S32 s32HwIdx;
1189
1190 for (s32HwIdx = 0; s32HwIdx < SEAL_PM_TBL_IP_NUM; s32HwIdx++)
1191 {
1192 if(ePmIP == PmIpTbl[s32HwIdx])
1193 {
1194 return s32HwIdx;
1195 }
1196 }
1197
1198 return (-1);
1199 }
1200
1201 ////////////////////////////////////////////////////////////////////////////////
1202 /// @brief \b Function \b Name: HAL_SEAL_GetProcessorIdx
1203 /// @brief \b Function \b Description: Get the processor index with respect to HW wired
1204 /// @param <IN> \b u32RegAddr: Processor index with respect to SW enum
1205 /// @param <OUT> \b None :
1206 /// @param <RET> \b MS_S32: Processor index with respect to HW wired
1207 /// @param <GLOBAL> \b None :
1208 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_GetProcessorIdx(eSeal_ProcessorId eProcessorId)1209 MS_S32 HAL_SEAL_GetProcessorIdx(eSeal_ProcessorId eProcessorId)
1210 {
1211 MS_S32 s32HwIdx;
1212
1213 for (s32HwIdx = 0; s32HwIdx < SEAL_TBL_PROCESSOR_NUM; s32HwIdx++)
1214 {
1215 if(eProcessorId == ProcessorTbl[s32HwIdx])
1216 {
1217 return s32HwIdx;
1218 }
1219 }
1220
1221 return (-1);
1222 }
1223
1224 ////////////////////////////////////////////////////////////////////////////////
1225 /// @brief \b Function \b Name: HAL_SEAL_GetLockIdx
1226 /// @brief \b Function \b Description: Get the lock index with respect to HW wired
1227 /// @param <IN> \b u32RegAddr: Lock index with respect to SW enum
1228 /// @param <OUT> \b None :
1229 /// @param <RET> \b MS_S32: Lock index with respect to HW wired
1230 /// @param <GLOBAL> \b None :
1231 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_GetLockIdx(eSeal_Lock eLockId)1232 MS_S32 HAL_SEAL_GetLockIdx(eSeal_Lock eLockId)
1233 {
1234 MS_S32 s32HwIdx;
1235
1236 for (s32HwIdx = 0; s32HwIdx < SEAL_TBL_LOCK_NUM; s32HwIdx++)
1237 {
1238 if(eLockId == LockTbl[s32HwIdx])
1239 {
1240 return s32HwIdx;
1241 }
1242 }
1243
1244 return (-1);
1245 }
1246
1247 //-------------------------------------------------------------------------------------------------
1248 // Type and Structure Declaration
1249 //-------------------------------------------------------------------------------------------------
1250
1251 //-------------------------------------------------------------------------------------------------
1252 // Global Functions
1253 //-------------------------------------------------------------------------------------------------
1254
1255 ////////////////////////////////////////////////////////////////////////////////
1256 /// @brief \b Function \b Name: HAL_SEAL_SetIOMapBase
1257 /// @brief \b Function \b Description: set io-base
1258 /// @param <IN> \b u32NonPmBaseAddr: Non-PM io-base address
1259 /// @param <IN> \b u32PmBaseAddr: PM io-base address
1260 /// @param <OUT> \b None :
1261 /// @param <RET> \b MS_U8
1262 /// @param <GLOBAL> \b None :
1263 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_SetIOMapBase(MS_VIRT u32NonPmBaseAddr,MS_VIRT u32PmBaseAddr)1264 void HAL_SEAL_SetIOMapBase(MS_VIRT u32NonPmBaseAddr, MS_VIRT u32PmBaseAddr)
1265 {
1266 MS_U32 u32RegAddr;
1267 MS_U8 u8Val;
1268
1269 _gSEAL_NonPmMapBase = u32NonPmBaseAddr;
1270 _gSEAL_PmMapBase = u32PmBaseAddr;
1271 HAL_SEAL_DBG(printf("SEAL _gSEAL_NonPmMapBase= %x\n", _gSEAL_NonPmMapBase));
1272 HAL_SEAL_DBG(printf("SEAL _gSEAL_PmMapBase= %x\n", _gSEAL_PmMapBase));
1273
1274 // Force RIU bank be controled by TZPC
1275 u32RegAddr = REG_TZPC_PROTECT_CTL;
1276 u8Val = HAL_SEAL_NonPmReadByte(u32RegAddr);
1277 u8Val = u8Val | (1 << 2);
1278 HAL_SEAL_NonPmWriteByte(u32RegAddr, u8Val);
1279 }
1280
1281 ////////////////////////////////////////////////////////////////////////////////
1282 /// @brief \b Function \b Name: HAL_Seal_SecureRangeSet
1283 /// @brief \b Function \b Description: set the secure range on MIU
1284 /// @param <IN> \b u8SecureRangeId : Secure range ID
1285 /// @param <IN> \b u64StartAddr : Start address of secure range
1286 /// @param <IN> \b u64EndAddr : End address of secure range
1287 /// @param <IN> \b u32Attribute : Attribute of secure range
1288 /// @param <OUT> \b OUT :
1289 /// @param <RET> \b RET
1290 /// @param <GLOBAL> \b GLOBAL :
1291 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_SecureRangeSet(MS_U8 u8SecureRangeId,MS_U64 u64StartAddr,MS_U64 u64EndAddr,MS_U32 u32Attribute)1292 MS_BOOL HAL_Seal_SecureRangeSet(
1293 MS_U8 u8SecureRangeId,
1294 MS_U64 u64StartAddr,
1295 MS_U64 u64EndAddr,
1296 MS_U32 u32Attribute
1297 )
1298 {
1299 MS_U32 u32RegStartAddr = 0;
1300 MS_U32 u32RegEndAddr = 0;
1301 MS_U32 u32RegAttribute = 0;
1302 MS_U32 u32RegDetEn = 0;
1303 MS_U64 u64StartOffset;
1304 MS_U64 u64EndOffset;
1305 MS_U8 u8MiuSel;
1306 MS_U16 u16Val = 0;
1307 MS_U32 u32RangeOffset = 0x08 * u8SecureRangeId;
1308
1309 if (u8SecureRangeId >= E_HAL_SEAL_SECURE_RANGE_NUM)
1310 {
1311 return FALSE;
1312 }
1313
1314 _phy_to_miu_offset(u8MiuSel, u64StartOffset, u64StartAddr);
1315 _phy_to_miu_offset(u8MiuSel, u64EndOffset, u64EndAddr);
1316
1317 if(u8MiuSel == E_CHIP_MIU_0)
1318 {
1319 u32RegDetEn = REG_SECURE0_DETECT_ENABLE;
1320 u32RegStartAddr = REG_SECURE0_RANGE0_START_ADDR + u32RangeOffset;
1321 u32RegEndAddr = REG_SECURE0_RANGE0_END_ADDR + u32RangeOffset;
1322 u32RegAttribute = REG_SECURE0_RANGE0_ATTRIBUTE + u32RangeOffset;
1323 }
1324 else if(u8MiuSel == E_CHIP_MIU_1)
1325 {
1326 u32RegDetEn = REG_SECURE1_DETECT_ENABLE;
1327 u32RegStartAddr = REG_SECURE1_RANGE0_START_ADDR + u32RangeOffset;
1328 u32RegEndAddr = REG_SECURE1_RANGE0_END_ADDR + u32RangeOffset;
1329 u32RegAttribute = REG_SECURE1_RANGE0_ATTRIBUTE + u32RangeOffset;
1330 }
1331 else
1332 {
1333 HAL_SEAL_ERR("%s MIU%u is not support\n", __FUNCTION__, (unsigned int)u8MiuSel);
1334 }
1335
1336 if ( (u32Attribute == 0x0)|| (u64StartOffset == 0 && u64EndOffset == 0))
1337 {
1338
1339 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAttribute);
1340 u16Val |= 0x0F00;
1341 HAL_SEAL_NonPmWrite2Byte(u32RegAttribute, u16Val);
1342
1343 // Set start address
1344 HAL_SEAL_NonPmWrite4Byte(u32RegStartAddr, 0x00);
1345
1346 // Set end address
1347 HAL_SEAL_NonPmWrite4Byte(u32RegEndAddr, 0x00);
1348
1349 // Trigger addr change
1350 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAttribute);
1351 u16Val |= SECURE_RANGE_ADDR_DYN_CH;
1352 HAL_SEAL_NonPmWrite2Byte(u32RegAttribute, u16Val);
1353 }
1354 else
1355 {
1356 // range value is 4k-shifted
1357 u64StartOffset = u64StartOffset >> 12;
1358 u64EndOffset = u64EndOffset >> 12;
1359
1360 // Reset attribute
1361 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAttribute);
1362 u16Val |= 0x0F00;
1363 HAL_SEAL_NonPmWrite2Byte(u32RegAttribute, u16Val);
1364
1365 // Set start address
1366 HAL_SEAL_NonPmWrite4Byte(u32RegStartAddr, u64StartOffset);
1367
1368 // Set end address
1369 HAL_SEAL_NonPmWrite4Byte(u32RegEndAddr, u64EndOffset);
1370
1371 // Trigger addr change
1372 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAttribute);
1373 u16Val |= SECURE_RANGE_ADDR_DYN_CH;
1374 HAL_SEAL_NonPmWrite2Byte(u32RegAttribute, u16Val);
1375
1376 // Set attribute
1377 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAttribute);
1378 u16Val &= ~(0x0F00);
1379 u16Val |= ((u32Attribute&0x0F)<<8);
1380 HAL_SEAL_NonPmWrite2Byte(u32RegAttribute, u16Val);
1381
1382 // Enable secure range detection
1383 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegDetEn);
1384 u16Val |= (1 << u8SecureRangeId);
1385 HAL_SEAL_NonPmWrite2Byte(u32RegDetEn, u16Val);
1386 }
1387
1388 return TRUE;
1389 }
1390
1391 ////////////////////////////////////////////////////////////////////////////////
1392 /// @brief \b Function \b Name: HAL_Seal_SecureRangeQuery
1393 /// @brief \b Function \b Description: Query the attribute of secure range
1394 /// @param <IN> \b u8SecureRangeId : Secure range ID
1395 /// @param <OUT> \b pAttribute : Attribute of secure range
1396 /// @param <OUT> \b pStartAddr : Start address of secure range
1397 /// @param <OUT> \b pEndAddr : End address of secure range
1398 /// @param <RET> \b RET
1399 /// @param <GLOBAL> \b GLOBAL :
1400 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_SecureRangeQuery(MS_U8 u8MiuDev,MS_U8 u8SecureRangeId,MS_U32 * pAttribute,MS_U64 * pStartAddr,MS_U64 * pEndAddr)1401 MS_BOOL HAL_Seal_SecureRangeQuery(
1402 MS_U8 u8MiuDev,
1403 MS_U8 u8SecureRangeId,
1404 MS_U32 *pAttribute,
1405 MS_U64 *pStartAddr,
1406 MS_U64 *pEndAddr)
1407 {
1408 MS_U32 u32RegStartAddr = 0;
1409 MS_U32 u32RegEndAddr = 0;
1410 MS_U32 u32RegAttribute = 0;
1411 MS_U32 u32RangeOffset = 0x08 * u8SecureRangeId;
1412
1413 if (u8SecureRangeId >= E_HAL_SEAL_SECURE_RANGE_NUM)
1414 {
1415 return FALSE;
1416 }
1417
1418 if(u8MiuDev == E_HAL_MIU_DEV0)
1419 {
1420 u32RegStartAddr = REG_SECURE0_RANGE0_START_ADDR + u32RangeOffset;
1421 u32RegEndAddr = REG_SECURE0_RANGE0_END_ADDR + u32RangeOffset;
1422 u32RegAttribute = REG_SECURE0_RANGE0_ATTRIBUTE + u32RangeOffset;
1423 }
1424 else if( u8MiuDev == E_HAL_MIU_DEV1 )
1425 {
1426 u32RegStartAddr = REG_SECURE1_RANGE0_START_ADDR + u32RangeOffset;
1427 u32RegEndAddr = REG_SECURE1_RANGE0_END_ADDR + u32RangeOffset;
1428 u32RegAttribute = REG_SECURE1_RANGE0_ATTRIBUTE + u32RangeOffset;
1429 }
1430 else
1431 {
1432 HAL_SEAL_ERR("%s MIU%u is not support\n", __FUNCTION__, (unsigned int)u8MiuDev);
1433 }
1434
1435 // Get secure range attribute
1436 *pAttribute = (MS_U32)((HAL_SEAL_NonPmRead2Byte(u32RegAttribute)& 0xF00))>>8;
1437
1438 // Get start address
1439 *pStartAddr = (HAL_SEAL_NonPmRead4Byte(u32RegStartAddr) & 0x0FFFFF) << 12; // 20-bit value, 4kb shifted
1440
1441 // Get end address
1442 *pEndAddr = (HAL_SEAL_NonPmRead4Byte(u32RegEndAddr) & 0x0FFFFF) << 12;
1443
1444 return TRUE;
1445 }
1446
1447 ////////////////////////////////////////////////////////////////////////////////
1448 /// @brief \b Function \b Name: HAL_Seal_IMI_RangeSet
1449 /// @brief \b Function \b Description: set the secure range on internel memory interface
1450 /// @param <IN> \b u32StartAddr : Start address of secure range on IMI
1451 /// @param <IN> \b u32EndAddr : End address of secure range on IMI
1452 /// @param <IN> \b bEnable : Enable/Disable secure range on IMI
1453 /// @param <OUT> \b OUT :
1454 /// @param <RET> \b RET
1455 /// @param <GLOBAL> \b GLOBAL :
1456 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_IMI_RangeSet(MS_U32 u32StartAddr,MS_U32 u32EndAddr,MS_BOOL bEnable)1457 MS_BOOL HAL_Seal_IMI_RangeSet(MS_U32 u32StartAddr, MS_U32 u32EndAddr, MS_BOOL bEnable)
1458 {
1459 MS_U32 u32RegStartAddr = 0;
1460 MS_U32 u32RegEndAddr = 0;
1461
1462 u32RegStartAddr = REG_IMI_RANGE_START_ADDR;
1463 u32RegEndAddr = REG_IMI_RANGE_END_ADDR;
1464
1465 if(bEnable == 1)
1466 {
1467 // Set start address
1468 HAL_SEAL_NonPmWrite4Byte(u32RegStartAddr, u32StartAddr);
1469
1470 // Set end address
1471 HAL_SEAL_NonPmWrite4Byte(u32RegEndAddr, u32EndAddr);
1472 }
1473 else
1474 {
1475 // Reset start address
1476 HAL_SEAL_NonPmWrite4Byte(u32RegStartAddr, 0x0);
1477
1478 // Reset end address
1479 HAL_SEAL_NonPmWrite4Byte(u32RegEndAddr,0x0);
1480 }
1481
1482 return TRUE;
1483 }
1484
1485 ////////////////////////////////////////////////////////////////////////////////
1486 /// @brief \b Function \b Name: HAL_Seal_GetMiuHitFlag
1487 /// @brief \b Function \b Description: Get the information about hitted flag on MIU
1488 /// @param <IN> \b u8MiuDev: 0:MIU0 1:MIU1 2:MIU2 3:MIU3
1489 /// @param <OUT> \b None:
1490 /// @param <RET> \b MS_BOOL: Hitted flag
1491 /// @param <GLOBAL> \b None :
1492 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_GetMiuHitFlag(MS_U8 u8MiuDev)1493 MS_BOOL HAL_Seal_GetMiuHitFlag(MS_U8 u8MiuDev)
1494 {
1495 MS_U32 u32RegLogAddr;
1496 MS_U16 u16Val;
1497
1498 switch(u8MiuDev)
1499 {
1500 case E_HAL_MIU_DEV0:
1501 u32RegLogAddr = REG_SECURE0_HITTED_STATUS;
1502 break;
1503 case E_HAL_MIU_DEV1:
1504 u32RegLogAddr = REG_SECURE1_HITTED_STATUS;
1505 break;
1506 default:
1507 return FALSE;
1508 }
1509
1510 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegLogAddr);
1511
1512 if(REG_SECURE_HITTED_FALG & u16Val)
1513 {
1514 return TRUE;
1515 }
1516 else
1517 {
1518 return FALSE;
1519 }
1520 }
1521
1522 ////////////////////////////////////////////////////////////////////////////////
1523 /// @brief \b Function \b Name: HAL_Seal_GetHitRangeID
1524 /// @brief \b Function \b Description: Get the information about the ID of hitted secure range on MIU
1525 /// @param <IN> \b u8MiuDev: 0:MIU0 1:MIU1 2:MIU2 3:MIU3
1526 /// @param <OUT> \b None:
1527 /// @param <RET> \b MS_U8: ID of hitted secure range
1528 /// @param <GLOBAL> \b None :
1529 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_GetMiuHitRangeID(MS_U8 u8MiuDev)1530 MS_U8 HAL_Seal_GetMiuHitRangeID(MS_U8 u8MiuDev)
1531 {
1532 MS_U32 u32RegLogAddr;
1533 MS_U16 u16Val;
1534 MS_U16 u8ret;
1535
1536 switch(u8MiuDev)
1537 {
1538 case E_HAL_MIU_DEV0:
1539 u32RegLogAddr = REG_SECURE0_HITTED_RANGE_ID;
1540 break;
1541 case E_HAL_MIU_DEV1:
1542 u32RegLogAddr = REG_SECURE1_HITTED_RANGE_ID;
1543 break;
1544 default:
1545 return FALSE;
1546 }
1547
1548 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegLogAddr);
1549
1550 u8ret =(MS_U8)GET_HIT_RANGE_ID(u16Val);
1551
1552 return u8ret;
1553 }
1554
1555 ////////////////////////////////////////////////////////////////////////////////
1556 /// @brief \b Function \b Name: HAL_Seal_GetHitClientID
1557 /// @brief \b Function \b Description: Get the information about the ID of hittd MIU client ID on MIU
1558 /// @param <IN> \b u8MiuDev: 0:MIU0 1:MIU1 2:MIU2 3:MIU3
1559 /// @param <OUT> \b None:
1560 /// @param <RET> \b MS_U8: hittd MIU client ID
1561 /// @param <GLOBAL> \b None :
1562 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_GetMiuHitClientID(MS_U8 u8MiuDev)1563 MS_U8 HAL_Seal_GetMiuHitClientID(MS_U8 u8MiuDev)
1564 {
1565 MS_U32 u32RegLogAddr;
1566 MS_U16 u16Val;
1567 MS_U16 u8ret;
1568
1569 switch(u8MiuDev)
1570 {
1571 case E_HAL_MIU_DEV0:
1572 u32RegLogAddr = REG_SECURE0_HITTED_STATUS;
1573 break;
1574 case E_HAL_MIU_DEV1:
1575 u32RegLogAddr = REG_SECURE1_HITTED_STATUS;
1576 break;
1577 default:
1578 return FALSE;
1579 }
1580
1581 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegLogAddr);
1582 u8ret =(MS_U8)GET_HIT_CLIENT_ID(u16Val);
1583
1584 return u8ret;
1585 }
1586
1587 ////////////////////////////////////////////////////////////////////////////////
1588 /// @brief \b Function \b Name: HAL_Seal_GetSecureFlag
1589 /// @brief \b Function \b Description: Get the information about the hitted client on MIU be secure or not
1590 /// @param <IN> \b u8MiuDev: 0:MIU0 1:MIU1 2:MIU2 3:MIU3
1591 /// @param <OUT> \b None:
1592 /// @param <RET> \b MS_BOOL: Secure flag
1593 /// @param <GLOBAL> \b None :
1594 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_GetMiuSecureFlag(MS_U8 u8MiuDev)1595 MS_BOOL HAL_Seal_GetMiuSecureFlag(MS_U8 u8MiuDev)
1596 {
1597 MS_U32 u32RegLogAddr;
1598 MS_U16 u16Val;
1599
1600 switch(u8MiuDev)
1601 {
1602 case E_HAL_MIU_DEV0:
1603 u32RegLogAddr = REG_SECURE0_HITTED_STATUS;
1604 break;
1605 case E_HAL_MIU_DEV1:
1606 u32RegLogAddr = REG_SECURE1_HITTED_STATUS;
1607 break;
1608 default:
1609 return FALSE;
1610 }
1611
1612 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegLogAddr);
1613
1614 if(REG_SECURE_HITTED_IS_NONSECURE & u16Val)
1615 {
1616 return FALSE;
1617 }
1618 else
1619 {
1620 return TRUE;
1621 }
1622 }
1623
1624 ////////////////////////////////////////////////////////////////////////////////
1625 /// @brief \b Function \b Name: HAL_Seal_GetWriteFlag
1626 /// @brief \b Function \b Description: Get the information about the violation on MIU be write or read access
1627 /// @param <IN> \b u8MiuDev: 0:MIU0 1:MIU1 2:MIU2 3:MIU3
1628 /// @param <OUT> \b None:
1629 /// @param <RET> \b MS_BOOL: Write flag
1630 /// @param <GLOBAL> \b None :
1631 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_GetMiuWriteFlag(MS_U8 u8MiuDev)1632 MS_BOOL HAL_Seal_GetMiuWriteFlag(MS_U8 u8MiuDev)
1633 {
1634 MS_U32 u32RegLogAddr;
1635 MS_U16 u16Val;
1636
1637 switch(u8MiuDev)
1638 {
1639 case E_HAL_MIU_DEV0:
1640 u32RegLogAddr = REG_SECURE0_HITTED_STATUS;
1641 break;
1642 case E_HAL_MIU_DEV1:
1643 u32RegLogAddr = REG_SECURE1_HITTED_STATUS;
1644 break;
1645 default:
1646 return FALSE;
1647 }
1648
1649 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegLogAddr);
1650
1651 if(REG_SECURE_HITTED_IS_WRITE & u16Val)
1652 {
1653 return TRUE;
1654 }
1655 else
1656 {
1657 return FALSE;
1658 }
1659 }
1660
1661 ////////////////////////////////////////////////////////////////////////////////
1662 /// @brief \b Function \b Name: HAL_Seal_GetHitAddr
1663 /// @brief \b Function \b Description: Get the information about the hitted address on MIU
1664 /// @param <IN> \b u8MiuDev: 0:MIU0 1:MIU1 2:MIU2 3:MIU3
1665 /// @param <OUT> \b None:
1666 /// @param <RET> \b MS_U32: Hitted address
1667 /// @param <GLOBAL> \b None :
1668 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_GetMiuHitAddr(MS_U8 u8MiuDev)1669 MS_U64 HAL_Seal_GetMiuHitAddr(MS_U8 u8MiuDev)
1670 {
1671 MS_U32 u32RegAddr;
1672 MS_U64 u64Val;
1673
1674 switch(u8MiuDev)
1675 {
1676 case E_HAL_MIU_DEV0:
1677 u32RegAddr = REG_SECURE0_HITTED_ADDR;
1678 break;
1679 case E_HAL_MIU_DEV1:
1680 u32RegAddr = REG_SECURE1_HITTED_ADDR;
1681 break;
1682 default:
1683 return FALSE;
1684 }
1685
1686 u64Val = HAL_SEAL_NonPmRead4Byte(u32RegAddr);
1687 return u64Val;
1688 }
1689
1690 ////////////////////////////////////////////////////////////////////////////////
1691 /// @brief \b Function \b Name: HAL_Seal_ClearMiuHitLog
1692 /// @brief \b Function \b Description: Clear the hitted log on MIU
1693 /// @param <IN> \b u8MiuDev: 0:MIU0 1:MIU1 2:MIU2 3:MIU3
1694 /// @param <OUT> \b None:
1695 /// @param <RET> \b RET:
1696 /// @param <GLOBAL> \b None :
1697 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_ClearMiuHitLog(MS_U8 u8MiuDev)1698 MS_BOOL HAL_Seal_ClearMiuHitLog(MS_U8 u8MiuDev)
1699 {
1700 MS_U32 u32RegLogAddr;
1701
1702 switch(u8MiuDev)
1703 {
1704 case E_HAL_MIU_DEV0:
1705 u32RegLogAddr = REG_SECURE0_HITTED_STATUS;
1706 break;
1707 case E_HAL_MIU_DEV1:
1708 u32RegLogAddr = REG_SECURE1_HITTED_STATUS;
1709 break;
1710 default:
1711 return FALSE;
1712 }
1713
1714 HAL_SEAL_NonPmWrite2BytesBit(u32RegLogAddr, TRUE, REG_SECURE_HITTED_LOG_CLR);
1715 HAL_SEAL_NonPmWrite2BytesBit(u32RegLogAddr, FALSE, REG_SECURE_HITTED_LOG_CLR);
1716 return TRUE;
1717 }
1718
1719 ////////////////////////////////////////////////////////////////////////////////
1720 /// @brief \b Function \b Name: HAL_Seal_SecureRangeLock
1721 /// @brief \b Function \b Description: One-way setting to lock the specific secure range
1722 /// @param <IN> \b u8MiuDev: 0:MIU0 1:MIU1 2:MIU2 3:MIU3
1723 /// @param <IN> \b u8SecureRangeId: Secure range ID
1724 /// @param <OUT> \b None:
1725 /// @param <RET> \b RET
1726 /// @param <GLOBAL> \b None :
1727 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_SecureRangeLock(MS_U8 u8MiuDev,MS_U8 u8SecureRangeId)1728 MS_BOOL HAL_Seal_SecureRangeLock(MS_U8 u8MiuDev, MS_U8 u8SecureRangeId)
1729 {
1730 MS_U32 u32RegAddr;
1731 MS_U16 u16Val;
1732
1733 if (u8SecureRangeId >= E_HAL_SEAL_SECURE_RANGE_NUM)
1734 {
1735 return FALSE;
1736 }
1737
1738 switch(u8MiuDev)
1739 {
1740 case E_HAL_MIU_DEV0:
1741 u32RegAddr = REG_SECURE0_LOCK;
1742 break;
1743 case E_HAL_MIU_DEV1:
1744 u32RegAddr = REG_SECURE1_LOCK;
1745 break;
1746 default:
1747 HAL_SEAL_ERR("%s MIU%u is not support\n", __FUNCTION__, (unsigned int)u8MiuDev);
1748 return false;
1749 }
1750
1751 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
1752 u16Val = u16Val | (1 << u8SecureRangeId);
1753 HAL_SEAL_NonPmWrite2Byte(u32RegAddr, u16Val);
1754
1755 return TRUE;
1756 }
1757
1758 ////////////////////////////////////////////////////////////////////////////////
1759 /// @brief \b Function \b Name: HAL_Seal_SecureProcessorSet
1760 /// @brief \b Function \b Description: Define the specific processor be secure or not
1761 /// @param <IN> \b u8ProcessorId: Processor ID
1762 /// @param <IN> \b bSecure: 1: non-secure 0:secure
1763 /// @param <OUT> \b None:
1764 /// @param <RET> \b RET
1765 /// @param <GLOBAL> \b None :
1766 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_NonSecureProcessorSet(MS_U8 u8ProcessorId,MS_BOOL bNonSecure)1767 MS_BOOL HAL_Seal_NonSecureProcessorSet(MS_U8 u8ProcessorId, MS_BOOL bNonSecure)
1768 {
1769 MS_U32 u32RegAddr;
1770 MS_U16 u16Val;
1771 MS_S32 s32HwIdx;
1772
1773 // special case for HEMCU
1774 if(u8ProcessorId == E_SEAL_HEMCU)
1775 {
1776 if(bNonSecure)
1777 HAL_SEAL_NonPmWriteRegBit(REG_TZPC_NONSECURE_HEMCU, BIT3, ENABLE);
1778 else
1779 HAL_SEAL_NonPmWriteRegBit(REG_TZPC_NONSECURE_HEMCU, BIT3, DISABLE);
1780
1781 return TRUE;
1782 }
1783
1784 s32HwIdx = HAL_SEAL_GetProcessorIdx(u8ProcessorId);
1785
1786 if(s32HwIdx == -1)
1787 {
1788 HAL_SEAL_ERR("Processor ID:%u doesn't exist !\n", (unsigned int)u8ProcessorId);
1789 return FALSE;
1790 }
1791
1792 u32RegAddr = REG_TZPC_NONSECURE_PROCESSOR;
1793 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
1794
1795 if(bNonSecure)
1796 {
1797 u16Val = u16Val | (1 << (s32HwIdx * 2));
1798 }
1799 else
1800 {
1801 u16Val = u16Val & ~(1 << (s32HwIdx * 2));
1802 }
1803
1804 HAL_SEAL_NonPmWrite2Byte(u32RegAddr, u16Val);
1805
1806 return TRUE;
1807 }
1808
1809 ////////////////////////////////////////////////////////////////////////////////
1810 /// @brief \b Function \b Name: HAL_Seal_SecureProcessorQuery
1811 /// @brief \b Function \b Description: Query the specific processor be secure or not
1812 /// @param <IN> \b u8ProcessorId: Processor ID
1813 /// @param <OUT> \b pSecure: 1: non-secure 0:secure
1814 /// @param <RET> \b RET
1815 /// @param <GLOBAL> \b None :
1816 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_NonSecureProcessorQuery(MS_U8 u8ProcessorId,MS_BOOL * pNonSecure)1817 MS_BOOL HAL_Seal_NonSecureProcessorQuery(MS_U8 u8ProcessorId, MS_BOOL *pNonSecure)
1818 {
1819 MS_U32 u32RegAddr;
1820 MS_U16 u16Val;
1821 MS_U16 s32HwIdx;
1822
1823 // special case for HEMCU
1824 if(u8ProcessorId == E_SEAL_HEMCU)
1825 {
1826 u32RegAddr = REG_TZPC_NONSECURE_HEMCU;
1827 u16Val = (MS_U8)HAL_SEAL_NonPmReadByte(u32RegAddr);
1828
1829 if(u16Val & BIT3)
1830 {
1831 *pNonSecure = 1;
1832 }
1833 else
1834 {
1835 *pNonSecure = 0;
1836 }
1837 return TRUE;
1838 }
1839
1840 s32HwIdx = HAL_SEAL_GetProcessorIdx(u8ProcessorId);
1841
1842 if(s32HwIdx == -1)
1843 {
1844 HAL_SEAL_ERR("Processor ID:%u doesn't exist !\n", (unsigned int)u8ProcessorId);
1845 return FALSE;
1846 }
1847
1848 u32RegAddr = REG_TZPC_NONSECURE_PROCESSOR;
1849 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
1850
1851 if(u16Val & (1 << (s32HwIdx * 2)))
1852 {
1853 *pNonSecure = 1;
1854 }
1855 else
1856 {
1857 *pNonSecure = 0;
1858 }
1859
1860 return TRUE;
1861 }
1862
1863 ////////////////////////////////////////////////////////////////////////////////
1864 /// @brief \b Function \b Name: HAL_Seal_SecureSlaveSet
1865 /// @brief \b Function \b Description: Define the specific slave IP be secure or not
1866 /// @param <IN> \b u32SlaveId: Slave ID
1867 /// @param <IN> \b bSecure: 0: non-secure 1:secure
1868 /// @param <OUT> \b None:
1869 /// @param <RET> \b RET
1870 /// @param <GLOBAL> \b None :
1871 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_SecureSlaveSet(MS_U32 u32SlaveId,MS_BOOL bSecure)1872 MS_BOOL HAL_Seal_SecureSlaveSet(MS_U32 u32SlaveId, MS_BOOL bSecure)
1873 {
1874 MS_U32 u32RegAddr;
1875 MS_U16 u16Val;
1876 MS_S32 s32HwIdx;
1877 MS_U8 u8GroupId;
1878 MS_U8 u8ClientId;
1879 MS_BOOL bIsPm;
1880
1881 bIsPm = 0;
1882 s32HwIdx = HAL_SEAL_GetNonPmIpIdx(u32SlaveId);
1883
1884 //Slave ID not in Non-PM group, check if u32SlaveId in PM group
1885 if(s32HwIdx == -1)
1886 {
1887 s32HwIdx = HAL_SEAL_GetPmIpIdx(u32SlaveId);
1888 bIsPm = 1;
1889
1890 //Slave ID not in Non-PM nor PM group
1891 if(s32HwIdx == -1)
1892 {
1893 HAL_SEAL_ERR("Slave ID:%u doesn't exist !\n", (unsigned int)u32SlaveId);
1894 return FALSE;
1895 }
1896 }
1897
1898 if(bIsPm == 0)
1899 {
1900 u8GroupId = (MS_U8)(s32HwIdx / SEAL_NONPM_GROUP_IP_NUM);
1901 u8ClientId = (MS_U8)(s32HwIdx % SEAL_NONPM_GROUP_IP_NUM);
1902 u32RegAddr = (MS_U32)(REG_TZPC_NONPM_SECURE_SLAVE + (u8GroupId * 2));
1903
1904 if(bSecure == 1)
1905 {
1906 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
1907 u16Val = u16Val & (~(1 << u8ClientId));
1908 HAL_SEAL_NonPmWrite2Byte(u32RegAddr, u16Val);
1909 }
1910 else
1911 {
1912 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
1913 u16Val = u16Val | (1 << u8ClientId);
1914 HAL_SEAL_NonPmWrite2Byte(u32RegAddr, u16Val);
1915 }
1916 }
1917 else
1918 {
1919 u8GroupId = (MS_U8)(s32HwIdx / SEAL_PM_GROUP_IP_NUM);
1920 u8ClientId = (MS_U8)(s32HwIdx % SEAL_PM_GROUP_IP_NUM);
1921 u32RegAddr = (MS_U32)(REG_TZPC_PM_SECURE_SLAVE + (u8GroupId * 2));
1922
1923 if(bSecure == 1)
1924 {
1925 u16Val = HAL_SEAL_PmRead2Byte(u32RegAddr);
1926 u16Val = u16Val & (~(1 << u8ClientId));
1927 HAL_SEAL_PmWrite2Byte(u32RegAddr, u16Val);
1928 }
1929 else
1930 {
1931 u16Val = HAL_SEAL_PmRead2Byte(u32RegAddr);
1932 u16Val = u16Val | (1 << u8ClientId);
1933 HAL_SEAL_PmWrite2Byte(u32RegAddr, u16Val);
1934 }
1935 }
1936 return TRUE;
1937 }
1938
1939 ////////////////////////////////////////////////////////////////////////////////
1940 /// @brief \b Function \b Name: HAL_Seal_SecureSlaveQuery
1941 /// @brief \b Function \b Description: Query the specific slave IP be secure or not
1942 /// @param <IN> \b u32SlaveId: Slave ID
1943 /// @param <IN> \b pSecure: 0: non-secure 1:secure
1944 /// @param <OUT> \b None:
1945 /// @param <RET> \b RET
1946 /// @param <GLOBAL> \b None :
1947 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_SecureSlaveQuery(MS_U32 u32SlaveId,MS_BOOL * pSecure)1948 MS_BOOL HAL_Seal_SecureSlaveQuery(MS_U32 u32SlaveId, MS_BOOL *pSecure)
1949 {
1950 MS_U32 u32RegAddr;
1951 MS_U16 u16Val;
1952 MS_S32 s32HwIdx;
1953 MS_U8 u8GroupId;
1954 MS_U8 u8ClientId;
1955 MS_BOOL bIsPm;
1956
1957 bIsPm = 0;
1958 s32HwIdx = HAL_SEAL_GetNonPmIpIdx(u32SlaveId);
1959
1960 //Slave ID not in Non-PM group, check if u32SlaveId in PM group
1961 if(s32HwIdx == -1)
1962 {
1963 s32HwIdx = HAL_SEAL_GetPmIpIdx(u32SlaveId);
1964 bIsPm = 1;
1965
1966 //Slave ID not in Non-PM nor PM group
1967 if(s32HwIdx == -1)
1968 {
1969 HAL_SEAL_ERR("Slave ID:%u doesn't exist !\n", (unsigned int)u32SlaveId);
1970 return FALSE;
1971 }
1972 }
1973
1974 if(bIsPm == 0)
1975 {
1976 u8GroupId = (MS_U8)(s32HwIdx / SEAL_NONPM_GROUP_IP_NUM);
1977 u8ClientId = (MS_U8)(s32HwIdx % SEAL_NONPM_GROUP_IP_NUM);
1978 u32RegAddr = (MS_U32)(REG_TZPC_NONPM_SECURE_SLAVE + (u8GroupId * 2));
1979
1980 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
1981 }
1982 else
1983 {
1984 u8GroupId = (MS_U8)(s32HwIdx / SEAL_PM_GROUP_IP_NUM);
1985 u8ClientId = (MS_U8)(s32HwIdx % SEAL_PM_GROUP_IP_NUM);
1986 u32RegAddr = (MS_U32)(REG_TZPC_PM_SECURE_SLAVE + (u8GroupId * 2));
1987
1988 u16Val = HAL_SEAL_PmRead2Byte(u32RegAddr);
1989 }
1990
1991 if(u16Val & (1 << u8ClientId))
1992 {
1993 *pSecure = 0;
1994 }
1995 else
1996 {
1997 *pSecure = 1;
1998 }
1999
2000 return TRUE;
2001 }
2002
2003 ////////////////////////////////////////////////////////////////////////////////
2004 /// @brief \b Function \b Name: HAL_Seal_SecureMasterSet
2005 /// @brief \b Function \b Description: Define the specific master IP be secure or not
2006 /// @param <IN> \b u32SlaveId: Master ID
2007 /// @param <IN> \b bSecure: 0: non-secure 1:secure
2008 /// @param <OUT> \b None:
2009 /// @param <RET> \b RET
2010 /// @param <GLOBAL> \b None :
2011 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_SecureMasterSet(MS_U32 u32MasterId,MS_BOOL bSecure)2012 MS_BOOL HAL_Seal_SecureMasterSet(MS_U32 u32MasterId, MS_BOOL bSecure)
2013 {
2014 MS_U32 u32RegAddr;
2015 MS_U16 u16Val;
2016 MS_S32 s32HwIdx;
2017 MS_U8 u8GroupId;
2018 MS_U8 u8ClientId;
2019
2020 s32HwIdx = HAL_SEAL_GetNonPmIpIdx(u32MasterId);
2021
2022 if(s32HwIdx == -1)
2023 {
2024 HAL_SEAL_ERR("Master ID:%u doesn't exist !\n", (unsigned int)u32MasterId);
2025 return FALSE;
2026 }
2027
2028 u8GroupId = (MS_U8)(s32HwIdx / SEAL_NONPM_GROUP_IP_NUM);
2029 u8ClientId = (MS_U8)(s32HwIdx % SEAL_NONPM_GROUP_IP_NUM);
2030 u32RegAddr = (MS_U32)(REG_TZPC_NONPM_SECURE_MASTER + (u8GroupId * 2));
2031
2032 if(bSecure == 1)
2033 {
2034 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
2035 u16Val = u16Val & (~(1 << u8ClientId));
2036 HAL_SEAL_NonPmWrite2Byte(u32RegAddr, u16Val);
2037 }
2038 else
2039 {
2040 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
2041 u16Val = u16Val | (1 << u8ClientId);
2042 HAL_SEAL_NonPmWrite2Byte(u32RegAddr, u16Val);
2043 }
2044
2045 return TRUE;
2046 }
2047
2048 ////////////////////////////////////////////////////////////////////////////////
2049 /// @brief \b Function \b Name: HAL_Seal_SecureMasterQuery
2050 /// @brief \b Function \b Description: Query the specific master IP be secure or not
2051 /// @param <IN> \b u32SlaveId: Master ID
2052 /// @param <IN> \b pSecure: 0: non-secure 1:secure
2053 /// @param <OUT> \b None:
2054 /// @param <RET> \b RET
2055 /// @param <GLOBAL> \b None :
2056 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_SecureMasterQuery(MS_U32 u32MasterId,MS_BOOL * pSecure)2057 MS_BOOL HAL_Seal_SecureMasterQuery(MS_U32 u32MasterId, MS_BOOL *pSecure)
2058 {
2059 MS_U32 u32RegAddr;
2060 MS_U16 u16Val;
2061 MS_S32 s32HwIdx;
2062 MS_U8 u8GroupId;
2063 MS_U8 u8ClientId;
2064
2065 s32HwIdx = HAL_SEAL_GetNonPmIpIdx(u32MasterId);
2066
2067 if(s32HwIdx == -1)
2068 {
2069 HAL_SEAL_ERR("Master ID:%u doesn't exist !\n", (unsigned int)u32MasterId);
2070 return FALSE;
2071 }
2072
2073 u8GroupId = (MS_U8)(s32HwIdx / SEAL_NONPM_GROUP_IP_NUM);
2074 u8ClientId = (MS_U8)(s32HwIdx % SEAL_NONPM_GROUP_IP_NUM);
2075 u32RegAddr = (MS_U32)(REG_TZPC_NONPM_SECURE_MASTER + (u8GroupId * 2));
2076
2077 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
2078
2079 if(u16Val & (1 << u8ClientId))
2080 {
2081 *pSecure = 0;
2082 }
2083 else
2084 {
2085 *pSecure = 1;
2086 }
2087
2088 return TRUE;
2089 }
2090
2091 ////////////////////////////////////////////////////////////////////////////////
2092 /// @brief \b Function \b Name: HAL_Seal_BufferLock
2093 /// @brief \b Function \b Description: Lock the specific buffer
2094 /// @param <IN> \b u8SecureRangeId: Secure buffer ID
2095 /// @param <IN> \b bLock: 0: unlock 1:lock
2096 /// @param <OUT> \b None:
2097 /// @param <RET> \b RET
2098 /// @param <GLOBAL> \b None :
2099 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_BufferLock(MS_U8 u8BufferLockId,MS_BOOL bLock)2100 MS_BOOL HAL_Seal_BufferLock(MS_U8 u8BufferLockId, MS_BOOL bLock)
2101 {
2102 MS_U32 u32RegAddr;
2103 MS_U16 u16Val;
2104 MS_S32 s32HwIdx;
2105 MS_U8 u8GroupId;
2106 MS_U8 u8ClientId;
2107
2108 s32HwIdx = HAL_SEAL_GetLockIdx(u8BufferLockId);
2109
2110 //Check if u8SecureBufferId exist
2111 if(s32HwIdx == -1)
2112 {
2113 HAL_SEAL_ERR("Secure buffer lock ID:%u doesn't exist !\n", (unsigned int)u8BufferLockId);
2114 return FALSE;
2115 }
2116
2117 u8GroupId = (MS_U8)(s32HwIdx / SEAL_LOCK_NUM_PERGROUP);
2118 u8ClientId = (MS_U8)(s32HwIdx % SEAL_LOCK_NUM_PERGROUP);
2119 u32RegAddr = (MS_U32)(REG_TZPC_BUFFER_LOCK + (u8GroupId * 2));
2120
2121 if(bLock == 1)
2122 {
2123 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
2124 u16Val = u16Val & (~(1 << u8ClientId));
2125 HAL_SEAL_NonPmWrite2Byte(u32RegAddr, u16Val);
2126 }
2127 else
2128 {
2129 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
2130 u16Val = u16Val | (1 << u8ClientId);
2131 HAL_SEAL_NonPmWrite2Byte(u32RegAddr, u16Val);
2132 }
2133
2134 return TRUE;
2135 }
2136
2137
HAL_Seal_QueryBufferLocked(eSeal_Lock eLockId,MS_BOOL * bLocked)2138 MS_BOOL HAL_Seal_QueryBufferLocked(eSeal_Lock eLockId, MS_BOOL* bLocked)
2139 {
2140 MS_U32 u32RegAddr;
2141 MS_U16 u16Val;
2142 MS_S32 s32HwIdx;
2143 MS_U8 u8GroupId;
2144 MS_U8 u8ClientId;
2145
2146 s32HwIdx = HAL_SEAL_GetLockIdx(eLockId);
2147
2148 //Check if u8SecureBufferId exist
2149 if(s32HwIdx == -1)
2150 {
2151 HAL_SEAL_ERR("Secure buffer lock ID:%u doesn't exist !\n", (unsigned int)eLockId);
2152 return FALSE;
2153 }
2154
2155 u8GroupId = (MS_U8)(s32HwIdx / SEAL_LOCK_NUM_PERGROUP);
2156 u8ClientId = (MS_U8)(s32HwIdx % SEAL_LOCK_NUM_PERGROUP);
2157 u32RegAddr = (MS_U32)(REG_TZPC_BUFFER_LOCK + (u8GroupId * 2));
2158
2159 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
2160 *bLocked = (u16Val & (1 << u8ClientId)) ? FALSE : TRUE;
2161
2162 return TRUE;
2163 }
2164
2165
2166 ////////////////////////////////////////////////////////////////////////////////
2167 /// @brief \b Function \b Name: HAL_Seal_MaskInterruptFlag
2168 /// @brief \b Function \b Description: mask/unmask irq mask bit
2169 /// @param <IN> \b u8MiuDev: 0:MIU0 1:MIU1 2:MIU2 3:MIU3
2170 /// @param <IN> \b bMask: FLASE: unmask ; TRUE: mask
2171 /// @param <OUT> \b None:
2172 /// @param <RET> \b RET:
2173 /// @param <GLOBAL> \b None :
2174 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_MaskInterruptFlag(MS_U8 u8MiuDev,MS_BOOL bMask)2175 MS_BOOL HAL_Seal_MaskInterruptFlag(MS_U8 u8MiuDev, MS_BOOL bMask)
2176 {
2177 MS_U32 u32RegLogAddr;
2178
2179 switch(u8MiuDev)
2180 {
2181 case E_HAL_MIU_DEV0:
2182 u32RegLogAddr = REG_SECURE0_HITTED_STATUS;
2183 break;
2184 case E_HAL_MIU_DEV1:
2185 u32RegLogAddr = REG_SECURE1_HITTED_STATUS;
2186 break;
2187 default:
2188 return FALSE;
2189 }
2190
2191 HAL_SEAL_NonPmWrite2BytesBit(u32RegLogAddr, bMask, REG_SECURE_HITTED_IRQ_MASK);
2192
2193 return TRUE;
2194 }
2195
2196 ////////////////////////////////////////////////////////////////////////////////
2197 /// @brief \b Function \b Name: HAL_Seal_CheckSecureRange
2198 /// @brief \b Function \b Description: Is Overlap Secure Range
2199 /// @param <IN> \b phyStartAddr : start address
2200 /// @param <IN> \b u32Length : protect length
2201 /// @param <IN> \b eCheckSecureRangeType : check SecureRange type
2202 /// @param <OUT> \b None:
2203 /// @param <RET> \b RET:
2204 /// @param <GLOBAL> \b None :
2205 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_CheckSecureRange(MS_PHY phyStartAddr,MS_U32 u32Length,eSeal_CheckSecureRangeType eCheckSecureRangeType)2206 MS_BOOL HAL_Seal_CheckSecureRange(MS_PHY phyStartAddr, MS_U32 u32Length, eSeal_CheckSecureRangeType eCheckSecureRangeType)
2207 {
2208 MS_U8 u8MiuSel;
2209 MS_U8 u8Val;
2210 MS_U8 RangeNum;
2211 MS_U64 u64Offset;
2212 MS_U32 u32RegStartAddr;
2213 MS_U32 u32RegEndAddr;
2214 MS_U32 u32RegAttribute;
2215 MS_U32 u32RegDetEn;
2216 MS_U64 u64StartAddr;
2217 MS_U64 u64EndAddr;
2218
2219 _phy_to_miu_offset(u8MiuSel, u64Offset, phyStartAddr);
2220
2221 switch(u8MiuSel)
2222 {
2223 case E_CHIP_MIU_0:
2224 u32RegDetEn = REG_SECURE0_DETECT_ENABLE;
2225 u32RegStartAddr = REG_SECURE0_RANGE0_START_ADDR;
2226 u32RegEndAddr = REG_SECURE0_RANGE0_END_ADDR;
2227 u32RegAttribute = REG_SECURE0_RANGE0_ATTRIBUTE + RANGE_ADDR_HBYTE_OFFSET;
2228 break;
2229 case E_CHIP_MIU_1:
2230 u32RegDetEn = REG_SECURE1_DETECT_ENABLE;
2231 u32RegStartAddr = REG_SECURE1_RANGE0_START_ADDR;
2232 u32RegEndAddr = REG_SECURE1_RANGE0_END_ADDR;
2233 u32RegAttribute = REG_SECURE1_RANGE0_ATTRIBUTE + RANGE_ADDR_HBYTE_OFFSET;
2234 break;
2235 default:
2236 printf("%s: Wrong paramater-MiuSel %d \n", __FUNCTION__, u8MiuSel);
2237 return TRUE;
2238 }
2239
2240 u8Val = HAL_SEAL_NonPmReadByte(u32RegDetEn);
2241 //shift 4k align
2242 u64Offset = u64Offset >> 12;
2243 u32Length = u32Length >> 12;
2244
2245 for(RangeNum = E_HAL_SEAL_SECURE_RANGE_ID0; RangeNum < E_HAL_SEAL_SECURE_RANGE_NUM; RangeNum++, u32RegStartAddr+=RANGE_ADDR_OFFSET, u32RegEndAddr+=RANGE_ADDR_OFFSET, u32RegAttribute+=RANGE_ADDR_OFFSET)
2246 {
2247 if( HAL_SEAL_NonPmReadByte(u32RegAttribute) == (E_SEAL_SECURE_READ | E_SEAL_SECURE_WRITE) && (u8Val & (1<<RangeNum))) // Already set secure range
2248 {
2249 //check overlap
2250 u64StartAddr = HAL_SEAL_NonPmRead4Byte(u32RegStartAddr);
2251 u64EndAddr = HAL_SEAL_NonPmRead4Byte(u32RegEndAddr);
2252 //shift 4k align
2253 u64StartAddr = u64StartAddr << 12;
2254 u64EndAddr = u64EndAddr << 12;
2255
2256 switch(eCheckSecureRangeType)
2257 {
2258 case E_SEAL_OVERLAP:
2259 if ( u64StartAddr <= u64Offset && u64EndAddr > u64Offset )
2260 return TRUE;
2261 else if ( u64StartAddr > u64Offset && u64StartAddr < (u64Offset + u32Length))
2262 return TRUE;
2263 break;
2264 case E_SEAL_CONTAIN:
2265 if ( u64StartAddr <= u64Offset && u64EndAddr >= (u64Offset + u32Length) )
2266 return TRUE;
2267 break;
2268 default:
2269 printf("%s: Wrong paramater-eCheckSecureRangeType %d \n", __FUNCTION__, eCheckSecureRangeType);
2270 return TRUE;
2271 }
2272 }
2273 }
2274 return FALSE;
2275 }
2276
2277
2278 #ifdef MSOS_TYPE_OPTEE
HAL_Seal_ChangeIPSecureDMAAbillity(MS_U32 u32ModuleID,MS_U32 u32ModuleParameter,MS_U32 u32IsSecure)2279 MS_BOOL HAL_Seal_ChangeIPSecureDMAAbillity(MS_U32 u32ModuleID, MS_U32 u32ModuleParameter, MS_U32 u32IsSecure)
2280 {
2281 switch(u32ModuleID)
2282 {
2283 case MODULE_XC:
2284 HAL_Seal_SecureMasterSet(E_SEAL_MSC_PROT_NONPM, u32IsSecure);
2285 HAL_Seal_SecureMasterSet(E_SEAL_SC0_PROT_NONPM, u32IsSecure);
2286 HAL_Seal_SecureMasterSet(E_SEAL_SC1_PROT_NONPM, u32IsSecure);
2287 HAL_Seal_SecureMasterSet(E_SEAL_SC2_PROT_NONPM, u32IsSecure);
2288 HAL_Seal_SecureMasterSet(E_SEAL_SC3_PROT_NONPM, u32IsSecure);
2289 HAL_Seal_SecureMasterSet(E_SEAL_SC4_PROT_NONPM, u32IsSecure);
2290 break;
2291 case MODULE_VDEC_EX:
2292 case MODULE_VDEC:
2293 switch(u32ModuleParameter)
2294 {
2295 case E_SEAL_IPGROUP_VDEC_R2:
2296 HAL_Seal_SecureMasterSet(E_SEAL_VD_MHEG5_PROT_NONPM, u32IsSecure);
2297 HAL_Seal_SecureMasterSet(E_SEAL_VD_EVD_R2_NONPM, u32IsSecure);
2298 break;
2299 case E_SEAL_IPGROUP_VDEC_DECODER:
2300 HAL_Seal_SecureMasterSet(E_SEAL_MVD_PROT_NONPM, u32IsSecure);
2301 HAL_Seal_SecureMasterSet(E_SEAL_HVD_PROT_NONPM, u32IsSecure);
2302 HAL_Seal_SecureMasterSet(E_SEAL_EVD_NONPM, u32IsSecure);
2303 HAL_Seal_SecureMasterSet(E_SEAL_MAU_EVD_NONPM, u32IsSecure);
2304 HAL_Seal_SecureMasterSet(E_SEAL_HIREG_EVD_PROT_NONPM, u32IsSecure);
2305 HAL_Seal_SecureMasterSet(E_SEAL_MAU_EVD_LV2_0_NONPM, u32IsSecure);
2306 HAL_Seal_SecureMasterSet(E_SEAL_MFDEC_PROT_NONPM, u32IsSecure);
2307 break;
2308 default:
2309 printf("%s: Unknown module paramater\n", __FUNCTION__);
2310 break;
2311 }
2312 break;
2313 case MODULE_MVOP:
2314 HAL_Seal_SecureMasterSet(E_SEAL_MVOPSUB_PROT_NONPM, u32IsSecure);
2315 HAL_Seal_SecureMasterSet(E_SEAL_MVOP_PROT_NONPM, u32IsSecure);
2316 break;
2317 case MODULE_AUDIO:
2318 HAL_Seal_SecureMasterSet(E_SEAL_VIVALDI2_PROT_NONPM, u32IsSecure);
2319 HAL_Seal_SecureMasterSet(E_SEAL_VIVALDI3_PROT_NONPM, u32IsSecure);
2320 HAL_Seal_SecureMasterSet(E_SEAL_VIVALDI7_PROT_NONPM, u32IsSecure);
2321 break;
2322 case MODULE_TVENCODER:
2323 HAL_Seal_SecureMasterSet(E_SEAL_VE_0_PROT_NONPM, u32IsSecure);
2324 HAL_Seal_SecureMasterSet(E_SEAL_VE_1_PROT_NONPM, u32IsSecure);
2325 HAL_Seal_SecureMasterSet(E_SEAL_VE_2_PROT_NONPM, u32IsSecure);
2326 break;
2327 case MODULE_DIP:
2328 HAL_Seal_SecureMasterSet(E_SEAL_MSC_PROT_NONPM, u32IsSecure);
2329 break;
2330 case MODULE_DMX:
2331 HAL_Seal_SecureMasterSet(E_SEAL_TSP0_PROT_NONPM, u32IsSecure);
2332 HAL_Seal_SecureMasterSet(E_SEAL_TSP1_PROT_NONPM, u32IsSecure);
2333 HAL_Seal_SecureMasterSet(E_SEAL_SPARE1_PROT_NONPM, u32IsSecure);
2334 HAL_Seal_SecureMasterSet(E_SEAL_SPARE3_PROT_NONPM, u32IsSecure);
2335 HAL_Seal_SecureMasterSet(E_SEAL_TSP2_PROT_NONPM, u32IsSecure);
2336 HAL_Seal_SecureMasterSet(E_SEAL_TSP3_PROT_NONPM, u32IsSecure);
2337 HAL_Seal_SecureMasterSet(E_SEAL_TSP5_NONPM, u32IsSecure);
2338 break;
2339 default:
2340 printf("%s, Unsupported ModuleID\n", __FUNCTION__);
2341 break;
2342 }
2343 return TRUE;
2344 }
2345
HAL_Seal_SetSecureRange(MS_PHY u64phy,MS_U32 u32Length,MS_U32 u32IsSecure)2346 MS_BOOL HAL_Seal_SetSecureRange(MS_PHY u64phy, MS_U32 u32Length, MS_U32 u32IsSecure)
2347 {
2348 MS_U8 u8MiuSel;
2349 MS_U64 u64Offset;
2350 MS_U32 u32RegDetEn;
2351 MS_U8 i;
2352 MS_U8 u8Val;
2353 MS_U32 u32RegStartAddr;
2354 MS_U64 u64StartAddr;
2355
2356 _phy_to_miu_offset(u8MiuSel, u64Offset, u64phy);
2357
2358 switch(u8MiuSel)
2359 {
2360 case E_CHIP_MIU_0:
2361 {
2362 u32RegDetEn = REG_SECURE0_DETECT_ENABLE;
2363 break;
2364 }
2365 case E_CHIP_MIU_1:
2366 {
2367 u32RegDetEn = REG_SECURE1_DETECT_ENABLE;
2368 break;
2369 }
2370 default:
2371 {
2372 return FALSE;
2373 }
2374 }
2375
2376 u8Val = HAL_SEAL_NonPmReadByte(u32RegDetEn);
2377
2378 if(u8MiuSel == E_CHIP_MIU_0)
2379 {
2380 u32RegStartAddr = REG_SECURE0_RANGE0_START_ADDR;
2381 }
2382 else if( u8MiuSel == E_CHIP_MIU_1 )
2383 {
2384 u32RegStartAddr = REG_SECURE1_RANGE0_START_ADDR;
2385 }
2386 else
2387 {
2388 return FALSE;
2389 }
2390
2391 if (u32IsSecure) // setup a new securerange
2392 {
2393 for (i=E_HAL_SEAL_SECURE_RANGE_ID0; i<E_HAL_SEAL_SECURE_RANGE_NUM; i++, u32RegStartAddr+=RANGE_ADDR_OFFSET)
2394 {
2395 u64StartAddr = HAL_SEAL_NonPmRead6Byte(u32RegStartAddr);
2396 u64StartAddr = u64StartAddr << 12;
2397 if ((MS_U32)u64StartAddr == (MS_U32)u64Offset && (u8Val & (1<<i)))
2398 {
2399 printf("Secure range overlaps\n");
2400 return TRUE;
2401 }
2402 }
2403
2404 for (i=E_HAL_SEAL_SECURE_RANGE_ID0; i<E_HAL_SEAL_SECURE_RANGE_NUM; i++)
2405 {
2406 if ( !(u8Val & (1<<i)) ) // got a free range
2407 {
2408 return HAL_Seal_SecureRangeSet(i, u64phy, u64phy+u32Length, E_SEAL_SECURE_READ | E_SEAL_SECURE_WRITE);
2409 }
2410 }
2411
2412 return FALSE; // no free range
2413 }
2414 else // disable existing securerange
2415 {
2416 for (i=E_HAL_SEAL_SECURE_RANGE_ID0; i<E_HAL_SEAL_SECURE_RANGE_NUM; i++, u32RegStartAddr+=RANGE_ADDR_OFFSET)
2417 {
2418 u64StartAddr = HAL_SEAL_NonPmRead6Byte(u32RegStartAddr);
2419 u64StartAddr = u64StartAddr << 12;
2420 if ((MS_U32)u64StartAddr == (MS_U32)u64Offset && (u8Val & (1<<i)))
2421 {
2422 return HAL_Seal_SecureRangeSet(i, u64phy, u64phy+u32Length, 0x0);
2423 }
2424 }
2425
2426 return FALSE; // no such range
2427 }
2428 }
2429 #endif
2430