1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
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27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
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47 //
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55 //
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64 //
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66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
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74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2006-2008 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // (¡§MStar Confidential Information¡¨) by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 #include "MsCommon.h"
100 #include "MsTypes.h"
101 #include "regSEAL.h"
102 #include "halSEAL.h"
103 #include "drvSEAL.h"
104 #include "halCHIP.h"
105
106 //-------------------------------------------------------------------------------------------------
107 // Driver Compiler Options
108 //-------------------------------------------------------------------------------------------------
109
110
111 //-------------------------------------------------------------------------------------------------
112 // Local Defines
113 //-------------------------------------------------------------------------------------------------
114 #define HAL_SEAL_DBG(x) //x
115 #define HAL_SEAL_ERR(x, args...) {printf(x, ##args);}\
116
117 //Non PM IP group
118 #define SEAL_NON_PM_GROUP0 \
119 E_SEAL_RIU_DBG_PROT_NONPM, \
120 E_SEAL_FUART1_PROT_NONPM, \
121 E_SEAL_URDMA1_PROT_NONPM, \
122 E_SEAL_VD_MHEG5_PROT_NONPM, \
123 E_SEAL_MAU1_PROT_NONPM, \
124 E_SEAL_HIREG_PROT_NONPM, \
125 E_SEAL_POR_STATUS_PROT_NONPM, \
126 E_SEAL_INTR_CPUINT_PROT_NONPM, \
127 E_SEAL_MIU2_PROT_NONPM, \
128 E_SEAL_USB0_PROT_NONPM, \
129 E_SEAL_USB1_PROT_NONPM, \
130 E_SEAL_UPLL0_PROT_NONPM, \
131 E_SEAL_BDMA_CH0_PROT_NONPM, \
132 E_SEAL_BDMA_CH1_PROT_NONPM, \
133 E_SEAL_UART0_PROT_NONPM, \
134 E_SEAL_CLKGEN2_PROT_NONPM
135
136 #define SEAL_NON_PM_GROUP1 \
137 E_SEAL_CLKGEN0_PROT_NONPM, \
138 E_SEAL_DSCRMB_PROT_NONPM, \
139 E_SEAL_UHC1_PROT_NONPM, \
140 E_SEAL_MHEG5_PROT_NONPM, \
141 E_SEAL_INTR_CTRL1_PROT_NONPM, \
142 E_SEAL_MVD_PROT_NONPM, \
143 E_SEAL_MIU_PROT_NONPM, \
144 E_SEAL_MVOPSUB_PROT_NONPM, \
145 E_SEAL_MVOP_PROT_NONPM, \
146 E_SEAL_TSP0_PROT_NONPM, \
147 E_SEAL_TSP1_PROT_NONPM, \
148 E_SEAL_JPD_PROT_NONPM, \
149 E_SEAL_SEMAPH_PROT_NONPM, \
150 E_SEAL_MAU0_PROT_NONPM, \
151 E_SEAL_L3_AXI_PROT_NONPM, \
152 E_SEAL_INTR_CTRL_PROT_NONPM
153
154 #define SEAL_NON_PM_GROUP2 \
155 E_SEAL_HVD_PROT_NONPM, \
156 E_SEAL_TSP2_PROT_NONPM, \
157 E_SEAL_MCU_ARM_PROT_NONPM, \
158 E_SEAL_CHIP_PROT_NONPM, \
159 E_SEAL_GOP_PROT_NONPM, \
160 E_SEAL_EMAC0_PROT_NONPM, \
161 E_SEAL_EMAC1_PROT_NONPM, \
162 E_SEAL_EMAC2_PROT_NONPM, \
163 E_SEAL_EMAC3_PROT_NONPM, \
164 E_SEAL_UHC0_PROT_NONPM, \
165 E_SEAL_ADC_ATOP_PROT_NONPM, \
166 E_SEAL_ADC_DTOP_PROT_NONPM, \
167 E_SEAL_GE0_PROT_NONPM, \
168 E_SEAL_SMART_PROT_NONPM, \
169 E_SEAL_CI_PROT_NONPM, \
170 E_SEAL_CHIPGPIO_PROT_NONPM
171
172 #define SEAL_NON_PM_GROUP3 \
173 E_SEAL_VP6_PROT_NONPM, \
174 E_SEAL_LDM_DMA0_PROT_NONPM, \
175 E_SEAL_LDM_DMA1_PROT_NONPM, \
176 E_SEAL_SC0_PROT_NONPM, \
177 E_SEAL_SC1_PROT_NONPM, \
178 E_SEAL_SC2_PROT_NONPM, \
179 E_SEAL_SC3_PROT_NONPM, \
180 E_SEAL_SC4_PROT_NONPM, \
181 E_SEAL_CLKGEN1_PROT_NONPM, \
182 E_SEAL_MAILBOX_PROT_NONPM, \
183 E_SEAL_MIIC_PROT_NONPM, \
184 E_SEAL_PCM_PROT_NONPM, \
185 E_SEAL_VDMCU51_IF_PROT_NONPM, \
186 E_SEAL_DMDMCU51_IF_PROT_NONPM, \
187 E_SEAL_VDMCU51_1_IF_PROT_NONPM, \
188 E_SEAL_URDMA_PROT_NONPM
189
190 #define SEAL_NON_PM_GROUP4 \
191 E_SEAL_AFEC_PROT_NONPM, \
192 E_SEAL_COMB_PROT_NONPM, \
193 E_SEAL_VBI_PROT_NONPM, \
194 E_SEAL_SCM_PROT_NONPM, \
195 E_SEAL_UTMI2_PROT_NONPM, \
196 E_SEAL_PATGEN_PROT_NONPM, \
197 E_SEAL_UTMI1_PROT_NONPM, \
198 E_SEAL_UTMI_PROT_NONPM, \
199 E_SEAL_VE_0_PROT_NONPM, \
200 E_SEAL_REG_PIU_NONPM_PROT_NONPM, \
201 E_SEAL_ADC_ATOPB_PROT_NONPM, \
202 E_SEAL_VE_1_PROT_NONPM, \
203 E_SEAL_VE_2_PROT_NONPM, \
204 E_SEAL_SC_GP1_NONPM, \
205 E_SEAL_CHIPGPIO1_NONPM, \
206 E_SEAL_MPIF_PROT_NONPM
207
208 #define SEAL_NON_PM_GROUP5 \
209 E_SEAL_GPD_PROT_NONPM, \
210 E_SEAL_UART1_PROT_NONPM, \
211 E_SEAL_FUART_PROT_NONPM, \
212 E_SEAL_GE1_PROT_NONPM, \
213 E_SEAL_GPU_NONPM, \
214 E_SEAL_TS_SAMPLE_NONPM, \
215 E_SEAL_NR_HSD_PROT_NONPM, \
216 E_SEAL_ANA_MISC2_NONPM, \
217 E_SEAL_ANA_MISC_PROT_NONPM, \
218 E_SEAL_ANA_MISC_GMAC_PROT_NONPM, \
219 E_SEAL_MIU_ATOP_PROT_NONPM, \
220 E_SEAL_NR_PROT_NONPM, \
221 E_SEAL_DI_PROT_NONPM, \
222 E_SEAL_MFE0_PROT_NONPM, \
223 E_SEAL_MFE1_PROT_NONPM, \
224 E_SEAL_ADC_DTOPB_PROT_NONPM
225
226 #define SEAL_NON_PM_GROUP6 \
227 E_SEAL_NFIE0_PROT_NONPM, \
228 E_SEAL_NFIE1_PROT_NONPM, \
229 E_SEAL_NFIE2_PROT_NONPM, \
230 E_SEAL_VIVALDIc_PROT_NONPM, \
231 E_SEAL_VIVALDId_PROT_NONPM, \
232 E_SEAL_MIIC0_PROT_NONPM, \
233 E_SEAL_MIIC1_PROT_NONPM, \
234 E_SEAL_MIIC2_PROT_NONPM, \
235 E_SEAL_MIIC3_PROT_NONPM, \
236 E_SEAL_MOD2_PROT_NONPM, \
237 E_SEAL_CLKGEN_DMD_PROT_NONPM, \
238 E_SEAL_DEMOD_0_PROT_NONPM, \
239 E_SEAL_DEMOD_1_PROT_NONPM, \
240 E_SEAL_DEMOD_2_PROT_NONPM, \
241 E_SEAL_DEMOD_3_PROT_NONPM, \
242 E_SEAL_DEMOD_4_PROT_NONPM
243
244 #define SEAL_NON_PM_GROUP7 \
245 E_SEAL_DEMOD_5_PROT_NONPM, \
246 E_SEAL_DEMOD_6_PROT_NONPM, \
247 E_SEAL_DEMOD_7_PROT_NONPM, \
248 E_SEAL_DMD_ANA_MISC_PROT_NONPM, \
249 E_SEAL_AUR20_PROT_NONPM, \
250 E_SEAL_VIVALDI0_PROT_NONPM, \
251 E_SEAL_VIVALDI1_PROT_NONPM, \
252 E_SEAL_VIVALDI2_PROT_NONPM, \
253 E_SEAL_VIVALDI3_PROT_NONPM, \
254 E_SEAL_VIVALDI4_PROT_NONPM, \
255 E_SEAL_VIVALDI5_PROT_NONPM, \
256 E_SEAL_AU_MAU_NONPM, \
257 E_SEAL_AU_GDMA_NONPM, \
258 E_SEAL_CLKGEN_SC_FE, \
259 E_SEAL_CLKGEN_SC_BE, \
260 E_SEAL_CLKGEN_SC_GP2
261
262 #define SEAL_NON_PM_GROUP8 \
263 E_SEAL_SC_GPLUS, \
264 E_SEAL_USB2_PROT_NONPM, \
265 E_SEAL_UHC2_PROT_NONPM, \
266 E_SEAL_TSO_PROT_NONPM, \
267 E_SEAL_DRM_SECURE_PROT_NONPM, \
268 E_SEAL_DSCRMB2_PROT_NONPM, \
269 E_SEAL_DSCRMB3_PROT_NONPM, \
270 E_SEAL_GPD0_PROT_NONPM, \
271 E_SEAL_GPD1_PROT_NONPM, \
272 E_SEAL_GOP0G_0_PROT_NONPM, \
273 E_SEAL_GOP0G_1_PROT_NONPM, \
274 E_SEAL_GOP0G_ST_PROT_NONPM, \
275 E_SEAL_GOP1G_0_PROT_NONPM, \
276 E_SEAL_GOP1G_1_PROT_NONPM, \
277 E_SEAL_GOP1G_ST_PROT_NONPM, \
278 E_SEAL_GOP2G_0_PROT_NONPM
279
280 #define SEAL_NON_PM_GROUP9 \
281 E_SEAL_GOP2G_1_PROT_NONPM, \
282 E_SEAL_GOP2G_ST_PROT_NONPM, \
283 E_SEAL_GOP3G_0_PROT_NONPM, \
284 E_SEAL_GOP3G_1_PROT_NONPM, \
285 E_SEAL_GOP3G_ST_PROT_NONPM, \
286 E_SEAL_GOPD_PROT_NONPM, \
287 E_SEAL_SDIO0_PROT_NONPM, \
288 E_SEAL_SPARE1_PROT_NONPM, \
289 E_SEAL_SPARE3_PROT_NONPM, \
290 E_SEAL_MIU_ARB256_PROT_NONPM, \
291 E_SEAL_TZPC_NONPM2_NONPM, \
292 E_SEAL_GOP4G_0_PROT_NONPM, \
293 E_SEAL_MIIC4_PROT_NONPM, \
294 E_SEAL_MIIC5_PROT_NONPM, \
295 E_SEAL_GOP4G_1_PROT_NONPM, \
296 E_SEAL_GOP4G_ST_PROT_NONPM
297
298 #define SEAL_NON_PM_GROUP10 \
299 E_SEAL_COMBO_PHY2_P0_PROT_NONPM, \
300 E_SEAL_SDIO1_PROT_NONPM, \
301 E_SEAL_SDIO2_PROT_NONPM, \
302 E_SEAL_SEC_R2_PROT_NONPM, \
303 E_SEAL_SEC_MAU0_PROT_NONPM, \
304 E_SEAL_DSCRMB4_PROT_NONPM, \
305 E_SEAL_MOBF_PROT_NONPM, \
306 E_SEAL_DC_SCL_PROT_NONPM, \
307 E_SEAL_JPD1_PROT_NONPM, \
308 E_SEAL_JPD2_PROT_NONPM, \
309 E_SEAL_JPD3_PROT_NONPM, \
310 E_SEAL_CMDQ_PROT_NONPM, \
311 E_SEAL_USBBC0_PROT_NONPM, \
312 E_SEAL_USBBC1_PROT_NONPM, \
313 E_SEAL_USBBC2_PROT_NONPM, \
314 E_SEAL_SECURERANGE0_PROT_NONPM
315
316 #define SEAL_NON_PM_GROUP11 \
317 E_SEAL_SECURERANGE1_PROT_NONPM, \
318 E_SEAL_TZPC_NONPM_PROT_NONPM, \
319 E_SEAL_NFIE3_PROT_NONPM, \
320 E_SEAL_DSCRMB5_PROT_NONPM, \
321 E_SEAL_TSO1_NONPM, \
322 E_SEAL_EMMC_PLL_PROT_NONPM, \
323 E_SEAL_MSC_PROT_NONPM, \
324 E_SEAL_MSC1_NONPM, \
325 E_SEAL_PATGEN_CODEC_PROT_NONPM, \
326 E_SEAL_PATGEN_VIV_PROT_NONPM, \
327 E_SEAL_PATGEN_CPU_PROT_NONPM, \
328 E_SEAL_PATGEN_GPU_PROT_NONPM, \
329 E_SEAL_PATGEN_DEMOD_PROT_NONPM, \
330 E_SEAL_PATGEN_TSP_PROT_NONPM, \
331 E_SEAL_PATGEN_DVI_PROT_NONPM, \
332 E_SEAL_PATGEN_EVD_PROT_NONPM
333
334 #define SEAL_NON_PM_GROUP12 \
335 E_SEAL_PATGEN_SC0_PROT_NONPM, \
336 E_SEAL_PATGEN_SC1_PROT_NONPM, \
337 E_SEAL_PATGEN_SC2_PROT_NONPM, \
338 E_SEAL_PAD_MUX_NONPM, \
339 E_SEAL_COMB1_PROT_NONPM, \
340 E_SEAL_COMB2_PROT_NONPM, \
341 E_SEAL_COMB3_PROT_NONPM, \
342 E_SEAL_COMB4_PROT_NONPM, \
343 E_SEAL_COMB5_PROT_NONPM, \
344 E_SEAL_MSPI0_PROT_NONPM, \
345 E_SEAL_MSPI1_PROT_NONPM, \
346 E_SEAL_MSPI_MCARD_PROT_NONPM, \
347 E_SEAL_DMD_MCU2_PROT_NONPM, \
348 E_SEAL_VIVALDI6_PROT_NONPM, \
349 E_SEAL_VIVALDI7_PROT_NONPM, \
350 E_SEAL_GMAC0_PROT_NONPM
351
352 #define SEAL_NON_PM_GROUP13 \
353 E_SEAL_GMAC1_PROT_NONPM, \
354 E_SEAL_GMAC2_PROT_NONPM, \
355 E_SEAL_GMAC3_PROT_NONPM, \
356 E_SEAL_GMAC4_PROT_NONPM, \
357 E_SEAL_PCM2_PROT_NONPM, \
358 E_SEAL_TSP3_PROT_NONPM, \
359 E_SEAL_EVD_NONPM, \
360 E_SEAL_DYN_SCL_PROT_NONPM, \
361 E_SEAL_VP9_TOP_PROT_NONPM, \
362 E_SEAL_GPU_PLL_PROT_NONPM, \
363 E_SEAL_MIU_ARB_SC_NONPM, \
364 E_SEAL_MIU_ARB2_SC_NONPM, \
365 E_SEAL_CODEC_MRQ_PROT_NONPM, \
366 E_SEAL_MIU_ARB_NONPM, \
367 E_SEAL_MIU_ATOP2_PROT_NONPM, \
368 E_SEAL_MIU_ARB2_NONPM
369
370 #define SEAL_NON_PM_GROUP14 \
371 E_SEAL_GE2_NONPM, \
372 E_SEAL_GE3_NONPM, \
373 E_SEAL_AU_R2_1_NONPM, \
374 E_SEAL_AU_MAU_1_NONPM, \
375 E_SEAL_AU_GDMA_1_NONPM, \
376 E_SEAL_VD_EVD_R2_NONPM, \
377 E_SEAL_MAU_EVD_NONPM, \
378 E_SEAL_HIREG_EVD_PROT_NONPM, \
379 E_SEAL_MAU1_LV2_0_NONPM, \
380 E_SEAL_MAU1_LV2_1_NONPM, \
381 E_SEAL_MAU_EVD_LV2_0_NONPM, \
382 E_SEAL_MAU_EVD_LV2_1_NONPM, \
383 E_SEAL_SEC_MAU_LV2_0_NONPM, \
384 E_SEAL_SEC_MAU_LV2_1_NONPM, \
385 E_SEAL_TSP5_NONPM, \
386 E_SEAL_VIVALDI8_PROT_NONPM
387
388 #define SEAL_NON_PM_GROUP15 \
389 E_SEAL_VIVALDI9_PROT_NONPM, \
390 E_SEAL_VIVALDIa_0_PROT_NONPM, \
391 E_SEAL_VIVALDIa_1_PROT_NONPM, \
392 E_SEAL_VIVALDIa_2_PROT_NONPM, \
393 E_SEAL_VIVALDIa_3_PROT_NONPM, \
394 E_SEAL_VIVALDIb_0_PROT_NONPM, \
395 E_SEAL_VIVALDIb_1_PROT_NONPM, \
396 E_SEAL_VIVALDIb_2_PROT_NONPM, \
397 E_SEAL_VIVALDIb_3_PROT_NONPM , \
398 E_SEAL_COMBO_PHY0_P0_PROT_NONPM, \
399 E_SEAL_COMBO_PHY1_P0_PROT_NONPM, \
400 E_SEAL_DVI_DTOP_DUAL_P0_PROT_NONPM, \
401 E_SEAL_DVI_RSV_DUAL_P0_PROT_NONPM, \
402 E_SEAL_HDCP_DUAL_P0_PROT_NONPM, \
403 E_SEAL_HDMI_DUAL_0_PROT_NONPM, \
404 E_SEAL_HDMI2_DUAL_0_PROT_NONPM
405
406 #define SEAL_NON_PM_GROUP16 \
407 E_SEAL_HDMI3_DUAL_0_PROT_NONPM, \
408 E_SEAL_HDCPKEY_PROT_NONPM, \
409 E_SEAL_COMBO_GP_TOP_PROT_NONPM, \
410 E_SEAL_SECURE_TZPC_PROT_NONPM, \
411 E_SEAL_X32_GPUAPB0_NONPM, \
412 E_SEAL_X32_GPUAPB1_NONPM, \
413 E_SEAL_X32_GPUAPB2_NONPM, \
414 E_SEAL_X32_EMAC0_NONPM, \
415 E_SEAL_X32_EMAC1_NONPM, \
416 E_SEAL_X32_EMAC2_NONPM, \
417 E_SEAL_DUMMY, \
418 E_SEAL_DUMMY, \
419 E_SEAL_DUMMY, \
420 E_SEAL_DUMMY, \
421 E_SEAL_DUMMY, \
422 E_SEAL_DUMMY
423
424 #define SEAL_NON_PM_GROUP17 \
425 E_SEAL_DUMMY, \
426 E_SEAL_DUMMY, \
427 E_SEAL_DUMMY, \
428 E_SEAL_DUMMY, \
429 E_SEAL_DUMMY, \
430 E_SEAL_DUMMY, \
431 E_SEAL_DUMMY, \
432 E_SEAL_DUMMY, \
433 E_SEAL_DUMMY, \
434 E_SEAL_DUMMY, \
435 E_SEAL_DUMMY, \
436 E_SEAL_DUMMY, \
437 E_SEAL_DUMMY, \
438 E_SEAL_DUMMY, \
439 E_SEAL_DUMMY, \
440 E_SEAL_DUMMY
441
442 #define SEAL_NON_PM_GROUP18 \
443 E_SEAL_DUMMY, \
444 E_SEAL_DUMMY, \
445 E_SEAL_DUMMY, \
446 E_SEAL_DUMMY, \
447 E_SEAL_DUMMY, \
448 E_SEAL_DUMMY, \
449 E_SEAL_DUMMY, \
450 E_SEAL_DUMMY, \
451 E_SEAL_DUMMY, \
452 E_SEAL_DUMMY, \
453 E_SEAL_DUMMY, \
454 E_SEAL_DUMMY, \
455 E_SEAL_DUMMY, \
456 E_SEAL_DUMMY, \
457 E_SEAL_DUMMY, \
458 E_SEAL_DUMMY
459
460 #define SEAL_NON_PM_GROUP19 \
461 E_SEAL_DUMMY, \
462 E_SEAL_DUMMY, \
463 E_SEAL_DUMMY, \
464 E_SEAL_DUMMY, \
465 E_SEAL_DUMMY, \
466 E_SEAL_DUMMY, \
467 E_SEAL_DUMMY, \
468 E_SEAL_DUMMY, \
469 E_SEAL_DUMMY, \
470 E_SEAL_DUMMY, \
471 E_SEAL_DUMMY, \
472 E_SEAL_DUMMY, \
473 E_SEAL_DUMMY, \
474 E_SEAL_DUMMY, \
475 E_SEAL_DUMMY, \
476 E_SEAL_DUMMY
477
478 #define SEAL_NON_PM_GROUP20 \
479 E_SEAL_DUMMY, \
480 E_SEAL_DUMMY, \
481 E_SEAL_DUMMY, \
482 E_SEAL_DUMMY, \
483 E_SEAL_DUMMY, \
484 E_SEAL_DUMMY, \
485 E_SEAL_DUMMY, \
486 E_SEAL_DUMMY, \
487 E_SEAL_DUMMY, \
488 E_SEAL_DUMMY, \
489 E_SEAL_DUMMY, \
490 E_SEAL_DUMMY, \
491 E_SEAL_DUMMY, \
492 E_SEAL_DUMMY, \
493 E_SEAL_DUMMY, \
494 E_SEAL_DUMMY
495
496 #define SEAL_NON_PM_GROUP21 \
497 E_SEAL_DUMMY, \
498 E_SEAL_DUMMY, \
499 E_SEAL_DUMMY, \
500 E_SEAL_DUMMY, \
501 E_SEAL_DUMMY, \
502 E_SEAL_DUMMY, \
503 E_SEAL_DUMMY, \
504 E_SEAL_DUMMY, \
505 E_SEAL_DUMMY, \
506 E_SEAL_DUMMY, \
507 E_SEAL_DUMMY, \
508 E_SEAL_DUMMY, \
509 E_SEAL_DUMMY, \
510 E_SEAL_DUMMY, \
511 E_SEAL_DUMMY, \
512 E_SEAL_DUMMY
513
514 #define SEAL_NON_PM_GROUP22 \
515 E_SEAL_DUMMY, \
516 E_SEAL_DUMMY, \
517 E_SEAL_DUMMY, \
518 E_SEAL_DUMMY, \
519 E_SEAL_DUMMY, \
520 E_SEAL_DUMMY, \
521 E_SEAL_DUMMY, \
522 E_SEAL_DUMMY, \
523 E_SEAL_DUMMY, \
524 E_SEAL_DUMMY, \
525 E_SEAL_DUMMY, \
526 E_SEAL_DUMMY, \
527 E_SEAL_DUMMY, \
528 E_SEAL_DUMMY, \
529 E_SEAL_DUMMY, \
530 E_SEAL_DUMMY
531
532 #define SEAL_NON_PM_GROUP23 \
533 E_SEAL_DUMMY, \
534 E_SEAL_DUMMY, \
535 E_SEAL_DUMMY, \
536 E_SEAL_DUMMY, \
537 E_SEAL_DUMMY, \
538 E_SEAL_DUMMY, \
539 E_SEAL_DUMMY, \
540 E_SEAL_DDI_1_PROT_NONPM, \
541 E_SEAL_DDI_0_PROT_NONPM, \
542 E_SEAL_DIP_1_PROT_NONPM, \
543 E_SEAL_DIP_0_PROT_NONPM, \
544 E_SEAL_PDW1_PROT_NONPM, \
545 E_SEAL_PDW0_PROT_NONPM, \
546 E_SEAL_DWIN1_PROT_NONPM, \
547 E_SEAL_DWIN0_PROT_NONPM, \
548 E_SEAL_DIP_PROT_NONPM
549
550 //PM IP group
551 #define SEAL_PM_GROUP0 \
552 E_SEAL_RIU_DBG_PROT_PM, \
553 E_SEAL_MENULOAD_PROT_PM, \
554 E_SEAL_GDMA_PROT_PM, \
555 E_SEAL_DDC_PROT_PM, \
556 E_SEAL_PM_PATGEN_PROT_PM, \
557 E_SEAL_PM_POR_PROT_PM, \
558 E_SEAL_ISP_PROT_PM, \
559 E_SEAL_FSP_PROT_PM, \
560 E_SEAL_QSPI_PROT_PM, \
561 E_SEAL_PM_SLEEP_PROT_PM, \
562 E_SEAL_PM_GPIO_PROT_PM, \
563 E_SEAL_MCU_PROT_PM, \
564 E_SEAL_PM_CEC_PROT_PM, \
565 E_SEAL_PM_RTC0_PROT_PM, \
566 E_SEAL_PM_RTC1_PROT_PM, \
567 E_SEAL_PM_SAR_PROT_PM
568
569 #define SEAL_PM_GROUP1 \
570 E_SEAL_PM_AV_LINK_PROT_PM, \
571 E_SEAL_PM_TOP_PROT_PM, \
572 E_SEAL_MHL_CBUS_PROT_PM, \
573 E_SEAL_EFUSE_PROT_PM, \
574 E_SEAL_IRQ_PROT_PM, \
575 E_SEAL_CACHE_PROT_PM, \
576 E_SEAL_XDMIU_PROT_PM, \
577 E_SEAL_PM_MISC_PROT_PM, \
578 E_SEAL_PM_MHL_CBUS_PROT_PM, \
579 E_SEAL_WDT_PROT_PM, \
580 E_SEAL_TIMER0_PROT_PM, \
581 E_SEAL_TIMER1_PROT_PM, \
582 E_SEAL_TIMER2_PROT_PM, \
583 E_SEAL_ALBANY0_PROT_PM, \
584 E_SEAL_ALBANY1_PROT_PM, \
585 E_SEAL_ALBANY2_PROT_PM
586
587 #define SEAL_PM_GROUP2 \
588 E_SEAL_DID_KEY_PROT_PM, \
589 E_SEAL_TZPC_PROT_PM, \
590 E_SEAL_REG_PIU_MISC_0_PROT_PM, \
591 E_SEAL_IR_PROT_PM, \
592 E_SEAL_PM_SPARE0_PROT_PM, \
593 E_SEAL_PM_SPARE1_PROT_PM, \
594 E_SEAL_SCDC_0_PROT_PM, \
595 E_SEAL_SCDC_1_PROT_PM, \
596 E_SEAL_SCDC_2_PROT_PM, \
597 E_SEAL_SCDC_3_PROT_PM, \
598 E_SEAL_DUMMY, \
599 E_SEAL_DUMMY, \
600 E_SEAL_DUMMY, \
601 E_SEAL_DUMMY, \
602 E_SEAL_DUMMY, \
603 E_SEAL_DUMMY
604
605 //processor group
606 #define SEAL_PROCESSOR_GROUP0 \
607 E_SEAL_DBBUS, \
608 E_SEAL_MCU51, \
609 E_SEAL_CPU2, \
610 E_SEAL_VD_R2, \
611 E_SEAL_SECURE_R2, \
612 E_SEAL_SC, \
613 E_SEAL_CMDQ, \
614 E_SEAL_HEMCU ,\
615 E_SEAL_PROCESSOR_NUM,\
616
617 //lock group
618 #define SEAL_LOCK_GROUP_DUMMY \
619 E_SEAL_LOCK_DUMMY, \
620 E_SEAL_LOCK_DUMMY, \
621 E_SEAL_LOCK_DUMMY, \
622 E_SEAL_LOCK_DUMMY, \
623 E_SEAL_LOCK_DUMMY, \
624 E_SEAL_LOCK_DUMMY, \
625 E_SEAL_LOCK_DUMMY, \
626 E_SEAL_LOCK_DUMMY, \
627 E_SEAL_LOCK_DUMMY, \
628 E_SEAL_LOCK_DUMMY, \
629 E_SEAL_LOCK_DUMMY, \
630 E_SEAL_LOCK_DUMMY, \
631 E_SEAL_LOCK_DUMMY, \
632 E_SEAL_LOCK_DUMMY, \
633 E_SEAL_LOCK_DUMMY, \
634 E_SEAL_LOCK_DUMMY
635
636 #define SEAL_LOCK_GROUP0 \
637 E_SEAL_SC_WP_DIPW, \
638 E_SEAL_SC_RP_DIPW, \
639 E_SEAL_SC_WP_DIPR, \
640 E_SEAL_SC_RP_DIPR, \
641 E_SEAL_AUDIO_LCL_R2_WR_PROTN_0, \
642 E_SEAL_AUDIO_LCL_R2_WR_PROTN_1, \
643 E_SEAL_AUDIO_LCL_R2_WR_PROTN_2, \
644 E_SEAL_AUDIO_LCL_R2_WR_PROTN_3, \
645 E_SEAL_AUDIO_SCL_R2_WR_PROTN_0, \
646 E_SEAL_AUDIO_SCL_R2_WR_PROTN_1, \
647 E_SEAL_AUDIO_SCL_R2_WR_PROTN_2, \
648 E_SEAL_AUDIO_SCL_R2_WR_PROTN_3, \
649 E_SEAL_SECURE_R2_WR_PROTN_0, \
650 E_SEAL_SECURE_R2_WR_PROTN_1, \
651 E_SEAL_SECURE_R2_WR_PROTN_2, \
652 E_SEAL_SECURE_R2_WR_PROTN_3
653
654 #define SEAL_LOCK_GROUP1 \
655 E_SEAL_CIPHERENG_WP_SYSKEY, \
656 E_SEAL_CIPHERENG_RP_SYSKEY, \
657 E_SEAL_DSCRMB_WP_RIV0, \
658 E_SEAL_DSCRMB_RP_RIV0, \
659 E_SEAL_DSCRMB_WP_RIV1, \
660 E_SEAL_DSCRMB_RP_RIV1, \
661 E_SEAL_DSCRMB_WP_WDATA, \
662 E_SEAL_DSCRMB_RP_WDATA, \
663 E_SEAL_DSCRMB_WP_RIV2, \
664 E_SEAL_DSCRMB_RP_RIV2, \
665 E_SEAL_DSCRMB_WP_RIV3, \
666 E_SEAL_DSCRMB_RP_RIV3, \
667 E_SEAL_SC2_WP_SCM_M, \
668 E_SEAL_SC2_RP_SCM_M, \
669 E_SEAL_MVOP_WP_TLB, \
670 E_SEAL_AUDIO_PAS_PROTN
671
672 #define SEAL_LOCK_GROUP2 \
673 E_SEAL_DSCRMB_RP_RDATA, \
674 E_SEAL_LOCK_DUMMY, \
675 E_SEAL_LOCK_DUMMY, \
676 E_SEAL_LOCK_DUMMY, \
677 E_SEAL_RNG_PROTECT, \
678 E_SEAL_RSA_PROTECT, \
679 E_SEAL_SHA_PROTECT, \
680 E_SEAL_LOCK_DUMMY, \
681 E_SEAL_EVD_R2_WR_PROTN_0, \
682 E_SEAL_EVD_R2_WR_PROTN_1, \
683 E_SEAL_EVD_R2_WR_PROTN_2, \
684 E_SEAL_EVD_R2_WR_PROTN_3, \
685 E_SEAL_HVD_R2_WR_PROTN_0, \
686 E_SEAL_HVD_R2_WR_PROTN_1, \
687 E_SEAL_HVD_R2_WR_PROTN_2, \
688 E_SEAL_HVD_R2_WR_PROTN_3
689
690 #define SEAL_LOCK_GROUP3 \
691 E_SEAL_HVD_ES0_BUF, \
692 E_SEAL_HVD_ES1_BUF, \
693 E_SEAL_HVD_ES2_BUF, \
694 E_SEAL_LOCK_DUMMY, \
695 E_SEAL_MFE0_ES_BUF, \
696 E_SEAL_MVD_WR_PROTN_0, \
697 E_SEAL_MVD_WR_PROTN_1, \
698 E_SEAL_MVD_WR_PROTN_2, \
699 E_SEAL_EVD_0_WR_PROTN_0, \
700 E_SEAL_EVD_1_WR_PROTN_0, \
701 E_SEAL_MHEG5_WR_PROTN_0, \
702 E_SEAL_AUDIO_DSP_ES_PROTN, \
703 E_SEAL_AUDIO_DSP_CACHE_PROTN, \
704 E_SEAL_EVD_0_WR_PROTN_1, \
705 E_SEAL_EVD_1_WR_PROTN_1, \
706 E_SEAL_VP9_TOP
707
708 #define SEAL_LOCK_GROUP4 \
709 E_SEAL_TSO_WP_TSOFI, \
710 E_SEAL_TSO_RP_TSOFI, \
711 E_SEAL_MMFI_WP_MMFI0, \
712 E_SEAL_MMFI_RP_MMFI0, \
713 E_SEAL_MMFI_WP_MMFI1, \
714 E_SEAL_MMFI_RP_MMFI1, \
715 E_SEAL_TSP0_WP_PVR, \
716 E_SEAL_TSP0_RP_PVR, \
717 E_SEAL_TSP0_WP_PVR1, \
718 E_SEAL_TSP0_RP_PVR1, \
719 E_SEAL_TSP0_WP_FILEIN, \
720 E_SEAL_TSP0_RP_FILEIN, \
721 E_SEAL_TSP0_WP_QMEM, \
722 E_SEAL_TSP0_RP_QMEM, \
723 E_SEAL_TSP0_WP_FW, \
724 E_SEAL_TSP0_RP_FW
725
726 #define SEAL_LOCK_GROUP5 \
727 E_SEAL_VE_WP, \
728 E_SEAL_VE_RP, \
729 E_SEAL_SC_WP_OD, \
730 E_SEAL_SC_RP_OD, \
731 E_SEAL_SC_WP_SCM_M, \
732 E_SEAL_SC_RP_SCM_M, \
733 E_SEAL_SC_WP_SCM_S, \
734 E_SEAL_SC_RP_SCM_S, \
735 E_SEAL_SC_WP_PDW0, \
736 E_SEAL_SC_RP_PDW0, \
737 E_SEAL_SC_WP_PDW1, \
738 E_SEAL_SC_RP_PDW1, \
739 E_SEAL_SC_WP_OPW, \
740 E_SEAL_SC_RP_OPW, \
741 E_SEAL_GOPD_PROTN, \
742 E_SEAL_AUDIO_AL_PROTN
743
744 #define SEAL_LOCK_GROUP6 \
745 E_SEAL_GE0_SB_PROTN, \
746 E_SEAL_GE0_DB_PROTN, \
747 E_SEAL_GE1_SB_PROTN, \
748 E_SEAL_GE1_DB_PROTN, \
749 E_SEAL_LOCK_DUMMY, \
750 E_SEAL_LOCK_DUMMY, \
751 E_SEAL_LOCK_DUMMY, \
752 E_SEAL_LOCK_DUMMY, \
753 E_SEAL_LOCK_DUMMY, \
754 E_SEAL_LOCK_DUMMY, \
755 E_SEAL_LOCK_DUMMY, \
756 E_SEAL_LOCK_DUMMY, \
757 E_SEAL_LOCK_DUMMY, \
758 E_SEAL_LOCK_DUMMY, \
759 E_SEAL_LOCK_DUMMY, \
760 E_SEAL_LOCK_DUMMY
761
762 #define SEAL_LOCK_GROUP7 \
763 E_SEAL_LOCK_DUMMY, \
764 E_SEAL_LOCK_DUMMY, \
765 E_SEAL_LOCK_DUMMY, \
766 E_SEAL_LOCK_DUMMY, \
767 E_SEAL_LOCK_DUMMY, \
768 E_SEAL_LOCK_DUMMY, \
769 E_SEAL_LOCK_DUMMY, \
770 E_SEAL_LOCK_DUMMY, \
771 E_SEAL_LOCK_DUMMY, \
772 E_SEAL_LOCK_DUMMY, \
773 E_SEAL_LOCK_DUMMY, \
774 E_SEAL_LOCK_DUMMY, \
775 E_SEAL_LOCK_DUMMY, \
776 E_SEAL_LOCK_DUMMY, \
777 E_SEAL_LOCK_DUMMY, \
778 E_SEAL_LOCK_DUMMY
779
780 #define SEAL_LOCK_GROUP8 \
781 E_SEAL_LOCK_DUMMY, \
782 E_SEAL_LOCK_DUMMY, \
783 E_SEAL_LOCK_DUMMY, \
784 E_SEAL_LOCK_DUMMY, \
785 E_SEAL_LOCK_DUMMY, \
786 E_SEAL_LOCK_DUMMY, \
787 E_SEAL_LOCK_DUMMY, \
788 E_SEAL_LOCK_DUMMY, \
789 E_SEAL_LOCK_DUMMY, \
790 E_SEAL_LOCK_DUMMY, \
791 E_SEAL_LOCK_DUMMY, \
792 E_SEAL_LOCK_DUMMY, \
793 E_SEAL_LOCK_DUMMY, \
794 E_SEAL_LOCK_DUMMY, \
795 E_SEAL_LOCK_DUMMY, \
796 E_SEAL_LOCK_DUMMY
797
798 #define SEAL_LOCK_GROUP9 \
799 E_SEAL_LOCK_DUMMY, \
800 E_SEAL_LOCK_DUMMY, \
801 E_SEAL_LOCK_DUMMY, \
802 E_SEAL_LOCK_DUMMY, \
803 E_SEAL_LOCK_DUMMY, \
804 E_SEAL_LOCK_DUMMY, \
805 E_SEAL_LOCK_DUMMY, \
806 E_SEAL_LOCK_DUMMY, \
807 E_SEAL_LOCK_DUMMY, \
808 E_SEAL_LOCK_DUMMY, \
809 E_SEAL_LOCK_DUMMY, \
810 E_SEAL_LOCK_DUMMY, \
811 E_SEAL_LOCK_DUMMY, \
812 E_SEAL_LOCK_DUMMY, \
813 E_SEAL_LOCK_DUMMY, \
814 E_SEAL_LOCK_DUMMY
815
816 #define SEAL_LOCK_GROUP10 \
817 E_SEAL_FCIE_WR_PROT_ENABLE_0, \
818 E_SEAL_FCIE_WR_PROT_ENABLE_1, \
819 E_SEAL_FCIE_WR_PROT_ENABLE_2, \
820 E_SEAL_FCIE_WR_PROT_ENABLE_3, \
821 E_SEAL_HDCP_RIU_R_PROTN, \
822 E_SEAL_HDCP_XIU_R_PROTN, \
823 E_SEAL_HDCP_RIU_W_PROTN, \
824 E_SEAL_HDCP_XIU_W_PROTN, \
825 E_SEAL_FCIE_WR_PROT_0_LOCK, \
826 E_SEAL_FCIE_WR_PROT_1_LOCK, \
827 E_SEAL_FCIE_WR_PROT_2_LOCK, \
828 E_SEAL_FCIE_WR_PROT_3_LOCK, \
829 E_SEAL_LOCK_DUMMY, \
830 E_SEAL_LOCK_DUMMY, \
831 E_SEAL_LOCK_DUMMY, \
832 E_SEAL_LOCK_DUMMY
833
834
835 //-------------------------------------------------------------------------------------------------
836 // Local Structures
837 //-------------------------------------------------------------------------------------------------
838 const eSeal_IP NonPmIpTbl[SEAL_NONPM_TBL_IP_NUM] =
839 {
840 SEAL_NON_PM_GROUP0, SEAL_NON_PM_GROUP1, SEAL_NON_PM_GROUP2,
841 SEAL_NON_PM_GROUP3, SEAL_NON_PM_GROUP4, SEAL_NON_PM_GROUP5,
842 SEAL_NON_PM_GROUP6, SEAL_NON_PM_GROUP7, SEAL_NON_PM_GROUP8,
843 SEAL_NON_PM_GROUP9, SEAL_NON_PM_GROUP10, SEAL_NON_PM_GROUP11,
844 SEAL_NON_PM_GROUP12, SEAL_NON_PM_GROUP13, SEAL_NON_PM_GROUP14,
845 SEAL_NON_PM_GROUP15, SEAL_NON_PM_GROUP16, SEAL_NON_PM_GROUP17,
846 SEAL_NON_PM_GROUP18, SEAL_NON_PM_GROUP19, SEAL_NON_PM_GROUP20,
847 SEAL_NON_PM_GROUP21, SEAL_NON_PM_GROUP22, SEAL_NON_PM_GROUP23
848 };
849
850 const eSeal_IP PmIpTbl[SEAL_PM_TBL_IP_NUM] =
851 {
852 SEAL_PM_GROUP0, SEAL_PM_GROUP1, SEAL_PM_GROUP2
853 };
854
855 const eSeal_ProcessorId ProcessorTbl[SEAL_TBL_PROCESSOR_NUM] =
856 {
857 SEAL_PROCESSOR_GROUP0
858 };
859
860 const eSeal_Lock LockTbl[SEAL_TBL_LOCK_NUM] =
861 {
862 SEAL_LOCK_GROUP10, /*0x64*/
863 SEAL_LOCK_GROUP_DUMMY,
864 SEAL_LOCK_GROUP_DUMMY,
865 SEAL_LOCK_GROUP_DUMMY,
866 SEAL_LOCK_GROUP_DUMMY,
867 SEAL_LOCK_GROUP_DUMMY,
868 SEAL_LOCK_GROUP_DUMMY,
869 SEAL_LOCK_GROUP_DUMMY,
870 SEAL_LOCK_GROUP_DUMMY,
871 SEAL_LOCK_GROUP_DUMMY,
872 SEAL_LOCK_GROUP_DUMMY,
873 SEAL_LOCK_GROUP_DUMMY,
874 SEAL_LOCK_GROUP_DUMMY,
875 SEAL_LOCK_GROUP_DUMMY,
876 SEAL_LOCK_GROUP_DUMMY,
877 SEAL_LOCK_GROUP_DUMMY,
878 SEAL_LOCK_GROUP0, /*0x74*/
879 SEAL_LOCK_GROUP1,
880 SEAL_LOCK_GROUP2,
881 SEAL_LOCK_GROUP3,
882 SEAL_LOCK_GROUP4,
883 SEAL_LOCK_GROUP5,
884 SEAL_LOCK_GROUP6,
885 SEAL_LOCK_GROUP7,
886 SEAL_LOCK_GROUP8,
887 SEAL_LOCK_GROUP9
888 };
889 //-------------------------------------------------------------------------------------------------
890 // Global Variables
891 //-------------------------------------------------------------------------------------------------
892
893 //-------------------------------------------------------------------------------------------------
894 // Local Variables
895 //-------------------------------------------------------------------------------------------------
896 static MS_VIRT _gSEAL_NonPmMapBase = 0;
897 static MS_VIRT _gSEAL_PmMapBase = 0;
898
899 //-------------------------------------------------------------------------------------------------
900 // Debug Functions
901 //-------------------------------------------------------------------------------------------------
902
903 //-------------------------------------------------------------------------------------------------
904 // Local Functions
905 //-------------------------------------------------------------------------------------------------
906
907 ////////////////////////////////////////////////////////////////////////////////
908 /// @brief \b Function \b Name: HAL_SEAL_NonPmReadByte
909 /// @brief \b Function \b Description: read 1 Byte data
910 /// @param <IN> \b u32RegAddr: register address
911 /// @param <OUT> \b None :
912 /// @param <RET> \b MS_U8
913 /// @param <GLOBAL> \b None :
914 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_NonPmReadByte(MS_U32 u32RegAddr)915 MS_U8 HAL_SEAL_NonPmReadByte(MS_U32 u32RegAddr)
916 {
917 return ((volatile MS_U8*)(_gSEAL_NonPmMapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)];
918 }
919
920 ////////////////////////////////////////////////////////////////////////////////
921 /// @brief \b Function \b Name: HAL_SEAL_PmReadByte
922 /// @brief \b Function \b Description: read 1 Byte data
923 /// @param <IN> \b u32RegAddr: register address
924 /// @param <OUT> \b None :
925 /// @param <RET> \b MS_U8
926 /// @param <GLOBAL> \b None :
927 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_PmReadByte(MS_U32 u32RegAddr)928 MS_U8 HAL_SEAL_PmReadByte(MS_U32 u32RegAddr)
929 {
930 return ((volatile MS_U8*)(_gSEAL_PmMapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)];
931 }
932
933 ////////////////////////////////////////////////////////////////////////////////
934 /// @brief \b Function \b Name: HAL_SEAL_NonPmRead2Byte
935 /// @brief \b Function \b Description: read 2 Byte data
936 /// @param <IN> \b u32RegAddr: register address
937 /// @param <OUT> \b None :
938 /// @param <RET> \b MS_U16
939 /// @param <GLOBAL> \b None :
940 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_NonPmRead2Byte(MS_U32 u32RegAddr)941 MS_U16 HAL_SEAL_NonPmRead2Byte(MS_U32 u32RegAddr)
942 {
943 return ((volatile MS_U16*)(_gSEAL_NonPmMapBase))[u32RegAddr];
944 }
945
946 ////////////////////////////////////////////////////////////////////////////////
947 /// @brief \b Function \b Name: HAL_SEAL_PmRead2Byte
948 /// @brief \b Function \b Description: read 2 Byte data
949 /// @param <IN> \b u32RegAddr: register address
950 /// @param <OUT> \b None :
951 /// @param <RET> \b MS_U16
952 /// @param <GLOBAL> \b None :
953 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_PmRead2Byte(MS_U32 u32RegAddr)954 MS_U16 HAL_SEAL_PmRead2Byte(MS_U32 u32RegAddr)
955 {
956 return ((volatile MS_U16*)(_gSEAL_PmMapBase))[u32RegAddr];
957 }
958
959 ////////////////////////////////////////////////////////////////////////////////
960 /// @brief \b Function \b Name: HAL_SEAL_NonPmRead4Byte
961 /// @brief \b Function \b Description: read 4 Byte data
962 /// @param <IN> \b u32RegAddr: register address
963 /// @param <OUT> \b None :
964 /// @param <RET> \b MS_U32
965 /// @param <GLOBAL> \b None :
966 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_NonPmRead4Byte(MS_U32 u32RegAddr)967 MS_U32 HAL_SEAL_NonPmRead4Byte(MS_U32 u32RegAddr)
968 {
969 return (HAL_SEAL_NonPmRead2Byte(u32RegAddr) | HAL_SEAL_NonPmRead2Byte(u32RegAddr+2) << 16);
970 }
971
972 ////////////////////////////////////////////////////////////////////////////////
973 /// @brief \b Function \b Name: HAL_SEAL_NonPmRead6Byte
974 /// @brief \b Function \b Description: read 6 Byte data
975 /// @param <IN> \b u32RegAddr: register address
976 /// @param <OUT> \b None :
977 /// @param <RET> \b MS_U64
978 /// @param <GLOBAL> \b None :
979 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_NonPmRead6Byte(MS_U32 u32RegAddr)980 MS_U64 HAL_SEAL_NonPmRead6Byte(MS_U32 u32RegAddr)
981 {
982 MS_U64 u64HitAddr;
983
984 u64HitAddr = 0;
985 u64HitAddr |= (MS_U64)HAL_SEAL_NonPmRead2Byte(u32RegAddr);
986 u64HitAddr |= (MS_U64)HAL_SEAL_NonPmRead2Byte(u32RegAddr + 2) << 16;
987 u64HitAddr |= (MS_U64)(HAL_SEAL_NonPmRead2Byte(u32RegAddr + 4)) << 32;
988
989 return u64HitAddr;
990 }
991
992 ////////////////////////////////////////////////////////////////////////////////
993 /// @brief \b Function \b Name: HAL_SEAL_NonPmWriteByte
994 /// @brief \b Function \b Description: write 1 Byte data
995 /// @param <IN> \b u32RegAddr: register address
996 /// @param <IN> \b u8Val : 1 byte data
997 /// @param <OUT> \b None :
998 /// @param <RET> \b TRUE: Ok FALSE: Fail
999 /// @param <GLOBAL> \b None :
1000 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_NonPmWriteByte(MS_U32 u32RegAddr,MS_U8 u8Val)1001 MS_BOOL HAL_SEAL_NonPmWriteByte(MS_U32 u32RegAddr, MS_U8 u8Val)
1002 {
1003 if (!u32RegAddr)
1004 {
1005 HAL_SEAL_ERR("%s reg error!\n", __FUNCTION__);
1006 return FALSE;
1007 }
1008
1009 ((volatile MS_U8*)(_gSEAL_NonPmMapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)] = u8Val;
1010 return TRUE;
1011 }
1012
1013 ////////////////////////////////////////////////////////////////////////////////
1014 /// @brief \b Function \b Name: HAL_SEAL_PmWriteByte
1015 /// @brief \b Function \b Description: write 1 Byte data
1016 /// @param <IN> \b u32RegAddr: register address
1017 /// @param <IN> \b u8Val : 1 byte data
1018 /// @param <OUT> \b None :
1019 /// @param <RET> \b TRUE: Ok FALSE: Fail
1020 /// @param <GLOBAL> \b None :
1021 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_PmWriteByte(MS_U32 u32RegAddr,MS_U8 u8Val)1022 MS_BOOL HAL_SEAL_PmWriteByte(MS_U32 u32RegAddr, MS_U8 u8Val)
1023 {
1024 if (!u32RegAddr)
1025 {
1026 HAL_SEAL_ERR("%s reg error!\n", __FUNCTION__);
1027 return FALSE;
1028 }
1029
1030 ((volatile MS_U8*)(_gSEAL_PmMapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)] = u8Val;
1031 return TRUE;
1032 }
1033
1034 ////////////////////////////////////////////////////////////////////////////////
1035 /// @brief \b Function \b Name: HAL_SEAL_NonPmWrite2Byte
1036 /// @brief \b Function \b Description: write 2 Byte data
1037 /// @param <IN> \b u32RegAddr: register address
1038 /// @param <IN> \b u16Val : 2 byte data
1039 /// @param <OUT> \b None :
1040 /// @param <RET> \b TRUE: Ok FALSE: Fail
1041 /// @param <GLOBAL> \b None :
1042 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_NonPmWrite2Byte(MS_U32 u32RegAddr,MS_U16 u16Val)1043 MS_BOOL HAL_SEAL_NonPmWrite2Byte(MS_U32 u32RegAddr, MS_U16 u16Val)
1044 {
1045 if (!u32RegAddr)
1046 {
1047 HAL_SEAL_ERR("%s reg error!\n", __FUNCTION__);
1048 return FALSE;
1049 }
1050
1051 ((volatile MS_U16*)(_gSEAL_NonPmMapBase))[u32RegAddr] = u16Val;
1052 return TRUE;
1053 }
1054
1055 ////////////////////////////////////////////////////////////////////////////////
1056 /// @brief \b Function \b Name: HAL_SEAL_PmWrite2Byte
1057 /// @brief \b Function \b Description: write 2 Byte data
1058 /// @param <IN> \b u32RegAddr: register address
1059 /// @param <IN> \b u16Val : 2 byte data
1060 /// @param <OUT> \b None :
1061 /// @param <RET> \b TRUE: Ok FALSE: Fail
1062 /// @param <GLOBAL> \b None :
1063 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_PmWrite2Byte(MS_U32 u32RegAddr,MS_U16 u16Val)1064 MS_BOOL HAL_SEAL_PmWrite2Byte(MS_U32 u32RegAddr, MS_U16 u16Val)
1065 {
1066 if (!u32RegAddr)
1067 {
1068 HAL_SEAL_ERR("%s reg error!\n", __FUNCTION__);
1069 return FALSE;
1070 }
1071
1072 ((volatile MS_U16*)(_gSEAL_PmMapBase))[u32RegAddr] = u16Val;
1073 return TRUE;
1074 }
1075
1076 ////////////////////////////////////////////////////////////////////////////////
1077 /// @brief \b Function \b Name: HAL_SEAL_NonPmWrite4Byte
1078 /// @brief \b Function \b Description: write 4 Byte data
1079 /// @param <IN> \b u32RegAddr: register address
1080 /// @param <IN> \b u32Val : 4 byte data
1081 /// @param <OUT> \b None :
1082 /// @param <RET> \b TRUE: Ok FALSE: Fail
1083 /// @param <GLOBAL> \b None :
1084 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_NonPmWrite4Byte(MS_U32 u32RegAddr,MS_U32 u32Val)1085 MS_BOOL HAL_SEAL_NonPmWrite4Byte(MS_U32 u32RegAddr, MS_U32 u32Val)
1086 {
1087 if (!u32RegAddr)
1088 {
1089 HAL_SEAL_ERR("%s reg error!\n", __FUNCTION__);
1090 return FALSE;
1091 }
1092
1093 HAL_SEAL_NonPmWrite2Byte(u32RegAddr, u32Val & 0x0000FFFF);
1094 HAL_SEAL_NonPmWrite2Byte(u32RegAddr+2, u32Val >> 16);
1095 return TRUE;
1096 }
1097
1098 ////////////////////////////////////////////////////////////////////////////////
1099 /// @brief \b Function \b Name: HAL_SEAL_NonPmWrite6Byte
1100 /// @brief \b Function \b Description: write 6 Byte data
1101 /// @param <IN> \b u32RegAddr: register address
1102 /// @param <IN> \b u64Val : 4 byte data
1103 /// @param <OUT> \b None :
1104 /// @param <RET> \b TRUE: Ok FALSE: Fail
1105 /// @param <GLOBAL> \b None :
1106 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_NonPmWrite6Byte(MS_U32 u32RegAddr,MS_U64 u64Val)1107 MS_BOOL HAL_SEAL_NonPmWrite6Byte(MS_U32 u32RegAddr, MS_U64 u64Val)
1108 {
1109 HAL_SEAL_NonPmWrite2Byte(u32RegAddr, u64Val & 0xFFFF);
1110 HAL_SEAL_NonPmWrite2Byte(u32RegAddr + 2,(u64Val >> 16) & 0xFFFF);
1111 HAL_SEAL_NonPmWrite2Byte(u32RegAddr + 4,(u64Val >> 32) & 0xFFFF);
1112 return TRUE;
1113 }
1114
1115 ////////////////////////////////////////////////////////////////////////////////
1116 /// @brief \b Function \b Name: HAL_SEAL_NonPmWriteRegBit
1117 /// @brief \b Function \b Description: set or reset one bit in 1-byte data
1118 /// @param <IN> \b u32RegAddr: register address
1119 /// @param <IN> \b u8Mask: 1-byte mask
1120 /// @param <IN> \b bEnabl: decide if set or reset bits
1121 /// @param <RET> \b TRUE: Ok FALSE: Fail
1122 /// @param <GLOBAL> \b None :
1123 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_NonPmWriteRegBit(MS_U32 u32RegAddr,MS_U8 u8Mask,MS_BOOL bEnable)1124 MS_BOOL HAL_SEAL_NonPmWriteRegBit(MS_U32 u32RegAddr, MS_U8 u8Mask, MS_BOOL bEnable)
1125 {
1126 MS_U8 u8Val = HAL_SEAL_NonPmReadByte(u32RegAddr);
1127 if (!u32RegAddr)
1128 {
1129 HAL_SEAL_ERR("%s reg error!\n", __FUNCTION__);
1130 return FALSE;
1131 }
1132
1133 u8Val = HAL_SEAL_NonPmReadByte(u32RegAddr);
1134 u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask);
1135 HAL_SEAL_NonPmWriteByte(u32RegAddr, u8Val);
1136 return TRUE;
1137 }
1138
1139 ////////////////////////////////////////////////////////////////////////////////
1140 /// @brief \b Function \b Name: HAL_SEAL_NonPmWrite2BytesBit
1141 /// @brief \b Function \b Description: set or reset one bit in 2-byte data
1142 /// @param <IN> \b u32RegAddr: register address
1143 /// @param <IN> \b u8Mask: 2-byte mask
1144 /// @param <IN> \b bEnabl: decide if set or reset bits
1145 /// @param <RET> \b TRUE: Ok FALSE: Fail
1146 /// @param <GLOBAL> \b None :
1147 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_NonPmWrite2BytesBit(MS_U32 u32RegOffset,MS_BOOL bEnable,MS_U16 u16Mask)1148 void HAL_SEAL_NonPmWrite2BytesBit(MS_U32 u32RegOffset, MS_BOOL bEnable, MS_U16 u16Mask)
1149 {
1150 MS_U16 val = HAL_SEAL_NonPmRead2Byte(u32RegOffset);
1151 val = (bEnable) ? (val | u16Mask) : (val & ~u16Mask);
1152 HAL_SEAL_NonPmWrite2Byte(u32RegOffset, val);
1153 }
1154
1155 ////////////////////////////////////////////////////////////////////////////////
1156 /// @brief \b Function \b Name: HAL_SEAL_GetNonPmIpIdx
1157 /// @brief \b Function \b Description: Get the Non-PM IP index with respect to HW wired
1158 /// @param <IN> \b u32RegAddr: Non-PM IP index with respect to SW enum
1159 /// @param <OUT> \b None :
1160 /// @param <RET> \b MS_S32: Non-PM IP index with respect to HW wired
1161 /// @param <GLOBAL> \b None :
1162 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_GetNonPmIpIdx(eSeal_IP eNonPmIP)1163 MS_S32 HAL_SEAL_GetNonPmIpIdx(eSeal_IP eNonPmIP)
1164 {
1165 MS_S32 s32HwIdx;
1166
1167 for (s32HwIdx = 0; s32HwIdx < SEAL_NONPM_TBL_IP_NUM; s32HwIdx++)
1168 {
1169 if(eNonPmIP == NonPmIpTbl[s32HwIdx])
1170 {
1171 return s32HwIdx;
1172 }
1173 }
1174
1175 return (-1);
1176 }
1177
1178 ////////////////////////////////////////////////////////////////////////////////
1179 /// @brief \b Function \b Name: HAL_SEAL_GetPmIpIdx
1180 /// @brief \b Function \b Description: Get the PM IP index with respect to HW wired
1181 /// @param <IN> \b u32RegAddr: PM IP index with respect to SW enum
1182 /// @param <OUT> \b None :
1183 /// @param <RET> \b MS_S32: PM IP index with respect to HW wired
1184 /// @param <GLOBAL> \b None :
1185 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_GetPmIpIdx(eSeal_IP ePmIP)1186 MS_S32 HAL_SEAL_GetPmIpIdx(eSeal_IP ePmIP)
1187 {
1188 MS_S32 s32HwIdx;
1189
1190 for (s32HwIdx = 0; s32HwIdx < SEAL_PM_TBL_IP_NUM; s32HwIdx++)
1191 {
1192 if(ePmIP == PmIpTbl[s32HwIdx])
1193 {
1194 return s32HwIdx;
1195 }
1196 }
1197
1198 return (-1);
1199 }
1200
1201 ////////////////////////////////////////////////////////////////////////////////
1202 /// @brief \b Function \b Name: HAL_SEAL_GetProcessorIdx
1203 /// @brief \b Function \b Description: Get the processor index with respect to HW wired
1204 /// @param <IN> \b u32RegAddr: Processor index with respect to SW enum
1205 /// @param <OUT> \b None :
1206 /// @param <RET> \b MS_S32: Processor index with respect to HW wired
1207 /// @param <GLOBAL> \b None :
1208 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_GetProcessorIdx(eSeal_ProcessorId eProcessorId)1209 MS_S32 HAL_SEAL_GetProcessorIdx(eSeal_ProcessorId eProcessorId)
1210 {
1211 MS_S32 s32HwIdx;
1212
1213 for (s32HwIdx = 0; s32HwIdx < SEAL_TBL_PROCESSOR_NUM; s32HwIdx++)
1214 {
1215 if(eProcessorId == ProcessorTbl[s32HwIdx])
1216 {
1217 return s32HwIdx;
1218 }
1219 }
1220
1221 return (-1);
1222 }
1223
1224 ////////////////////////////////////////////////////////////////////////////////
1225 /// @brief \b Function \b Name: HAL_SEAL_GetLockIdx
1226 /// @brief \b Function \b Description: Get the lock index with respect to HW wired
1227 /// @param <IN> \b u32RegAddr: Lock index with respect to SW enum
1228 /// @param <OUT> \b None :
1229 /// @param <RET> \b MS_S32: Lock index with respect to HW wired
1230 /// @param <GLOBAL> \b None :
1231 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_GetLockIdx(eSeal_Lock eLockId)1232 MS_S32 HAL_SEAL_GetLockIdx(eSeal_Lock eLockId)
1233 {
1234 MS_S32 s32HwIdx;
1235
1236 for (s32HwIdx = 0; s32HwIdx < SEAL_TBL_LOCK_NUM; s32HwIdx++)
1237 {
1238 if(eLockId == LockTbl[s32HwIdx])
1239 {
1240 return s32HwIdx;
1241 }
1242 }
1243
1244 return (-1);
1245 }
1246
1247 //-------------------------------------------------------------------------------------------------
1248 // Type and Structure Declaration
1249 //-------------------------------------------------------------------------------------------------
1250
1251 //-------------------------------------------------------------------------------------------------
1252 // Global Functions
1253 //-------------------------------------------------------------------------------------------------
1254
1255 ////////////////////////////////////////////////////////////////////////////////
1256 /// @brief \b Function \b Name: HAL_SEAL_SetIOMapBase
1257 /// @brief \b Function \b Description: set io-base
1258 /// @param <IN> \b u32NonPmBaseAddr: Non-PM io-base address
1259 /// @param <IN> \b u32PmBaseAddr: PM io-base address
1260 /// @param <OUT> \b None :
1261 /// @param <RET> \b MS_U8
1262 /// @param <GLOBAL> \b None :
1263 ////////////////////////////////////////////////////////////////////////////////
HAL_SEAL_SetIOMapBase(MS_VIRT u32NonPmBaseAddr,MS_VIRT u32PmBaseAddr)1264 void HAL_SEAL_SetIOMapBase(MS_VIRT u32NonPmBaseAddr, MS_VIRT u32PmBaseAddr)
1265 {
1266 MS_U32 u32RegAddr;
1267 MS_U8 u8Val;
1268
1269 _gSEAL_NonPmMapBase = u32NonPmBaseAddr;
1270 _gSEAL_PmMapBase = u32PmBaseAddr;
1271 HAL_SEAL_DBG(printf("SEAL _gSEAL_NonPmMapBase= %x\n", _gSEAL_NonPmMapBase));
1272 HAL_SEAL_DBG(printf("SEAL _gSEAL_PmMapBase= %x\n", _gSEAL_PmMapBase));
1273
1274 // Force RIU bank be controled by TZPC
1275 u32RegAddr = REG_TZPC_PROTECT_CTL;
1276 u8Val = HAL_SEAL_NonPmReadByte(u32RegAddr);
1277 u8Val = u8Val | (1 << 2);
1278 HAL_SEAL_NonPmWriteByte(u32RegAddr, u8Val);
1279 }
1280
1281 ////////////////////////////////////////////////////////////////////////////////
1282 /// @brief \b Function \b Name: HAL_Seal_SecureRangeSet
1283 /// @brief \b Function \b Description: set the secure range on MIU
1284 /// @param <IN> \b u8SecureRangeId : Secure range ID
1285 /// @param <IN> \b u64StartAddr : Start address of secure range
1286 /// @param <IN> \b u64EndAddr : End address of secure range
1287 /// @param <IN> \b u32Attribute : Attribute of secure range
1288 /// @param <OUT> \b OUT :
1289 /// @param <RET> \b RET
1290 /// @param <GLOBAL> \b GLOBAL :
1291 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_SecureRangeSet(MS_U8 u8SecureRangeId,MS_U64 u64StartAddr,MS_U64 u64EndAddr,MS_U32 u32Attribute)1292 MS_BOOL HAL_Seal_SecureRangeSet(
1293 MS_U8 u8SecureRangeId,
1294 MS_U64 u64StartAddr,
1295 MS_U64 u64EndAddr,
1296 MS_U32 u32Attribute
1297 )
1298 {
1299 MS_U32 u32RegStartAddr = 0;
1300 MS_U32 u32RegEndAddr = 0;
1301 MS_U32 u32RegAttribute = 0;
1302 MS_U32 u32RegDetEn = 0;
1303 MS_U32 u32RegDetEnDummy = 0; // work-around for 0x76 not readable issue
1304 MS_U64 u64StartOffset;
1305 MS_U64 u64EndOffset;
1306 MS_U8 u8MiuSel;
1307 MS_U8 u8Val;
1308
1309 _phy_to_miu_offset(u8MiuSel, u64StartOffset, u64StartAddr);
1310 _phy_to_miu_offset(u8MiuSel, u64EndOffset, u64EndAddr);
1311
1312 if(u8MiuSel == E_CHIP_MIU_0)
1313 {
1314 u32RegDetEn = REG_SECURE0_DETECT_ENABLE;
1315 u32RegDetEnDummy = REG_SECURE0_DUMMY0;
1316
1317 switch(u8SecureRangeId)
1318 {
1319 case E_HAL_SEAL_SECURE_RANGE_ID0:
1320 u32RegStartAddr = REG_SECURE0_RANGE0_START_ADDR;
1321 u32RegEndAddr = REG_SECURE0_RANGE0_END_ADDR;
1322 u32RegAttribute = REG_SECURE0_RANGE0_ATTRIBUTE;
1323 break;
1324 case E_HAL_SEAL_SECURE_RANGE_ID1:
1325 u32RegStartAddr = REG_SECURE0_RANGE1_START_ADDR;
1326 u32RegEndAddr = REG_SECURE0_RANGE1_END_ADDR;
1327 u32RegAttribute = REG_SECURE0_RANGE1_ATTRIBUTE;
1328 break;
1329 case E_HAL_SEAL_SECURE_RANGE_ID2:
1330 u32RegStartAddr = REG_SECURE0_RANGE2_START_ADDR;
1331 u32RegEndAddr = REG_SECURE0_RANGE2_END_ADDR;
1332 u32RegAttribute = REG_SECURE0_RANGE2_ATTRIBUTE;
1333 break;
1334 case E_HAL_SEAL_SECURE_RANGE_ID3:
1335 u32RegStartAddr = REG_SECURE0_RANGE3_START_ADDR;
1336 u32RegEndAddr = REG_SECURE0_RANGE3_END_ADDR;
1337 u32RegAttribute = REG_SECURE0_RANGE3_ATTRIBUTE;
1338 break;
1339 case E_HAL_SEAL_SECURE_RANGE_ID4:
1340 u32RegStartAddr = REG_SECURE0_RANGE4_START_ADDR;
1341 u32RegEndAddr = REG_SECURE0_RANGE4_END_ADDR;
1342 u32RegAttribute = REG_SECURE0_RANGE4_ATTRIBUTE;
1343 break;
1344 case E_HAL_SEAL_SECURE_RANGE_ID5:
1345 u32RegStartAddr = REG_SECURE0_RANGE5_START_ADDR;
1346 u32RegEndAddr = REG_SECURE0_RANGE5_END_ADDR;
1347 u32RegAttribute = REG_SECURE0_RANGE5_ATTRIBUTE;
1348 break;
1349 case E_HAL_SEAL_SECURE_RANGE_ID6:
1350 u32RegStartAddr = REG_SECURE0_RANGE6_START_ADDR;
1351 u32RegEndAddr = REG_SECURE0_RANGE6_END_ADDR;
1352 u32RegAttribute = REG_SECURE0_RANGE6_ATTRIBUTE;
1353 break;
1354 case E_HAL_SEAL_SECURE_RANGE_ID7:
1355 u32RegStartAddr = REG_SECURE0_RANGE7_START_ADDR;
1356 u32RegEndAddr = REG_SECURE0_RANGE7_END_ADDR;
1357 u32RegAttribute = REG_SECURE0_RANGE7_ATTRIBUTE;
1358 break;
1359 default:
1360 return false;
1361 }
1362 }
1363 else if(u8MiuSel == E_CHIP_MIU_1)
1364 {
1365 u32RegDetEn = REG_SECURE1_DETECT_ENABLE;
1366 u32RegDetEnDummy = REG_SECURE1_DUMMY0;
1367
1368 switch(u8SecureRangeId)
1369 {
1370 case E_HAL_SEAL_SECURE_RANGE_ID0:
1371 u32RegStartAddr = REG_SECURE1_RANGE0_START_ADDR;
1372 u32RegEndAddr = REG_SECURE1_RANGE0_END_ADDR;
1373 u32RegAttribute = REG_SECURE1_RANGE0_ATTRIBUTE;
1374 break;
1375 case E_HAL_SEAL_SECURE_RANGE_ID1:
1376 u32RegStartAddr = REG_SECURE1_RANGE1_START_ADDR;
1377 u32RegEndAddr = REG_SECURE1_RANGE1_END_ADDR;
1378 u32RegAttribute = REG_SECURE1_RANGE1_ATTRIBUTE;
1379 break;
1380 case E_HAL_SEAL_SECURE_RANGE_ID2:
1381 u32RegStartAddr = REG_SECURE1_RANGE2_START_ADDR;
1382 u32RegEndAddr = REG_SECURE1_RANGE2_END_ADDR;
1383 u32RegAttribute = REG_SECURE1_RANGE2_ATTRIBUTE;
1384 break;
1385 case E_HAL_SEAL_SECURE_RANGE_ID3:
1386 u32RegStartAddr = REG_SECURE1_RANGE3_START_ADDR;
1387 u32RegEndAddr = REG_SECURE1_RANGE3_END_ADDR;
1388 u32RegAttribute = REG_SECURE1_RANGE3_ATTRIBUTE;
1389 break;
1390 case E_HAL_SEAL_SECURE_RANGE_ID4:
1391 u32RegStartAddr = REG_SECURE1_RANGE4_START_ADDR;
1392 u32RegEndAddr = REG_SECURE1_RANGE4_END_ADDR;
1393 u32RegAttribute = REG_SECURE1_RANGE4_ATTRIBUTE;
1394 break;
1395 case E_HAL_SEAL_SECURE_RANGE_ID5:
1396 u32RegStartAddr = REG_SECURE1_RANGE5_START_ADDR;
1397 u32RegEndAddr = REG_SECURE1_RANGE5_END_ADDR;
1398 u32RegAttribute = REG_SECURE1_RANGE5_ATTRIBUTE;
1399 break;
1400 case E_HAL_SEAL_SECURE_RANGE_ID6:
1401 u32RegStartAddr = REG_SECURE1_RANGE6_START_ADDR;
1402 u32RegEndAddr = REG_SECURE1_RANGE6_END_ADDR;
1403 u32RegAttribute = REG_SECURE1_RANGE6_ATTRIBUTE;
1404 break;
1405 case E_HAL_SEAL_SECURE_RANGE_ID7:
1406 u32RegStartAddr = REG_SECURE1_RANGE7_START_ADDR;
1407 u32RegEndAddr = REG_SECURE1_RANGE7_END_ADDR;
1408 u32RegAttribute = REG_SECURE1_RANGE7_ATTRIBUTE;
1409 break;
1410 default:
1411 return false;
1412 }
1413 }
1414 else
1415 {
1416 HAL_SEAL_ERR("%s MIU%d is not support\n", __FUNCTION__, u8MiuSel);
1417 }
1418
1419 if ( (u32Attribute == 0x0)|| (u64StartOffset == 0 && u64EndOffset == 0) )
1420 {
1421 // Disable secure range detection
1422 u8Val = HAL_SEAL_NonPmReadByte(u32RegDetEnDummy);
1423 u8Val &= ~(1 << u8SecureRangeId);
1424 HAL_SEAL_NonPmWriteByte(u32RegDetEn, u8Val);
1425 HAL_SEAL_NonPmWriteByte(u32RegDetEnDummy, u8Val);
1426
1427 // Reset secure range attribute
1428 HAL_SEAL_NonPmWriteByte(u32RegAttribute, 0x0f);
1429
1430 // Set start address
1431 HAL_SEAL_NonPmWrite6Byte(u32RegStartAddr, 0x00);
1432
1433 // Set end address
1434 HAL_SEAL_NonPmWrite6Byte(u32RegEndAddr, 0x00);
1435 }
1436 else
1437 {
1438 // Disable secure range detection
1439 u8Val = HAL_SEAL_NonPmReadByte(u32RegDetEnDummy);
1440 u8Val &= ~(1 << u8SecureRangeId);
1441 HAL_SEAL_NonPmWriteByte(u32RegDetEn, u8Val);
1442 HAL_SEAL_NonPmWriteByte(u32RegDetEnDummy, u8Val);
1443
1444 // Reset secure range attribute
1445 HAL_SEAL_NonPmWriteByte(u32RegAttribute, 0x0f);
1446
1447 // Set start address
1448 HAL_SEAL_NonPmWrite6Byte(u32RegStartAddr, u64StartOffset);
1449
1450 // Set end address
1451 HAL_SEAL_NonPmWrite6Byte(u32RegEndAddr, u64EndOffset);
1452
1453 // Set secure range attribute
1454 HAL_SEAL_NonPmWriteByte(u32RegAttribute, u32Attribute);
1455
1456 // Enable secure range detection
1457 u8Val = HAL_SEAL_NonPmReadByte(u32RegDetEnDummy);
1458 u8Val |= (1 << u8SecureRangeId);
1459 HAL_SEAL_NonPmWriteByte(u32RegDetEn, u8Val);
1460 HAL_SEAL_NonPmWriteByte(u32RegDetEnDummy, u8Val);
1461 }
1462
1463 return TRUE;
1464 }
1465
1466 ////////////////////////////////////////////////////////////////////////////////
1467 /// @brief \b Function \b Name: HAL_Seal_SecureRangeQuery
1468 /// @brief \b Function \b Description: Query the attribute of secure range
1469 /// @param <IN> \b u8SecureRangeId : Secure range ID
1470 /// @param <OUT> \b pAttribute : Attribute of secure range
1471 /// @param <OUT> \b pStartAddr : Start address of secure range
1472 /// @param <OUT> \b pEndAddr : End address of secure range
1473 /// @param <RET> \b RET
1474 /// @param <GLOBAL> \b GLOBAL :
1475 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_SecureRangeQuery(MS_U8 u8MiuDev,MS_U8 u8SecureRangeId,MS_U32 * pAttribute,MS_U64 * pStartAddr,MS_U64 * pEndAddr)1476 MS_BOOL HAL_Seal_SecureRangeQuery(
1477 MS_U8 u8MiuDev,
1478 MS_U8 u8SecureRangeId,
1479 MS_U32 *pAttribute,
1480 MS_U64 *pStartAddr,
1481 MS_U64 *pEndAddr)
1482 {
1483 MS_U32 u32RegStartAddr = 0;
1484 MS_U32 u32RegEndAddr = 0;
1485 MS_U32 u32RegAttribute = 0;
1486
1487 if(u8MiuDev == E_HAL_MIU_DEV0)
1488 {
1489 switch(u8SecureRangeId)
1490 {
1491 case E_HAL_SEAL_SECURE_RANGE_ID0:
1492 u32RegStartAddr = REG_SECURE0_RANGE0_START_ADDR;
1493 u32RegEndAddr = REG_SECURE0_RANGE0_END_ADDR;
1494 u32RegAttribute = REG_SECURE0_RANGE0_ATTRIBUTE;
1495 break;
1496 case E_HAL_SEAL_SECURE_RANGE_ID1:
1497 u32RegStartAddr = REG_SECURE0_RANGE1_START_ADDR;
1498 u32RegEndAddr = REG_SECURE0_RANGE1_END_ADDR;
1499 u32RegAttribute = REG_SECURE0_RANGE1_ATTRIBUTE;
1500 break;
1501 case E_HAL_SEAL_SECURE_RANGE_ID2:
1502 u32RegStartAddr = REG_SECURE0_RANGE2_START_ADDR;
1503 u32RegEndAddr = REG_SECURE0_RANGE2_END_ADDR;
1504 u32RegAttribute = REG_SECURE0_RANGE2_ATTRIBUTE;
1505 break;
1506 case E_HAL_SEAL_SECURE_RANGE_ID3:
1507 u32RegStartAddr = REG_SECURE0_RANGE3_START_ADDR;
1508 u32RegEndAddr = REG_SECURE0_RANGE3_END_ADDR;
1509 u32RegAttribute = REG_SECURE0_RANGE3_ATTRIBUTE;
1510 break;
1511 case E_HAL_SEAL_SECURE_RANGE_ID4:
1512 u32RegStartAddr = REG_SECURE0_RANGE4_START_ADDR;
1513 u32RegEndAddr = REG_SECURE0_RANGE4_END_ADDR;
1514 u32RegAttribute = REG_SECURE0_RANGE4_ATTRIBUTE;
1515 break;
1516 case E_HAL_SEAL_SECURE_RANGE_ID5:
1517 u32RegStartAddr = REG_SECURE0_RANGE5_START_ADDR;
1518 u32RegEndAddr = REG_SECURE0_RANGE5_END_ADDR;
1519 u32RegAttribute = REG_SECURE0_RANGE5_ATTRIBUTE;
1520 break;
1521 case E_HAL_SEAL_SECURE_RANGE_ID6:
1522 u32RegStartAddr = REG_SECURE0_RANGE6_START_ADDR;
1523 u32RegEndAddr = REG_SECURE0_RANGE6_END_ADDR;
1524 u32RegAttribute = REG_SECURE0_RANGE6_ATTRIBUTE;
1525 break;
1526 case E_HAL_SEAL_SECURE_RANGE_ID7:
1527 u32RegStartAddr = REG_SECURE0_RANGE7_START_ADDR;
1528 u32RegEndAddr = REG_SECURE0_RANGE7_END_ADDR;
1529 u32RegAttribute = REG_SECURE0_RANGE7_ATTRIBUTE;
1530 break;
1531 default:
1532 return false;
1533 }
1534 }
1535 else if( u8MiuDev == E_HAL_MIU_DEV1 )
1536 {
1537 switch(u8SecureRangeId)
1538 {
1539 case E_HAL_SEAL_SECURE_RANGE_ID0:
1540 u32RegStartAddr = REG_SECURE1_RANGE0_START_ADDR;
1541 u32RegEndAddr = REG_SECURE1_RANGE0_END_ADDR;
1542 u32RegAttribute = REG_SECURE1_RANGE0_ATTRIBUTE;
1543 break;
1544 case E_HAL_SEAL_SECURE_RANGE_ID1:
1545 u32RegStartAddr = REG_SECURE1_RANGE1_START_ADDR;
1546 u32RegEndAddr = REG_SECURE1_RANGE1_END_ADDR;
1547 u32RegAttribute = REG_SECURE1_RANGE1_ATTRIBUTE;
1548 break;
1549 case E_HAL_SEAL_SECURE_RANGE_ID2:
1550 u32RegStartAddr = REG_SECURE1_RANGE2_START_ADDR;
1551 u32RegEndAddr = REG_SECURE1_RANGE2_END_ADDR;
1552 u32RegAttribute = REG_SECURE1_RANGE2_ATTRIBUTE;
1553 break;
1554 case E_HAL_SEAL_SECURE_RANGE_ID3:
1555 u32RegStartAddr = REG_SECURE1_RANGE3_START_ADDR;
1556 u32RegEndAddr = REG_SECURE1_RANGE3_END_ADDR;
1557 u32RegAttribute = REG_SECURE1_RANGE3_ATTRIBUTE;
1558 break;
1559 case E_HAL_SEAL_SECURE_RANGE_ID4:
1560 u32RegStartAddr = REG_SECURE1_RANGE4_START_ADDR;
1561 u32RegEndAddr = REG_SECURE1_RANGE4_END_ADDR;
1562 u32RegAttribute = REG_SECURE1_RANGE4_ATTRIBUTE;
1563 break;
1564 case E_HAL_SEAL_SECURE_RANGE_ID5:
1565 u32RegStartAddr = REG_SECURE1_RANGE5_START_ADDR;
1566 u32RegEndAddr = REG_SECURE1_RANGE5_END_ADDR;
1567 u32RegAttribute = REG_SECURE1_RANGE5_ATTRIBUTE;
1568 break;
1569 case E_HAL_SEAL_SECURE_RANGE_ID6:
1570 u32RegStartAddr = REG_SECURE1_RANGE6_START_ADDR;
1571 u32RegEndAddr = REG_SECURE1_RANGE6_END_ADDR;
1572 u32RegAttribute = REG_SECURE1_RANGE6_ATTRIBUTE;
1573 break;
1574 case E_HAL_SEAL_SECURE_RANGE_ID7:
1575 u32RegStartAddr = REG_SECURE1_RANGE7_START_ADDR;
1576 u32RegEndAddr = REG_SECURE1_RANGE7_END_ADDR;
1577 u32RegAttribute = REG_SECURE1_RANGE7_ATTRIBUTE;
1578 break;
1579 default:
1580 return false;
1581 }
1582 }
1583 else
1584 {
1585 HAL_SEAL_ERR("%s MIU%d is not support\n", __FUNCTION__, u8MiuDev);
1586 }
1587
1588 // Get secure range attribute
1589 *pAttribute = (MS_U32)(HAL_SEAL_NonPmReadByte(u32RegAttribute));
1590
1591 // Get start address
1592 *pStartAddr = HAL_SEAL_NonPmRead6Byte(u32RegStartAddr);
1593
1594 // Get end address
1595 *pEndAddr = HAL_SEAL_NonPmRead6Byte(u32RegEndAddr);
1596
1597 return TRUE;
1598 }
1599
1600 ////////////////////////////////////////////////////////////////////////////////
1601 /// @brief \b Function \b Name: HAL_Seal_IMI_RangeSet
1602 /// @brief \b Function \b Description: set the secure range on internel memory interface
1603 /// @param <IN> \b u32StartAddr : Start address of secure range on IMI
1604 /// @param <IN> \b u32EndAddr : End address of secure range on IMI
1605 /// @param <IN> \b bEnable : Enable/Disable secure range on IMI
1606 /// @param <OUT> \b OUT :
1607 /// @param <RET> \b RET
1608 /// @param <GLOBAL> \b GLOBAL :
1609 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_IMI_RangeSet(MS_U32 u32StartAddr,MS_U32 u32EndAddr,MS_BOOL bEnable)1610 MS_BOOL HAL_Seal_IMI_RangeSet(MS_U32 u32StartAddr, MS_U32 u32EndAddr, MS_BOOL bEnable)
1611 {
1612 MS_U32 u32RegStartAddr = 0;
1613 MS_U32 u32RegEndAddr = 0;
1614
1615 u32RegStartAddr = REG_IMI_RANGE_START_ADDR;
1616 u32RegEndAddr = REG_IMI_RANGE_END_ADDR;
1617
1618 if(bEnable == 1)
1619 {
1620 // Set start address
1621 HAL_SEAL_NonPmWrite4Byte(u32RegStartAddr, u32StartAddr);
1622
1623 // Set end address
1624 HAL_SEAL_NonPmWrite4Byte(u32RegEndAddr, u32EndAddr);
1625 }
1626 else
1627 {
1628 // Reset start address
1629 HAL_SEAL_NonPmWrite4Byte(u32RegStartAddr, 0x0);
1630
1631 // Reset end address
1632 HAL_SEAL_NonPmWrite4Byte(u32RegEndAddr,0x0);
1633 }
1634
1635 return TRUE;
1636 }
1637
1638 ////////////////////////////////////////////////////////////////////////////////
1639 /// @brief \b Function \b Name: HAL_Seal_GetMiuHitFlag
1640 /// @brief \b Function \b Description: Get the information about hitted flag on MIU
1641 /// @param <IN> \b u8MiuDev: 0:MIU0 1:MIU1 2:MIU2 3:MIU3
1642 /// @param <OUT> \b None:
1643 /// @param <RET> \b MS_BOOL: Hitted flag
1644 /// @param <GLOBAL> \b None :
1645 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_GetMiuHitFlag(MS_U8 u8MiuDev)1646 MS_BOOL HAL_Seal_GetMiuHitFlag(MS_U8 u8MiuDev)
1647 {
1648 MS_U32 u32RegLogAddr;
1649 MS_U16 u16Val;
1650
1651 switch(u8MiuDev)
1652 {
1653 case E_HAL_MIU_DEV0:
1654 u32RegLogAddr = REG_SECURE0_HITTED_STATUS;
1655 break;
1656 case E_HAL_MIU_DEV1:
1657 u32RegLogAddr = REG_SECURE1_HITTED_STATUS;
1658 break;
1659 default:
1660 return FALSE;
1661 }
1662
1663 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegLogAddr);
1664
1665 if(REG_SECURE_HITTED_FALG & u16Val)
1666 {
1667 return TRUE;
1668 }
1669 else
1670 {
1671 return FALSE;
1672 }
1673 }
1674
1675 ////////////////////////////////////////////////////////////////////////////////
1676 /// @brief \b Function \b Name: HAL_Seal_GetHitRangeID
1677 /// @brief \b Function \b Description: Get the information about the ID of hitted secure range on MIU
1678 /// @param <IN> \b u8MiuDev: 0:MIU0 1:MIU1 2:MIU2 3:MIU3
1679 /// @param <OUT> \b None:
1680 /// @param <RET> \b MS_U8: ID of hitted secure range
1681 /// @param <GLOBAL> \b None :
1682 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_GetMiuHitRangeID(MS_U8 u8MiuDev)1683 MS_U8 HAL_Seal_GetMiuHitRangeID(MS_U8 u8MiuDev)
1684 {
1685 MS_U32 u32RegLogAddr;
1686 MS_U16 u16Val;
1687 MS_U16 u8ret;
1688
1689 switch(u8MiuDev)
1690 {
1691 case E_HAL_MIU_DEV0:
1692 u32RegLogAddr = REG_SECURE0_HITTED_STATUS;
1693 break;
1694 case E_HAL_MIU_DEV1:
1695 u32RegLogAddr = REG_SECURE1_HITTED_STATUS;
1696 break;
1697 default:
1698 return FALSE;
1699 }
1700
1701 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegLogAddr);
1702
1703 u8ret =(MS_U8)GET_HIT_RANGE_ID(u16Val);
1704
1705 return u8ret;
1706 }
1707
1708 ////////////////////////////////////////////////////////////////////////////////
1709 /// @brief \b Function \b Name: HAL_Seal_GetHitClientID
1710 /// @brief \b Function \b Description: Get the information about the ID of hittd MIU client ID on MIU
1711 /// @param <IN> \b u8MiuDev: 0:MIU0 1:MIU1 2:MIU2 3:MIU3
1712 /// @param <OUT> \b None:
1713 /// @param <RET> \b MS_U8: hittd MIU client ID
1714 /// @param <GLOBAL> \b None :
1715 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_GetMiuHitClientID(MS_U8 u8MiuDev)1716 MS_U8 HAL_Seal_GetMiuHitClientID(MS_U8 u8MiuDev)
1717 {
1718 MS_U32 u32RegLogAddr;
1719 MS_U16 u16Val;
1720 MS_U16 u8ret;
1721
1722 switch(u8MiuDev)
1723 {
1724 case E_HAL_MIU_DEV0:
1725 u32RegLogAddr = REG_SECURE0_HITTED_STATUS;
1726 break;
1727 case E_HAL_MIU_DEV1:
1728 u32RegLogAddr = REG_SECURE1_HITTED_STATUS;
1729 break;
1730 default:
1731 return FALSE;
1732 }
1733
1734 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegLogAddr);
1735 u8ret =(MS_U8)GET_HIT_CLIENT_ID(u16Val);
1736
1737 return u8ret;
1738 }
1739
1740 ////////////////////////////////////////////////////////////////////////////////
1741 /// @brief \b Function \b Name: HAL_Seal_GetSecureFlag
1742 /// @brief \b Function \b Description: Get the information about the hitted client on MIU be secure or not
1743 /// @param <IN> \b u8MiuDev: 0:MIU0 1:MIU1 2:MIU2 3:MIU3
1744 /// @param <OUT> \b None:
1745 /// @param <RET> \b MS_BOOL: Secure flag
1746 /// @param <GLOBAL> \b None :
1747 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_GetMiuSecureFlag(MS_U8 u8MiuDev)1748 MS_BOOL HAL_Seal_GetMiuSecureFlag(MS_U8 u8MiuDev)
1749 {
1750 return TRUE;
1751 }
1752
1753 ////////////////////////////////////////////////////////////////////////////////
1754 /// @brief \b Function \b Name: HAL_Seal_GetWriteFlag
1755 /// @brief \b Function \b Description: Get the information about the violation on MIU be write or read access
1756 /// @param <IN> \b u8MiuDev: 0:MIU0 1:MIU1 2:MIU2 3:MIU3
1757 /// @param <OUT> \b None:
1758 /// @param <RET> \b MS_BOOL: Write flag
1759 /// @param <GLOBAL> \b None :
1760 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_GetMiuWriteFlag(MS_U8 u8MiuDev)1761 MS_BOOL HAL_Seal_GetMiuWriteFlag(MS_U8 u8MiuDev)
1762 {
1763 MS_U32 u32RegLogAddr;
1764 MS_U16 u16Val;
1765
1766 switch(u8MiuDev)
1767 {
1768 case E_HAL_MIU_DEV0:
1769 u32RegLogAddr = REG_SECURE0_HITTED_STATUS;
1770 break;
1771 case E_HAL_MIU_DEV1:
1772 u32RegLogAddr = REG_SECURE1_HITTED_STATUS;
1773 break;
1774 default:
1775 return FALSE;
1776 }
1777
1778 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegLogAddr);
1779
1780 if(REG_SECURE_HITTED_IS_WRITE & u16Val)
1781 {
1782 return TRUE;
1783 }
1784 else
1785 {
1786 return FALSE;
1787 }
1788 }
1789
1790 ////////////////////////////////////////////////////////////////////////////////
1791 /// @brief \b Function \b Name: HAL_Seal_GetHitAddr
1792 /// @brief \b Function \b Description: Get the information about the hitted address on MIU
1793 /// @param <IN> \b u8MiuDev: 0:MIU0 1:MIU1 2:MIU2 3:MIU3
1794 /// @param <OUT> \b None:
1795 /// @param <RET> \b MS_U32: Hitted address
1796 /// @param <GLOBAL> \b None :
1797 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_GetMiuHitAddr(MS_U8 u8MiuDev)1798 MS_U64 HAL_Seal_GetMiuHitAddr(MS_U8 u8MiuDev)
1799 {
1800 MS_U32 u32RegAddr;
1801 MS_U64 u64Val;
1802
1803 switch(u8MiuDev)
1804 {
1805 case E_HAL_MIU_DEV0:
1806 u32RegAddr = REG_SECURE0_HITTED_ADDR;
1807 break;
1808 case E_HAL_MIU_DEV1:
1809 u32RegAddr = REG_SECURE1_HITTED_ADDR;
1810 break;
1811 default:
1812 return FALSE;
1813 }
1814
1815 u64Val = HAL_SEAL_NonPmRead6Byte(u32RegAddr);
1816 return u64Val;
1817 }
1818
1819 ////////////////////////////////////////////////////////////////////////////////
1820 /// @brief \b Function \b Name: HAL_Seal_ClearMiuHitLog
1821 /// @brief \b Function \b Description: Clear the hitted log on MIU
1822 /// @param <IN> \b u8MiuDev: 0:MIU0 1:MIU1 2:MIU2 3:MIU3
1823 /// @param <OUT> \b None:
1824 /// @param <RET> \b RET:
1825 /// @param <GLOBAL> \b None :
1826 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_ClearMiuHitLog(MS_U8 u8MiuDev)1827 MS_BOOL HAL_Seal_ClearMiuHitLog(MS_U8 u8MiuDev)
1828 {
1829 MS_U32 u32RegLogAddr;
1830
1831 switch(u8MiuDev)
1832 {
1833 case E_HAL_MIU_DEV0:
1834 u32RegLogAddr = REG_SECURE0_HITTED_STATUS;
1835 break;
1836 case E_HAL_MIU_DEV1:
1837 u32RegLogAddr = REG_SECURE1_HITTED_STATUS;
1838 break;
1839 default:
1840 return FALSE;
1841 }
1842
1843 HAL_SEAL_NonPmWrite2BytesBit(u32RegLogAddr, TRUE, REG_SECURE_HITTED_LOG_CLR);
1844 HAL_SEAL_NonPmWrite2BytesBit(u32RegLogAddr, FALSE, REG_SECURE_HITTED_LOG_CLR);
1845 return TRUE;
1846 }
1847
1848 ////////////////////////////////////////////////////////////////////////////////
1849 /// @brief \b Function \b Name: HAL_Seal_SecureRangeLock
1850 /// @brief \b Function \b Description: One-way setting to lock the specific secure range
1851 /// @param <IN> \b u8MiuDev: 0:MIU0 1:MIU1 2:MIU2 3:MIU3
1852 /// @param <IN> \b u8SecureRangeId: Secure range ID
1853 /// @param <OUT> \b None:
1854 /// @param <RET> \b RET
1855 /// @param <GLOBAL> \b None :
1856 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_SecureRangeLock(MS_U8 u8MiuDev,MS_U8 u8SecureRangeId)1857 MS_BOOL HAL_Seal_SecureRangeLock(MS_U8 u8MiuDev, MS_U8 u8SecureRangeId)
1858 {
1859 MS_U32 u32RegAddr;
1860 MS_U8 u8Val;
1861
1862 switch(u8MiuDev)
1863 {
1864 case E_HAL_MIU_DEV0:
1865 u32RegAddr = REG_SECURE0_LOCK;
1866 break;
1867 case E_HAL_MIU_DEV1:
1868 u32RegAddr = REG_SECURE1_LOCK;
1869 break;
1870 default:
1871 HAL_SEAL_ERR("%s MIU%d is not support\n", __FUNCTION__, u8MiuDev);
1872 return false;
1873 }
1874
1875 u8Val = HAL_SEAL_NonPmReadByte(u32RegAddr);
1876 u8Val = u8Val | (1 << u8SecureRangeId);
1877 HAL_SEAL_NonPmWriteByte(u32RegAddr, u8Val);
1878
1879 return TRUE;
1880 }
1881
1882 ////////////////////////////////////////////////////////////////////////////////
1883 /// @brief \b Function \b Name: HAL_Seal_SecureProcessorSet
1884 /// @brief \b Function \b Description: Define the specific processor be secure or not
1885 /// @param <IN> \b u8ProcessorId: Processor ID
1886 /// @param <IN> \b bSecure: 1: non-secure 0:secure
1887 /// @param <OUT> \b None:
1888 /// @param <RET> \b RET
1889 /// @param <GLOBAL> \b None :
1890 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_NonSecureProcessorSet(MS_U8 u8ProcessorId,MS_BOOL bNonSecure)1891 MS_BOOL HAL_Seal_NonSecureProcessorSet(MS_U8 u8ProcessorId, MS_BOOL bNonSecure)
1892 {
1893 MS_U32 u32RegAddr;
1894 MS_U16 u16Val;
1895 MS_S32 s32HwIdx;
1896
1897 s32HwIdx = HAL_SEAL_GetProcessorIdx(u8ProcessorId);
1898
1899 if(s32HwIdx == -1)
1900 {
1901 HAL_SEAL_ERR("Processor ID:%d doesn't exist !\n", u8ProcessorId);
1902 return FALSE;
1903 }
1904
1905 // special case for HEMCU
1906 if(u8ProcessorId == E_SEAL_HEMCU)
1907 {
1908 if(bNonSecure)
1909 HAL_SEAL_NonPmWriteRegBit(REG_TZPC_NONSECURE_HEMCU, BIT3, ENABLE);
1910 else
1911 HAL_SEAL_NonPmWriteRegBit(REG_TZPC_NONSECURE_HEMCU, BIT3, DISABLE);
1912
1913 return TRUE;
1914 }
1915
1916 u32RegAddr = REG_TZPC_NONSECURE_PROCESSOR;
1917 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
1918
1919 if(bNonSecure)
1920 {
1921 u16Val = u16Val | (1 << (s32HwIdx * 2));
1922 }
1923 else
1924 {
1925 u16Val = u16Val & ~(1 << (s32HwIdx * 2));
1926 }
1927
1928 HAL_SEAL_NonPmWrite2Byte(u32RegAddr, u16Val);
1929
1930 return TRUE;
1931 }
1932
1933 ////////////////////////////////////////////////////////////////////////////////
1934 /// @brief \b Function \b Name: HAL_Seal_SecureProcessorQuery
1935 /// @brief \b Function \b Description: Query the specific processor be secure or not
1936 /// @param <IN> \b u8ProcessorId: Processor ID
1937 /// @param <OUT> \b pSecure: 1: non-secure 0:secure
1938 /// @param <RET> \b RET
1939 /// @param <GLOBAL> \b None :
1940 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_NonSecureProcessorQuery(MS_U8 u8ProcessorId,MS_BOOL * pNonSecure)1941 MS_BOOL HAL_Seal_NonSecureProcessorQuery(MS_U8 u8ProcessorId, MS_BOOL *pNonSecure)
1942 {
1943 MS_U32 u32RegAddr;
1944 MS_U16 u16Val;
1945 MS_U16 s32HwIdx;
1946
1947 s32HwIdx = HAL_SEAL_GetProcessorIdx(u8ProcessorId);
1948
1949 if(s32HwIdx == -1)
1950 {
1951 HAL_SEAL_ERR("Processor ID:%d doesn't exist !\n", u8ProcessorId);
1952 return FALSE;
1953 }
1954
1955 // special case for HEMCU
1956 if(u8ProcessorId == E_SEAL_HEMCU)
1957 {
1958 u32RegAddr = REG_TZPC_NONSECURE_HEMCU;
1959 u16Val = (MS_U8)HAL_SEAL_NonPmReadByte(u32RegAddr);
1960
1961 if(u16Val & BIT3)
1962 {
1963 *pNonSecure = 1;
1964 }
1965 else
1966 {
1967 *pNonSecure = 0;
1968 }
1969 return TRUE;
1970 }
1971
1972 u32RegAddr = REG_TZPC_NONSECURE_PROCESSOR;
1973 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
1974
1975 if(u16Val & (1 << (s32HwIdx * 2)))
1976 {
1977 *pNonSecure = 1;
1978 }
1979 else
1980 {
1981 *pNonSecure = 0;
1982 }
1983
1984 return TRUE;
1985 }
1986
1987 ////////////////////////////////////////////////////////////////////////////////
1988 /// @brief \b Function \b Name: HAL_Seal_SecureSlaveSet
1989 /// @brief \b Function \b Description: Define the specific slave IP be secure or not
1990 /// @param <IN> \b u32SlaveId: Slave ID
1991 /// @param <IN> \b bSecure: 0: non-secure 1:secure
1992 /// @param <OUT> \b None:
1993 /// @param <RET> \b RET
1994 /// @param <GLOBAL> \b None :
1995 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_SecureSlaveSet(MS_U32 u32SlaveId,MS_BOOL bSecure)1996 MS_BOOL HAL_Seal_SecureSlaveSet(MS_U32 u32SlaveId, MS_BOOL bSecure)
1997 {
1998 MS_U32 u32RegAddr;
1999 MS_U16 u16Val;
2000 MS_S32 s32HwIdx;
2001 MS_U8 u8GroupId;
2002 MS_U8 u8ClientId;
2003 MS_BOOL bIsPm;
2004
2005 bIsPm = 0;
2006 s32HwIdx = HAL_SEAL_GetNonPmIpIdx(u32SlaveId);
2007
2008 //Slave ID not in Non-PM group, check if u32SlaveId in PM group
2009 if(s32HwIdx == -1)
2010 {
2011 s32HwIdx = HAL_SEAL_GetPmIpIdx(u32SlaveId);
2012 bIsPm = 1;
2013
2014 //Slave ID not in Non-PM nor PM group
2015 if(s32HwIdx == -1)
2016 {
2017 HAL_SEAL_ERR("Slave ID:%d doesn't exist !\n", (unsigned int)u32SlaveId);
2018 return FALSE;
2019 }
2020 }
2021
2022 if(bIsPm == 0)
2023 {
2024 u8GroupId = (MS_U8)(s32HwIdx / SEAL_NONPM_GROUP_IP_NUM);
2025 u8ClientId = (MS_U8)(s32HwIdx % SEAL_NONPM_GROUP_IP_NUM);
2026 u32RegAddr = (MS_U32)(REG_TZPC_NONPM_SECURE_SLAVE + (u8GroupId * 2));
2027
2028 if(bSecure == 1)
2029 {
2030 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
2031 u16Val = u16Val & (~(1 << u8ClientId));
2032 HAL_SEAL_NonPmWrite2Byte(u32RegAddr, u16Val);
2033 }
2034 else
2035 {
2036 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
2037 u16Val = u16Val | (1 << u8ClientId);
2038 HAL_SEAL_NonPmWrite2Byte(u32RegAddr, u16Val);
2039 }
2040 }
2041 else
2042 {
2043 u8GroupId = (MS_U8)(s32HwIdx / SEAL_PM_GROUP_IP_NUM);
2044 u8ClientId = (MS_U8)(s32HwIdx % SEAL_PM_GROUP_IP_NUM);
2045 u32RegAddr = (MS_U32)(REG_TZPC_PM_SECURE_SLAVE + (u8GroupId * 2));
2046
2047 if(bSecure == 1)
2048 {
2049 u16Val = HAL_SEAL_PmRead2Byte(u32RegAddr);
2050 u16Val = u16Val & (~(1 << u8ClientId));
2051 HAL_SEAL_PmWrite2Byte(u32RegAddr, u16Val);
2052 }
2053 else
2054 {
2055 u16Val = HAL_SEAL_PmRead2Byte(u32RegAddr);
2056 u16Val = u16Val | (1 << u8ClientId);
2057 HAL_SEAL_PmWrite2Byte(u32RegAddr, u16Val);
2058 }
2059 }
2060 return TRUE;
2061 }
2062
2063 ////////////////////////////////////////////////////////////////////////////////
2064 /// @brief \b Function \b Name: HAL_Seal_SecureSlaveQuery
2065 /// @brief \b Function \b Description: Query the specific slave IP be secure or not
2066 /// @param <IN> \b u32SlaveId: Slave ID
2067 /// @param <IN> \b pSecure: 0: non-secure 1:secure
2068 /// @param <OUT> \b None:
2069 /// @param <RET> \b RET
2070 /// @param <GLOBAL> \b None :
2071 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_SecureSlaveQuery(MS_U32 u32SlaveId,MS_BOOL * pSecure)2072 MS_BOOL HAL_Seal_SecureSlaveQuery(MS_U32 u32SlaveId, MS_BOOL *pSecure)
2073 {
2074 MS_U32 u32RegAddr;
2075 MS_U16 u16Val;
2076 MS_S32 s32HwIdx;
2077 MS_U8 u8GroupId;
2078 MS_U8 u8ClientId;
2079 MS_BOOL bIsPm;
2080
2081 bIsPm = 0;
2082 s32HwIdx = HAL_SEAL_GetNonPmIpIdx(u32SlaveId);
2083
2084 //Slave ID not in Non-PM group, check if u32SlaveId in PM group
2085 if(s32HwIdx == -1)
2086 {
2087 s32HwIdx = HAL_SEAL_GetPmIpIdx(u32SlaveId);
2088 bIsPm = 1;
2089
2090 //Slave ID not in Non-PM nor PM group
2091 if(s32HwIdx == -1)
2092 {
2093 HAL_SEAL_ERR("Slave ID:%d doesn't exist !\n", (unsigned int)u32SlaveId);
2094 return FALSE;
2095 }
2096 }
2097
2098 if(bIsPm == 0)
2099 {
2100 u8GroupId = (MS_U8)(s32HwIdx / SEAL_NONPM_GROUP_IP_NUM);
2101 u8ClientId = (MS_U8)(s32HwIdx % SEAL_NONPM_GROUP_IP_NUM);
2102 u32RegAddr = (MS_U32)(REG_TZPC_NONPM_SECURE_SLAVE + (u8GroupId * 2));
2103
2104 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
2105 }
2106 else
2107 {
2108 u8GroupId = (MS_U8)(s32HwIdx / SEAL_PM_GROUP_IP_NUM);
2109 u8ClientId = (MS_U8)(s32HwIdx % SEAL_PM_GROUP_IP_NUM);
2110 u32RegAddr = (MS_U32)(REG_TZPC_PM_SECURE_SLAVE + (u8GroupId * 2));
2111
2112 u16Val = HAL_SEAL_PmRead2Byte(u32RegAddr);
2113 }
2114
2115 if(u16Val & (1 << u8ClientId))
2116 {
2117 *pSecure = 0;
2118 }
2119 else
2120 {
2121 *pSecure = 1;
2122 }
2123
2124 return TRUE;
2125 }
2126
2127 ////////////////////////////////////////////////////////////////////////////////
2128 /// @brief \b Function \b Name: HAL_Seal_SecureMasterSet
2129 /// @brief \b Function \b Description: Define the specific master IP be secure or not
2130 /// @param <IN> \b u32SlaveId: Master ID
2131 /// @param <IN> \b bSecure: 0: non-secure 1:secure
2132 /// @param <OUT> \b None:
2133 /// @param <RET> \b RET
2134 /// @param <GLOBAL> \b None :
2135 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_SecureMasterSet(MS_U32 u32MasterId,MS_BOOL bSecure)2136 MS_BOOL HAL_Seal_SecureMasterSet(MS_U32 u32MasterId, MS_BOOL bSecure)
2137 {
2138 MS_U32 u32RegAddr;
2139 MS_U16 u16Val;
2140 MS_S32 s32HwIdx;
2141 MS_U8 u8GroupId;
2142 MS_U8 u8ClientId;
2143
2144 s32HwIdx = HAL_SEAL_GetNonPmIpIdx(u32MasterId);
2145
2146 if(s32HwIdx == -1)
2147 {
2148 HAL_SEAL_ERR("Master ID:%u doesn't exist !\n", (unsigned int)u32MasterId);
2149 return FALSE;
2150 }
2151
2152 u8GroupId = (MS_U8)(s32HwIdx / SEAL_NONPM_GROUP_IP_NUM);
2153 u8ClientId = (MS_U8)(s32HwIdx % SEAL_NONPM_GROUP_IP_NUM);
2154 u32RegAddr = (MS_U32)(REG_TZPC_NONPM_SECURE_MASTER + (u8GroupId * 2));
2155
2156 if(bSecure == 1)
2157 {
2158 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
2159 u16Val = u16Val & (~(1 << u8ClientId));
2160 HAL_SEAL_NonPmWrite2Byte(u32RegAddr, u16Val);
2161 }
2162 else
2163 {
2164 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
2165 u16Val = u16Val | (1 << u8ClientId);
2166 HAL_SEAL_NonPmWrite2Byte(u32RegAddr, u16Val);
2167 }
2168
2169 return TRUE;
2170 }
2171
2172 ////////////////////////////////////////////////////////////////////////////////
2173 /// @brief \b Function \b Name: HAL_Seal_SecureMasterQuery
2174 /// @brief \b Function \b Description: Query the specific master IP be secure or not
2175 /// @param <IN> \b u32SlaveId: Master ID
2176 /// @param <IN> \b pSecure: 0: non-secure 1:secure
2177 /// @param <OUT> \b None:
2178 /// @param <RET> \b RET
2179 /// @param <GLOBAL> \b None :
2180 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_SecureMasterQuery(MS_U32 u32MasterId,MS_BOOL * pSecure)2181 MS_BOOL HAL_Seal_SecureMasterQuery(MS_U32 u32MasterId, MS_BOOL *pSecure)
2182 {
2183 MS_U32 u32RegAddr;
2184 MS_U16 u16Val;
2185 MS_S32 s32HwIdx;
2186 MS_U8 u8GroupId;
2187 MS_U8 u8ClientId;
2188
2189 s32HwIdx = HAL_SEAL_GetNonPmIpIdx(u32MasterId);
2190
2191 if(s32HwIdx == -1)
2192 {
2193 HAL_SEAL_ERR("Master ID:%d doesn't exist !\n", (unsigned int)u32MasterId);
2194 return FALSE;
2195 }
2196
2197 u8GroupId = (MS_U8)(s32HwIdx / SEAL_NONPM_GROUP_IP_NUM);
2198 u8ClientId = (MS_U8)(s32HwIdx % SEAL_NONPM_GROUP_IP_NUM);
2199 u32RegAddr = (MS_U32)(REG_TZPC_NONPM_SECURE_MASTER + (u8GroupId * 2));
2200
2201 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
2202
2203 if(u16Val & (1 << u8ClientId))
2204 {
2205 *pSecure = 0;
2206 }
2207 else
2208 {
2209 *pSecure = 1;
2210 }
2211
2212 return TRUE;
2213 }
2214
2215 ////////////////////////////////////////////////////////////////////////////////
2216 /// @brief \b Function \b Name: HAL_Seal_BufferLock
2217 /// @brief \b Function \b Description: Lock the specific buffer
2218 /// @param <IN> \b u8SecureRangeId: Secure buffer ID
2219 /// @param <IN> \b bLock: 0: unlock 1:lock
2220 /// @param <OUT> \b None:
2221 /// @param <RET> \b RET
2222 /// @param <GLOBAL> \b None :
2223 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_BufferLock(MS_U8 u8BufferLockId,MS_BOOL bLock)2224 MS_BOOL HAL_Seal_BufferLock(MS_U8 u8BufferLockId, MS_BOOL bLock)
2225 {
2226 MS_U32 u32RegAddr;
2227 MS_U16 u16Val;
2228 MS_S32 s32HwIdx;
2229 MS_U8 u8GroupId;
2230 MS_U8 u8ClientId;
2231
2232 s32HwIdx = HAL_SEAL_GetLockIdx(u8BufferLockId);
2233
2234 //Check if u8SecureBufferId exist
2235 if(s32HwIdx == -1)
2236 {
2237 HAL_SEAL_ERR("Secure buffer lock ID:%u doesn't exist !\n", u8BufferLockId);
2238 return FALSE;
2239 }
2240
2241 u8GroupId = (MS_U8)(s32HwIdx / SEAL_LOCK_NUM_PERGROUP);
2242 u8ClientId = (MS_U8)(s32HwIdx % SEAL_LOCK_NUM_PERGROUP);
2243 u32RegAddr = (MS_U32)(REG_TZPC_BUFFER_LOCK + (u8GroupId * 2));
2244
2245 if(bLock == 1)
2246 {
2247 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
2248 u16Val = u16Val & (~(1 << u8ClientId));
2249 HAL_SEAL_NonPmWrite2Byte(u32RegAddr, u16Val);
2250 }
2251 else
2252 {
2253 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
2254 u16Val = u16Val | (1 << u8ClientId);
2255 HAL_SEAL_NonPmWrite2Byte(u32RegAddr, u16Val);
2256 }
2257
2258 return TRUE;
2259 }
2260
2261
HAL_Seal_QueryBufferLocked(eSeal_Lock eLockId,MS_BOOL * bLocked)2262 MS_BOOL HAL_Seal_QueryBufferLocked(eSeal_Lock eLockId, MS_BOOL* bLocked)
2263 {
2264 MS_U32 u32RegAddr;
2265 MS_U16 u16Val;
2266 MS_S32 s32HwIdx;
2267 MS_U8 u8GroupId;
2268 MS_U8 u8ClientId;
2269
2270 s32HwIdx = HAL_SEAL_GetLockIdx(eLockId);
2271
2272 //Check if u8SecureBufferId exist
2273 if(s32HwIdx == -1)
2274 {
2275 HAL_SEAL_ERR("Secure buffer lock ID:%u doesn't exist !\n", (unsigned int)eLockId);
2276 return FALSE;
2277 }
2278
2279 u8GroupId = (MS_U8)(s32HwIdx / SEAL_LOCK_NUM_PERGROUP);
2280 u8ClientId = (MS_U8)(s32HwIdx % SEAL_LOCK_NUM_PERGROUP);
2281 u32RegAddr = (MS_U32)(REG_TZPC_BUFFER_LOCK + (u8GroupId * 2));
2282
2283 u16Val = HAL_SEAL_NonPmRead2Byte(u32RegAddr);
2284 *bLocked = (u16Val & (1 << u8ClientId)) ? FALSE : TRUE;
2285
2286 return TRUE;
2287 }
2288
2289
2290 ////////////////////////////////////////////////////////////////////////////////
2291 /// @brief \b Function \b Name: HAL_Seal_MaskInterruptFlag
2292 /// @brief \b Function \b Description: mask/unmask irq mask bit
2293 /// @param <IN> \b u8MiuDev: 0:MIU0 1:MIU1 2:MIU2 3:MIU3
2294 /// @param <IN> \b bMask: FLASE: unmask ; TRUE: mask
2295 /// @param <OUT> \b None:
2296 /// @param <RET> \b RET:
2297 /// @param <GLOBAL> \b None :
2298 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_MaskInterruptFlag(MS_U8 u8MiuDev,MS_BOOL bMask)2299 MS_BOOL HAL_Seal_MaskInterruptFlag(MS_U8 u8MiuDev, MS_BOOL bMask)
2300 {
2301 MS_U32 u32RegLogAddr;
2302
2303 switch(u8MiuDev)
2304 {
2305 case E_HAL_MIU_DEV0:
2306 u32RegLogAddr = REG_SECURE0_HITTED_STATUS;
2307 break;
2308 case E_HAL_MIU_DEV1:
2309 u32RegLogAddr = REG_SECURE1_HITTED_STATUS;
2310 break;
2311 default:
2312 return FALSE;
2313 }
2314
2315 HAL_SEAL_NonPmWrite2BytesBit(u32RegLogAddr, bMask, REG_SECURE_HITTED_IRQ_MASK);
2316
2317 return TRUE;
2318 }
2319
2320 ////////////////////////////////////////////////////////////////////////////////
2321 /// @brief \b Function \b Name: HAL_Seal_CheckSecureRange
2322 /// @brief \b Function \b Description: Is Overlap Secure Range
2323 /// @param <IN> \b phyStartAddr : start address
2324 /// @param <IN> \b u32Length : protect length
2325 /// @param <IN> \b eCheckSecureRangeType : check SecureRange type
2326 /// @param <OUT> \b None:
2327 /// @param <RET> \b RET:
2328 /// @param <GLOBAL> \b None :
2329 ////////////////////////////////////////////////////////////////////////////////
HAL_Seal_CheckSecureRange(MS_PHY phyStartAddr,MS_U32 u32Length,eSeal_CheckSecureRangeType eCheckSecureRangeType)2330 MS_BOOL HAL_Seal_CheckSecureRange(MS_PHY phyStartAddr, MS_U32 u32Length, eSeal_CheckSecureRangeType eCheckSecureRangeType)
2331 {
2332 MS_U8 u8MiuSel;
2333 MS_U8 u8Val;
2334 MS_U8 RangeNum;
2335 MS_U64 u64Offset;
2336 MS_U32 u32RegStartAddr;
2337 MS_U32 u32RegEndAddr;
2338 MS_U32 u32RegAttribute;
2339 MS_U32 u32RegDetEnDummy; // work-around for 0x76 not readable issue
2340 MS_U64 u64StartAddr;
2341 MS_U64 u64EndAddr;
2342
2343 _phy_to_miu_offset(u8MiuSel, u64Offset, phyStartAddr);
2344
2345 switch(u8MiuSel)
2346 {
2347 case E_CHIP_MIU_0:
2348 u32RegDetEnDummy = REG_SECURE0_DUMMY0;
2349 u32RegStartAddr = REG_SECURE0_RANGE0_START_ADDR;
2350 u32RegEndAddr = REG_SECURE0_RANGE0_END_ADDR;
2351 u32RegAttribute = REG_SECURE0_RANGE0_ATTRIBUTE;
2352 break;
2353 case E_CHIP_MIU_1:
2354 u32RegDetEnDummy = REG_SECURE1_DUMMY0;
2355 u32RegStartAddr = REG_SECURE1_RANGE0_START_ADDR;
2356 u32RegEndAddr = REG_SECURE1_RANGE0_END_ADDR;
2357 u32RegAttribute = REG_SECURE1_RANGE0_ATTRIBUTE;
2358 break;
2359 default:
2360 printf("%s: Wrong paramater-MiuSel %d \n", __FUNCTION__, u8MiuSel);
2361 return TRUE;
2362 }
2363
2364 u8Val = HAL_SEAL_NonPmReadByte(u32RegDetEnDummy);
2365
2366 for(RangeNum = E_HAL_SEAL_SECURE_RANGE_ID0; RangeNum < E_HAL_SEAL_SECURE_RANGE_NUM; RangeNum++, u32RegStartAddr+=RANGE_ADDR_OFFSET, u32RegEndAddr+=RANGE_ADDR_OFFSET, u32RegAttribute+=RANGE_ADDR_OFFSET)
2367 {
2368 if( HAL_SEAL_NonPmReadByte(u32RegAttribute) == (E_SEAL_SECURE_READ | E_SEAL_SECURE_WRITE) && (u8Val & (1<<RangeNum))) // Already set secure range
2369 {
2370 //check overlap
2371 u64StartAddr = HAL_SEAL_NonPmRead6Byte(u32RegStartAddr);
2372 u64EndAddr = HAL_SEAL_NonPmRead6Byte(u32RegEndAddr);
2373 switch(eCheckSecureRangeType)
2374 {
2375 case E_SEAL_OVERLAP:
2376 if ( u64StartAddr <= u64Offset && u64EndAddr > u64Offset )
2377 return TRUE;
2378 else if ( u64StartAddr > u64Offset && u64StartAddr < (u64Offset + u32Length))
2379 return TRUE;
2380 break;
2381 case E_SEAL_CONTAIN:
2382 if ( u64StartAddr <= u64Offset && u64EndAddr >= (u64Offset + u32Length) )
2383 return TRUE;
2384 break;
2385 default:
2386 printf("%s: Wrong paramater-eCheckSecureRangeType %d \n", __FUNCTION__, eCheckSecureRangeType);
2387 return TRUE;
2388 }
2389 }
2390 }
2391 return FALSE;
2392 }
2393
2394 #ifdef MSOS_TYPE_OPTEE
HAL_Seal_ChangeIPSecureDMAAbillity(MS_U32 u32ModuleID,MS_U32 u32ModuleParameter,MS_U32 u32IsSecure)2395 MS_BOOL HAL_Seal_ChangeIPSecureDMAAbillity(MS_U32 u32ModuleID, MS_U32 u32ModuleParameter, MS_U32 u32IsSecure)
2396 {
2397 switch(u32ModuleID)
2398 {
2399 case MODULE_XC:
2400 HAL_Seal_SecureMasterSet(E_SEAL_MSC_PROT_NONPM, u32IsSecure);
2401 HAL_Seal_SecureMasterSet(E_SEAL_SC0_PROT_NONPM, u32IsSecure);
2402 HAL_Seal_SecureMasterSet(E_SEAL_SC1_PROT_NONPM, u32IsSecure);
2403 HAL_Seal_SecureMasterSet(E_SEAL_SC2_PROT_NONPM, u32IsSecure);
2404 HAL_Seal_SecureMasterSet(E_SEAL_SC3_PROT_NONPM, u32IsSecure);
2405 HAL_Seal_SecureMasterSet(E_SEAL_SC4_PROT_NONPM, u32IsSecure);
2406 break;
2407 case MODULE_VDEC_EX:
2408 case MODULE_VDEC:
2409 switch(u32ModuleParameter)
2410 {
2411 case E_SEAL_IPGROUP_VDEC_R2:
2412 HAL_Seal_SecureMasterSet(E_SEAL_VD_MHEG5_PROT_NONPM, u32IsSecure);
2413 HAL_Seal_SecureMasterSet(E_SEAL_VD_EVD_R2_NONPM, u32IsSecure);
2414 break;
2415 case E_SEAL_IPGROUP_VDEC_DECODER:
2416 HAL_Seal_SecureMasterSet(E_SEAL_MVD_PROT_NONPM, u32IsSecure);
2417 HAL_Seal_SecureMasterSet(E_SEAL_HVD_PROT_NONPM, u32IsSecure);
2418 HAL_Seal_SecureMasterSet(E_SEAL_EVD_NONPM, u32IsSecure);
2419 HAL_Seal_SecureMasterSet(E_SEAL_MAU_EVD_NONPM, u32IsSecure);
2420 HAL_Seal_SecureMasterSet(E_SEAL_HIREG_EVD_PROT_NONPM, u32IsSecure);
2421 HAL_Seal_SecureMasterSet(E_SEAL_MAU_EVD_LV2_0_NONPM, u32IsSecure);
2422 HAL_Seal_SecureMasterSet(E_SEAL_MFDEC_PROT_NONPM, u32IsSecure);
2423 break;
2424 default:
2425 printf("%s: Unknown module paramater\n", __FUNCTION__);
2426 break;
2427 }
2428 break;
2429 case MODULE_MVOP:
2430 HAL_Seal_SecureMasterSet(E_SEAL_MVOPSUB_PROT_NONPM, u32IsSecure);
2431 HAL_Seal_SecureMasterSet(E_SEAL_MVOP_PROT_NONPM, u32IsSecure);
2432 break;
2433 case MODULE_AUDIO:
2434 HAL_Seal_SecureMasterSet(E_SEAL_VIVALDI2_PROT_NONPM, u32IsSecure);
2435 HAL_Seal_SecureMasterSet(E_SEAL_VIVALDI3_PROT_NONPM, u32IsSecure);
2436 HAL_Seal_SecureMasterSet(E_SEAL_VIVALDI7_PROT_NONPM, u32IsSecure);
2437 break;
2438 case MODULE_TVENCODER:
2439 HAL_Seal_SecureMasterSet(E_SEAL_VE_0_PROT_NONPM, u32IsSecure);
2440 HAL_Seal_SecureMasterSet(E_SEAL_VE_1_PROT_NONPM, u32IsSecure);
2441 HAL_Seal_SecureMasterSet(E_SEAL_VE_2_PROT_NONPM, u32IsSecure);
2442 break;
2443 case MODULE_DIP:
2444 HAL_Seal_SecureMasterSet(E_SEAL_MSC_PROT_NONPM, u32IsSecure);
2445 break;
2446 case MODULE_DMX:
2447 HAL_Seal_SecureMasterSet(E_SEAL_TSP0_PROT_NONPM, u32IsSecure);
2448 HAL_Seal_SecureMasterSet(E_SEAL_TSP1_PROT_NONPM, u32IsSecure);
2449 HAL_Seal_SecureMasterSet(E_SEAL_TSP_SPARE_PROT_NONPM, u32IsSecure);
2450 HAL_Seal_SecureMasterSet(E_SEAL_TSP2_PROT_NONPM, u32IsSecure);
2451 HAL_Seal_SecureMasterSet(E_SEAL_TSP3_PROT_NONPM, u32IsSecure);
2452 HAL_Seal_SecureMasterSet(E_SEAL_TSP4_NONPM, u32IsSecure);
2453 HAL_Seal_SecureMasterSet(E_SEAL_TSP6_PROT_NONPM, u32IsSecure);
2454 HAL_Seal_SecureMasterSet(E_SEAL_TSP5_NONPM, u32IsSecure);
2455 break;
2456 default:
2457 printf("%s, Unsupported ModuleID\n", __FUNCTION__);
2458 break;
2459 }
2460 return TRUE;
2461 }
2462
HAL_Seal_SetSecureRange(MS_PHY u64phy,MS_U32 u32Length,MS_U32 u32IsSecure)2463 MS_BOOL HAL_Seal_SetSecureRange(MS_PHY u64phy, MS_U32 u32Length, MS_U32 u32IsSecure)
2464 {
2465 MS_U8 u8MiuSel;
2466 MS_U64 u64Offset;
2467 MS_U32 u32RegDetEn;
2468 MS_U8 i;
2469 MS_U8 u8Val;
2470 MS_U32 u32RegStartAddr;
2471 MS_U64 u64StartAddr;
2472
2473 _phy_to_miu_offset(u8MiuSel, u64Offset, u64phy);
2474
2475 switch(u8MiuSel)
2476 {
2477 case E_CHIP_MIU_0:
2478 {
2479 u32RegDetEn = REG_SECURE0_DETECT_ENABLE;
2480 break;
2481 }
2482 case E_CHIP_MIU_1:
2483 {
2484 u32RegDetEn = REG_SECURE1_DETECT_ENABLE;
2485 break;
2486 }
2487 default:
2488 {
2489 return FALSE;
2490 }
2491 }
2492
2493 u8Val = HAL_SEAL_NonPmReadByte(u32RegDetEn);
2494
2495 if(u8MiuSel == E_CHIP_MIU_0)
2496 {
2497 u32RegStartAddr = REG_SECURE0_RANGE0_START_ADDR;
2498 }
2499 else if( u8MiuSel == E_CHIP_MIU_1 )
2500 {
2501 u32RegStartAddr = REG_SECURE1_RANGE0_START_ADDR;
2502 }
2503 else
2504 {
2505 return FALSE;
2506 }
2507
2508 if (u32IsSecure) // setup a new securerange
2509 {
2510 for (i=E_HAL_SEAL_SECURE_RANGE_ID0; i<E_HAL_SEAL_SECURE_RANGE_NUM; i++, u32RegStartAddr+=RANGE_ADDR_OFFSET)
2511 {
2512 u64StartAddr = HAL_SEAL_NonPmRead6Byte(u32RegStartAddr);
2513 if (u64StartAddr == u64Offset && (u8Val & (1<<i)))
2514 {
2515 printf("Secure range overlaps\n");
2516 return TRUE;
2517 }
2518 }
2519
2520 for (i=E_HAL_SEAL_SECURE_RANGE_ID0; i<E_HAL_SEAL_SECURE_RANGE_NUM; i++)
2521 {
2522 if ( !(u8Val & (1<<i)) ) // got a free range
2523 {
2524 return HAL_Seal_SecureRangeSet(i, u64phy, u64phy+u32Length, E_SEAL_SECURE_READ | E_SEAL_SECURE_WRITE);
2525 }
2526 }
2527
2528 return FALSE; // no free range
2529 }
2530 else // disable existing securerange
2531 {
2532 for (i=E_HAL_SEAL_SECURE_RANGE_ID0; i<E_HAL_SEAL_SECURE_RANGE_NUM; i++, u32RegStartAddr+=RANGE_ADDR_OFFSET)
2533 {
2534 u64StartAddr = HAL_SEAL_NonPmRead6Byte(u32RegStartAddr);
2535 if (u64StartAddr == u64Offset && (u8Val & (1<<i)))
2536 {
2537 return HAL_Seal_SecureRangeSet(i, u64phy, u64phy+u32Length, 0x0);
2538 }
2539 }
2540
2541 return FALSE; // no such range
2542 }
2543 }
2544 #endif
2545