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77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2009-2010 MStar Semiconductor, Inc.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #define HAL_SAR_C
96
97 //-------------------------------------------------------------------------------------------------
98 // Include Files
99 //-------------------------------------------------------------------------------------------------
100 // Common Definition
101 #include "MsCommon.h"
102 #include "MsTypes.h"
103
104 // Internal Definition
105 #include "regSAR.h"
106 #include "halSAR.h"
107
108 #ifdef CONFIG_MSTAR_DVFS_ENABLE
109 #include "halSAR_DVFS.h"
110 #endif
111
112 //-------------------------------------------------------------------------------------------------
113 // Driver Compiler Options
114 //-------------------------------------------------------------------------------------------------
115
116
117 //-------------------------------------------------------------------------------------------------
118 // Local Defines
119 //-------------------------------------------------------------------------------------------------
120 #define BIT0 BIT(0)
121 #define BIT1 BIT(1)
122 #define BIT2 BIT(2)
123 #define BIT3 BIT(3)
124 #define BIT4 BIT(4)
125 #define BIT5 BIT(5)
126 #define BIT6 BIT(6)
127 #define BIT7 BIT(7)
128
129 //-------------------------------------------------------------------------------------------------
130 // Local Structures
131 //-------------------------------------------------------------------------------------------------
132
133
134 //-------------------------------------------------------------------------------------------------
135 // Global Variables
136 //-------------------------------------------------------------------------------------------------
137
138
139 //-------------------------------------------------------------------------------------------------
140 // Local Variables
141 //-------------------------------------------------------------------------------------------------
142 static MS_U32 _gMIO_MapBase = 0;
143 static MS_U32 _gMIO_MapBase_NPM = 0;
144 static MS_S32 _s32SAR_Dvfs_Mutex;
145
146 //-------------------------------------------------------------------------------------------------
147 // Debug Functions
148 //-------------------------------------------------------------------------------------------------
149 #define HAL_SAR_ERR(x, args...) //{printf(x, ##args);}
150 #define HAL_SAR_INFO(x, args...) //{printf(x, ##args);}
151
152 //-------------------------------------------------------------------------------------------------
153 // Local Functions
154 //-------------------------------------------------------------------------------------------------
155 ////////////////////////////////////////////////////////////////////////////////
156 /// @brief \b Function \b Name: HAL_SAR_ReadByte
157 /// @brief \b Function \b Description: read 1 Byte data
158 /// @param <IN> \b u32RegAddr: register address
159 /// @param <OUT> \b None :
160 /// @param <RET> \b MS_U8
161 /// @param <GLOBAL> \b None :
162 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_ReadByte(MS_U32 u32RegAddr)163 static MS_U8 HAL_SAR_ReadByte(MS_U32 u32RegAddr)
164 {
165 return ((volatile MS_U8*)(_gMIO_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)];
166 }
167
168 ////////////////////////////////////////////////////////////////////////////////
169 /// @brief \b Function \b Name: HAL_SAR_Read2Byte
170 /// @brief \b Function \b Description: read 2 Byte data
171 /// @param <IN> \b u32RegAddr: register address
172 /// @param <OUT> \b None :
173 /// @param <RET> \b MS_U16
174 /// @param <GLOBAL> \b None :
175 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_Read2Byte(MS_U32 u32RegAddr)176 static MS_U16 HAL_SAR_Read2Byte(MS_U32 u32RegAddr)
177 {
178 return ((volatile MS_U16*)(_gMIO_MapBase))[(u32RegAddr)];
179 }
180
181 //////////////////////////////////////////////////////////////////////////////
182 /// @brief \b Function \b Name: HAL_SAR_WriteByte
183 /// @brief \b Function \b Description: write 1 Byte data
184 /// @param <IN> \b u32RegAddr: register address
185 /// @param <IN> \b u8Val : 1 byte data
186 /// @param <OUT> \b None :
187 /// @param <RET> \b TRUE: Ok FALSE: Fail
188 /// @param <GLOBAL> \b None :
189 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_WriteByte(MS_U32 u32RegAddr,MS_U8 u8Val)190 static MS_BOOL HAL_SAR_WriteByte(MS_U32 u32RegAddr, MS_U8 u8Val)
191 {
192 if (!u32RegAddr)
193 {
194 HAL_SAR_ERR("%s reg error!\n", __FUNCTION__);
195 return FALSE;
196 }
197
198 ((volatile MS_U8*)(_gMIO_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)] = u8Val;
199 return TRUE;
200 }
201
202 ////////////////////////////////////////////////////////////////////////////////
203 /// @brief \b Function \b Name: HAL_SAR_WriteByteMask
204 /// @brief \b Function \b Description: write 1 Byte data
205 /// @param <IN> \b u32RegAddr: register address
206 /// @param <IN> \b u8Val : 1 byte data
207 /// @param <OUT> \b None :
208 /// @param <RET> \b TRUE: Ok FALSE: Fail
209 /// @param <GLOBAL> \b None :
210 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_WriteByteMask(MS_U32 u32RegAddr,MS_U8 u8ValIn,MS_U8 u8Msk)211 static MS_BOOL HAL_SAR_WriteByteMask(MS_U32 u32RegAddr, MS_U8 u8ValIn, MS_U8 u8Msk)
212 {
213 MS_U8 u8Val;
214 if (!u32RegAddr)
215 {
216 HAL_SAR_ERR("%s reg error!\n", __FUNCTION__);
217 return FALSE;
218 }
219
220 u8Val = HAL_SAR_ReadByte(u32RegAddr);
221 u8Val = (u8Val & ~(u8Msk)) | ((u8ValIn) & (u8Msk));
222 HAL_SAR_WriteByte(u32RegAddr, u8Val);
223 return TRUE;
224 }
225
226 ////////////////////////////////////////////////////////////////////////////////
227 /// @brief \b Function \b Name: HAL_SAR_ReadRegBit
228 /// @brief \b Function \b Description: write 1 Byte data
229 /// @param <IN> \b u32RegAddr: register address
230 /// @param <IN> \b u8Val : 1 byte data
231 /// @param <RET> \b TRUE: Ok FALSE: Fail
232 /// @param <GLOBAL> \b None :
233 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_ReadRegBit(MS_U32 u32RegAddr,MS_U8 u8Mask)234 static MS_BOOL HAL_SAR_ReadRegBit(MS_U32 u32RegAddr, MS_U8 u8Mask)
235 {
236 MS_U8 u8Val;
237 if (!u32RegAddr)
238 {
239 HAL_SAR_ERR("%s reg error!\n", __FUNCTION__);
240 return FALSE;
241 }
242
243 u8Val = HAL_SAR_ReadByte(u32RegAddr);
244 return (u8Val & u8Mask);
245 }
246
247 ////////////////////////////////////////////////////////////////////////////////
248 /// @brief \b Function \b Name: HAL_SAR_ReadByte_NPM
249 /// @brief \b Function \b Description: read 1 Byte data
250 /// @param <IN> \b u32RegAddr: register address
251 /// @param <OUT> \b None :
252 /// @param <RET> \b MS_U8
253 /// @param <GLOBAL> \b None :
254 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_ReadByte_NPM(MS_U32 u32RegAddr)255 static MS_U8 HAL_SAR_ReadByte_NPM(MS_U32 u32RegAddr)
256 {
257 return ((volatile MS_U8*)(_gMIO_MapBase_NPM))[(u32RegAddr << 1) - (u32RegAddr & 1)];
258 }
259
260 ////////////////////////////////////////////////////////////////////////////////
261 /// @brief \b Function \b Name: HAL_SAR_WriteByte_NPM
262 /// @brief \b Function \b Description: write 1 Byte data
263 /// @param <IN> \b u32RegAddr: register address
264 /// @param <IN> \b u8Val : 1 byte data
265 /// @param <OUT> \b None :
266 /// @param <RET> \b TRUE: Ok FALSE: Fail
267 /// @param <GLOBAL> \b None :
268 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_WriteByte_NPM(MS_U32 u32RegAddr,MS_U8 u8Val)269 static MS_BOOL HAL_SAR_WriteByte_NPM(MS_U32 u32RegAddr, MS_U8 u8Val)
270 {
271 if (!u32RegAddr)
272 {
273 HAL_SAR_ERR("%s reg error!\n", __FUNCTION__);
274 return FALSE;
275 }
276
277 ((volatile MS_U8*)(_gMIO_MapBase_NPM))[(u32RegAddr << 1) - (u32RegAddr & 1)] = u8Val;
278 return TRUE;
279 }
280
281 ////////////////////////////////////////////////////////////////////////////////
282 /// @brief \b Function \b Name: HAL_SAR_WriteByteMask_NPM
283 /// @brief \b Function \b Description: write 1 Byte data
284 /// @param <IN> \b u32RegAddr: register address
285 /// @param <IN> \b u8Val : 1 byte data
286 /// @param <OUT> \b None :
287 /// @param <RET> \b TRUE: Ok FALSE: Fail
288 /// @param <GLOBAL> \b None :
289 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_WriteByteMask_NPM(MS_U32 u32RegAddr,MS_U8 u8ValIn,MS_U8 u8Msk)290 static MS_BOOL HAL_SAR_WriteByteMask_NPM(MS_U32 u32RegAddr, MS_U8 u8ValIn, MS_U8 u8Msk)
291 {
292 MS_U8 u8Val;
293 if (!u32RegAddr)
294 {
295 HAL_SAR_ERR("%s reg error!\n", __FUNCTION__);
296 return FALSE;
297 }
298
299 u8Val = HAL_SAR_ReadByte_NPM(u32RegAddr);
300 u8Val = (u8Val & ~(u8Msk)) | ((u8ValIn) & (u8Msk));
301 HAL_SAR_WriteByte_NPM(u32RegAddr, u8Val);
302 return TRUE;
303 }
304
305 #if 0//Temporarily marked out for compiler warning free
306 ////////////////////////////////////////////////////////////////////////////////
307 /// @brief \b Function \b Name: HAL_SAR_Read2Byte
308 /// @brief \b Function \b Description: read 2 Byte data
309 /// @param <IN> \b u32RegAddr: register address
310 /// @param <OUT> \b None :
311 /// @param <RET> \b MS_U16
312 /// @param <GLOBAL> \b None :
313 ////////////////////////////////////////////////////////////////////////////////
314 static MS_U16 HAL_SAR_Read2Byte(MS_U32 u32RegAddr)
315 {
316 return ((volatile MS_U16*)(_gMIO_MapBase))[u32RegAddr];
317 }
318
319 ////////////////////////////////////////////////////////////////////////////////
320 /// @brief \b Function \b Name: HAL_SAR_Write2Byte
321 /// @brief \b Function \b Description: write 2 Byte data
322 /// @param <IN> \b u32RegAddr: register address
323 /// @param <IN> \b u16Val : 2 byte data
324 /// @param <OUT> \b None :
325 /// @param <RET> \b TRUE: Ok FALSE: Fail
326 /// @param <GLOBAL> \b None :
327 ////////////////////////////////////////////////////////////////////////////////
328 static MS_BOOL HAL_SAR_Write2Byte(MS_U32 u32RegAddr, MS_U16 u16Val)
329 {
330 if (!u32RegAddr)
331 {
332 HAL_SAR_ERR("%s reg error!\n", __FUNCTION__);
333 return FALSE;
334 }
335
336 ((volatile MS_U16*)(_gMIO_MapBase))[u32RegAddr] = u16Val;
337 return TRUE;
338 }
339
340 ////////////////////////////////////////////////////////////////////////////////
341 /// @brief \b Function \b Name: HAL_SAR_Read4Byte
342 /// @brief \b Function \b Description: read 4 Byte data
343 /// @param <IN> \b u32RegAddr: register address
344 /// @param <OUT> \b None :
345 /// @param <RET> \b MS_U32
346 /// @param <GLOBAL> \b None :
347 ////////////////////////////////////////////////////////////////////////////////
348 static MS_U32 HAL_SAR_Read4Byte(MS_U32 u32RegAddr)
349 {
350 return (HAL_SAR_Read2Byte(u32RegAddr) | HAL_SAR_Read2Byte(u32RegAddr+2) << 16);
351 }
352
353 ////////////////////////////////////////////////////////////////////////////////
354 /// @brief \b Function \b Name: HAL_SAR_Write4Byte
355 /// @brief \b Function \b Description: write 4 Byte data
356 /// @param <IN> \b u32RegAddr: register address
357 /// @param <IN> \b u32Val : 4 byte data
358 /// @param <OUT> \b None :
359 /// @param <RET> \b TRUE: Ok FALSE: Fail
360 /// @param <GLOBAL> \b None :
361 ////////////////////////////////////////////////////////////////////////////////
362 static MS_BOOL HAL_SAR_Write4Byte(MS_U32 u32RegAddr, MS_U32 u32Val)
363 {
364 if (!u32RegAddr)
365 {
366 HAL_SAR_ERR("%s reg error!\n", __FUNCTION__);
367 return FALSE;
368 }
369
370 HAL_SAR_Write2Byte(u32RegAddr, u32Val & 0x0000FFFF);
371 HAL_SAR_Write2Byte(u32RegAddr+2, u32Val >> 16);
372 return TRUE;
373 }
374
375 ////////////////////////////////////////////////////////////////////////////////
376 /// @brief \b Function \b Name: HAL_SAR_WriteRegBit
377 /// @brief \b Function \b Description: write 1 Byte data
378 /// @param <IN> \b u32RegAddr: register address
379 /// @param <IN> \b u8Val : 1 byte data
380 /// @param <OUT> \b None :
381 /// @param <RET> \b TRUE: Ok FALSE: Fail
382 /// @param <GLOBAL> \b None :
383 ////////////////////////////////////////////////////////////////////////////////
384 static MS_BOOL HAL_SAR_WriteRegBit(MS_U32 u32RegAddr, MS_BOOL bEnable, MS_U8 u8Mask)
385 {
386 MS_U8 u8Val;
387 if (!u32RegAddr)
388 {
389 HAL_SAR_ERR("%s reg error!\n", __FUNCTION__);
390 return FALSE;
391 }
392
393 u8Val = HAL_SAR_ReadByte(u32RegAddr);
394 u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask);
395 HAL_SAR_WriteByte(u32RegAddr, u8Val);
396 return TRUE;
397 }
398 #endif
399
400 //-------------------------------------------------------------------------------------------------
401 // Global Functions
402 //-------------------------------------------------------------------------------------------------
403 ////////////////////////////////////////////////////////////////////////////////
404 /// @brief \b Function \b Name: HAL_SAR_SetIOMapBase
405 /// @brief \b Function \b Description: Set IO Map base
406 /// @param <IN> \b u32Base : io map base address
407 /// @param <OUT> \b None :
408 /// @param <RET> \b None :
409 /// @param <GLOBAL> \b None :
410 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_SetIOMapBase(MS_U32 u32Base)411 void HAL_SAR_SetIOMapBase(MS_U32 u32Base)
412 {
413 _gMIO_MapBase = u32Base;
414 HAL_SAR_INFO("SAR IOMap base:%8lx Reg offset:%4x\n", u32Base, SAR_REG_BASE);
415 }
416
417 ////////////////////////////////////////////////////////////////////////////////
418 /// @brief \b Function \b Name: HAL_SAR_GetIOMapBase
419 /// @brief \b Function \b Description: Get IO Map base
420 /// @param <IN> \b None :
421 /// @param <OUT> \b None :
422 /// @param <RET> \b MS_U32 : io map base address
423 /// @param <GLOBAL> \b None :
424 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_GetIOMapBase(void)425 MS_U32 HAL_SAR_GetIOMapBase(void)
426 {
427 return _gMIO_MapBase;
428 }
429
430
431 ////////////////////////////////////////////////////////////////////////////////
432 /// @brief \b Function \b Name: HAL_SAR_CfgChannelBound
433 /// @brief \b Function \b Description: Configure sar channel upper/lower bound
434 /// @param <IN> \b u8Channel : sar channel (0~7), psarBndCfg: sar bound info
435 /// @param <OUT> \b None :
436 /// @param <RET> \b TRUE: Ok FALSE: Fail
437 /// @param <GLOBAL> \b None :
438 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_CfgChannelBound(MS_U8 u8Channel,HAL_SAR_BndCfg * psarBndCfg)439 MS_BOOL HAL_SAR_CfgChannelBound(MS_U8 u8Channel ,HAL_SAR_BndCfg *psarBndCfg)
440 {
441 MS_U16 wChannelAdcValue = 0;
442
443 if(u8Channel >= HAL_SAR_CH_MAXID)
444 return FALSE;
445
446 switch(u8Channel)
447 {
448 case HAL_SAR_CH1:
449 {
450 wChannelAdcValue = psarBndCfg->u8UpBnd;
451 wChannelAdcValue <<= 2;
452 wChannelAdcValue |= 0x3;
453 HAL_SAR_WriteByteMask((REG_SAR_CH1_UPD + 1), (MS_U8) (wChannelAdcValue >> 8), 0x03);
454 HAL_SAR_WriteByteMask(REG_SAR_CH1_UPD, (MS_U8) wChannelAdcValue, _SAR_CHN_UPB_MSK);
455
456 wChannelAdcValue = psarBndCfg->u8LoBnd;
457 wChannelAdcValue <<= 2;
458 wChannelAdcValue |= 0x3;
459 HAL_SAR_WriteByteMask((REG_SAR_CH1_LOB + 1), (MS_U8) (wChannelAdcValue >> 8), 0x03);
460 HAL_SAR_WriteByteMask(REG_SAR_CH1_LOB, (MS_U8) wChannelAdcValue, _SAR_CHN_LOB_MSK);
461
462 //HAL_SAR_WriteByteMask(REG_SAR_CH1_UPD,psarBndCfg->u8UpBnd,_SAR_CHN_UPB_MSK);
463 //HAL_SAR_WriteByteMask(REG_SAR_CH1_LOB,psarBndCfg->u8LoBnd,_SAR_CHN_LOB_MSK);
464 }
465 break;
466
467 case HAL_SAR_CH2:
468 {
469 wChannelAdcValue = psarBndCfg->u8UpBnd;
470 wChannelAdcValue <<= 2;
471 wChannelAdcValue |= 0x3;
472 HAL_SAR_WriteByteMask((REG_SAR_CH2_UPD + 1), (MS_U8) (wChannelAdcValue >> 8), 0x03);
473 HAL_SAR_WriteByteMask(REG_SAR_CH2_UPD, (MS_U8) wChannelAdcValue, _SAR_CHN_UPB_MSK);
474
475 wChannelAdcValue = psarBndCfg->u8LoBnd;
476 wChannelAdcValue <<= 2;
477 wChannelAdcValue |= 0x3;
478 HAL_SAR_WriteByteMask((REG_SAR_CH2_LOB + 1), (MS_U8) (wChannelAdcValue >> 8), 0x03);
479 HAL_SAR_WriteByteMask(REG_SAR_CH2_LOB, (MS_U8) wChannelAdcValue, _SAR_CHN_LOB_MSK);
480
481 //HAL_SAR_WriteByteMask(REG_SAR_CH2_UPD,psarBndCfg->u8UpBnd,_SAR_CHN_UPB_MSK);
482 //HAL_SAR_WriteByteMask(REG_SAR_CH2_LOB,psarBndCfg->u8LoBnd,_SAR_CHN_LOB_MSK);
483 }
484 break;
485
486 case HAL_SAR_CH3:
487 {
488 wChannelAdcValue = psarBndCfg->u8UpBnd;
489 wChannelAdcValue <<= 2;
490 wChannelAdcValue |= 0x3;
491 HAL_SAR_WriteByteMask((REG_SAR_CH3_UPD + 1), (MS_U8) (wChannelAdcValue >> 8), 0x03);
492 HAL_SAR_WriteByteMask(REG_SAR_CH3_UPD, (MS_U8) wChannelAdcValue, _SAR_CHN_UPB_MSK);
493
494 wChannelAdcValue = psarBndCfg->u8LoBnd;
495 wChannelAdcValue <<= 2;
496 wChannelAdcValue |= 0x3;
497 HAL_SAR_WriteByteMask((REG_SAR_CH3_LOB + 1), (MS_U8) (wChannelAdcValue >> 8), 0x03);
498 HAL_SAR_WriteByteMask(REG_SAR_CH3_LOB, (MS_U8) wChannelAdcValue, _SAR_CHN_LOB_MSK);
499
500 //HAL_SAR_WriteByteMask(REG_SAR_CH3_UPD,psarBndCfg->u8UpBnd,_SAR_CHN_UPB_MSK);
501 //HAL_SAR_WriteByteMask(REG_SAR_CH3_LOB,psarBndCfg->u8LoBnd,_SAR_CHN_LOB_MSK);
502 }
503 break;
504
505 case HAL_SAR_CH4:
506 {
507 wChannelAdcValue = psarBndCfg->u8UpBnd;
508 wChannelAdcValue <<= 2;
509 wChannelAdcValue |= 0x3;
510 HAL_SAR_WriteByteMask((REG_SAR_CH4_UPD + 1), (MS_U8) (wChannelAdcValue >> 8), 0x03);
511 HAL_SAR_WriteByteMask(REG_SAR_CH4_UPD, (MS_U8) wChannelAdcValue, _SAR_CHN_UPB_MSK);
512
513 wChannelAdcValue = psarBndCfg->u8LoBnd;
514 wChannelAdcValue <<= 2;
515 wChannelAdcValue |= 0x3;
516 HAL_SAR_WriteByteMask((REG_SAR_CH4_LOB + 1), (MS_U8) (wChannelAdcValue >> 8), 0x03);
517 HAL_SAR_WriteByteMask(REG_SAR_CH4_LOB, (MS_U8) wChannelAdcValue, _SAR_CHN_LOB_MSK);
518
519 //HAL_SAR_WriteByteMask(REG_SAR_CH4_UPD,psarBndCfg->u8UpBnd,_SAR_CHN_UPB_MSK);
520 //HAL_SAR_WriteByteMask(REG_SAR_CH4_LOB,psarBndCfg->u8LoBnd,_SAR_CHN_LOB_MSK);
521 }
522 break;
523
524 case HAL_SAR_CH5:
525 {
526 wChannelAdcValue = psarBndCfg->u8UpBnd;
527 wChannelAdcValue <<= 2;
528 wChannelAdcValue |= 0x3;
529 HAL_SAR_WriteByteMask((REG_SAR_CH5_UPD + 1), (MS_U8) (wChannelAdcValue >> 8), 0x03);
530 HAL_SAR_WriteByteMask(REG_SAR_CH5_UPD, (MS_U8) wChannelAdcValue, _SAR_CHN_UPB_MSK);
531
532 wChannelAdcValue = psarBndCfg->u8LoBnd;
533 wChannelAdcValue <<= 2;
534 wChannelAdcValue |= 0x3;
535 HAL_SAR_WriteByteMask((REG_SAR_CH5_LOB + 1), (MS_U8) (wChannelAdcValue >> 8), 0x03);
536 HAL_SAR_WriteByteMask(REG_SAR_CH5_LOB, (MS_U8) wChannelAdcValue, _SAR_CHN_LOB_MSK);
537
538 //HAL_SAR_WriteByteMask(REG_SAR_CH5_UPD,psarBndCfg->u8UpBnd,_SAR_CHN_UPB_MSK);
539 //HAL_SAR_WriteByteMask(REG_SAR_CH5_LOB,psarBndCfg->u8LoBnd,_SAR_CHN_LOB_MSK);
540 }
541 break;
542
543 case HAL_SAR_CH6:
544 {
545 wChannelAdcValue = psarBndCfg->u8UpBnd;
546 wChannelAdcValue <<= 2;
547 wChannelAdcValue |= 0x3;
548 HAL_SAR_WriteByteMask((REG_SAR_CH6_UPD + 1), (MS_U8) (wChannelAdcValue >> 8), 0x03);
549 HAL_SAR_WriteByteMask(REG_SAR_CH6_UPD, (MS_U8) wChannelAdcValue, _SAR_CHN_UPB_MSK);
550
551 wChannelAdcValue = psarBndCfg->u8LoBnd;
552 wChannelAdcValue <<= 2;
553 wChannelAdcValue |= 0x3;
554 HAL_SAR_WriteByteMask((REG_SAR_CH6_LOB + 1), (MS_U8) (wChannelAdcValue >> 8), 0x03);
555 HAL_SAR_WriteByteMask(REG_SAR_CH6_LOB, (MS_U8) wChannelAdcValue, _SAR_CHN_LOB_MSK);
556
557 //HAL_SAR_WriteByteMask(REG_SAR_CH6_UPD,psarBndCfg->u8UpBnd,_SAR_CHN_UPB_MSK);
558 //HAL_SAR_WriteByteMask(REG_SAR_CH6_LOB,psarBndCfg->u8LoBnd,_SAR_CHN_LOB_MSK);
559 }
560 break;
561
562 case HAL_SAR_CH7:
563 {
564 wChannelAdcValue = psarBndCfg->u8UpBnd;
565 wChannelAdcValue <<= 2;
566 wChannelAdcValue |= 0x3;
567 HAL_SAR_WriteByteMask((REG_SAR_CH7_UPD + 1), (MS_U8) (wChannelAdcValue >> 8), 0x03);
568 HAL_SAR_WriteByteMask(REG_SAR_CH7_UPD, (MS_U8) wChannelAdcValue, _SAR_CHN_UPB_MSK);
569
570 wChannelAdcValue = psarBndCfg->u8LoBnd;
571 wChannelAdcValue <<= 2;
572 wChannelAdcValue |= 0x3;
573 HAL_SAR_WriteByteMask((REG_SAR_CH7_LOB + 1), (MS_U8) (wChannelAdcValue >> 8), 0x03);
574 HAL_SAR_WriteByteMask(REG_SAR_CH7_LOB, (MS_U8) wChannelAdcValue, _SAR_CHN_LOB_MSK);
575
576 //HAL_SAR_WriteByteMask(REG_SAR_CH7_UPD,psarBndCfg->u8UpBnd,_SAR_CHN_UPB_MSK);
577 //HAL_SAR_WriteByteMask(REG_SAR_CH7_LOB,psarBndCfg->u8LoBnd,_SAR_CHN_LOB_MSK);
578 }
579 break;
580
581 case HAL_SAR_CH8:
582 {
583 wChannelAdcValue = psarBndCfg->u8UpBnd;
584 wChannelAdcValue <<= 2;
585 wChannelAdcValue |= 0x3;
586 HAL_SAR_WriteByteMask((REG_SAR_CH8_UPD + 1), (MS_U8) (wChannelAdcValue >> 8), 0x03);
587 HAL_SAR_WriteByteMask(REG_SAR_CH8_UPD, (MS_U8) wChannelAdcValue, _SAR_CHN_UPB_MSK);
588
589 wChannelAdcValue = psarBndCfg->u8LoBnd;
590 wChannelAdcValue <<= 2;
591 wChannelAdcValue |= 0x3;
592 HAL_SAR_WriteByteMask((REG_SAR_CH8_LOB + 1), (MS_U8) (wChannelAdcValue >> 8), 0x03);
593 HAL_SAR_WriteByteMask(REG_SAR_CH8_LOB, (MS_U8) wChannelAdcValue, _SAR_CHN_LOB_MSK);
594
595 //HAL_SAR_WriteByteMask(REG_SAR_CH8_UPD,psarBndCfg->u8UpBnd,_SAR_CHN_UPB_MSK);
596 //HAL_SAR_WriteByteMask(REG_SAR_CH8_LOB,psarBndCfg->u8LoBnd,_SAR_CHN_LOB_MSK);
597 }
598 break;
599
600 }
601
602 return TRUE;
603 }
604
605 ////////////////////////////////////////////////////////////////////////////////
606 /// @brief \b Function \b Name: HAL_SAR_GetChannelADC
607 /// @brief \b Function \b Description: Get sar channel ADC value
608 /// @param <IN> \b u8Channel : sar channel (0~7)
609 /// @param <OUT> \b None :
610 /// @param <RET> \b MS_U8: sar ADC value
611 /// @param <GLOBAL> \b None :
612 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_GetChannelADC(MS_U8 u8Channel)613 MS_U8 HAL_SAR_GetChannelADC(MS_U8 u8Channel)
614 {
615 MS_U32 u32Reg = REG_SAR_ADC_CH1_DATA;
616 MS_U16 wChannelAdcValue = 0;
617
618 if(u8Channel >= HAL_SAR_CH_MAXID)
619 return HAL_SAR_ADC_DATA_MAX;
620
621 switch(u8Channel)
622 {
623 case HAL_SAR_CH1:
624 u32Reg = REG_SAR_ADC_CH1_DATA;
625 break;
626 case HAL_SAR_CH2:
627 u32Reg = REG_SAR_ADC_CH2_DATA;
628 break;
629 case HAL_SAR_CH3:
630 u32Reg = REG_SAR_ADC_CH3_DATA;
631 break;
632 case HAL_SAR_CH4:
633 u32Reg = REG_SAR_ADC_CH4_DATA;
634 break;
635 case HAL_SAR_CH5:
636 u32Reg = REG_SAR_ADC_CH5_DATA;
637 break;
638 case HAL_SAR_CH6:
639 u32Reg = REG_SAR_ADC_CH6_DATA;
640 break;
641 case HAL_SAR_CH7:
642 u32Reg = REG_SAR_ADC_CH7_DATA;
643 break;
644 case HAL_SAR_CH8:
645 u32Reg = REG_SAR_ADC_CH8_DATA;
646 break;
647 }
648
649 HAL_SAR_WriteByte(REG_SAR_CTRL1 ,HAL_SAR_ReadByte(REG_SAR_CTRL1)|_SAR_LOAD_EN);
650 wChannelAdcValue = (HAL_SAR_Read2Byte(u32Reg) & _SAR_ADC_OUT_10BITMSK);
651 wChannelAdcValue = ((wChannelAdcValue >> 2) & _SAR_ADC_OUT_8BITMSK);
652 /* because of interface can't be change , we return [9:2] to drv layer */
653
654 #ifdef CONFIG_MSTAR_DVFS_ENABLE
655 HAL_SAR_TSENSOR_OP();
656 #endif
657
658 return (MS_U8) wChannelAdcValue;
659 }
660
661 ////////////////////////////////////////////////////////////////////////////////
662 /// @brief \b Function \b Name: HAL_SAR_CfgSingleChannel
663 /// @brief \b Function \b Description: Configure channel for single channel mode
664 /// @param <IN> \b u8Channel : sar channel (0~7)
665 /// @param <OUT> \b None :
666 /// @param <RET> \b None:
667 /// @param <GLOBAL> \b None :
668 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_CfgSingleChannel(MS_U8 u8Channel)669 void HAL_SAR_CfgSingleChannel(MS_U8 u8Channel)
670 {
671 HAL_SAR_WriteByteMask(REG_SAR_CTRL0, u8Channel, _SAR_SINGLE_CH_MSK);
672 }
673
674 ////////////////////////////////////////////////////////////////////////////////
675 /// @brief \b Function \b Name: HAL_SAR_CfgTriggerMode
676 /// @brief \b Function \b Description: Configure keypad level(trigger) mode
677 /// @param <IN> \b bMode : 0: edge trigger mode, 1: level trigger mode
678 /// @param <OUT> \b None :
679 /// @param <RET> \b None :
680 /// @param <GLOBAL> \b None :
681 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_CfgTriggerMode(MS_U8 bMode)682 void HAL_SAR_CfgTriggerMode(MS_U8 bMode)
683 {
684 HAL_SAR_WriteByteMask(REG_SAR_CTRL0, ((bMode)? _SAR_LEVEL_TRIGGER : 0), _SAR_LEVEL_TRIGGER);
685 }
686
687 ////////////////////////////////////////////////////////////////////////////////
688 /// @brief \b Function \b Name: HAL_SAR_CfgSingleChannelEn
689 /// @brief \b Function \b Description: enable single channel mode
690 /// @param <IN> \b bEnable : 0: disable, 1: enable
691 /// @param <OUT> \b None :
692 /// @param <RET> \b None:
693 /// @param <GLOBAL> \b None :
694 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_CfgSingleChannelEn(MS_U8 bEnable)695 void HAL_SAR_CfgSingleChannelEn(MS_U8 bEnable)
696 {
697 HAL_SAR_WriteByteMask(REG_SAR_CTRL0, ((bEnable)? _SAR_SINGLE_CH_EN : 0), _SAR_SINGLE_CH_EN);
698 }
699
700 ////////////////////////////////////////////////////////////////////////////////
701 /// @brief \b Function \b Name: HAL_SAR_CfgDigitOperMode
702 /// @brief \b Function \b Description: Configure sar digital operation mode
703 /// @param <IN> \b u8Mode : 0: one-shot, 1: freerun
704 /// @param <OUT> \b None :
705 /// @param <RET> \b None:
706 /// @param <GLOBAL> \b None :
707 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_CfgDigitOperMode(MS_U8 u8Mode)708 void HAL_SAR_CfgDigitOperMode(MS_U8 u8Mode)
709 {
710 HAL_SAR_WriteByteMask(REG_SAR_CTRL0, ((u8Mode)? _SAR_MODE : 0), _SAR_MODE);
711 }
712
713 ////////////////////////////////////////////////////////////////////////////////
714 /// @brief \b Function \b Name: HAL_SAR_CfgDigitPowerdown
715 /// @brief \b Function \b Description: Configure sar digital power down
716 /// @param <IN> \b bEnable : 0: power up, 1: power down
717 /// @param <OUT> \b None :
718 /// @param <RET> \b None:
719 /// @param <GLOBAL> \b None :
720 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_CfgDigitPowerdown(MS_U8 bEnable)721 void HAL_SAR_CfgDigitPowerdown(MS_U8 bEnable)
722 {
723 HAL_SAR_WriteByteMask(REG_SAR_CTRL0, ((bEnable)? _SAR_PD : 0), _SAR_PD);
724 }
725
726 ////////////////////////////////////////////////////////////////////////////////
727 /// @brief \b Function \b Name: HAL_SAR_CfgStart
728 /// @brief \b Function \b Description: Configure sar to trigger start signal
729 /// @param <IN> \b bEnable : 0: stop, 1: trigger to start
730 /// @param <OUT> \b None :
731 /// @param <RET> \b None:
732 /// @param <GLOBAL> \b None :
733 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_CfgStart(MS_U8 bEnable)734 void HAL_SAR_CfgStart(MS_U8 bEnable)
735 {
736 HAL_SAR_WriteByteMask(REG_SAR_CTRL0, ((bEnable)? _SAR_START : 0), _SAR_START);
737 }
738
739 ////////////////////////////////////////////////////////////////////////////////
740 /// @brief \b Function \b Name: HAL_SAR_CfgAtopPowerdown
741 /// @brief \b Function \b Description: Configure sar atop power down
742 /// @param <IN> \b bEnable : 0: power up, 1: power down
743 /// @param <OUT> \b None :
744 /// @param <RET> \b None:
745 /// @param <GLOBAL> \b None :
746 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_CfgAtopPowerdown(MS_U8 bEnable)747 void HAL_SAR_CfgAtopPowerdown(MS_U8 bEnable)
748 {
749 HAL_SAR_WriteByteMask(REG_SAR_CTRL1, ((bEnable)? _SAR_ADC_PD : 0), _SAR_ADC_PD);
750 }
751
752 ////////////////////////////////////////////////////////////////////////////////
753 /// @brief \b Function \b Name: HAL_SAR_CfgAtopFreeRun
754 /// @brief \b Function \b Description: Configure sar atop freerun mode
755 /// @param <IN> \b bEnable : 0: controlled by digital, 1: freerun
756 /// @param <OUT> \b None :
757 /// @param <RET> \b None:
758 /// @param <GLOBAL> \b None :
759 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_CfgAtopFreeRun(MS_BOOL bEnable)760 void HAL_SAR_CfgAtopFreeRun(MS_BOOL bEnable)
761 {
762 HAL_SAR_WriteByteMask(REG_SAR_CTRL1, ((bEnable)? _SAR_FREERUN : 0), _SAR_FREERUN);
763 }
764
765 ////////////////////////////////////////////////////////////////////////////////
766 /// @brief \b Function \b Name: HAL_SAR_CfgSelection
767 /// @brief \b Function \b Description: Configure sar selection
768 /// @param <IN> \b bEnable : 0: disable, 1: enable
769 /// @param <OUT> \b None :
770 /// @param <RET> \b None:
771 /// @param <GLOBAL> \b None :
772 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_CfgSelection(MS_BOOL bEnable)773 void HAL_SAR_CfgSelection(MS_BOOL bEnable)
774 {
775 MS_U8 u8CtrlData,u8Mask=_SAR_SEL;
776
777 u8CtrlData = (bEnable)? u8Mask : 0;
778 HAL_SAR_WriteByteMask(REG_SAR_CTRL1, u8CtrlData, u8Mask);
779 }
780
781 ////////////////////////////////////////////////////////////////////////////////
782 /// @brief \b Function \b Name: HAL_SAR_CfgHighChannel
783 /// @brief \b Function \b Description: Configure to use high sar channel ( 4~7, or 4~5)
784 /// @param <IN> \b bEnable : 0: disable, 1: enable
785 /// @param <OUT> \b None :
786 /// @param <RET> \b None:
787 /// @param <GLOBAL> \b None :
788 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_CfgHighChannel(MS_BOOL bEnable)789 void HAL_SAR_CfgHighChannel(MS_BOOL bEnable)
790 {
791 HAL_SAR_WriteByteMask(REG_SAR_CTRL1, ((bEnable)? _SAR_NCH_EN : 0), _SAR_NCH_EN);
792 }
793
794 ////////////////////////////////////////////////////////////////////////////////
795 /// @brief \b Function \b Name: HAL_SAR_CfgClockSamplePeriod
796 /// @brief \b Function \b Description: Configure sample period
797 /// @param <IN> \b u8ClkSmpPrd :
798 /// @param <OUT> \b None :
799 /// @param <RET> \b None:
800 /// @param <GLOBAL> \b None :
801 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_CfgClockSamplePeriod(MS_U8 u8ClkSmpPrd)802 void HAL_SAR_CfgClockSamplePeriod(MS_U8 u8ClkSmpPrd)
803 {
804 HAL_SAR_WriteByteMask(REG_SAR_CKSAMP_PRD, u8ClkSmpPrd, _SAR_CKSAMP_PRD_MSK);
805 }
806
807 ////////////////////////////////////////////////////////////////////////////////
808 /// @brief \b Function \b Name: HAL_SAR_CfgAanlogInputSelect
809 /// @brief \b Function \b Description: Configure Analog Input/GPIO
810 /// @param <IN> \b u8Channel : sar channel (0~7)
811 /// @param <IN> \b bEnable : 0: GPIO, 1: Analog Input
812 /// @param <RET> \b None:
813 /// @param <GLOBAL> \b None :
814 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_CfgAanlogInputSelect(MS_U8 u8Channel,MS_BOOL bEnable)815 void HAL_SAR_CfgAanlogInputSelect(MS_U8 u8Channel, MS_BOOL bEnable)
816 {
817 MS_U8 u8CtrlData,u8Mask;
818
819 switch(u8Channel)
820 {
821 case HAL_SAR_CH1:
822 u8CtrlData = (bEnable)? _SAR_AISEL_CH1 : (~_SAR_AISEL_CH1);
823 u8Mask=_SAR_AISEL_CH1;
824 break;
825 case HAL_SAR_CH2:
826 u8CtrlData = (bEnable)? _SAR_AISEL_CH2 : (~_SAR_AISEL_CH2);
827 u8Mask=_SAR_AISEL_CH2;
828 break;
829 case HAL_SAR_CH3:
830 u8CtrlData = (bEnable)? _SAR_AISEL_CH3 : (~_SAR_AISEL_CH3);
831 u8Mask=_SAR_AISEL_CH3;
832 break;
833 case HAL_SAR_CH4:
834 u8CtrlData = (bEnable)? _SAR_AISEL_CH4 : (~_SAR_AISEL_CH4);
835 u8Mask=_SAR_AISEL_CH4;
836 break;
837 case HAL_SAR_CH5:
838 u8CtrlData = (bEnable)? _SAR_AISEL_CH5 : (~_SAR_AISEL_CH5);
839 u8Mask=_SAR_AISEL_CH5;
840 break;
841 default: return;
842 }
843 HAL_SAR_WriteByteMask(REG_SAR_AISEL, u8CtrlData, u8Mask);
844 }
845
846 ////////////////////////////////////////////////////////////////////////////////
847 /// @brief \b Function \b Name: HAL_SAR_CfgOutputEnable
848 /// @brief \b Function \b Description: Configure output enable for sar channel set as GPIO
849 /// @param <IN> \b u8Channel : sar channel (0~7)
850 /// @param <IN> \b bEnable: 0: output, 1: input
851 /// @param <RET> \b None:
852 /// @param <GLOBAL> \b None :
853 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_CfgOutputEnable(MS_U8 u8Channel,MS_BOOL bEnable)854 void HAL_SAR_CfgOutputEnable(MS_U8 u8Channel, MS_BOOL bEnable)
855 {
856 MS_U8 u8CtrlData,u8Mask;
857
858 switch(u8Channel)
859 {
860 case HAL_SAR_CH1:
861 u8CtrlData = (bEnable)? ~_SAR_OEN_GPIO_CH1 : _SAR_OEN_GPIO_CH1;
862 u8Mask = _SAR_OEN_GPIO_CH1;
863 break;
864 case HAL_SAR_CH2:
865 u8CtrlData = (bEnable)? ~_SAR_OEN_GPIO_CH2 : _SAR_OEN_GPIO_CH2;
866 u8Mask = _SAR_OEN_GPIO_CH2;
867 break;
868 case HAL_SAR_CH3:
869 u8CtrlData = (bEnable)? ~_SAR_OEN_GPIO_CH3 : _SAR_OEN_GPIO_CH3;
870 u8Mask = _SAR_OEN_GPIO_CH3;
871 break;
872 case HAL_SAR_CH4:
873 u8CtrlData = (bEnable)? ~_SAR_OEN_GPIO_CH4 : _SAR_OEN_GPIO_CH4;
874 u8Mask = _SAR_OEN_GPIO_CH4;
875 break;
876 case HAL_SAR_CH5:
877 u8CtrlData = (bEnable)? ~_SAR_OEN_GPIO_CH5 : _SAR_OEN_GPIO_CH5;
878 u8Mask = _SAR_OEN_GPIO_CH5;
879 break;
880 default: return;
881 }
882 HAL_SAR_WriteByteMask(REG_SAR_OEN_GPIO, u8CtrlData, u8Mask);
883 }
884
885 ////////////////////////////////////////////////////////////////////////////////
886 /// @brief \b Function \b Name: HAL_SAR_SetOutput
887 /// @brief \b Function \b Description: Set GPIO output value(high/low) for sar channel
888 /// @param <IN> \b u8Channel : sar channel (0~7)
889 /// @param <IN> \b bHighLow 0: low, 1: high
890 /// @param <RET> \b None:
891 /// @param <GLOBAL> \b None :
892 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_SetOutput(MS_U8 u8Channel,MS_BOOL bHighLow)893 void HAL_SAR_SetOutput(MS_U8 u8Channel, MS_BOOL bHighLow)
894 {
895 MS_U8 u8CtrlData,u8Mask;
896
897 switch(u8Channel)
898 {
899 case HAL_SAR_CH1:
900 u8CtrlData = (bHighLow)? _SAR_I_GPIO_CH1 : ~_SAR_I_GPIO_CH1;
901 u8Mask = _SAR_I_GPIO_CH1;
902 break;
903 case HAL_SAR_CH2:
904 u8CtrlData = (bHighLow)? _SAR_I_GPIO_CH2 : ~_SAR_I_GPIO_CH2;
905 u8Mask = _SAR_I_GPIO_CH2;
906 break;
907 case HAL_SAR_CH3:
908 u8CtrlData = (bHighLow)? _SAR_I_GPIO_CH3 : ~_SAR_I_GPIO_CH3;
909 u8Mask = _SAR_I_GPIO_CH3;
910 break;
911 case HAL_SAR_CH4:
912 u8CtrlData = (bHighLow)? _SAR_I_GPIO_CH4 : ~_SAR_I_GPIO_CH4;
913 u8Mask = _SAR_I_GPIO_CH4;
914 break;
915 case HAL_SAR_CH5:
916 u8CtrlData = (bHighLow)? _SAR_I_GPIO_CH5 : ~_SAR_I_GPIO_CH5;
917 u8Mask = _SAR_I_GPIO_CH5;
918 break;
919 default: return;
920 }
921 HAL_SAR_WriteByteMask(REG_SAR_I_GPIO, u8CtrlData, u8Mask);
922 }
923
924 ////////////////////////////////////////////////////////////////////////////////
925 /// @brief \b Function \b Name: HAL_SAR_GetInput
926 /// @brief \b Function \b Description: Get GPIO input value(high/low) for sar channel
927 /// @param <IN> \b u8Channel : sar channel (0~7)
928 /// @param <IN> \b bHighLow 0: low, 1: high
929 /// @param <RET> \b TRUE: High FALSE: Low
930 /// @param <GLOBAL> \b None :
931 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_GetInput(MS_U8 u8Channel)932 MS_BOOL HAL_SAR_GetInput(MS_U8 u8Channel)
933 {
934 MS_U8 u8Mask;
935
936 switch(u8Channel)
937 {
938 case HAL_SAR_CH1:
939 u8Mask = _SAR_C_GPIO_CH1;
940 break;
941 case HAL_SAR_CH2:
942 u8Mask = _SAR_C_GPIO_CH2;
943 break;
944 case HAL_SAR_CH3:
945 u8Mask = _SAR_C_GPIO_CH3;
946 break;
947 case HAL_SAR_CH4:
948 u8Mask = _SAR_C_GPIO_CH4;
949 break;
950 case HAL_SAR_CH5:
951 u8Mask = _SAR_C_GPIO_CH5;
952 break;
953 default: return FALSE;
954 }
955 return HAL_SAR_ReadRegBit(REG_SAR_C_GPIO, u8Mask);
956 }
957
958 ////////////////////////////////////////////////////////////////////////////////
959 /// @brief \b Function \b Name: HAL_SAR_CfgIntMask
960 /// @brief \b Function \b Description: Interrupt mask for sar int
961 /// @param <IN> \b bEnable : 0: enable int, 1: disable int
962 /// @param <OUT> \b None :
963 /// @param <RET> \b None:
964 /// @param <GLOBAL> \b None :
965 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_CfgIntMask(MS_BOOL bEnable)966 void HAL_SAR_CfgIntMask(MS_BOOL bEnable)
967 {
968 HAL_SAR_WriteByteMask(REG_SAR_STATUS0, ((bEnable)? _SAR_INT_MASK : 0), _SAR_INT_MASK);
969 }
970
971 ////////////////////////////////////////////////////////////////////////////////
972 /// @brief \b Function \b Name: HAL_SAR_CfgIntClear
973 /// @brief \b Function \b Description: Interrupt clear for sar int
974 /// @param <IN> \b bEnable : 0: not clear, 1: clear
975 /// @param <OUT> \b None :
976 /// @param <RET> \b None:
977 /// @param <GLOBAL> \b None :
978 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_CfgIntClear(MS_BOOL bEnable)979 void HAL_SAR_CfgIntClear(MS_BOOL bEnable)
980 {
981 HAL_SAR_WriteByteMask(REG_SAR_STATUS0, ((bEnable)? _SAR_INT_CLR : 0), _SAR_INT_CLR);
982 }
983
984 ////////////////////////////////////////////////////////////////////////////////
985 /// @brief \b Function \b Name: HAL_SAR_CfgIntForce
986 /// @brief \b Function \b Description: Force interrupt for sar int
987 /// @param <IN> \b bEnable : 0: not force, 1: force
988 /// @param <OUT> \b None :
989 /// @param <RET> \b None:
990 /// @param <GLOBAL> \b None :
991 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_CfgIntForce(MS_BOOL bEnable)992 void HAL_SAR_CfgIntForce(MS_BOOL bEnable)
993 {
994 HAL_SAR_WriteByteMask(REG_SAR_STATUS0, ((bEnable)? _SAR_INT_FORCE : 0), _SAR_INT_FORCE);
995 }
996
997 ////////////////////////////////////////////////////////////////////////////////
998 /// @brief \b Function \b Name: HAL_SAR_GetIntStatus
999 /// @brief \b Function \b Description: get sar interrupt status
1000 /// @param <IN> \b None : 0: not force, 1: force
1001 /// @param <OUT> \b None :
1002 /// @param <RET> \b TRUE: interrupt comes, FALSE: no interrupt
1003 /// @param <GLOBAL> \b None :
1004 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_GetIntStatus(void)1005 MS_BOOL HAL_SAR_GetIntStatus(void)
1006 {
1007 MS_U8 u8IntStatus;
1008
1009 u8IntStatus = HAL_SAR_ReadByte(REG_SAR_STATUS0) & _SAR_INT_STATUS;
1010 return (u8IntStatus)? ENABLE : DISABLE;
1011 }
1012
1013
1014 ////////////////////////////////////////////////////////////////////////////////
1015 /// @brief \b Function \b Name: HAL_SAR_SetIOMapBase_NPM
1016 /// @brief \b Function \b Description: Set IO Map base
1017 /// @param <IN> \b u32Base : io map base address
1018 /// @param <OUT> \b None :
1019 /// @param <RET> \b None :
1020 /// @param <GLOBAL> \b None :
1021 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_SetIOMapBase_NPM(MS_U32 u32Base)1022 void HAL_SAR_SetIOMapBase_NPM(MS_U32 u32Base)
1023 {
1024 _gMIO_MapBase_NPM = u32Base;
1025 HAL_SAR_INFO("SAR NPM IOMap base:%8lx Reg offset:%4x\n", u32Base);
1026 }
1027
1028 ////////////////////////////////////////////////////////////////////////////////
1029 /// @brief \b Function \b Name: HAL_SAR_GetIOMapBase_NPM
1030 /// @brief \b Function \b Description: Get IO Map base
1031 /// @param <IN> \b None :
1032 /// @param <OUT> \b None :
1033 /// @param <RET> \b MS_U32 : io map base address
1034 /// @param <GLOBAL> \b None :
1035 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_GetIOMapBase_NPM(void)1036 MS_U32 HAL_SAR_GetIOMapBase_NPM(void)
1037 {
1038 return _gMIO_MapBase_NPM;
1039 }
1040
1041 ////////////////////////////////////////////////////////////////////////////////
1042 /// @brief \b Function \b Name: HAL_SAR_SetAdcHSyncChannel
1043 /// @brief \b Function \b Description: Switch HSync signal to SAR High channel
1044 /// @param <IN> \b u8Channel : ADC HSync channel (0~2)
1045 /// @param <RET> \b TRUE: Success FALSE: Fail
1046 /// @param <GLOBAL> \b None :
1047 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_SetAdcHSyncChannel(MS_U8 u8Channel)1048 MS_BOOL HAL_SAR_SetAdcHSyncChannel(MS_U8 u8Channel)
1049 {
1050 MS_U8 u8HSyncCh;
1051
1052 switch(u8Channel)
1053 {
1054 case HAL_SAR_ADC_HSYNC_CH0:
1055 u8HSyncCh = _SAR2_HSYNC_CH0;
1056 break;
1057 case HAL_SAR_ADC_HSYNC_CH1:
1058 u8HSyncCh = _SAR2_HSYNC_CH1;
1059 break;
1060 case HAL_SAR_ADC_HSYNC_CH2:
1061 u8HSyncCh = _SAR2_HSYNC_CH2;
1062 break;
1063 case HAL_SAR_ADC_HSYNC_CH3:
1064 u8HSyncCh = _SAR2_HSYNC_CH3;
1065 break;
1066 default: return FALSE;
1067 }
1068 return HAL_SAR_WriteByteMask_NPM(REG_ADC_ATOP_SAR2, u8HSyncCh, _SAR2_HSYNC_MSK);
1069
1070 }
1071
1072 ////////////////////////////////////////////////////////////////////////////////
1073 /// @brief \b Function \b Name: HAL_SAR_Interrupt_EN
1074 /// @brief \b Function \b Description: Switch SAR Interrupt Enable/Disable
1075 /// @param <IN> \b u8Channel : ADC HSync channel (0~3)
1076 /// @param <IN> \b bEnablel : True: enable interrupt; False: disable interrupt
1077 /// @param <OUT> \b None :
1078 /// @param <RET> \b TRUE: Success FALSE: Fail
1079 /// @param <GLOBAL> \b None :
1080 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_Interrupt_EN(MS_U8 u8Channel,MS_BOOL bEnable)1081 MS_BOOL HAL_SAR_Interrupt_EN(MS_U8 u8Channel, MS_BOOL bEnable)
1082 {
1083 return HAL_SAR_WriteByteMask(REG_SAR_INT, ((bEnable)? 1<<u8Channel : 0), 1<<u8Channel);
1084 }
1085
1086 ////////////////////////////////////////////////////////////////////////////////
1087 /// @brief \b Function \b Name: HAL_SAR_Wakeup_EN
1088 /// @brief \b Function \b Description: Switch SAR Interrupt Wakeup Enable/Disable
1089 /// @param <IN> \b bEnablel : True: enable interrrupt wakeup; False: disable interrupt wakeup
1090 /// @param <OUT> \b None :
1091 /// @param <RET> \b TRUE: Success FALSE: Fail
1092 /// @param <GLOBAL> \b None :
1093 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_Wakeup_EN(MS_BOOL bEnable)1094 MS_BOOL HAL_SAR_Wakeup_EN(MS_BOOL bEnable)
1095 {
1096 return HAL_SAR_WriteByteMask(REG_WK_IRQ, ((bEnable)? _W_SAR : 0), _W_SAR);
1097 }
1098
1099 ////////////////////////////////////////////////////////////////////////////////
1100 /// @brief \b Function \b Name: HAL_SAR_CLR_INT
1101 /// @brief \b Function \b Description: Switch SAR Clear Interrupt Status
1102 /// @param <IN> \b u8Channel : ADC HSync channel (0~3)
1103 /// @param <OUT> \b None :
1104 /// @param <RET> \b None
1105 /// @param <GLOBAL> \b None :
1106 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_CLR_INT(MS_U8 u8Channel)1107 void HAL_SAR_CLR_INT(MS_U8 u8Channel)
1108 {
1109 HAL_SAR_WriteByteMask(REG_SAR_CLR_INT, 1<<u8Channel, 1<<u8Channel);
1110 HAL_SAR_WriteByteMask(REG_SAR_CLR_INT, 0, 1<<u8Channel);
1111 }
1112
1113 ////////////////////////////////////////////////////////////////////////////////
1114 /// @brief \b Function \b Name: HAL_SAR_INT_Status
1115 /// @brief \b Function \b Description: get sar interrupt status
1116 /// @param <IN> \b u8Channel : ADC HSync channel (0~3)
1117 /// @param <OUT> \b None :
1118 /// @param <RET> \b TRUE: interrupt comes, FALSE: no interrupt
1119 /// @param <GLOBAL> \b None :
1120 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_INT_Status(MS_U8 u8Channel)1121 MS_BOOL HAL_SAR_INT_Status(MS_U8 u8Channel)
1122 {
1123 return (HAL_SAR_ReadByte(REG_SAR_INT_STATUS) & (1<<u8Channel)) > 0? TRUE : FALSE;
1124 }
1125
1126 ////////////////////////////////////////////////////////////////////////////////
1127 /// @brief \b Function \b Name: HAL_SAR_SET_LEVEL
1128 /// @brief \b Function \b Description: set sar level is 2.0V or 3.3V
1129 /// @param <IN> \b bLevel : 1:3.3V , 0:2.0V
1130 /// @param <OUT> \b None :
1131 /// @param <RET> \b Nonw:
1132 /// @param <GLOBAL> \b None :
1133 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_SET_LEVEL(MS_BOOL bLevel)1134 void HAL_SAR_SET_LEVEL(MS_BOOL bLevel)
1135 {
1136 //HAL_SAR_WriteByteMask(REG_SAR_TEST0, (bLevel? 1<<6:0) , 1<<6);
1137 HAL_SAR_WriteByteMask(REG_SAR__REF_V_SEL, (bLevel?0xFF:0x00), 0xFF);
1138 }
1139
1140 #ifdef CONFIG_MSTAR_DVFS_ENABLE
1141 ////////////////////////////////////////////////////////////////////////////////
1142 /// @brief \b Function \b Name: HAL_SAR_TSENSOR_OP
1143 /// @brief \b Function \b Description: Read T-Sensor to Handle DVFS Flow
1144 /// @param <IN> \b None:
1145 /// @param <OUT> \b None:
1146 /// @param <RET> \b None:
1147 /// @param <GLOBAL> \b None:
1148 ////////////////////////////////////////////////////////////////////////////////
HAL_SAR_TSENSOR_OP(void)1149 void HAL_SAR_TSENSOR_OP(void)
1150 {
1151 unsigned int dwRegisterValue = 0;
1152 static MSTAR_DVFS_INFO hMstarDvfsInfo =
1153 {
1154 .bDvfsInitOk = 0,
1155 .bCpuClockLevel = CONFIG_DVFS_STATE_INIT,
1156 .dwOverCounter = 0,
1157 .dwEfuseSiddValue = 0,
1158
1159 .dwFinalCpuTemperature = 0,
1160 .dwAvgTempCounterCpu = 0,
1161 .dwCode25CValueCpu = 0,
1162
1163 #if CONFIG_DVFS_FULL_TEST_ENABLE
1164 .dwFinalPmTemperature = 0,
1165 .dwAvgTempCounterPm = 0,
1166 .dwCode25CValuePm = 0,
1167 #endif
1168 };
1169
1170 dwRegisterValue = *(volatile unsigned short *)(_gMIO_MapBase + (0x100500 << 1));
1171 if(dwRegisterValue == CONFIG_DVFS_ENABLE_PATTERN)
1172 {
1173 int dwCoreChipValue = 0;
1174 int dwChipTempValue = 0;
1175 int dwUpperTemperature = 0;
1176 int dwLowerTemperature = 0;
1177 int dwResetTemperature = 0;
1178
1179 if(hMstarDvfsInfo.bDvfsInitOk == 0)
1180 {
1181 _s32SAR_Dvfs_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, "Mutex SAR_DVFS", MSOS_PROCESS_SHARED);
1182 MS_ASSERT(_s32SAR_Dvfs_Mutex >= 0);
1183 }
1184
1185 if (FALSE == MsOS_ObtainMutex(_s32SAR_Dvfs_Mutex, CONFIG_DVFS_MUTEX_WAIT_TIME))
1186 {
1187 HAL_DVFS_INFO("[DVFS] Mutex Lock Fail\n");
1188 return;
1189 }
1190
1191 if(hMstarDvfsInfo.bDvfsInitOk == 0)
1192 {
1193 //Init Basic Register Settings
1194 // *(volatile unsigned short *)(_gMIO_MapBase + (0x100500 << 1)) = 0; //Enable
1195 // *(volatile unsigned short *)(_gMIO_MapBase + (0x100502 << 1)) = 900; //Current CPU Clock
1196 // *(volatile unsigned short *)(_gMIO_MapBase + (0x100504 << 1)) = 25; //Current Temperature (CPU)
1197 // *(volatile unsigned short *)(_gMIO_MapBase + (0x100506 << 1)) = 25; //Current Temperature (PM)
1198 // *(volatile unsigned short *)(_gMIO_MapBase + (0x100508 << 1)) = CONFIG_DVFS_UPPER_BOUND; //Upper Bound of T-sensor
1199 // *(volatile unsigned short *)(_gMIO_MapBase + (0x10050a << 1)) = CONFIG_DVFS_LOWER_BOUND; //Lower Bound of T-sensor
1200 // *(volatile unsigned short *)(_gMIO_MapBase + (0x10050c << 1)) = 0; //SIDD
1201 // *(volatile unsigned short *)(_gMIO_MapBase + (0x10050e << 1)) = CONFIG_DVFS_THRESHOLD; //Upper Bound of Global Reset
1202
1203 //=========================================================
1204 //SIDD = Bank1[21:12] = 0x00200E[5:0] + 0x00200C[15:12]
1205 hMstarDvfsInfo.dwEfuseSiddValue = *(volatile unsigned short *)(_gMIO_MapBase + (0x00200e << 1));
1206 hMstarDvfsInfo.dwEfuseSiddValue &= 0x3F;
1207 hMstarDvfsInfo.dwEfuseSiddValue <<= 4;
1208 dwRegisterValue = *(volatile unsigned short *)(_gMIO_MapBase + (0x00200c << 1));
1209 dwRegisterValue >>= 12;
1210 dwRegisterValue &= 0x0F;
1211 hMstarDvfsInfo.dwEfuseSiddValue |= hMstarDvfsInfo.dwEfuseSiddValue;
1212
1213 hMstarDvfsInfo.dwEfuseSiddThreshold = *(volatile unsigned short *)(_gMIO_MapBase + (0x10050c << 1));
1214
1215 if(hMstarDvfsInfo.dwEfuseSiddValue < hMstarDvfsInfo.dwEfuseSiddThreshold)
1216 {
1217 //Set VID = 2'b03 to change to 1.28V
1218 *(volatile unsigned short *)(_gMIO_MapBase + (0x110cb2 << 1)) = 0x1330;
1219 }
1220 else
1221 {
1222 //Set VID = 2'b01 to change to 1.20V
1223 *(volatile unsigned short *)(_gMIO_MapBase + (0x110cb2 << 1)) = 0x1130;
1224 }
1225
1226 //Enable VID
1227 dwRegisterValue = *(volatile unsigned short *)(_gMIO_MapBase + (0x000efa << 1));
1228 dwRegisterValue &= ~(0x01 << 8);
1229 *(volatile unsigned short *)(_gMIO_MapBase + (0x000efa << 1)) = dwRegisterValue;
1230
1231 #if CONFIG_DVFS_FULL_TEST_ENABLE
1232 //=========================================================
1233 //Read 25 degree in PM side
1234 *(volatile unsigned char *)(_gMIO_MapBase + (0x000e50 << 1)) = 0x06;
1235
1236 dwRegisterValue = *(volatile unsigned short *)(_gMIO_MapBase + (0x000ec4 << 1));
1237 dwRegisterValue &= ~(0x01 << 13);
1238 *(volatile unsigned short *)(_gMIO_MapBase + (0x000ec4 << 1)) = dwRegisterValue;
1239
1240 *(volatile unsigned short *)(_gMIO_MapBase + (0x001400 << 1)) = 0x0ab5;
1241 *(volatile unsigned short *)(_gMIO_MapBase + (0x001426 << 1)) &= ~(0x01 << 6); //Set PM SAR full scale = 2.0V
1242 MsOS_DelayTaskUs(CONFIG_DVFS_DELAY_US);
1243
1244 hMstarDvfsInfo.dwCode25CValuePm = *(volatile unsigned short *)(_gMIO_MapBase + (0x00148a << 1)); //CH6
1245 *(volatile unsigned short *)(_gMIO_MapBase + (0x001426 << 1)) |= (0x01 << 6); //Set PM SAR full scale = 3.3V
1246 *(volatile unsigned short *)(_gMIO_MapBase + (0x001400 << 1)) = 0x0a25;
1247 #endif
1248
1249 //=========================================================
1250 //Read 25 degree in CPU side
1251 *(volatile unsigned char *)(_gMIO_MapBase + (0x000e50 << 1)) = 0x07;
1252
1253 dwRegisterValue = *(volatile unsigned short *)(_gMIO_MapBase + (0x000ec4 << 1));
1254 dwRegisterValue &= ~(0x01 << 13);
1255 *(volatile unsigned short *)(_gMIO_MapBase + (0x000ec4 << 1)) = dwRegisterValue;
1256
1257 *(volatile unsigned short *)(_gMIO_MapBase + (0x001400 << 1)) = 0x0ab5;
1258 *(volatile unsigned short *)(_gMIO_MapBase + (0x001426 << 1)) &= ~(0x01 << 6); //Set PM SAR full scale = 2.0V
1259 MsOS_DelayTaskUs(CONFIG_DVFS_DELAY_US);
1260
1261 hMstarDvfsInfo.dwCode25CValueCpu = *(volatile unsigned short *)(_gMIO_MapBase + (0x00148a << 1)); //CH6
1262 *(volatile unsigned short *)(_gMIO_MapBase + (0x001426 << 1)) |= (0x01 << 6); //Set PM SAR full scale = 3.3V
1263 *(volatile unsigned short *)(_gMIO_MapBase + (0x001400 << 1)) = 0x0a25;
1264
1265 #if CONFIG_DVFS_CPU_CLOCK_DISPLAY_ENABLE
1266 //=========================================================
1267 //Init Test Bus for CPU Clock
1268 dwRegisterValue = *(volatile unsigned short *)(_gMIO_MapBase + (0x101896 << 1));
1269 dwRegisterValue &= ~(0x07);
1270 dwRegisterValue |= 0x01;
1271 *(volatile unsigned short *)(_gMIO_MapBase + (0x101896 << 1)) = dwRegisterValue;
1272
1273 dwRegisterValue = *(volatile unsigned short *)(_gMIO_MapBase + (0x101eec << 1));
1274 dwRegisterValue |= 0x0100;
1275 *(volatile unsigned short *)(_gMIO_MapBase + (0x101eec << 1)) = dwRegisterValue;
1276 *(volatile unsigned short *)(_gMIO_MapBase + (0x101eea << 1)) = 0;
1277
1278 dwRegisterValue = *(volatile unsigned short *)(_gMIO_MapBase + (0x101eea << 1));
1279 dwRegisterValue &= ~(0x07);
1280 dwRegisterValue |= 0x04;
1281 dwRegisterValue &= ~(0x01 << 4);
1282 dwRegisterValue &= ~(0x01 << 5);
1283 dwRegisterValue &= ~(0x01 << 6);
1284 dwRegisterValue |= (0x01 << 14);
1285 *(volatile unsigned short *)(_gMIO_MapBase + (0x101eea << 1)) = dwRegisterValue;
1286
1287 dwRegisterValue = *(volatile unsigned short *)(_gMIO_MapBase + (0x101eee << 1));
1288 dwRegisterValue &= ~(0x7F);
1289 dwRegisterValue |= 0x1F;
1290 *(volatile unsigned short *)(_gMIO_MapBase + (0x101eee << 1)) = dwRegisterValue;
1291 #endif
1292
1293 hMstarDvfsInfo.bCpuClockLevel = CONFIG_DVFS_STATE_INIT;
1294 hMstarDvfsInfo.bDvfsInitOk = 1;
1295 }
1296
1297 #if CONFIG_DVFS_FULL_TEST_ENABLE
1298 //=========================================================
1299 //Read Chip degree in PM side
1300 *(volatile unsigned char *)(_gMIO_MapBase + (0x000e50 << 1)) = 0x06;
1301
1302 dwRegisterValue = *(volatile unsigned short *)(_gMIO_MapBase + (0x000ec4 << 1));
1303 dwRegisterValue &= ~(0x01 << 13);
1304 *(volatile unsigned short *)(_gMIO_MapBase + (0x000ec4 << 1)) = dwRegisterValue;
1305 dwRegisterValue |= (0x01 << 13);
1306 *(volatile unsigned short *)(_gMIO_MapBase + (0x000ec4 << 1)) = dwRegisterValue;
1307
1308 *(volatile unsigned short *)(_gMIO_MapBase + (0x001400 << 1)) = 0x0ab5;
1309 *(volatile unsigned short *)(_gMIO_MapBase + (0x001426 << 1)) &= ~(0x01 << 6); //Set PM SAR full scale = 2.0V
1310 MsOS_DelayTaskUs(CONFIG_DVFS_DELAY_US);
1311
1312 dwCoreChipValue = *(volatile unsigned short *)(_gMIO_MapBase + (0x00148a << 1)); //CH6
1313 *(volatile unsigned short *)(_gMIO_MapBase + (0x001426 << 1)) |= (0x01 << 6); //Set PM SAR full scale = 3.3V
1314 *(volatile unsigned short *)(_gMIO_MapBase + (0x001400 << 1)) = 0x0a25;
1315
1316 hMstarDvfsInfo.dwAvgTempBufferPm[hMstarDvfsInfo.dwAvgTempCounterPm] = dwCoreChipValue;
1317 hMstarDvfsInfo.dwAvgTempCounterPm ++;
1318 if(hMstarDvfsInfo.dwAvgTempCounterPm >= CONFIG_DVFS_AVERAGE_COUNT)
1319 {
1320 unsigned int dwTempCounter = 0;
1321 unsigned int dwTempValue = 0;
1322
1323 HAL_DVFS_DEBUG("[DVFS] .................. Start\n");
1324
1325 HAL_DVFS_DEBUG("[DVFS] 25-degree (PM): 0x%04x\n", (unsigned int) hMstarDvfsInfo.dwCode25CValuePm);
1326 HAL_DVFS_DEBUG("[DVFS] Chip-degree (PM): ");
1327 for(dwTempCounter = 0; dwTempCounter < CONFIG_DVFS_AVERAGE_COUNT; dwTempCounter ++)
1328 {
1329 //HAL_DVFS_DEBUG(" - %d: 0x%04x\n", dwTempCounter, dwAvgTempBufferPm[dwTempCounter]);
1330 dwTempValue += hMstarDvfsInfo.dwAvgTempBufferPm[dwTempCounter];
1331 }
1332 dwTempValue /= CONFIG_DVFS_AVERAGE_COUNT;
1333
1334 HAL_DVFS_DEBUG("0x%04x\n", dwTempValue);
1335
1336 //dwChipTempValue = ((((((dwCode25CValuePm - dwTempValue) * 1000) * 2000) / 1024) / 1.545) + 25000);
1337 if(hMstarDvfsInfo.dwCode25CValuePm >= dwCoreChipValue)
1338 {
1339 dwChipTempValue = (((hMstarDvfsInfo.dwCode25CValuePm - dwTempValue) * 1264) + 29000);
1340 }
1341 else
1342 {
1343 dwChipTempValue = ((dwTempValue - hMstarDvfsInfo.dwCode25CValuePm) * 1264);
1344 dwChipTempValue = (29000 - dwChipTempValue);
1345 }
1346
1347 hMstarDvfsInfo.dwFinalPmTemperature = (dwChipTempValue / 1000);
1348 HAL_DVFS_DEBUG("[DVFS] Average Temperature (PM): %d\n", (unsigned int) hMstarDvfsInfo.dwFinalPmTemperature);
1349 *(volatile unsigned short *)(_gMIO_MapBase + (0x100506 << 1)) = hMstarDvfsInfo.dwFinalPmTemperature;
1350
1351 hMstarDvfsInfo.dwAvgTempCounterPm = 0;
1352
1353 HAL_DVFS_DEBUG("[DVFS] .................. End\n");
1354 }
1355 #endif
1356
1357 //=========================================================
1358 //Read Chip degree in CPU side
1359 *(volatile unsigned char *)(_gMIO_MapBase + (0x000e50 << 1)) = 0x07;
1360
1361 dwRegisterValue = *(volatile unsigned short *)(_gMIO_MapBase + (0x000ec4 << 1));
1362 dwRegisterValue &= ~(0x01 << 13);
1363 *(volatile unsigned short *)(_gMIO_MapBase + (0x000ec4 << 1)) = dwRegisterValue;
1364
1365 *(volatile unsigned short *)(_gMIO_MapBase + (0x001400 << 1)) = 0x0ab6;
1366 *(volatile unsigned short *)(_gMIO_MapBase + (0x001426 << 1)) &= ~(0x01 << 6); //Set PM SAR full scale = 2.0V
1367 MsOS_DelayTaskUs(CONFIG_DVFS_DELAY_US);
1368
1369 dwCoreChipValue = *(volatile unsigned short *)(_gMIO_MapBase + (0x00148c << 1)); //CH7
1370 *(volatile unsigned short *)(_gMIO_MapBase + (0x001426 << 1)) |= (0x01 << 6); //Set PM SAR full scale = 3.3V
1371 *(volatile unsigned short *)(_gMIO_MapBase + (0x001400 << 1)) = 0x0a26;
1372
1373 hMstarDvfsInfo.dwAvgTempBufferCpu[hMstarDvfsInfo.dwAvgTempCounterCpu] = dwCoreChipValue;
1374 hMstarDvfsInfo.dwAvgTempCounterCpu ++;
1375 if(hMstarDvfsInfo.dwAvgTempCounterCpu >= CONFIG_DVFS_AVERAGE_COUNT)
1376 {
1377 unsigned int dwTempCounter = 0;
1378 unsigned int dwTempValue = 0;
1379
1380 HAL_DVFS_DEBUG("[DVFS] .................. Start\n");
1381
1382 HAL_DVFS_DEBUG("[DVFS] 25-degree (CPU): 0x%04x\n", (unsigned int) hMstarDvfsInfo.dwCode25CValueCpu);
1383 HAL_DVFS_DEBUG("[DVFS] Chip-degree (CPU):");
1384 for(dwTempCounter = 0; dwTempCounter < CONFIG_DVFS_AVERAGE_COUNT; dwTempCounter ++)
1385 {
1386 //HAL_DVFS_DEBUG(" - %d: 0x%04x\n", dwTempCounter, dwAvgTempBufferCpu[dwTempCounter]);
1387 dwTempValue += hMstarDvfsInfo.dwAvgTempBufferCpu[dwTempCounter];
1388 }
1389 dwTempValue /= CONFIG_DVFS_AVERAGE_COUNT;
1390
1391 HAL_DVFS_DEBUG("0x%04x\n", dwTempValue);
1392
1393 //dwChipTempValue = ((((((dwCode25CValueCpu - dwTempValue) * 1000) * 2000) / 1024) / 1.545) + 25000);
1394 if(hMstarDvfsInfo.dwCode25CValueCpu >= dwTempValue)
1395 {
1396 dwChipTempValue = (((hMstarDvfsInfo.dwCode25CValueCpu - dwTempValue) * 1264) + 29000);
1397 }
1398 else
1399 {
1400 dwChipTempValue = ((dwTempValue - hMstarDvfsInfo.dwCode25CValueCpu) * 1264);
1401 dwChipTempValue = (29000 - dwChipTempValue);
1402 }
1403
1404 hMstarDvfsInfo.dwFinalCpuTemperature = (dwChipTempValue / 1000);
1405 HAL_DVFS_DEBUG("[DVFS] Average Temperature (CPU): %d\n", (unsigned int) hMstarDvfsInfo.dwFinalCpuTemperature);
1406 *(volatile unsigned short *)(_gMIO_MapBase + (0x100504 << 1)) = hMstarDvfsInfo.dwFinalCpuTemperature;
1407
1408 hMstarDvfsInfo.dwAvgTempCounterCpu = 0;
1409
1410 #if CONFIG_DVFS_CPU_CLOCK_DISPLAY_ENABLE
1411 dwRegisterValue = *(volatile unsigned short *)(_gMIO_MapBase + (0x101efc << 1));
1412 dwRegisterValue *= 12;
1413 dwRegisterValue /= 1000;
1414 dwRegisterValue *= 4;
1415 *(volatile unsigned short *)(_gMIO_MapBase + (0x100502 << 1)) = dwRegisterValue;
1416
1417 HAL_DVFS_DEBUG("[DVFS] Current CPU Clock: %dMHz\n", dwRegisterValue);
1418 #endif
1419
1420 HAL_DVFS_DEBUG("[DVFS] .................. End\n");
1421 }
1422
1423 //=========================================================
1424 dwUpperTemperature = *(volatile unsigned short *)(_gMIO_MapBase + (0x100508 << 1));
1425 if(dwUpperTemperature == 0)
1426 {
1427 dwUpperTemperature = *(volatile unsigned short *)(_gMIO_MapBase + (0x00144c << 1));
1428 }
1429
1430 dwLowerTemperature = *(volatile unsigned short *)(_gMIO_MapBase + (0x10050a << 1));
1431 if(dwLowerTemperature == 0)
1432 {
1433 dwLowerTemperature = *(volatile unsigned short *)(_gMIO_MapBase + (0x00146c << 1));
1434 }
1435
1436 dwResetTemperature = *(volatile unsigned short *)(_gMIO_MapBase + (0x10050e << 1));
1437 if(dwResetTemperature == 0)
1438 {
1439 dwResetTemperature = 150;
1440 }
1441
1442 if((hMstarDvfsInfo.dwFinalCpuTemperature > dwResetTemperature) && (hMstarDvfsInfo.bCpuClockLevel != CONFIG_DVFS_STATE_INIT))
1443 {
1444 if(hMstarDvfsInfo.dwOverCounter < CONFIG_DVFS_AVERAGE_COUNT)
1445 {
1446 HAL_DVFS_DEBUG("[DVFS] Over Temperature Protection: %d\n", (unsigned int) hMstarDvfsInfo.dwOverCounter);
1447 hMstarDvfsInfo.dwOverCounter ++;
1448 }
1449 else
1450 {
1451 //Trigger a WDT Reset
1452 HAL_DVFS_INFO("[DVFS] Over Temperature Protection\n");
1453 *(volatile unsigned short *)(_gMIO_MapBase + (0x00300a << 1)) = 0;
1454 *(volatile unsigned short *)(_gMIO_MapBase + (0x003008 << 1)) = 0;
1455 *(volatile unsigned short *)(_gMIO_MapBase + (0x00300a << 1)) = 5;
1456 *(volatile unsigned short *)(_gMIO_MapBase + (0x003000 << 1)) = 1;
1457
1458 HAL_DVFS_INFO("[DVFS] Edit while(1) to return for Coverity Warning;\n");
1459 return;
1460 }
1461 }
1462 else if((hMstarDvfsInfo.dwFinalCpuTemperature > dwUpperTemperature) && (hMstarDvfsInfo.bCpuClockLevel == CONFIG_DVFS_STATE_HIGH_SPEED))
1463 {
1464 if(hMstarDvfsInfo.dwOverCounter < CONFIG_DVFS_AVERAGE_COUNT)
1465 {
1466 hMstarDvfsInfo.dwOverCounter ++;
1467 }
1468 else
1469 {
1470 HAL_DVFS_INFO("[DVFS] Current Temperature: %d\n", (unsigned int) hMstarDvfsInfo.dwFinalCpuTemperature);
1471 HAL_DVFS_INFO("[DVFS] Change to Lower CPU Clock Setting\n");
1472
1473 //high to low
1474 *(volatile unsigned short *)(_gMIO_MapBase + (0x110cb0 << 1)) = 1; //switch to LPF control
1475 *(volatile unsigned short *)(_gMIO_MapBase + (0x110caa << 1)) = 6; //mu[2:0]
1476 *(volatile unsigned short *)(_gMIO_MapBase + (0x110cae << 1)) = 8; //lpf_update_cnt[7:0]
1477
1478 if(hMstarDvfsInfo.dwEfuseSiddValue < hMstarDvfsInfo.dwEfuseSiddThreshold)
1479 {
1480 //Set VID = 2'b03 to change to 1.28V
1481 *(volatile unsigned short *)(_gMIO_MapBase + (0x110cb2 << 1)) = 0x0330;
1482 }
1483 else
1484 {
1485 //Set VID = 2'b01 to change to 1.20V
1486 *(volatile unsigned short *)(_gMIO_MapBase + (0x110cb2 << 1)) = 0x0130;
1487 }
1488
1489 *(volatile unsigned short *)(_gMIO_MapBase + (0x110ca8 << 1)) = 0;
1490 *(volatile unsigned short *)(_gMIO_MapBase + (0x110ca8 << 1)) = 1;
1491
1492 if(hMstarDvfsInfo.dwEfuseSiddValue < hMstarDvfsInfo.dwEfuseSiddThreshold)
1493 {
1494 HAL_DVFS_DEBUG("[DVFS] Change CPU Power to 1.20V\n");
1495 *(volatile unsigned short *)(_gMIO_MapBase + (0x110cb2 << 1)) = 0x0130;
1496 }
1497 else
1498 {
1499 HAL_DVFS_DEBUG("[DVFS] Change CPU Power to 1.15V\n");
1500 *(volatile unsigned short *)(_gMIO_MapBase + (0x110cb2 << 1)) = 0x0030;
1501 }
1502
1503 hMstarDvfsInfo.bCpuClockLevel = CONFIG_DVFS_STATE_LOW_SPEED;
1504 hMstarDvfsInfo.dwOverCounter = 0;
1505 }
1506
1507 }
1508 else if((hMstarDvfsInfo.dwFinalCpuTemperature < dwLowerTemperature) && (hMstarDvfsInfo.bCpuClockLevel == CONFIG_DVFS_STATE_LOW_SPEED))
1509 {
1510 if(hMstarDvfsInfo.dwOverCounter < CONFIG_DVFS_AVERAGE_COUNT)
1511 {
1512 hMstarDvfsInfo.dwOverCounter ++;
1513 }
1514 else
1515 {
1516 HAL_DVFS_INFO("[DVFS] Current Temperature: %d\n", (unsigned int) hMstarDvfsInfo.dwFinalCpuTemperature);
1517
1518 if(hMstarDvfsInfo.dwEfuseSiddValue < hMstarDvfsInfo.dwEfuseSiddThreshold)
1519 {
1520 //Set VID = 2'b03 to change to 1.28V
1521 HAL_DVFS_DEBUG("[DVFS] Change CPU Power to 1.28V\n");
1522 *(volatile unsigned short *)(_gMIO_MapBase + (0x110cb2 << 1)) = 0x1330;
1523 }
1524 else
1525 {
1526 //Set VID = 2'b01 to change to 1.20V
1527 HAL_DVFS_DEBUG("[DVFS] Change CPU Power to 1.20V\n");
1528 *(volatile unsigned short *)(_gMIO_MapBase + (0x110cb2 << 1)) = 0x1130;
1529 }
1530
1531 //low to high
1532 HAL_DVFS_INFO("[DVFS] Change to Higher CPU Clock Setting\n");
1533 *(volatile unsigned short *)(_gMIO_MapBase + (0x110cb0 << 1)) = 1; //switch to LPF control
1534 *(volatile unsigned short *)(_gMIO_MapBase + (0x110caa << 1)) = 6; //mu[2:0]
1535 *(volatile unsigned short *)(_gMIO_MapBase + (0x110cae << 1)) = 8; //lpf_update_cnt[7:0]
1536 if(hMstarDvfsInfo.dwEfuseSiddValue < hMstarDvfsInfo.dwEfuseSiddThreshold)
1537 {
1538 *(volatile unsigned short *)(_gMIO_MapBase + (0x110cb2 << 1)) = 0x1330;
1539 }
1540 else
1541 {
1542 *(volatile unsigned short *)(_gMIO_MapBase + (0x110cb2 << 1)) = 0x1130;
1543 }
1544
1545 *(volatile unsigned short *)(_gMIO_MapBase + (0x110ca8 << 1)) = 0;
1546 *(volatile unsigned short *)(_gMIO_MapBase + (0x110ca8 << 1)) = 1;
1547
1548 hMstarDvfsInfo.bCpuClockLevel = CONFIG_DVFS_STATE_HIGH_SPEED;
1549 hMstarDvfsInfo.dwOverCounter = 0;
1550 }
1551
1552 }
1553 else
1554 {
1555 if(hMstarDvfsInfo.bCpuClockLevel == CONFIG_DVFS_STATE_INIT)
1556 {
1557
1558 dwRegisterValue = *(volatile unsigned short *)(_gMIO_MapBase + (0x11088a << 1));
1559
1560 if((dwRegisterValue & 0x0002) == 0)
1561 {
1562 hMstarDvfsInfo.dwOverCounter ++;
1563 HAL_DVFS_DEBUG("[DVFS] Wait for GPU Ready (%d)\n", (unsigned int) hMstarDvfsInfo.dwOverCounter);
1564 if(hMstarDvfsInfo.dwOverCounter >= 100)
1565 {
1566
1567 if(hMstarDvfsInfo.dwEfuseSiddValue < hMstarDvfsInfo.dwEfuseSiddThreshold)
1568 {
1569 //Set VID = 2'b03 to change to 1.28V
1570 HAL_DVFS_DEBUG("[DVFS] Change CPU Power to 1.28V\n");
1571 *(volatile unsigned short *)(_gMIO_MapBase + (0x110cb2 << 1)) = 0x1330;
1572 }
1573 else
1574 {
1575 //Set VID = 2'b01 to change to 1.20V
1576 HAL_DVFS_DEBUG("[DVFS] Change CPU Power to 1.20V\n");
1577 *(volatile unsigned short *)(_gMIO_MapBase + (0x110cb2 << 1)) = 0x1130;
1578 }
1579
1580 //low to high
1581 *(volatile unsigned short *)(_gMIO_MapBase + (0x110cb0 << 1)) = 1; //switch to LPF control
1582 *(volatile unsigned short *)(_gMIO_MapBase + (0x110caa << 1)) = 6; //mu[2:0]
1583 *(volatile unsigned short *)(_gMIO_MapBase + (0x110cae << 1)) = 8; //lpf_update_cnt[7:0]
1584 if(hMstarDvfsInfo.dwEfuseSiddValue < hMstarDvfsInfo.dwEfuseSiddThreshold)
1585 {
1586 *(volatile unsigned short *)(_gMIO_MapBase + (0x110cb2 << 1)) = 0x1330;
1587 }
1588 else
1589 {
1590 *(volatile unsigned short *)(_gMIO_MapBase + (0x110cb2 << 1)) = 0x1130;
1591 }
1592
1593 *(volatile unsigned short *)(_gMIO_MapBase + (0x110ca8 << 1)) = 0;
1594 *(volatile unsigned short *)(_gMIO_MapBase + (0x110ca8 << 1)) = 1;
1595
1596 hMstarDvfsInfo.bCpuClockLevel = CONFIG_DVFS_STATE_HIGH_SPEED;
1597 hMstarDvfsInfo.dwOverCounter = 0;
1598 }
1599 }
1600 else
1601 {
1602 hMstarDvfsInfo.dwOverCounter = 0;
1603 }
1604 }
1605 else
1606 {
1607 hMstarDvfsInfo.dwOverCounter = 0;
1608 }
1609 }
1610
1611 #if CONFIG_DVFS_FULL_TEST_ENABLE
1612 //=========================================================
1613 //Read 25 degree in PM side
1614 *(volatile unsigned char *)(_gMIO_MapBase + (0x000e50 << 1)) = 0x06;
1615
1616 dwRegisterValue = *(volatile unsigned short *)(_gMIO_MapBase + (0x000ec4 << 1));
1617 dwRegisterValue &= ~(0x01 << 13);
1618 *(volatile unsigned short *)(_gMIO_MapBase + (0x000ec4 << 1)) = dwRegisterValue;
1619
1620 *(volatile unsigned short *)(_gMIO_MapBase + (0x001400 << 1)) = 0x0ab5;
1621 *(volatile unsigned short *)(_gMIO_MapBase + (0x001426 << 1)) &= ~(0x01 << 6); //Set PM SAR full scale = 2.0V
1622 MsOS_DelayTaskUs(CONFIG_DVFS_DELAY_US);
1623
1624 hMstarDvfsInfo.dwCode25CValuePm = *(volatile unsigned short *)(_gMIO_MapBase + (0x00148a << 1)); //CH6
1625 *(volatile unsigned short *)(_gMIO_MapBase + (0x001426 << 1)) |= (0x01 << 6); //Set PM SAR full scale = 3.3V
1626 *(volatile unsigned short *)(_gMIO_MapBase + (0x001400 << 1)) = 0x0a25;
1627 #endif
1628
1629 //=========================================================
1630 //Read 25 degree in CPU side
1631 *(volatile unsigned char *)(_gMIO_MapBase + (0x000e50 << 1)) = 0x07;
1632
1633 dwRegisterValue = *(volatile unsigned short *)(_gMIO_MapBase + (0x000ec4 << 1));
1634 dwRegisterValue &= ~(0x01 << 13);
1635 *(volatile unsigned short *)(_gMIO_MapBase + (0x000ec4 << 1)) = dwRegisterValue;
1636
1637 *(volatile unsigned short *)(_gMIO_MapBase + (0x001400 << 1)) = 0x0ab5;
1638 *(volatile unsigned short *)(_gMIO_MapBase + (0x001426 << 1)) &= ~(0x01 << 6); //Set PM SAR full scale = 2.0V
1639 MsOS_DelayTaskUs(CONFIG_DVFS_DELAY_US);
1640
1641 hMstarDvfsInfo.dwCode25CValueCpu = *(volatile unsigned short *)(_gMIO_MapBase + (0x00148a << 1)); //CH6
1642 *(volatile unsigned short *)(_gMIO_MapBase + (0x001426 << 1)) |= (0x01 << 6); //Set PM SAR full scale = 3.3V
1643 *(volatile unsigned short *)(_gMIO_MapBase + (0x001400 << 1)) = 0x0a25;
1644
1645 MsOS_ReleaseMutex(_s32SAR_Dvfs_Mutex);
1646 }
1647 else
1648 {
1649 //Disable DVFS
1650 *(volatile unsigned short *)(_gMIO_MapBase + (0x110cb0 << 1)) = 0;
1651 }
1652
1653 }
1654 #endif
1655
1656 #undef HAL_SAR_C
1657
1658