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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regWDT.h 98 /// @brief Piu Watch Dog Timer Registers Definition 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_RTC_H_ 103 #define _REG_RTC_H_ 104 105 //////////////////////////////////////////////////////////////////////////////// 106 // Macro and Define 107 //////////////////////////////////////////////////////////////////////////////// 108 109 #define REG_RTC_BASE_0 (0x1200UL) 110 #define REG_RTC_BASE_2 (0x1300UL) 111 112 #define REG_RTC_CTRL_REG (0x0000UL) 113 #define RTC_SOFT_RSTZ_BIT (0x0001UL)//BIT0 114 #define RTC_CNT_EN_BIT (0x0002UL)//BIT1 115 #define RTC_WRAP_EN_BIT (0x0004UL)//BIT2 116 #define RTC_LOAD_EN_BIT (0x0008UL)//BIT3 117 #define RTC_READ_EN_BIT (0x0010UL)//BIT4 118 #define RTC_INT_MASK_BIT (0x0020UL)//BIT5 119 #define RTC_INT_FORCE_BIT (0x0040UL)//BIT6 120 #define RTC_INT_CLEAR_BIT (0x0080UL)//BIT7 121 #define REG_RTC_FREQ_CW (0x0002UL) //BIT0-BIT31 122 #define REG_RTC_LOAD_VAL (0x0006UL) //BIT0-BIT31 123 #define REG_RTC_MATCH_VAL (0x000AUL) //BIT0-BIT31 124 #define REG_RTC_INT (0x000EUL) 125 #define RTC_RAW_INT_BIT (0x0001UL)//BIT0 126 #define RTC_INT_BIT (0x0002UL)//BIT1 127 #define REG_RTC_CNT (0x0010UL) //BIT0-BIT31 128 129 //////////////////////////////////////////////////////////////////////////////// 130 // Type and Structure 131 //////////////////////////////////////////////////////////////////////////////// 132 133 #endif // _REG_WDT_H_ 134 135