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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _HAL_PWM_H_ 96 #define _HAL_PWM_H_ 97 98 //////////////////////////////////////////////////////////////////////////////// 99 /// @file HALPWM.h 100 /// @author MStar Semiconductor Inc. 101 /// @brief Pulse Width Modulation hal 102 //////////////////////////////////////////////////////////////////////////////// 103 104 #define PWM_Num 5 /* Max. 6 */ 105 #define MAX_3DPWM_NUM (4) 106 //////////////////////////////////////////////////////////////////////////////// 107 // Macro for utility 108 //////////////////////////////////////////////////////////////////////////////// 109 #define MST_MACRO_START do { 110 #define MST_MACRO_END } while (0) 111 112 #define UNUSED( var ) ((void)(var)) 113 114 //////////////////////////////////////////////////////////////////////////////// 115 // Macro for bitwise 116 //////////////////////////////////////////////////////////////////////////////// 117 #define _BITMASK(loc_msb, loc_lsb) ((1U << (loc_msb)) - (1U << (loc_lsb)) + (1U << (loc_msb))) 118 #define BITMASK(x) _BITMASK(1?x, 0?x) 119 #define BITFLAG(loc) (1U << (loc)) 120 121 #define BIT0 0x0001 122 #define BIT1 0x0002 123 #define BIT2 0x0004 124 #define BIT3 0x0008 125 #define BIT4 0x0010 126 #define BIT5 0x0020 127 #define BIT6 0x0040 128 #define BIT7 0x0080 129 #define BIT8 0x0100 130 #define BIT9 0x0200 131 #define BIT10 0x0400 132 #define BIT11 0x0800 133 #define BIT12 0x1000 134 #define BIT13 0x2000 135 #define BIT14 0x4000 136 #define BIT15 0x8000 137 138 #define SETBIT(REG, BIT) ((REG) |= (1UL << (BIT))) 139 #define CLRBIT(REG, BIT) ((REG) &= ~(1UL << (BIT))) 140 #define GETBIT(REG, BIT) (((REG) >> (BIT)) & 0x01UL) 141 #define COMPLEMENT(a) (~(a)) 142 143 typedef struct _PWM_3D_RegisterInfo 144 { 145 MS_U32 u32RegOffset; 146 MS_U8 u8NumBit; 147 } PWM_3D_RegisterInfo; 148 149 typedef struct _PWM_3D_RegisterOffset 150 { 151 PWM_3D_RegisterInfo regShift; 152 PWM_3D_RegisterInfo regDuty; 153 } PWM_3D_RegisterOffset; 154 155 //////////////////////////////////////////////////////////////////////////////////////// 156 // Extern function 157 //////////////////////////////////////////////////////////////////////////////// 158 void HAL_PWM_SetIOMapBase(MS_VIRT virtBase, MS_VIRT virtBase1); 159 void HAL_PWM_SetChipTopIOMapBase(MS_VIRT virtBase); 160 MS_VIRT HAL_PWM_GetIOMapBase(void); 161 MS_BOOL HAL_PWM_Init(void); 162 MS_BOOL HAL_PWM_Oen(PWM_ChNum index, MS_BOOL letch); 163 MS_BOOL HAL_PWM_GetOen(PWM_ChNum index); 164 MS_BOOL HAL_PWM_UnitDiv(MS_U16 u16DivPWM); 165 void HAL_PWM_Period(PWM_ChNum index, MS_U32 u32PeriodPWM); 166 void HAL_PWM_DutyCycle(PWM_ChNum index, MS_U32 u32DutyPWM); 167 void HAL_PWM_Div(PWM_ChNum index, MS_U16 u16DivPWM); 168 MS_U16 HAL_PWM_GetDiv(PWM_ChNum index); 169 void HAL_PWM_Polarity(PWM_ChNum index, MS_BOOL bPolPWM); 170 MS_BOOL HAL_PWM_GetPolarity(PWM_ChNum index); 171 void HAL_PWM_VDBen(PWM_ChNum index, MS_BOOL bVdbenPWM); 172 MS_BOOL HAL_PWM_GetVDBen(PWM_ChNum index); 173 void HAL_PWM_Vrest(PWM_ChNum index, MS_BOOL bRstPWM); 174 MS_BOOL HAL_PWM_GetVrest(PWM_ChNum index); 175 void HAL_PWM_DBen(PWM_ChNum index, MS_BOOL bdbenPWM); 176 MS_BOOL HAL_PWM_GetDBen(PWM_ChNum index); 177 void HAL_PWM_RstMux(PWM_ChNum index, MS_BOOL bMuxPWM); 178 void HAL_PWM_RstCnt(PWM_ChNum index, MS_U8 u8RstCntPWM); 179 void HAL_PWM_BypassUnit(PWM_ChNum index, MS_BOOL bBypassPWM); 180 MS_BOOL HAL_PWM01_CntMode(PWM_CntMode CntMode); 181 MS_BOOL HAL_PWM23_CntMode(PWM_CntMode CntMode); 182 MS_BOOL HAL_PWM67_CntMode(PWM_CntMode CntMode); 183 MS_BOOL HAL_PWM_Shift(PWM_ChNum index, MS_U32 u32ShiftPWM); 184 MS_U32 HAL_PWM_GetShift(PWM_ChNum index); 185 void HAL_PWM_IMPULSE_EN(PWM_ChNum index, MS_BOOL bdbenPWM); 186 void HAL_PWM_ODDEVEN_SYNC(PWM_ChNum index, MS_BOOL bdbenPWM); 187 void HAL_PWM_Nvsync(PWM_ChNum index, MS_BOOL bNvsPWM); 188 void HAL_PWM_Align(PWM_ChNum index, MS_BOOL bAliPWM); 189 MS_BOOL HAL_PWM_IsSupport3D(PWM_ChNum index); 190 void HAL_PWM_SetMultiDiff(MS_BOOL bEnable); 191 MS_BOOL HAL_PWM_Set3D_DiffWaveform(PWM_ChNum index, MS_U8 u8WaveformIndex, MS_U32 u32Shift, MS_U32 u32Duty); 192 void HAL_PM_PWM_Enable(void); 193 void HAL_PM_PWM_Period(MS_U16 u16PeriodPWM); 194 void HAL_PM_PWM_DutyCycle(MS_U16 u16DutyPWM); 195 void HAL_PM_PWM_Div(MS_U8 u8DivPWM); 196 void HAL_PM_PWM_Polarity(MS_BOOL bPolPWM); 197 void HAL_PM_PWM_DBen(MS_BOOL bdbenPWM); 198 MS_U32 HAL_PWM_GetPeriod(PWM_ChNum index); 199 MS_U32 HAL_PWM_GetDutyCycle(PWM_ChNum index); 200 MS_BOOL HAL_PWM_INV_3D_Flag(MS_BOOL bInvPWM); 201 void HAL_PWM_LR_RST_SEL(PWM_ChNum index, N_LR_SYNC_SEL eLR_Sync); 202 #endif // _HAL_PWM_H_ 203 204