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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _REG_PWM_H_ 96 #define _REG_PWM_H_ 97 98 //////////////////////////////////////////////////////////////////////////////// 99 // Header Files 100 //////////////////////////////////////////////////////////////////////////////// 101 102 //////////////////////////////////////////////////////////////////////////////// 103 // Define & and data type 104 //////////////////////////////////////////////////////////////////////////////// 105 #define REG_ALL_PAD_IN (0x50) //bit 15;set all pads (except SPI) as input 106 #define REG_PWM_OEN (0x03) //bit 0~4 107 108 #define REG_PWM_MODE (0x64) 109 #define PAD_PWM0_OUT (BIT2) 110 #define PAD_PWM1_OUT (BIT6) 111 #define PAD_PWM2_OUT (BIT7) 112 #define PAD_PWM3_OUT (BIT12) 113 #define PAD_PWM4_OUT (BIT13) 114 115 #define REG_PM_BASE (0x1C00) 116 #define REG_TOP_BASE (0x3C00) 117 #define REG_PWM_BASE (0x7E800) 118 119 #define REG_PWM0_PERIOD (0x02) //bit0~15 120 #define REG_PWM1_PERIOD (0x05) //bit0~15 121 #define REG_PWM2_PERIOD (0x08) //bit0~15 122 #define REG_PWM3_PERIOD (0x0B) //bit0~15 123 #define REG_PWM4_PERIOD (0x0E) //bit0~15 124 //#define REG_PWM5_PERIOD (0x11) //bit0~15 125 //#define REG_PWM6_PERIOD (0x40) //bit0~15 126 //#define REG_PWM7_PERIOD (0x43) //bit0~15 127 //#define REG_PWM8_PERIOD (0x46) //bit0~15 128 129 #define REG_PWM0_DUTY (0x03) //bit0~15 130 #define REG_PWM1_DUTY (0x06) //bit0~15 131 #define REG_PWM2_DUTY (0x09) //bit0~15 132 #define REG_PWM3_DUTY (0x0C) //bit0~15 133 #define REG_PWM4_DUTY (0x0F) //bit0~15 134 //#define REG_PWM5_DUTY (0x12) //bit0~15 135 //#define REG_PWM6_DUTY (0x41) //bit0~15 136 //#define REG_PWM7_DUTY (0x44) //bit0~15 137 //#define REG_PWM8_DUTY (0x47) //bit0~15 138 139 #define REG_PWM0_DIV (0x04) //bit0~7 140 #define REG_PWM1_DIV (0x07) //bit0~7 141 #define REG_PWM2_DIV (0x0A) //bit0~7 142 #define REG_PWM3_DIV (0x0D) //bit0~7 143 #define REG_PWM4_DIV (0x10) //bit0~7 144 //#define REG_PWM5_DIV (0x13) //bit0~7 145 //#define REG_PWM6_DIV (0x42) //bit0~7 146 //#define REG_PWM7_DIV (0x45) //bit0~7 147 //#define REG_PWM8_DIV (0x48) //bit0~7 148 149 #define REG_PWM0_PORARITY (0x04) //bit8 150 #define REG_PWM1_PORARITY (0x07) //bit8 151 #define REG_PWM2_PORARITY (0x0A) //bit8 152 #define REG_PWM3_PORARITY (0x0D) //bit8 153 #define REG_PWM4_PORARITY (0x10) //bit8 154 //#define REG_PWM5_PORARITY (0x13) //bit8 155 //#define REG_PWM6_PORARITY (0x42) //bit8 156 //#define REG_PWM7_PORARITY (0x45) //bit8 157 //#define REG_PWM8_PORARITY (0x48) //bit8 158 159 #define REG_PWM0_VDBEN (0x04) //bit9 160 #define REG_PWM1_VDBEN (0x07) //bit9 161 #define REG_PWM2_VDBEN (0x0A) //bit9 162 #define REG_PWM3_VDBEN (0x0D) //bit9 163 #define REG_PWM4_VDBEN (0x10) //bit9 164 //#define REG_PWM5_VDBEN (0x13) //bit9 165 //#define REG_PWM6_VDBEN (0x42) //bit9 166 //#define REG_PWM7_VDBEN (0x45) //bit9 167 //#define REG_PWM8_VDBEN (0x48) //bit9 168 169 #define REG_PWM0_RESET_EN (0x04) //bit10 170 #define REG_PWM1_RESET_EN (0x07) //bit10 171 #define REG_PWM2_RESET_EN (0x0A) //bit10 172 #define REG_PWM3_RESET_EN (0x0D) //bit10 173 #define REG_PWM4_RESET_EN (0x10) //bit10 174 //#define REG_PWM5_RESET_EN (0x13) //bit10 175 //#define REG_PWM6_RESET_EN (0x42) //bit10 176 //#define REG_PWM7_RESET_EN (0x45) //bit10 177 //#define REG_PWM8_RESET_EN (0x48) //bit10 178 179 #define REG_PWM0_DBEN (0x04) //bit11 180 #define REG_PWM1_DBEN (0x07) //bit11 181 #define REG_PWM2_DBEN (0x0A) //bit11 182 #define REG_PWM3_DBEN (0x0D) //bit11 183 #define REG_PWM4_DBEN (0x10) //bit11 184 //#define REG_PWM5_DBEN (0x13) //bit11 185 //#define REG_PWM6_DBEN (0x42) //bit11 186 //#define REG_PWM7_DBEN (0x45) //bit11 187 //#define REG_PWM8_DBEN (0x48) //bit11 188 189 #define REG_PWM0_IMPULSE_EN (0x04) //bit12 190 #define REG_PWM1_IMPULSE_EN (0x07) //bit12 191 #define REG_PWM2_IMPULSE_EN (0x0A) //bit12 192 #define REG_PWM3_IMPULSE_EN (0x0D) //bit12 193 #define REG_PWM4_IMPULSE_EN (0x10) //bit12 194 #define REG_PWM5_IMPULSE_EN (0x13) //bit12 195 #define REG_PWM6_IMPULSE_EN (0x42) //bit12 196 #define REG_PWM7_IMPULSE_EN (0x45) //bit12 197 #define REG_PWM8_IMPULSE_EN (0x48) //bit12 198 199 #define REG_PWM0_ODDEVEN_SYNC (0x04) //bit13 200 #define REG_PWM1_ODDEVEN_SYNC (0x07) //bit13 201 #define REG_PWM2_ODDEVEN_SYNC (0x0A) //bit13 202 #define REG_PWM3_ODDEVEN_SYNC (0x0D) //bit13 203 #define REG_PWM4_ODDEVEN_SYNC (0x10) //bit13 204 #define REG_PWM5_ODDEVEN_SYNC (0x13) //bit13 205 #define REG_PWM6_ODDEVEN_SYNC (0x42) //bit13 206 #define REG_PWM7_ODDEVEN_SYNC (0x45) //bit13 207 #define REG_PWM8_ODDEVEN_SYNC (0x48) //bit13 208 209 // Add from T8 210 #define REG_PWM0_VDBEN_SW (0x04) //bit14 211 #define REG_PWM1_VDBEN_SW (0x07) //bit14 212 #define REG_PWM2_VDBEN_SW (0x0A) //bit14 213 #define REG_PWM3_VDBEN_SW (0x0D) //bit14 214 #define REG_PWM4_VDBEN_SW (0x10) //bit14 215 216 /* If chiptop provides the related reg, please use them at chiptop reg. */ 217 //#define REG_PWM0_OEN (0x04) //bit15 218 //#define REG_PWM1_OEN (0x07) //bit15 219 //#define REG_PWM2_OEN (0x0a) //bit15 220 //#define REG_PWM3_OEN (0x0d) //bit15 221 //#define REG_PWM4_OEN (0x10) //bit15 222 //#define REG_PWM5_OEN (0x13) //bit15 223 //#define REG_PWM6_OEN (0x42) //bit15 224 //#define REG_PWM7_OEN (0x45) //bit15 225 //#define REG_PWM8_OEN (0x48) //bit15 226 227 #define REG_RST_MUX0 (0x14) //bit15 228 #define REG_RST_MUX1 (0x14) //bit7 229 #define REG_RST_MUX2 (0x15) //bit15 230 #define REG_RST_MUX3 (0x15) //bit7 231 #define REG_RST_MUX4 (0x16) //bit15 232 //#define REG_RST_MUX5 (0x16) //bit7 233 //#define REG_RST_MUX6 (0x49) //bit15 234 //#define REG_RST_MUX7 (0x49) //bit7 235 //#define REG_RST_MUX8 (0x4A) //bit15 236 237 #define REG_HS_RST_CNT0 (0x14) //bit8~11 238 #define REG_HS_RST_CNT1 (0x14) //bit0~3 239 #define REG_HS_RST_CNT2 (0x15) //bit8~11 240 #define REG_HS_RST_CNT3 (0x15) //bit0~3 241 #define REG_HS_RST_CNT4 (0x16) //bit8~11 242 //#define REG_HS_RST_CNT5 (0x16) //bit0~3 243 //#define REG_HS_RST_CNT6 (0x49) //bit8~11 244 //#define REG_HS_RST_CNT7 (0x49) //bit0~3 245 //#define REG_HS_RST_CNT8 (0x4A) //bit8~11 246 247 #define REG_PWM0_PERIOD_EXT (0x20) //bit0~1 248 #define REG_PWM1_PERIOD_EXT (0x20) //bit2~3 249 #define REG_PWM2_PERIOD_EXT (0x20) //bit4~5 250 #define REG_PWM3_PERIOD_EXT (0x20) //bit6~7 251 #define REG_PWM4_PERIOD_EXT (0x20) //bit8~9 252 //#define REG_PWM5_PERIOD_EXT (0x20) //bit10~11 253 //#define REG_PWM6_PERIOD_EXT (0x4B) //bit0~1 254 //#define REG_PWM7_PERIOD_EXT (0x4B) //bit2~3 255 //#define REG_PWM8_PERIOD_EXT (0x4B) //bit4~5 256 257 #define REG_PWM0_DUTY_EXT (0x21) //bit0~1 258 #define REG_PWM1_DUTY_EXT (0x21) //bit2~3 259 #define REG_PWM2_DUTY_EXT (0x21) //bit4~5 260 #define REG_PWM3_DUTY_EXT (0x21) //bit6~7 261 #define REG_PWM4_DUTY_EXT (0x21) //bit8~9 262 //#define REG_PWM5_DUTY_EXT (0x21) //bit10~11 263 //#define REG_PWM6_DUTY_EXT (0x4B) //bit8~9 264 //#define REG_PWM7_DUTY_EXT (0x4B) //bit10~11 265 //#define REG_PWM8_DUTY_EXT (0x4B) //bit12~13 266 267 #define REG_PWM0_DIV_EXT (0x22) //bit0~7 268 #define REG_PWM1_DIV_EXT (0x22) //bit8~15 269 #define REG_PWM2_DIV_EXT (0x23) //bit0~7 270 #define REG_PWM3_DIV_EXT (0x23) //bit8~15 271 #define REG_PWM4_DIV_EXT (0x24) //bit0~7 272 //#define REG_PWM5_DIV_EXT (0x24) //bit8~15 273 //#define REG_PWM6_DIV_EXT (0x4C) //bit0~7 274 //#define REG_PWM7_DIV_EXT (0x4C) //bit8~15 275 //#define REG_PWM8_DIV_EXT (0x4D) //bit0~7 276 277 #define REG_PWM0_MOD_DBG_SEL_0 (0x26) //bit0~1 278 #define REG_PWM1_MOD_DBG_SEL_1 (0x26) //bit2~3 279 #define REG_PWM2_MOD_DBG_SEL_2 (0x26) //bit4~5 280 #define REG_PWM3_MOD_DBG_SEL_3 (0x26) //bit6~7 281 #define REG_PWM4_MOD_DBG_SEL_4 (0x26) //bit8~9 282 #define REG_PWM5_MOD_DBG_SEL_5 (0x26) //bit10~11 283 #define REG_PWM_MOD_EN (0x26) //bit12 284 285 286 #define REG_PWM0_SHIFT_L (0x28) //bit0~15 287 #define REG_PWM0_SHIFT_H (0x29) //bit0~1 288 #define REG_PWM1_SHIFT_L (0x2A) //bit0~15 289 #define REG_PWM1_SHIFT_H (0x2B) //bit0~1 290 #define REG_PWM2_SHIFT_L (0x2C) //bit0~15 291 #define REG_PWM2_SHIFT_H (0x2D) //bit0~1 292 #define REG_PWM3_SHIFT_L (0x2E) //bit0~15 293 #define REG_PWM3_SHIFT_H (0x2F) //bit0~1 294 #define REG_PWM4_SHIFT_L (0x30) //bit0~15 295 #define REG_PWM4_SHIFT_H (0x31) //bit0~1 296 //#define REG_PWM5_SHIFT_L (0x32) //bit0~15 297 //#define REG_PWM5_SHIFT_H (0x33) //bit0~1 298 //#define REG_PWM6_SHIFT_L (0x4E) //bit0~15 299 //#define REG_PWM6_SHIFT_H (0x4F) //bit0~1 300 //#define REG_PWM7_SHIFT_L (0x50) //bit0~15 301 //#define REG_PWM7_SHIFT_H (0x51) //bit0~1 302 //#define REG_PWM8_SHIFT_L (0x52) //bit0~15 303 //#define REG_PWM8_SHIFT_H (0x53) //bit0~1 304 305 #define REG_PWM0_NVS (0x34) //bit0 306 #define REG_PWM1_NVS (0x34) //bit1 307 #define REG_PWM2_NVS (0x34) //bit2 308 #define REG_PWM3_NVS (0x34) //bit3 309 #define REG_PWM4_NVS (0x34) //bit4 310 311 #define REG_PWM0_Align (0x35) //bit0 312 #define REG_PWM1_Align (0x35) //bit1 313 #define REG_PWM2_Align (0x35) //bit2 314 #define REG_PWM3_Align (0x35) //bit3 315 #define REG_PWM4_Align (0x35) //bit4 316 317 318 #define reg_pwm_as_chip_config (0x70) //bit0 319 #define REG_PM_PWM0_IS_GPIO (0x1C) //bit5 320 #define REG_PM_PWM0_PERIOD (0x6A) //bit0~15 321 #define REG_PM_PWM0_DUTY (0x69) //bit0~15 322 #define REG_PM_PWM0_DIV (0x68) //bit0~7 323 #define REG_PM_PWM0_PORARITY (0x6B) //bit0 324 #define REG_PM_PWM0_DBEN (0x6B) //bit1 325 326 327 //For Debug Use 328 #define REG_PWM_DUMMY2 (0x36) //bit0~15 Default:0x0000 329 #define REG_PWM_DUMMY3 (0x37) //bit0~15 Default:0xFFFF 330 #define REG_INV_3D_FLAG (0x78) //bit15, inverse 3D flag 331 332 333 //For PWM 3D Mode 334 #define REG_PWM_MULTI_DIFF (0x38) //bit0~15 335 #define PWM_MULTI_DIEF_EN BIT(3) 336 #define REG_PWM0_HIT_CNT_ST (0x54) //bit0~15 //3D PMW_01 shift 337 #define REG_PWM0_HIT_CNT_END (0x55) //bit0~15 //3D PWM_01 duty 338 #define REG_PWM1_HIT_CNT_ST (0x56) //bit0~15 //3D PWM_11 shift 339 #define REG_PWM1_HIT_CNT_END (0x57) //bit0~15 //3D PWM_11 duty 340 #define REG_PWM0_HIT_CNT_ST2 (0x68) //bit0~15 //3D PMW_02 shift 341 #define REG_PWM0_HIT_CNT_END2 (0x69) //bit0~15 //3D PWM_02 duty 342 #define REG_PWM1_HIT_CNT_ST2 (0x6a) //bit0~15 //3D PWM_12 shift 343 #define REG_PWM1_HIT_CNT_END2 (0x6b) //bit0~15 //3D PWM_12 duty 344 #define REG_PWM0_SHIFT4 (0x50) //bit0~15 //3D PMW_03 shift 345 #define REG_PWM0_DUTY4 (0x51) //bit0~15 //3D PWM_03 duty 346 #define REG_PWM1_SHIFT4 (0x52) //bit0~15 //3D PMW_13 shift 347 #define REG_PWM1_DUTY4 (0x53) //bit0~15 //3D PWM_13 duty 348 349 #define REG_DIM0_3_RST_P_SEL_0 (0x71) //bit8~9 350 #define REG_DIM4_7_RST_P_SEL_1 (0x71) //bit10~11 351 #define REG_DIM8_11_RST_P_SEL_2 (0x71) //bit12~13 352 353 #endif // _REG_PWM_H_ 354 355