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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _DRVPQ_DEFINE_H_ 96 #define _DRVPQ_DEFINE_H_ 97 #include "drvPQ_Define_cus.h" 98 99 #define PQ_ENABLE_DEBUG 0 100 #define PQ_ENABLE_CHECK 0 101 102 #define ENABLE_PQ_MLOAD 1 103 #define ENABLE_PQ_EX 1 104 105 #define PQ_ENABLE_VD_SAMPLING 1 106 #define PQ_ENABLE_PIP 1 107 #define PQ_ENABLE_3D_VIDEO 1 108 #define PQ_ENABLE_IOCTL 1 109 110 #define PQ_SKIPRULE_ENABLE 1 111 #define PQ_SKIPCOMMTB_ENABLE FALSE 112 113 #define PQ_XRULE_DB_ENABLE 0 114 #define ESTIMATE_AVAILABLE_RATE 85 115 #define PQ_BW_H264_ENABLE 0 116 #define PQ_BW_MM_ENABLE 0 117 #define PQ_BW_RMVB_ENABLE 0 118 #define PQ_BW_G3D_ENABLE 0 119 #define PQ_BW_PIP_ENABLE 0 //PIP case, bw needs strong setting 120 #define PQ_BW_MVC4kx1k_ENABLE 0 121 #define PQ_BW_HDMI4kx2k_ENABLE 1 122 #define PQ_BW_DUALDECODE_ENABLE 0 123 #define PQ_BW_4K2KPIP_SUPPORT 0 124 125 #define PQ_MADI_88X_MODE 1 126 #define PQ_UC_CTL 1 127 #define PQ_MADI_DFK 1 128 #define PQ_VIP_CTL 1 129 #define PQ_VIP_OFF_MINUS16 1 130 #define PQ_VIP_RGBCMY_CTL 0 131 #define PQ_QM_MWE_CLONE_VER2 1 132 #define PQ_QM_3D_CLONE_ENABLE 1 133 134 #define PQ_ENABLE_MULTI_LEVEL_AUTO_NR 1 135 136 #define PQ_EN_DMS_SW_CTRL TRUE 137 #define PQ_ENABLE_RFBL TRUE//FALSE 138 #define PQ_EN_UCNR_OFF TRUE 139 #define PQ_ENABLE_FORCE_MADI ENABLE 140 #define PQ_NEW_HSD_SAMPLING_TYPE TRUE 141 #define PQ_EN_UCNR_3D_MADI TRUE 142 143 #define PQ_4K2K_P2P_H_OFFSET_LIMITIOM 0 144 #define PQ_FRCM_CBCR_SWAP_BY_SW 1 145 #define PQ_SUPPORT_HDMI_4K2K_P2P 1 146 #define PQ_SUPPORT_DVI_4K2K 1 147 #define PQ_DISABLE_BYPASS_MODE2_BY_SW 148 #define PQ_4K2K_PHOTO 1 149 150 #define U8 MS_U8 151 #define code 152 153 extern MS_S32 _PQ_Mutex ; 154 155 #if defined (MSOS_TYPE_LINUX) 156 extern pthread_mutex_t _PQ_MLoad_Mutex; 157 #endif 158 159 #if PQ_ENABLE_DEBUG 160 extern MS_BOOL _u16DbgSwitch; 161 #define PQ_DBG(x) \ 162 do{ \ 163 if (_u16DbgSwitch){ \ 164 x; \ 165 } \ 166 }while(0) 167 168 #define PQ_DUMP_DBG(x) x 169 #define PQ_DUMP_FILTER_DBG(x) x 170 #else 171 #define PQ_DBG(x) //x 172 #define PQ_DUMP_DBG(x) //x 173 #define PQ_DUMP_FILTER_DBG(x) //x 174 #endif 175 176 #define PQ_MAP_REG(reg) (((reg)>>8)&0xFF), ((reg)&0xFF) 177 #define REG_ADDR_SIZE 2 178 #define REG_MASK_SIZE 1 179 180 #define PQ_IP_NULL 0xFF 181 182 #define PQTBL_EX 0x10 183 #define PQTBL_NORMAL 0x11 184 185 #define E_XRULE_HSD 0 186 #define E_XRULE_VSD 1 187 #define E_XRULE_HSP 2 188 #define E_XRULE_VSP 3 189 #define E_XRULE_CSC 4 190 191 #if PQ_XRULE_DB_ENABLE 192 #define E_XRULE_DB_NTSC 5 193 #define E_XRULE_DB_PAL 6 194 #define E_XRULE_NUM 7 195 #else 196 #define E_XRULE_NUM 5 197 #endif 198 199 200 #define _END_OF_TBL_ 0xFFFF 201 #define _END_OF_BW_TBL_ 0xFFFFFF 202 203 typedef enum { 204 PQ_TABTYPE_GENERAL, 205 PQ_TABTYPE_COMB, 206 PQ_TABTYPE_SCALER, 207 PQ_TABTYPE_SRAM1, 208 PQ_TABTYPE_SRAM2, 209 PQ_TABTYPE_SRAM3, 210 PQ_TABTYPE_SRAM4, 211 PQ_TABTYPE_C_SRAM1, 212 PQ_TABTYPE_C_SRAM2, 213 PQ_TABTYPE_C_SRAM3, 214 PQ_TABTYPE_C_SRAM4, 215 PQ_TABTYPE_SRAM_COLOR_INDEX, 216 PQ_TABTYPE_SRAM_COLOR_GAIN_SNR, 217 PQ_TABTYPE_SRAM_COLOR_GAIN_DNR, 218 PQ_TABTYPE_VIP_IHC_CRD_SRAM, 219 PQ_TABTYPE_VIP_ICC_CRD_SRAM, 220 PQ_TABTYPE_XVYCC_DE_GAMMA_SRAM, 221 PQ_TABTYPE_XVYCC_GAMMA_SRAM, 222 PQ_TABTYPE_SWDRIVER, 223 224 PQ_TABTYPE_UFSC_GENERAL = 50, 225 PQ_TABTYPE_UFSC_COMB = 51, 226 PQ_TABTYPE_UFSC_SCALER = 52, 227 PQ_TABTYPE_UFSC_SRAM1 = 53, 228 PQ_TABTYPE_UFSC_SRAM2 = 54, 229 PQ_TABTYPE_UFSC_SRAM3 = 55, 230 PQ_TABTYPE_UFSC_SRAM4 = 56, 231 PQ_TABTYPE_UFSC_C_SRAM1 = 57, 232 PQ_TABTYPE_UFSC_C_SRAM2 = 58, 233 PQ_TABTYPE_UFSC_C_SRAM3 = 59, 234 PQ_TABTYPE_UFSC_C_SRAM4 = 60, 235 PQ_TABTYPE_UFSC_SRAM_COLOR_INDEX = 61, 236 PQ_TABTYPE_UFSC_SRAM_COLOR_GAIN_SNR = 62, 237 PQ_TABTYPE_UFSC_SRAM_COLOR_GAIN_DNR = 63, 238 PQ_TABTYPE_UFSC_VIP_IHC_CRD_SRAM = 64, 239 PQ_TABTYPE_UFSC_VIP_ICC_CRD_SRAM = 65, 240 PQ_TABTYPE_UFSC_XVYCC_DE_GAMMA_SRAM = 66, 241 PQ_TABTYPE_UFSC_XVYCC_GAMMA_SRAM = 67, 242 PQ_TABTYPE_UFSC_SWDRIVER = 68, 243 PQ_TABTYPE_UFSC_100SERIES = 69, 244 } EN_PQ_TABTYPE; 245 246 247 typedef enum 248 { 249 PQ_MD_720x480_60I, // 00 250 PQ_MD_720x480_60P, // 01 251 PQ_MD_720x576_50I, // 02 252 PQ_MD_720x576_50P, // 03 253 PQ_MD_1280x720_50P, // 04 254 PQ_MD_1280x720_60P, // 05 255 PQ_MD_1920x1080_50I, // 06 256 PQ_MD_1920x1080_60I, // 07 257 PQ_MD_1920x1080_24P, // 08 258 PQ_MD_1920x1080_25P, // 09 259 PQ_MD_1920x1080_30P, // 10 260 PQ_MD_1920x1080_50P, // 11 261 PQ_MD_1920x1080_60P, // 12 262 PQ_MD_Num, 263 }PQ_MODE_INDEX; 264 265 266 typedef struct 267 { 268 MS_U8 *pIPCommTable; 269 MS_U8 *pIPTable; 270 MS_U8 u8TabNums; 271 MS_U8 u8TabType; 272 } EN_IPTAB_INFO; 273 274 typedef struct 275 { 276 MS_U8 *pIPTable; 277 MS_U8 u8TabNums; 278 MS_U8 u8TabType; 279 MS_U8 u8TabIdx; 280 } EN_IP_Info; 281 282 enum 283 { 284 PQ_FUNC_DUMP_REG, 285 PQ_FUNC_CHK_REG, 286 }; 287 288 #define PQ_MUX_DEBUG 0 289 290 #define BK_UFSC_SCALER_BASE 0x140000 291 292 #define SCALER_REGISTER_SPREAD 1 293 294 #if(SCALER_REGISTER_SPREAD) 295 #define BK_SCALER_BASE 0x130000 296 297 // no need to store bank for spread reg 298 #define SC_BK_STORE_NOMUTEX 299 300 #define SC_BK_RESTORE_NOMUTEX 301 302 #if(PQ_MUX_DEBUG) 303 // no need to store bank for spread reg 304 #define SC_BK_STORE_MUTEX \ 305 if(!MsOS_ObtainMutex(_PQ_Mutex, MSOS_WAIT_FOREVER)) \ 306 { \ 307 printf("==========================\n"); \ 308 printf("[%s][%s][%06d] Mutex taking timeout\n",__FILE__,__FUNCTION__,__LINE__); \ 309 } 310 311 // restore bank 312 #define SC_BK_RESTORE_MUTEX \ 313 MsOS_ReleaseMutex(_PQ_Mutex); 314 #else 315 #define SC_BK_STORE_MUTEX \ 316 if(!MsOS_ObtainMutex(_PQ_Mutex, MSOS_WAIT_FOREVER)) \ 317 { \ 318 } 319 320 // restore bank 321 #define SC_BK_RESTORE_MUTEX \ 322 MsOS_ReleaseMutex(_PQ_Mutex); 323 #endif 324 325 // switch bank 326 #define SC_BK_SWITCH(_x_) 327 328 #define SC_BK_CURRENT (u8CurBank) 329 #else 330 #define BK_SCALER_BASE 0x102F00 331 332 #define SC_BK_STORE_NOMUTEX \ 333 MS_U8 u8Bank; \ 334 u8Bank = MApi_XC_ReadByte(BK_SCALER_BASE) 335 336 // restore bank 337 #define SC_BK_RESTORE_NOMUTEX MApi_XC_WriteByte(BK_SCALER_BASE, u8Bank); 338 339 #define SC_MUTEX_ENTRY \ 340 if(!MsOS_ObtainMutex(_PQ_Mutex, MSOS_WAIT_FOREVER)) \ 341 { \ 342 } \ 343 344 #define SC_MUTEX_RETURN \ 345 MsOS_ReleaseMutex(_PQ_Mutex); 346 347 #if(PQ_MUX_DEBUG) 348 // store bank 349 #define SC_BK_STORE_MUTEX \ 350 MS_U8 u8Bank; \ 351 if(!MsOS_ObtainMutex(_PQ_Mutex, MSOS_WAIT_FOREVER)) \ 352 { \ 353 printf("==========================\n"); \ 354 printf("[%s][%s][%06d] Mutex taking timeout\n",__FILE__,__FUNCTION__,__LINE__); \ 355 } \ 356 u8Bank = MApi_XC_ReadByte(BK_SCALER_BASE) 357 358 // restore bank 359 #define SC_BK_RESTORE_MUTEX \ 360 MApi_XC_WriteByte(BK_SCALER_BASE, u8Bank); \ 361 MsOS_ReleaseMutex(_PQ_Mutex); 362 #else 363 #define SC_BK_STORE_MUTEX \ 364 MS_U8 u8Bank; \ 365 if(!MsOS_ObtainMutex(_PQ_Mutex, MSOS_WAIT_FOREVER)) \ 366 { \ 367 } \ 368 u8Bank = MApi_XC_ReadByte(BK_SCALER_BASE) 369 370 // restore bank 371 #define SC_BK_RESTORE_MUTEX \ 372 MApi_XC_WriteByte(BK_SCALER_BASE, u8Bank); \ 373 MsOS_ReleaseMutex(_PQ_Mutex); 374 #endif 375 376 // switch bank 377 #define SC_BK_SWITCH(_x_)\ 378 MApi_XC_WriteByte(BK_SCALER_BASE, _x_) 379 380 #define SC_BK_CURRENT \ 381 MApi_XC_ReadByte(BK_SCALER_BASE) 382 #endif 383 384 385 386 387 // store bank 388 #define COMB_BK_STORE \ 389 MS_U8 u8Bank; \ 390 u8Bank = MApi_XC_ReadByte(COMB_REG_BASE) 391 392 // restore bank 393 #define COMB_BK_RESTORE \ 394 MApi_XC_WriteByte(COMB_REG_BASE, u8Bank) 395 396 // switch bank 397 #define COMB_BK_SWITCH(_x_)\ 398 MApi_XC_WriteByte(COMB_REG_BASE, _x_) 399 400 #define COMB_BK_CURRENT \ 401 MApi_XC_ReadByte(COMB_REG_BASE) 402 403 #define PQ_IP_COMM 0xfe 404 #define PQ_IP_ALL 0xff 405 406 407 #endif /* _DRVPQ_DEFINE_H_ */ 408 409