1 //////////////////////////////////////////////////////////////////////////////// 2 // 3 // Copyright (c) 2008-2009 MStar Semiconductor, Inc. 4 // All rights reserved. 5 // 6 // Unless otherwise stipulated in writing, any and all information contained 7 // herein regardless in any format shall remain the sole proprietary of 8 // MStar Semiconductor Inc. and be kept in strict confidence 9 // (; MStar; Confidential; Information; ) by the recipient. 10 // Any unauthorized act including without limitation unauthorized disclosure, 11 // copying, use, reproduction, sale, distribution, modification, disassembling, 12 // reverse engineering and compiling of the contents of MStar Confidential 13 // Information is unlawful and strictly prohibited. MStar hereby reserves the 14 // rights to any and all damages, losses, costs and expenses resulting therefrom. 15 // 16 //**************************************************** 17 // Quality Map CodeGen Version 4.0 18 // 1920 19 // Kano 20 // 5/12/2016 15:51 21 // 7/1/2008 10:31 22 //**************************************************** 23 24 #ifndef _KANO_MAIN_EX_C_ 25 #define _KANO_MAIN_EX_C_ 26 27 #if PQ_SKIPRULE_ENABLE 28 29 code U8 MST_SkipRule_IP_Main_Ex[PQ_IP_NUM_Main_Ex]= 30 { 31 /* AFEC_no_comm */ 1, /* SPF_DBK */ 0, /* DMS */ 0, 32 }; 33 34 #endif 35 //**************************************************** 36 // AFEC_no_comm 37 //**************************************************** 38 code U8 MST_AFEC_no_comm_COM_Main_Ex[][4] = 39 { // Reg Mask Value 40 { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } 41 }; 42 43 code U8 MST_AFEC_no_comm_Main_Ex[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AFEC_no_comm_NUMS_Main_Ex]= 44 { 45 { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } 46 }; 47 48 //**************************************************** 49 // SPF_DBK 50 //**************************************************** 51 code U8 MST_SPF_DBK_COM_Main_Ex[][4] = 52 { // Reg Mask Value 53 { PQ_MAP_REG(REG_SC_BK0C_48_L), 0xFF, 0xEF }, 54 { PQ_MAP_REG(REG_SC_BK0C_48_H), 0xFF, 0xDC }, 55 { PQ_MAP_REG(REG_SC_BK0C_49_L), 0xFF, 0xBA }, 56 { PQ_MAP_REG(REG_SC_BK0C_49_H), 0xFF, 0x98 }, 57 { PQ_MAP_REG(REG_SC_BK0C_4A_L), 0xFF, 0x76 }, 58 { PQ_MAP_REG(REG_SC_BK0C_4A_H), 0xFF, 0x54 }, 59 { PQ_MAP_REG(REG_SC_BK0C_4B_L), 0xFF, 0x32 }, 60 { PQ_MAP_REG(REG_SC_BK0C_4B_H), 0xFF, 0x10 }, 61 { PQ_MAP_REG(REG_SC_BK0C_4C_L), 0xFF, 0xEF }, 62 { PQ_MAP_REG(REG_SC_BK0C_4C_H), 0xFF, 0xDC }, 63 { PQ_MAP_REG(REG_SC_BK0C_4D_L), 0xFF, 0xBA }, 64 { PQ_MAP_REG(REG_SC_BK0C_4D_H), 0xFF, 0x98 }, 65 { PQ_MAP_REG(REG_SC_BK0C_4E_L), 0xFF, 0x76 }, 66 { PQ_MAP_REG(REG_SC_BK0C_4E_H), 0xFF, 0x54 }, 67 { PQ_MAP_REG(REG_SC_BK0C_4F_L), 0xFF, 0x32 }, 68 { PQ_MAP_REG(REG_SC_BK0C_4F_H), 0xFF, 0x10 }, 69 { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } 70 }; 71 72 code U8 MST_SPF_DBK_Main_Ex[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SPF_DBK_NUMS_Main_Ex]= 73 { 74 { PQ_MAP_REG(REG_SC_BK0C_71_L), 0x01, 0x00/*OFF*/, 75 0x01/*LON*/, }, 76 { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } 77 }; 78 79 //**************************************************** 80 // DMS 81 //**************************************************** 82 code U8 MST_DMS_COM_Main_Ex[][4] = 83 { // Reg Mask Value 84 { PQ_MAP_REG(REG_SC_BK26_10_L), 0x02, 0x02 }, 85 { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } 86 }; 87 88 code U8 MST_DMS_Main_Ex[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_DMS_NUMS_Main_Ex]= 89 { 90 { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } 91 }; 92 93 94 code EN_IPTAB_INFO PQ_IPTAB_INFO_Main_Ex[]= 95 { 96 {*MST_AFEC_no_comm_COM_Main_Ex, *MST_AFEC_no_comm_Main_Ex, PQ_IP_AFEC_no_comm_NUMS_Main_Ex, PQ_TABTYPE_GENERAL}, 97 {*MST_SPF_DBK_COM_Main_Ex, *MST_SPF_DBK_Main_Ex, PQ_IP_SPF_DBK_NUMS_Main_Ex, PQ_TABTYPE_SCALER}, 98 {*MST_DMS_COM_Main_Ex, *MST_DMS_Main_Ex, PQ_IP_DMS_NUMS_Main_Ex, PQ_TABTYPE_SCALER}, 99 }; 100 101 #endif 102