1 #define PQ_GRULE_UFSC_MPEG_NR_ENABLE 1 2 #define PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE 1 3 #define PQ_GRULE_UFSC_SR_CONTROL_ENABLE 1 4 #define PQ_GRULE_UFSC_DS_PARAMETERS_ENABLE 1 5 #define PQ_GRULE_UFSC_HDR_ENABLE 1 6 #define PQ_GRULE_DEFINE_AUTO_GEN 1 7 #if (PQ_GRULE_UFSC_MPEG_NR_ENABLE) || (PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE) || (PQ_GRULE_UFSC_SR_CONTROL_ENABLE) || (PQ_GRULE_UFSC_DS_PARAMETERS_ENABLE) || (PQ_GRULE_UFSC_HDR_ENABLE) 8 typedef enum 9 { 10 #if PQ_GRULE_UFSC_MPEG_NR_ENABLE 11 PQ_GRule_MPEG_NR_UFSC, 12 #endif 13 14 #if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE 15 PQ_GRule_DYNAMIC_CONTRAST_UFSC, 16 #endif 17 18 #if PQ_GRULE_UFSC_SR_CONTROL_ENABLE 19 PQ_GRule_SR_CONTROL_UFSC, 20 #endif 21 22 #if PQ_GRULE_UFSC_DS_PARAMETERS_ENABLE 23 PQ_GRule_DS_PARAMETERS_UFSC, 24 #endif 25 26 #if PQ_GRULE_UFSC_HDR_ENABLE 27 PQ_GRule_HDR_UFSC, 28 #endif 29 30 } 31 MST_GRule_Index_UFSC; 32 #endif 33 34 #if PQ_GRULE_UFSC_MPEG_NR_ENABLE 35 typedef enum 36 { 37 PQ_GRule_MPEG_NR_Off_UFSC, 38 PQ_GRule_MPEG_NR_Low_UFSC, 39 PQ_GRule_MPEG_NR_Middle_UFSC, 40 PQ_GRule_MPEG_NR_High_UFSC, 41 } 42 MST_GRule_MPEG_NR_Index_UFSC; 43 #endif 44 45 #if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE 46 typedef enum 47 { 48 PQ_GRule_DYNAMIC_CONTRAST_Off_UFSC, 49 PQ_GRule_DYNAMIC_CONTRAST_On_UFSC, 50 } 51 MST_GRule_DYNAMIC_CONTRAST_Index_UFSC; 52 #endif 53 54 #if PQ_GRULE_UFSC_SR_CONTROL_ENABLE 55 typedef enum 56 { 57 PQ_GRule_SR_CONTROL_Off_UFSC, 58 PQ_GRule_SR_CONTROL_Low_UFSC, 59 PQ_GRule_SR_CONTROL_Middle_UFSC, 60 PQ_GRule_SR_CONTROL_On_High_UFSC, 61 } 62 MST_GRule_SR_CONTROL_Index_UFSC; 63 #endif 64 65 #if PQ_GRULE_UFSC_DS_PARAMETERS_ENABLE 66 typedef enum 67 { 68 PQ_GRule_DS_PARAMETERS_L_SD_UFSC, 69 PQ_GRule_DS_PARAMETERS_SD_UFSC, 70 PQ_GRule_DS_PARAMETERS_FHD_UFSC, 71 PQ_GRule_DS_PARAMETERS_4K_UFSC, 72 } 73 MST_GRule_DS_PARAMETERS_Index_UFSC; 74 #endif 75 76 #if PQ_GRULE_UFSC_HDR_ENABLE 77 typedef enum 78 { 79 PQ_GRule_HDR_On_UFSC, 80 PQ_GRule_HDR_Ref_UFSC, 81 PQ_GRule_HDR_HDR_OFF_1920_UFSC, 82 PQ_GRule_HDR_HDR_OFF_1366_UFSC, 83 PQ_GRule_HDR_HDR_OFF_4K_UFSC, 84 PQ_GRule_HDR_Dolby_ON_UFSC, 85 PQ_GRule_HDR_Dolby_User_UFSC, 86 } 87 MST_GRule_HDR_Index_UFSC; 88 #endif 89 90 #if PQ_GRULE_UFSC_MPEG_NR_ENABLE 91 typedef enum 92 { 93 PQ_GRule_Lvl_MPEG_NR_Off_UFSC, 94 PQ_GRule_Lvl_MPEG_NR_Low_UFSC, 95 PQ_GRule_Lvl_MPEG_NR_Middle_UFSC, 96 PQ_GRule_Lvl_MPEG_NR_High_UFSC, 97 } 98 MST_GRule_MPEG_NR_LvL_Index_UFSC; 99 #endif 100 101 #if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE 102 typedef enum 103 { 104 PQ_GRule_Lvl_DYNAMIC_CONTRAST_Off_UFSC, 105 PQ_GRule_Lvl_DYNAMIC_CONTRAST_On_UFSC, 106 } 107 MST_GRule_DYNAMIC_CONTRAST_LvL_Index_UFSC; 108 #endif 109 110 #if PQ_GRULE_UFSC_SR_CONTROL_ENABLE 111 typedef enum 112 { 113 PQ_GRule_Lvl_SR_CONTROL_Off_UFSC, 114 PQ_GRule_Lvl_SR_CONTROL_Low_UFSC, 115 PQ_GRule_Lvl_SR_CONTROL_Middle_UFSC, 116 PQ_GRule_Lvl_SR_CONTROL_High_UFSC, 117 } 118 MST_GRule_SR_CONTROL_LvL_Index_UFSC; 119 #endif 120 121 #if PQ_GRULE_UFSC_DS_PARAMETERS_ENABLE 122 typedef enum 123 { 124 PQ_GRule_Lvl_DS_PARAMETERS_L_SD_UFSC, 125 PQ_GRule_Lvl_DS_PARAMETERS_SD_UFSC, 126 PQ_GRule_Lvl_DS_PARAMETERS_FHD_UFSC, 127 PQ_GRule_Lvl_DS_PARAMETERS_4K_UFSC, 128 } 129 MST_GRule_DS_PARAMETERS_LvL_Index_UFSC; 130 #endif 131 132 #if PQ_GRULE_UFSC_HDR_ENABLE 133 typedef enum 134 { 135 PQ_GRule_Lvl_HDR_Off_UFSC, 136 PQ_GRule_Lvl_HDR_Open_Auto_UFSC, 137 PQ_GRule_Lvl_HDR_Open_High_UFSC, 138 PQ_GRule_Lvl_HDR_Open_Mid_UFSC, 139 PQ_GRule_Lvl_HDR_Open_Low_UFSC, 140 PQ_GRule_Lvl_HDR_Open_Ref_UFSC, 141 PQ_GRule_Lvl_HDR_Dolby_Vivid_UFSC, 142 PQ_GRule_Lvl_HDR_Dolby_User_UFSC, 143 PQ_GRule_Lvl_HDR_Dolby_Brightness_UFSC, 144 PQ_GRule_Lvl_HDR_Dolby_Dark_UFSC, 145 } 146 MST_GRule_HDR_LvL_Index_UFSC; 147 #endif 148 149 150 #define PQ_GRULE_RULE_NUM_UFSC 5 151 152 #if PQ_GRULE_UFSC_MPEG_NR_ENABLE 153 #define PQ_GRULE_MPEG_NR_IP_NUM_UFSC 3 154 #define PQ_GRULE_MPEG_NR_NUM_UFSC 4 155 #define PQ_GRULE_MPEG_NR_LVL_NUM_UFSC 4 156 #endif 157 158 #if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE 159 #define PQ_GRULE_DYNAMIC_CONTRAST_IP_NUM_UFSC 1 160 #define PQ_GRULE_DYNAMIC_CONTRAST_NUM_UFSC 2 161 #define PQ_GRULE_DYNAMIC_CONTRAST_LVL_NUM_UFSC 2 162 #endif 163 164 #if PQ_GRULE_UFSC_SR_CONTROL_ENABLE 165 #define PQ_GRULE_SR_CONTROL_IP_NUM_UFSC 6 166 #define PQ_GRULE_SR_CONTROL_NUM_UFSC 4 167 #define PQ_GRULE_SR_CONTROL_LVL_NUM_UFSC 4 168 #endif 169 170 #if PQ_GRULE_UFSC_DS_PARAMETERS_ENABLE 171 #define PQ_GRULE_DS_PARAMETERS_IP_NUM_UFSC 5 172 #define PQ_GRULE_DS_PARAMETERS_NUM_UFSC 4 173 #define PQ_GRULE_DS_PARAMETERS_LVL_NUM_UFSC 4 174 #endif 175 176 #if PQ_GRULE_UFSC_HDR_ENABLE 177 #define PQ_GRULE_HDR_IP_NUM_UFSC 5 178 #define PQ_GRULE_HDR_NUM_UFSC 7 179 #define PQ_GRULE_HDR_LVL_NUM_UFSC 10 180 #endif 181 182 #if PQ_GRULE_UFSC_MPEG_NR_ENABLE 183 extern code U8 MST_GRule_MPEG_NR_IP_Index_UFSC[PQ_GRULE_MPEG_NR_IP_NUM_UFSC]; 184 extern code U8 MST_GRule_MPEG_NR_UFSC[QM_INPUTTYPE_NUM_UFSC][PQ_GRULE_MPEG_NR_NUM_UFSC][PQ_GRULE_MPEG_NR_IP_NUM_UFSC]; 185 #endif 186 187 #if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE 188 extern code U8 MST_GRule_DYNAMIC_CONTRAST_IP_Index_UFSC[PQ_GRULE_DYNAMIC_CONTRAST_IP_NUM_UFSC]; 189 extern code U8 MST_GRule_DYNAMIC_CONTRAST_UFSC[QM_INPUTTYPE_NUM_UFSC][PQ_GRULE_DYNAMIC_CONTRAST_NUM_UFSC][PQ_GRULE_DYNAMIC_CONTRAST_IP_NUM_UFSC]; 190 #endif 191 192 #if PQ_GRULE_UFSC_SR_CONTROL_ENABLE 193 extern code U8 MST_GRule_SR_CONTROL_IP_Index_UFSC[PQ_GRULE_SR_CONTROL_IP_NUM_UFSC]; 194 extern code U8 MST_GRule_SR_CONTROL_UFSC[QM_INPUTTYPE_NUM_UFSC][PQ_GRULE_SR_CONTROL_NUM_UFSC][PQ_GRULE_SR_CONTROL_IP_NUM_UFSC]; 195 #endif 196 197 #if PQ_GRULE_UFSC_DS_PARAMETERS_ENABLE 198 extern code U8 MST_GRule_DS_PARAMETERS_IP_Index_UFSC[PQ_GRULE_DS_PARAMETERS_IP_NUM_UFSC]; 199 extern code U8 MST_GRule_DS_PARAMETERS_UFSC[QM_INPUTTYPE_NUM_UFSC][PQ_GRULE_DS_PARAMETERS_NUM_UFSC][PQ_GRULE_DS_PARAMETERS_IP_NUM_UFSC]; 200 #endif 201 202 #if PQ_GRULE_UFSC_HDR_ENABLE 203 extern code U8 MST_GRule_HDR_IP_Index_UFSC[PQ_GRULE_HDR_IP_NUM_UFSC]; 204 extern code U8 MST_GRule_HDR_UFSC[QM_INPUTTYPE_NUM_UFSC][PQ_GRULE_HDR_NUM_UFSC][PQ_GRULE_HDR_IP_NUM_UFSC]; 205 #endif 206 207 #if PQ_GRULE_UFSC_MPEG_NR_ENABLE 208 extern code U8 MST_GRule_1920_MPEG_NR_UFSC[PQ_GRULE_MPEG_NR_LVL_NUM_UFSC]; 209 #endif 210 #if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE 211 extern code U8 MST_GRule_1920_DYNAMIC_CONTRAST_UFSC[PQ_GRULE_DYNAMIC_CONTRAST_LVL_NUM_UFSC]; 212 #endif 213 #if PQ_GRULE_UFSC_SR_CONTROL_ENABLE 214 extern code U8 MST_GRule_1920_SR_CONTROL_UFSC[PQ_GRULE_SR_CONTROL_LVL_NUM_UFSC]; 215 #endif 216 #if PQ_GRULE_UFSC_DS_PARAMETERS_ENABLE 217 extern code U8 MST_GRule_1920_DS_PARAMETERS_UFSC[PQ_GRULE_DS_PARAMETERS_LVL_NUM_UFSC]; 218 #endif 219 #if PQ_GRULE_UFSC_HDR_ENABLE 220 extern code U8 MST_GRule_1920_HDR_UFSC[PQ_GRULE_HDR_LVL_NUM_UFSC]; 221 #endif 222 223 #if PQ_GRULE_UFSC_MPEG_NR_ENABLE 224 extern code U8 MST_GRule_1366_MPEG_NR_UFSC[PQ_GRULE_MPEG_NR_LVL_NUM_UFSC]; 225 #endif 226 #if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE 227 extern code U8 MST_GRule_1366_DYNAMIC_CONTRAST_UFSC[PQ_GRULE_DYNAMIC_CONTRAST_LVL_NUM_UFSC]; 228 #endif 229 #if PQ_GRULE_UFSC_SR_CONTROL_ENABLE 230 extern code U8 MST_GRule_1366_SR_CONTROL_UFSC[PQ_GRULE_SR_CONTROL_LVL_NUM_UFSC]; 231 #endif 232 #if PQ_GRULE_UFSC_DS_PARAMETERS_ENABLE 233 extern code U8 MST_GRule_1366_DS_PARAMETERS_UFSC[PQ_GRULE_DS_PARAMETERS_LVL_NUM_UFSC]; 234 #endif 235 #if PQ_GRULE_UFSC_HDR_ENABLE 236 extern code U8 MST_GRule_1366_HDR_UFSC[PQ_GRULE_HDR_LVL_NUM_UFSC]; 237 #endif 238 239 #if PQ_GRULE_UFSC_MPEG_NR_ENABLE 240 extern code U8 MST_GRule_4K_MPEG_NR_UFSC[PQ_GRULE_MPEG_NR_LVL_NUM_UFSC]; 241 #endif 242 #if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE 243 extern code U8 MST_GRule_4K_DYNAMIC_CONTRAST_UFSC[PQ_GRULE_DYNAMIC_CONTRAST_LVL_NUM_UFSC]; 244 #endif 245 #if PQ_GRULE_UFSC_SR_CONTROL_ENABLE 246 extern code U8 MST_GRule_4K_SR_CONTROL_UFSC[PQ_GRULE_SR_CONTROL_LVL_NUM_UFSC]; 247 #endif 248 #if PQ_GRULE_UFSC_DS_PARAMETERS_ENABLE 249 extern code U8 MST_GRule_4K_DS_PARAMETERS_UFSC[PQ_GRULE_DS_PARAMETERS_LVL_NUM_UFSC]; 250 #endif 251 #if PQ_GRULE_UFSC_HDR_ENABLE 252 extern code U8 MST_GRule_4K_HDR_UFSC[PQ_GRULE_HDR_LVL_NUM_UFSC]; 253 #endif 254 255