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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _DRVPQ_DEFINE_H_ 96 #define _DRVPQ_DEFINE_H_ 97 #include "drvPQ_Define_cus.h" 98 #if (defined (ANDROID)) 99 #include <pthread.h> 100 #endif 101 102 #define PQ_ENABLE_DEBUG 0 103 #define PQ_ENABLE_CHECK 0 104 105 #define ENABLE_PQ_MLOAD 1 106 #define ENABLE_PQ_EX 0 107 108 #define PQ_ENABLE_VD_SAMPLING 1 109 #define PQ_ENABLE_PIP 1 110 #define PQ_ENABLE_3D_VIDEO 1 111 #define PQ_ENABLE_IOCTL 1 112 113 #define PQ_SKIPRULE_ENABLE 1 114 #define PQ_SKIPCOMMTB_ENABLE FALSE 115 116 #define PQ_XRULE_DB_ENABLE 0 117 #define ESTIMATE_AVAILABLE_RATE 85 118 #define PQ_BW_H264_ENABLE 0 119 #define PQ_BW_MM_ENABLE 0 120 #define PQ_BW_RMVB_ENABLE 0 121 #define PQ_BW_G3D_ENABLE 0 122 #define PQ_BW_PIP_ENABLE 0 //PIP case, bw needs strong setting 123 #define PQ_BW_MVC4kx1k_ENABLE 0 124 #define PQ_BW_HDMI4kx2k_ENABLE 1 125 #define PQ_BW_DUALDECODE_ENABLE 0 126 #define PQ_BW_4K2KPIP_SUPPORT 1 127 128 #define PQ_MADI_88X_MODE 1 129 #define PQ_UC_CTL 1 130 #define PQ_MADI_DFK 1 131 #define PQ_VIP_CTL 1 132 #define PQ_VIP_OFF_MINUS16 0 133 #define PQ_VIP_RGBCMY_CTL 0 134 #define PQ_QM_MWE_CLONE_VER2 1 135 #define PQ_QM_3D_CLONE_ENABLE 1 136 137 #define PQ_ENABLE_MULTI_LEVEL_AUTO_NR 1 138 139 #define PQ_EN_DMS_SW_CTRL TRUE 140 #define PQ_ENABLE_RFBL TRUE//FALSE 141 #define PQ_EN_UCNR_OFF TRUE 142 #define PQ_ENABLE_FORCE_MADI ENABLE 143 #define PQ_NEW_HSD_SAMPLING_TYPE TRUE 144 #define PQ_EN_UCNR_3D_MADI TRUE 145 146 #define PQ_4K2K_P2P_H_OFFSET_LIMITIOM 0 147 #define PQ_FRCM_CBCR_SWAP_BY_SW 1 148 #define PQ_SUPPORT_HDMI_4K2K_P2P 1 149 #define PQ_SUPPORT_DVI_4K2K 1 150 #define PQ_DISABLE_BYPASS_MODE2_BY_SW 151 #define PQ_4K2K_PHOTO 1 152 #define PQ_SUPPORT_SUB_POSTCCS 0 153 #define PQ_SUPPORT_SUB_DHD 0 154 155 #define U8 MS_U8 156 #define code 157 158 extern MS_S32 _PQ_Mutex ; 159 160 #if defined (MSOS_TYPE_LINUX) 161 #if (defined (ANDROID)) 162 pthread_mutex_t _PQ_MLoad_Mutex; 163 #else 164 extern pthread_mutex_t _PQ_MLoad_Mutex; 165 #endif 166 #endif 167 168 #if PQ_ENABLE_DEBUG 169 extern MS_BOOL _u16DbgSwitch; 170 #define PQ_DBG(x) \ 171 do{ \ 172 if (_u16DbgSwitch){ \ 173 x; \ 174 } \ 175 }while(0) 176 177 #define PQ_DUMP_DBG(x) x 178 #define PQ_DUMP_FILTER_DBG(x) x 179 #else 180 #define PQ_DBG(x) //x 181 #define PQ_DUMP_DBG(x) //x 182 #define PQ_DUMP_FILTER_DBG(x) //x 183 #endif 184 185 #define PQ_MAP_REG(reg) (((reg)>>8)&0xFF), ((reg)&0xFF) 186 #define REG_ADDR_SIZE 2 187 #define REG_MASK_SIZE 1 188 189 #define PQ_IP_NULL 0xFF 190 191 #define PQTBL_EX 0x10 192 #define PQTBL_NORMAL 0x11 193 194 #define E_XRULE_HSD 0 195 #define E_XRULE_VSD 1 196 #define E_XRULE_HSP 2 197 #define E_XRULE_VSP 3 198 #define E_XRULE_CSC 4 199 200 #if PQ_XRULE_DB_ENABLE 201 #define E_XRULE_DB_NTSC 5 202 #define E_XRULE_DB_PAL 6 203 #define E_XRULE_NUM 7 204 #else 205 #define E_XRULE_NUM 5 206 #endif 207 208 209 #define _END_OF_TBL_ 0xFFFF 210 #define _END_OF_BW_TBL_ 0xFFFFFF 211 #define MaseratiLinearRGB 212 213 #define DS_PQ_MAX_NUM 200 214 typedef struct 215 { 216 MS_U16 u16Addr; 217 MS_U16 u16Value; 218 MS_U16 u16Mask; 219 MS_U16 u16Bank; 220 } stDS_PQ_REG; 221 222 typedef enum { 223 PQ_TABTYPE_GENERAL, 224 PQ_TABTYPE_COMB, 225 PQ_TABTYPE_SCALER, 226 PQ_TABTYPE_SRAM1, 227 PQ_TABTYPE_SRAM2, 228 PQ_TABTYPE_SRAM3, 229 PQ_TABTYPE_SRAM4, 230 PQ_TABTYPE_C_SRAM1, 231 PQ_TABTYPE_C_SRAM2, 232 PQ_TABTYPE_C_SRAM3, 233 PQ_TABTYPE_C_SRAM4, 234 PQ_TABTYPE_SRAM_COLOR_INDEX, 235 PQ_TABTYPE_SRAM_COLOR_GAIN_SNR, 236 PQ_TABTYPE_SRAM_COLOR_GAIN_DNR, 237 PQ_TABTYPE_VIP_IHC_CRD_SRAM, 238 PQ_TABTYPE_VIP_ICC_CRD_SRAM, 239 PQ_TABTYPE_XVYCC_DE_GAMMA_SRAM, 240 PQ_TABTYPE_XVYCC_GAMMA_SRAM, 241 PQ_TABTYPE_SWDRIVER, 242 PQ_TABTYPE_LinearRGB_DE_GAMMA_SRAM, 243 PQ_TABTYPE_LinearRGB_GAMMA_SRAM, 244 245 PQ_TABTYPE_UFSC_GENERAL = 50, 246 PQ_TABTYPE_UFSC_COMB = 51, 247 PQ_TABTYPE_UFSC_SCALER = 52, 248 PQ_TABTYPE_UFSC_SRAM1 = 53, 249 PQ_TABTYPE_UFSC_SRAM2 = 54, 250 PQ_TABTYPE_UFSC_SRAM3 = 55, 251 PQ_TABTYPE_UFSC_SRAM4 = 56, 252 PQ_TABTYPE_UFSC_C_SRAM1 = 57, 253 PQ_TABTYPE_UFSC_C_SRAM2 = 58, 254 PQ_TABTYPE_UFSC_C_SRAM3 = 59, 255 PQ_TABTYPE_UFSC_C_SRAM4 = 60, 256 PQ_TABTYPE_UFSC_SRAM_COLOR_INDEX = 61, 257 PQ_TABTYPE_UFSC_SRAM_COLOR_GAIN_SNR = 62, 258 PQ_TABTYPE_UFSC_SRAM_COLOR_GAIN_DNR = 63, 259 PQ_TABTYPE_UFSC_VIP_IHC_CRD_SRAM = 64, 260 PQ_TABTYPE_UFSC_VIP_ICC_CRD_SRAM = 65, 261 PQ_TABTYPE_UFSC_XVYCC_DE_GAMMA_SRAM = 66, 262 PQ_TABTYPE_UFSC_XVYCC_GAMMA_SRAM = 67, 263 PQ_TABTYPE_UFSC_SWDRIVER = 68, 264 PQ_TABTYPE_UFSC_100SERIES = 69, 265 } EN_PQ_TABTYPE; 266 267 268 typedef enum 269 { 270 PQ_MD_720x480_60I, // 00 271 PQ_MD_720x480_60P, // 01 272 PQ_MD_720x576_50I, // 02 273 PQ_MD_720x576_50P, // 03 274 PQ_MD_1280x720_50P, // 04 275 PQ_MD_1280x720_60P, // 05 276 PQ_MD_1920x1080_50I, // 06 277 PQ_MD_1920x1080_60I, // 07 278 PQ_MD_1920x1080_24P, // 08 279 PQ_MD_1920x1080_25P, // 09 280 PQ_MD_1920x1080_30P, // 10 281 PQ_MD_1920x1080_50P, // 11 282 PQ_MD_1920x1080_60P, // 12 283 PQ_MD_Num, 284 }PQ_MODE_INDEX; 285 286 287 typedef struct 288 { 289 MS_U8 *pIPCommTable; 290 MS_U8 *pIPTable; 291 MS_U8 u8TabNums; 292 MS_U8 u8TabType; 293 } EN_IPTAB_INFO; 294 295 typedef struct 296 { 297 MS_U8 *pIPTable; 298 MS_U8 u8TabNums; 299 MS_U8 u8TabType; 300 MS_U8 u8TabIdx; 301 } EN_IP_Info; 302 303 enum 304 { 305 PQ_FUNC_DUMP_REG, 306 PQ_FUNC_CHK_REG, 307 }; 308 309 #define PQ_MUX_DEBUG 0 310 311 #define BK_UFSC_SCALER_BASE 0x140000 312 313 #define SCALER_REGISTER_SPREAD 1 314 315 #if(SCALER_REGISTER_SPREAD) 316 #define BK_SCALER_BASE 0x130000 317 318 // no need to store bank for spread reg 319 #define SC_BK_STORE_NOMUTEX 320 321 #define SC_BK_RESTORE_NOMUTEX 322 323 #if(PQ_MUX_DEBUG) 324 // no need to store bank for spread reg 325 #define SC_BK_STORE_MUTEX \ 326 if(!MsOS_ObtainMutex(_PQ_Mutex, MSOS_WAIT_FOREVER)) \ 327 { \ 328 printf("==========================\n"); \ 329 printf("[%s][%s][%06d] Mutex taking timeout\n",__FILE__,__FUNCTION__,__LINE__); \ 330 } 331 332 // restore bank 333 #define SC_BK_RESTORE_MUTEX \ 334 MsOS_ReleaseMutex(_PQ_Mutex); 335 #else 336 #define SC_BK_STORE_MUTEX \ 337 if(!MsOS_ObtainMutex(_PQ_Mutex, MSOS_WAIT_FOREVER)) \ 338 { \ 339 } 340 341 // restore bank 342 #define SC_BK_RESTORE_MUTEX \ 343 MsOS_ReleaseMutex(_PQ_Mutex); 344 #endif 345 346 // switch bank 347 #define SC_BK_SWITCH(_x_) 348 349 #define SC_BK_CURRENT (u8CurBank) 350 #else 351 #define BK_SCALER_BASE 0x102F00 352 353 #define SC_BK_STORE_NOMUTEX \ 354 MS_U8 u8Bank; \ 355 u8Bank = MApi_XC_ReadByte(BK_SCALER_BASE) 356 357 // restore bank 358 #define SC_BK_RESTORE_NOMUTEX MApi_XC_WriteByte(BK_SCALER_BASE, u8Bank); 359 360 #define SC_MUTEX_ENTRY \ 361 if(!MsOS_ObtainMutex(_PQ_Mutex, MSOS_WAIT_FOREVER)) \ 362 { \ 363 } \ 364 365 #define SC_MUTEX_RETURN \ 366 MsOS_ReleaseMutex(_PQ_Mutex); 367 368 #if(PQ_MUX_DEBUG) 369 // store bank 370 #define SC_BK_STORE_MUTEX \ 371 MS_U8 u8Bank; \ 372 if(!MsOS_ObtainMutex(_PQ_Mutex, MSOS_WAIT_FOREVER)) \ 373 { \ 374 printf("==========================\n"); \ 375 printf("[%s][%s][%06d] Mutex taking timeout\n",__FILE__,__FUNCTION__,__LINE__); \ 376 } \ 377 u8Bank = MApi_XC_ReadByte(BK_SCALER_BASE) 378 379 // restore bank 380 #define SC_BK_RESTORE_MUTEX \ 381 MApi_XC_WriteByte(BK_SCALER_BASE, u8Bank); \ 382 MsOS_ReleaseMutex(_PQ_Mutex); 383 #else 384 #define SC_BK_STORE_MUTEX \ 385 MS_U8 u8Bank; \ 386 if(!MsOS_ObtainMutex(_PQ_Mutex, MSOS_WAIT_FOREVER)) \ 387 { \ 388 } \ 389 u8Bank = MApi_XC_ReadByte(BK_SCALER_BASE) 390 391 // restore bank 392 #define SC_BK_RESTORE_MUTEX \ 393 MApi_XC_WriteByte(BK_SCALER_BASE, u8Bank); \ 394 MsOS_ReleaseMutex(_PQ_Mutex); 395 #endif 396 397 // switch bank 398 #define SC_BK_SWITCH(_x_)\ 399 MApi_XC_WriteByte(BK_SCALER_BASE, _x_) 400 401 #define SC_BK_CURRENT \ 402 MApi_XC_ReadByte(BK_SCALER_BASE) 403 #endif 404 405 406 407 408 // store bank 409 #define COMB_BK_STORE \ 410 MS_U8 u8Bank; \ 411 u8Bank = MApi_XC_ReadByte(COMB_REG_BASE) 412 413 // restore bank 414 #define COMB_BK_RESTORE \ 415 MApi_XC_WriteByte(COMB_REG_BASE, u8Bank) 416 417 // switch bank 418 #define COMB_BK_SWITCH(_x_)\ 419 MApi_XC_WriteByte(COMB_REG_BASE, _x_) 420 421 #define COMB_BK_CURRENT \ 422 MApi_XC_ReadByte(COMB_REG_BASE) 423 424 #define PQ_IP_COMM 0xfe 425 #define PQ_IP_ALL 0xff 426 427 428 #endif /* _DRVPQ_DEFINE_H_ */ 429 430