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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 //////////////////////////////////////////////////////////////////////////////// 93 94 #ifndef _REGPM_H_ 95 #define _REGPM_H_ 96 97 //////////////////////////////////////////////////////////////////////////////// 98 // Header Files 99 //////////////////////////////////////////////////////////////////////////////// 100 101 //////////////////////////////////////////////////////////////////////////////// 102 // Define & data type 103 //////////////////////////////////////////////////////////////////////////////// 104 //v: value n: shift n bits 105 #define __BIT(x) ((MS_U8)(1 << (x))) 106 #define __BIT0 __BIT(0) 107 #define __BIT1 __BIT(1) 108 #define __BIT2 __BIT(2) 109 #define __BIT3 __BIT(3) 110 #define __BIT4 __BIT(4) 111 #define __BIT5 __BIT(5) 112 #define __BIT6 __BIT(6) 113 #define __BIT7 __BIT(7) 114 115 #define PM_REG_BASE 0x0e00 //(0x0700*2) 116 #define PM_MSIC_REG_BASE 0x2e00 //(0x1700*2) 117 #define PMSLEEP_REG_GPIO 0x0f00 //(0x0780*2) 118 #define PMRTC_REG_BASE 0x1200 //(0x0900*2) 119 #define PMRTC1_REG_BASE 0x1300 //(0x0980*2) 120 121 122 //----------------------------------------------------------------------------- 123 // PM register 124 //----------------------------------------------------------------------------- 125 // bank, regiter 126 #define REG_PM_GPIO_PM_LOCK ((PM_REG_BASE + 0x12UL * 2)) 127 #define REG_PM_CKG_RTC ((PM_REG_BASE + 0x22UL * 2)) 128 129 130 #define REG_PM_DUMMY_ACTIVE_STANDBY ((PM_REG_BASE + 0x38UL * 2)) 131 #define REG_PM_DUMMY_POWERON_MODE ((PM_REG_BASE + 0x38UL * 2 + 1)) 132 #define REG_PM_DUMMY_WAKEUP_SOURCE ((PM_REG_BASE + 0x39UL * 2)) 133 134 #define PM_REG1_ScratchPad ((PM_REG_BASE + 0x52UL*2)) 135 #define PM_REG2_ScratchPad ((PM_REG_BASE + 0x53UL*2)) 136 #define PM_REG3_ScratchPad ((PM_REG_BASE + 0x54UL*2)) 137 #define PM_REG4_ScratchPad ((PM_REG_BASE + 0x55UL*2)) 138 139 //----------------------------------------------------------------------------- 140 // PM MISC register 141 //----------------------------------------------------------------------------- 142 // bank, regiter 143 #define REG_PM_CHIP_CFG_OVERWRITE ((PM_MSIC_REG_BASE + 0x1FUL * 2)) 144 #define CHIP_CFG_MIPS_EN __BIT2 145 #define CHIP_CFG_MIPS_VAL __BIT6 146 #define REG_PM_CPU_SW_RST ((PM_MSIC_REG_BASE + 0x29UL * 2 + 1)) 147 #define PM_51_SW_RST __BIT4 148 149 //----------------------------------------------------------------------------- 150 // PM GPIO register 151 //----------------------------------------------------------------------------- 152 #define REG_PM_GPIO4_OEN ((PMSLEEP_REG_GPIO + 0x04UL * 2)) 153 #define REG_PM_GPIO4_OUT ((PMSLEEP_REG_GPIO + 0x04UL * 2)) 154 #define PMGPIO_OEN __BIT0 155 #define PMGPIO_OUT __BIT1 156 #define PMGPIO_IN __BIT2 157 158 //------------------------------------------------------------------------------ 159 // PM_SLEEP RTC register 160 //------------------------------------------------------------------------------ 161 // bank, regiter 162 #define REG_PMRTC_CTRL ((PMRTC_REG_BASE + 0x00UL * 2))//RTC_REG_BASE + 0x00 163 #define PMRTC_CTRL_NOT_RSTZ (1 << 0) 164 #define PMRTC_CTRL_CNT_EN (1 << 1) 165 #define PMRTC_CTRL_WRAP_EN (1 << 2) 166 #define PMRTC_CTRL_LOAD_EN (1 << 3) 167 #define PMRTC_CTRL_READ_EN (1 << 4) 168 #define PMRTC_CTRL_INT_MASK (1 << 5) 169 #define PMRTC_CTRL_INT_FORCE (1 << 6) 170 #define PMRTC_CTRL_INT_CLEAR (1 << 7) 171 172 173 #define REG_PMRTC_FREQ_CW ((PMRTC_REG_BASE + 0x01UL * 2))//(RTC_REG_BASE + 0x01 * 2) 174 #define REG_PMRTC_LOAD_VAL ((PMRTC_REG_BASE + 0x03UL * 2))//(RTC_REG_BASE + 0x03 * 2) 175 #define REG_PMRTC_MATCH_VAL ((PMRTC_REG_BASE + 0x07UL * 2))//(RTC_REG_BASE + 0x05 * 2) 176 #define REG_PMRTC_INTERRUPT ((PMRTC_REG_BASE + 0x00UL * 2 + 1))//(RTC_REG_BASE + 0x07 * 2) 177 #define PMRTC_INT_RAW_STATUS (1 << 0) 178 #define PMRTC_INT_STATUS (1 << 1) 179 180 #define REG_PMRTC_CNT ((PMRTC_REG_BASE + 0x0bUL * 2))//(PMRTC_REG_BASE + 0x08 * 2) 181 182 183 //------------------------------------------------------------------------------ 184 // PM_SLEEP RTC1 register 185 //------------------------------------------------------------------------------ 186 // bank, regiter 187 #define REG_PMRTC1_CTRL ((PMRTC1_REG_BASE + 0x00UL * 2))//RTC_REG_BASE + 0x00 188 #define PMRTC1_CTRL_NOT_RSTZ (1 << 0) 189 #define PMRTC1_CTRL_CNT_EN (1 << 1) 190 #define PMRTC1_CTRL_WRAP_EN (1 << 2) 191 #define PMRTC1_CTRL_LOAD_EN (1 << 3) 192 #define PMRTC1_CTRL_READ_EN (1 << 4) 193 #define PMRTC1_CTRL_INT_MASK (1 << 5) 194 #define PMRTC1_CTRL_INT_FORCE (1 << 6) 195 #define PMRTC1_CTRL_INT_CLEAR (1 << 7) 196 197 #define REG_PMRTC1_FREQ_CW ((PMRTC1_REG_BASE + 0x01UL * 2))//(RTC_REG_BASE + 0x01 * 2) 198 #define REG_PMRTC1_LOAD_VAL ((PMRTC1_REG_BASE + 0x03UL * 2))//(RTC_REG_BASE + 0x03 * 2) 199 #define REG_PMRTC1_MATCH_VAL ((PMRTC1_REG_BASE + 0x07UL * 2))//(RTC_REG_BASE + 0x05 * 2) 200 #define REG_PMRTC1_INTERRUPT ((PMRTC1_REG_BASE + 0x00UL * 2 + 1))//(RTC_REG_BASE + 0x07 * 2) 201 #define PMRTC1_INT_RAW_STATUS (1 << 0) 202 #define PMRTC1_INT_STATUS (1 << 1) 203 #define REG_PMRTC1_CNT ((PMRTC1_REG_BASE + 0x0bUL * 2))//(PMRTC_REG_BASE + 0x08 * 2) 204 205 #endif //_REGPM_H_ 206