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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regNJPD.h 98 /// @brief NJPD Register Table 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_NJPD_H_ 103 #define _REG_NJPD_H_ 104 105 106 //------------------------------------------------------------------------------------------------- 107 // Hardware Capability 108 //------------------------------------------------------------------------------------------------- 109 110 111 //------------------------------------------------------------------------------------------------- 112 // Macro and Define 113 //------------------------------------------------------------------------------------------------- 114 #define NJPD_MEM_SCWGIF_BASE 0x0000 115 #define NJPD_MEM_SYMIDX_BASE 0x0400 116 #define NJPD_MEM_QTBL_BASE 0x0800 117 #define NJPD_MEM_TBL_TOTAL_SIZE 0x1000 118 119 120 #define NJPD_CLKGEN0_BASE 0x00B00 121 #define NJPD1_REG_BASE 0x23200 122 #define NJPD2_REG_BASE 0x23300 123 124 125 // NJPD1 register======================================================================= 126 127 // Global Setting 128 #define BK_NJPD1_GLOBAL_SETTING00 (NJPD1_REG_BASE+NJPD_OFFSET(0x00)) 129 #define BK_NJPD1_GLOBAL_SETTING01 (NJPD1_REG_BASE+NJPD_OFFSET(0x01)) 130 #define BK_NJPD1_GLOBAL_SETTING02 (NJPD1_REG_BASE+NJPD_OFFSET(0x02)) 131 132 // Pitch Width 133 #define BK_NJPD1_PITCH_WIDTH (NJPD1_REG_BASE+NJPD_OFFSET(0x03)) 134 135 // Restart Interval 136 #define BK_NJPD1_RESTART_INTERVAL (NJPD1_REG_BASE+NJPD_OFFSET(0x05)) 137 138 // Image Size 139 #define BK_NJPD1_IMG_HSIZE (NJPD1_REG_BASE+NJPD_OFFSET(0x06)) 140 #define BK_NJPD1_IMG_VSIZE (NJPD1_REG_BASE+NJPD_OFFSET(0x07)) 141 142 // Write-one-clear 143 #define BK_NJPD1_WRITE_ONE_CLEAR (NJPD1_REG_BASE+NJPD_OFFSET(0x08)) 144 145 // Region of Interest 146 #define BK_NJPD1_ROI_H_START (NJPD1_REG_BASE+NJPD_OFFSET(0x09)) 147 #define BK_NJPD1_ROI_V_START (NJPD1_REG_BASE+NJPD_OFFSET(0x0a)) 148 #define BK_NJPD1_ROI_H_SIZE (NJPD1_REG_BASE+NJPD_OFFSET(0x0b)) 149 #define BK_NJPD1_ROI_V_SIZE (NJPD1_REG_BASE+NJPD_OFFSET(0x0c)) 150 151 // Gated-Clock Control 152 #define BK_NJPD1_GATED_CLOCK_CTRL (NJPD1_REG_BASE+NJPD_OFFSET(0x0d)) 153 154 // Miu Interface 155 #define BK_NJPD1_MIU_READ_STATUS (NJPD1_REG_BASE+NJPD_OFFSET(0x0e)) 156 #define BK_NJPD1_MIU_IBUFFER_CNT (NJPD1_REG_BASE+NJPD_OFFSET(0x0f)) 157 #define BK_NJPD1_MIU_READ_START_ADDR_L (NJPD1_REG_BASE+NJPD_OFFSET(0x10)) 158 #define BK_NJPD1_MIU_READ_START_ADDR_H (NJPD1_REG_BASE+NJPD_OFFSET(0x11)) 159 #define BK_NJPD1_MIU_READ_BUFFER0_START_ADDR_L (NJPD1_REG_BASE+NJPD_OFFSET(0x12)) 160 #define BK_NJPD1_MIU_READ_BUFFER0_START_ADDR_H (NJPD1_REG_BASE+NJPD_OFFSET(0x13)) 161 #define BK_NJPD1_MIU_READ_BUFFER0_END_ADDR_L (NJPD1_REG_BASE+NJPD_OFFSET(0x14)) 162 #define BK_NJPD1_MIU_READ_BUFFER0_END_ADDR_H (NJPD1_REG_BASE+NJPD_OFFSET(0x15)) 163 #define BK_NJPD1_MIU_READ_BUFFER1_START_ADDR_L (NJPD1_REG_BASE+NJPD_OFFSET(0x16)) 164 #define BK_NJPD1_MIU_READ_BUFFER1_START_ADDR_H (NJPD1_REG_BASE+NJPD_OFFSET(0x17)) 165 #define BK_NJPD1_MIU_READ_BUFFER1_END_ADDR_L (NJPD1_REG_BASE+NJPD_OFFSET(0x18)) 166 #define BK_NJPD1_MIU_READ_BUFFER1_END_ADDR_H (NJPD1_REG_BASE+NJPD_OFFSET(0x19)) 167 #define BK_NJPD1_MIU_WRITE_START_ADDR_L (NJPD1_REG_BASE+NJPD_OFFSET(0x1a)) 168 #define BK_NJPD1_MIU_WRITE_START_ADDR_H (NJPD1_REG_BASE+NJPD_OFFSET(0x1b)) 169 #define BK_NJPD1_MIU_WRITE_POINTER_ADDR_L (NJPD1_REG_BASE+NJPD_OFFSET(0x1c)) 170 #define BK_NJPD1_MIU_WRITE_POINTER_ADDR_H (NJPD1_REG_BASE+NJPD_OFFSET(0x1d)) 171 #define BK_NJPD1_MIU_READ_POINTER_ADDR_L (NJPD1_REG_BASE+NJPD_OFFSET(0x1e)) 172 #define BK_NJPD1_MIU_READ_POINTER_ADDR_H (NJPD1_REG_BASE+NJPD_OFFSET(0x1f)) 173 #define BK_NJPD1_MIU_HTABLE_START_ADDR_L (NJPD1_REG_BASE+NJPD_OFFSET(0x20)) 174 #define BK_NJPD1_MIU_HTABLE_START_ADDR_H (NJPD1_REG_BASE+NJPD_OFFSET(0x21)) 175 #define BK_NJPD1_MIU_GTABLE_START_ADDR_L (NJPD1_REG_BASE+NJPD_OFFSET(0x22)) 176 #define BK_NJPD1_MIU_GTABLE_START_ADDR_H (NJPD1_REG_BASE+NJPD_OFFSET(0x23)) 177 #define BK_NJPD1_MIU_QTABLE_START_ADDR_L (NJPD1_REG_BASE+NJPD_OFFSET(0x24)) 178 #define BK_NJPD1_MIU_QTABLE_START_ADDR_H (NJPD1_REG_BASE+NJPD_OFFSET(0x25)) 179 #define BK_NJPD1_MIU_HTABLE_SIZE (NJPD1_REG_BASE+NJPD_OFFSET(0x26)) 180 #define BK_NJPD1_SET_CHROMA_VALUE (NJPD1_REG_BASE+NJPD_OFFSET(0x27)) 181 #define BK_NJPD1_IBUF_READ_LENGTH (NJPD1_REG_BASE+NJPD_OFFSET(0x28)) 182 183 184 // Interrupt 185 #define BK_NJPD1_IRQ_CLEAR (NJPD1_REG_BASE+NJPD_OFFSET(0x29)) 186 #define BK_NJPD1_IRQ_FORCE (NJPD1_REG_BASE+NJPD_OFFSET(0x2a)) 187 #define BK_NJPD1_IRQ_MASK (NJPD1_REG_BASE+NJPD_OFFSET(0x2b)) 188 #define BK_NJPD1_IRQ_FINAL_S (NJPD1_REG_BASE+NJPD_OFFSET(0x2c)) 189 #define BK_NJPD1_IRQ_RAW_S (NJPD1_REG_BASE+NJPD_OFFSET(0x2d)) 190 191 // Sram Gated-Clock Control 192 #define BK_NJPD1_MIU_TLB (NJPD1_REG_BASE+NJPD_OFFSET(0x2f)+1) 193 194 // Debug 195 #define BK_NJPD1_ROW_IDEX (NJPD1_REG_BASE+NJPD_OFFSET(0x30)) 196 #define BK_NJPD1_COLUMN_IDEX (NJPD1_REG_BASE+NJPD_OFFSET(0x31)) 197 #define BK_NJPD1_DEBUG_BUS_SELECT (NJPD1_REG_BASE+NJPD_OFFSET(0x32)) 198 #define BK_NJPD1_DEBUG_BUS_H (NJPD1_REG_BASE+NJPD_OFFSET(0x33)) 199 #define BK_NJPD1_DEBUG_BUS_L (NJPD1_REG_BASE+NJPD_OFFSET(0x34)) 200 #define BK_NJPD1_IBUF_BYTE_COUNT_L (NJPD1_REG_BASE+NJPD_OFFSET(0x35)) 201 #define BK_NJPD1_IBUF_BYTE_COUNT_H (NJPD1_REG_BASE+NJPD_OFFSET(0x36)) 202 #define BK_NJPD1_VLD_BYTE_COUNT_L (NJPD1_REG_BASE+NJPD_OFFSET(0x37)) 203 #define BK_NJPD1_VLD_BYTE_COUNT_H (NJPD1_REG_BASE+NJPD_OFFSET(0x38)) 204 #define BK_NJPD1_VLD_DECODING_DATA_L (NJPD1_REG_BASE+NJPD_OFFSET(0x39)) 205 #define BK_NJPD1_VLD_DECODING_DATA_H (NJPD1_REG_BASE+NJPD_OFFSET(0x3a)) 206 #define BK_NJPD1_DEBUG_TRIG_CYCLE (NJPD1_REG_BASE+NJPD_OFFSET(0x3b)) 207 #define BK_NJPD1_DEBUG_TRIG_MBX (NJPD1_REG_BASE+NJPD_OFFSET(0x3c)) 208 #define BK_NJPD1_DEBUG_TRIG_MBY (NJPD1_REG_BASE+NJPD_OFFSET(0x3d)) 209 #define BK_NJPD1_DEBUG_TRIGGER (NJPD1_REG_BASE+NJPD_OFFSET(0x3e)) 210 211 212 // BIST 213 #define BK_NJPD1_BIST_FAIL (NJPD1_REG_BASE+NJPD_OFFSET(0x3f)) 214 215 216 // TBC RIU Interface 217 #define BK_NJPD1_TBC (NJPD1_REG_BASE+NJPD_OFFSET(0x40)) 218 #define BK_NJPD1_TBC_WDATA0 (NJPD1_REG_BASE+NJPD_OFFSET(0x41)) 219 #define BK_NJPD1_TBC_WDATA1 (NJPD1_REG_BASE+NJPD_OFFSET(0x42)) 220 #define BK_NJPD1_TBC_RDATA_L (NJPD1_REG_BASE+NJPD_OFFSET(0x43)) 221 #define BK_NJPD1_TBC_RDATA_H (NJPD1_REG_BASE+NJPD_OFFSET(0x44)) 222 223 224 // Max Huffman Table Address 225 #define BK_NJPD1_Y_MAX_HUFFTABLE_ADDRESS (NJPD1_REG_BASE+NJPD_OFFSET(0x45)) 226 #define BK_NJPD1_CB_MAX_HUFFTABLE_ADDRESS (NJPD1_REG_BASE+NJPD_OFFSET(0x46)) 227 #define BK_NJPD1_CR_MAX_HUFFTABLE_ADDRESS (NJPD1_REG_BASE+NJPD_OFFSET(0x47)) 228 229 230 // Spare 231 #define BK_NJPD1_SPARE00 (NJPD1_REG_BASE+NJPD_OFFSET(0x48)) 232 #define BK_NJPD1_SPARE01 (NJPD1_REG_BASE+NJPD_OFFSET(0x49)) 233 #define BK_NJPD1_SPARE02 (NJPD1_REG_BASE+NJPD_OFFSET(0x4a)) 234 #define BK_NJPD1_SPARE03 (NJPD1_REG_BASE+NJPD_OFFSET(0x4b)) 235 #define BK_NJPD1_SPARE04 (NJPD1_REG_BASE+NJPD_OFFSET(0x4c)) 236 #define BK_NJPD1_SPARE05 (NJPD1_REG_BASE+NJPD_OFFSET(0x4d)) 237 #define BK_NJPD1_SPARE06 (NJPD1_REG_BASE+NJPD_OFFSET(0x4e)) 238 #define BK_NJPD1_SPARE07 (NJPD1_REG_BASE+NJPD_OFFSET(0x4f)) 239 240 #define BK_NJPD1_SPARE07 (NJPD1_REG_BASE+NJPD_OFFSET(0x4f)) 241 242 #define BK_NJPD1_MARB_SETTING_00 (NJPD1_REG_BASE+NJPD_OFFSET(0x50)) 243 #define BK_NJPD1_MARB_SETTING_01 (NJPD1_REG_BASE+NJPD_OFFSET(0x51)) 244 #define BK_NJPD1_MARB_SETTING_02 (NJPD1_REG_BASE+NJPD_OFFSET(0x52)) 245 #define BK_NJPD1_MARB_SETTING_03 (NJPD1_REG_BASE+NJPD_OFFSET(0x53)) 246 #define BK_NJPD1_MARB_SETTING_04 (NJPD1_REG_BASE+NJPD_OFFSET(0x54)) 247 #define BK_NJPD1_MARB_SETTING_05 (NJPD1_REG_BASE+NJPD_OFFSET(0x55)) 248 #define BK_NJPD1_MARB_SETTING_06 (NJPD1_REG_BASE+NJPD_OFFSET(0x56)) 249 #define BK_NJPD1_MARB_SETTING_07 (NJPD1_REG_BASE+NJPD_OFFSET(0x57)) 250 251 #define BK_NJPD1_MARB_UBOUND_0_L (NJPD1_REG_BASE+NJPD_OFFSET(0x58)) 252 #define BK_NJPD1_MARB_UBOUND_0_H (NJPD1_REG_BASE+NJPD_OFFSET(0x59)) 253 #define BK_NJPD1_MARB_LBOUND_0_L (NJPD1_REG_BASE+NJPD_OFFSET(0x5a)) 254 #define BK_NJPD1_MARB_LBOUND_0_H (NJPD1_REG_BASE+NJPD_OFFSET(0x5b)) 255 256 257 #define BK_NJPD1_CRC_MODE (NJPD1_REG_BASE+NJPD_OFFSET(0x6d)) 258 259 // Miu Arbiter 260 // TODO: MIU Arbiter registers 261 262 263 #define BK_NJPD1_MARB_CRC_RESULT_0 (NJPD1_REG_BASE+NJPD_OFFSET(0x70)) 264 #define BK_NJPD1_MARB_CRC_RESULT_1 (NJPD1_REG_BASE+NJPD_OFFSET(0x71)) 265 #define BK_NJPD1_MARB_CRC_RESULT_2 (NJPD1_REG_BASE+NJPD_OFFSET(0x72)) 266 #define BK_NJPD1_MARB_CRC_RESULT_3 (NJPD1_REG_BASE+NJPD_OFFSET(0x73)) 267 #define BK_NJPD1_MARB_RESET (NJPD1_REG_BASE+NJPD_OFFSET(0x74)) 268 #define BK_NJPD1_HANDSHAKE_CNT (NJPD1_REG_BASE+NJPD_OFFSET(0x74)+1) 269 #define BK_NJPD1_SW_MB_ROW_CNT (NJPD1_REG_BASE+NJPD_OFFSET(0x75)) 270 #define BK_NJPD1_HANDSHAKE (NJPD1_REG_BASE+NJPD_OFFSET(0x75)+1) 271 #define BK_NJPD1_TOP_MARB_PORT_ENABLE (NJPD1_REG_BASE+NJPD_OFFSET(0x76)) 272 273 #define BK_NJPD1_GENERAL(x) (NJPD1_REG_BASE+NJPD_OFFSET(x)) 274 275 276 // NJPD2 register======================================================================= 277 278 279 // Global Setting 280 #define BK_NJPD2_GLOBAL_SETTING00 (NJPD2_REG_BASE+NJPD_OFFSET(0x00)) 281 #define BK_NJPD2_GLOBAL_SETTING01 (NJPD2_REG_BASE+NJPD_OFFSET(0x01)) 282 #define BK_NJPD2_GLOBAL_SETTING02 (NJPD2_REG_BASE+NJPD_OFFSET(0x02)) 283 284 // Pitch Width 285 #define BK_NJPD2_PITCH_WIDTH (NJPD2_REG_BASE+NJPD_OFFSET(0x03)) 286 287 // Restart Interval 288 #define BK_NJPD2_RESTART_INTERVAL (NJPD2_REG_BASE+NJPD_OFFSET(0x05)) 289 290 // Image Size 291 #define BK_NJPD2_IMG_HSIZE (NJPD2_REG_BASE+NJPD_OFFSET(0x06)) 292 #define BK_NJPD2_IMG_VSIZE (NJPD2_REG_BASE+NJPD_OFFSET(0x07)) 293 294 // Write-one-clear 295 #define BK_NJPD2_WRITE_ONE_CLEAR (NJPD2_REG_BASE+NJPD_OFFSET(0x08)) 296 297 // Region of Interest 298 #define BK_NJPD2_ROI_H_START (NJPD2_REG_BASE+NJPD_OFFSET(0x09)) 299 #define BK_NJPD2_ROI_V_START (NJPD2_REG_BASE+NJPD_OFFSET(0x0a)) 300 #define BK_NJPD2_ROI_H_SIZE (NJPD2_REG_BASE+NJPD_OFFSET(0x0b)) 301 #define BK_NJPD2_ROI_V_SIZE (NJPD2_REG_BASE+NJPD_OFFSET(0x0c)) 302 303 // Gated-Clock Control 304 #define BK_NJPD2_GATED_CLOCK_CTRL (NJPD2_REG_BASE+NJPD_OFFSET(0x0d)) 305 306 // Miu Interface 307 #define BK_NJPD2_MIU_READ_STATUS (NJPD2_REG_BASE+NJPD_OFFSET(0x0e)) 308 #define BK_NJPD2_MIU_IBUFFER_CNT (NJPD2_REG_BASE+NJPD_OFFSET(0x0f)) 309 #define BK_NJPD2_MIU_READ_START_ADDR_L (NJPD2_REG_BASE+NJPD_OFFSET(0x10)) 310 #define BK_NJPD2_MIU_READ_START_ADDR_H (NJPD2_REG_BASE+NJPD_OFFSET(0x11)) 311 #define BK_NJPD2_MIU_READ_BUFFER0_START_ADDR_L (NJPD2_REG_BASE+NJPD_OFFSET(0x12)) 312 #define BK_NJPD2_MIU_READ_BUFFER0_START_ADDR_H (NJPD2_REG_BASE+NJPD_OFFSET(0x13)) 313 #define BK_NJPD2_MIU_READ_BUFFER0_END_ADDR_L (NJPD2_REG_BASE+NJPD_OFFSET(0x14)) 314 #define BK_NJPD2_MIU_READ_BUFFER0_END_ADDR_H (NJPD2_REG_BASE+NJPD_OFFSET(0x15)) 315 #define BK_NJPD2_MIU_READ_BUFFER1_START_ADDR_L (NJPD2_REG_BASE+NJPD_OFFSET(0x16)) 316 #define BK_NJPD2_MIU_READ_BUFFER1_START_ADDR_H (NJPD2_REG_BASE+NJPD_OFFSET(0x17)) 317 #define BK_NJPD2_MIU_READ_BUFFER1_END_ADDR_L (NJPD2_REG_BASE+NJPD_OFFSET(0x18)) 318 #define BK_NJPD2_MIU_READ_BUFFER1_END_ADDR_H (NJPD2_REG_BASE+NJPD_OFFSET(0x19)) 319 #define BK_NJPD2_MIU_WRITE_START_ADDR_L (NJPD2_REG_BASE+NJPD_OFFSET(0x1a)) 320 #define BK_NJPD2_MIU_WRITE_START_ADDR_H (NJPD2_REG_BASE+NJPD_OFFSET(0x1b)) 321 #define BK_NJPD2_MIU_WRITE_POINTER_ADDR_L (NJPD2_REG_BASE+NJPD_OFFSET(0x1c)) 322 #define BK_NJPD2_MIU_WRITE_POINTER_ADDR_H (NJPD2_REG_BASE+NJPD_OFFSET(0x1d)) 323 #define BK_NJPD2_MIU_READ_POINTER_ADDR_L (NJPD2_REG_BASE+NJPD_OFFSET(0x1e)) 324 #define BK_NJPD2_MIU_READ_POINTER_ADDR_H (NJPD2_REG_BASE+NJPD_OFFSET(0x1f)) 325 #define BK_NJPD2_MIU_HTABLE_START_ADDR_L (NJPD2_REG_BASE+NJPD_OFFSET(0x20)) 326 #define BK_NJPD2_MIU_HTABLE_START_ADDR_H (NJPD2_REG_BASE+NJPD_OFFSET(0x21)) 327 #define BK_NJPD2_MIU_GTABLE_START_ADDR_L (NJPD2_REG_BASE+NJPD_OFFSET(0x22)) 328 #define BK_NJPD2_MIU_GTABLE_START_ADDR_H (NJPD2_REG_BASE+NJPD_OFFSET(0x23)) 329 #define BK_NJPD2_MIU_QTABLE_START_ADDR_L (NJPD2_REG_BASE+NJPD_OFFSET(0x24)) 330 #define BK_NJPD2_MIU_QTABLE_START_ADDR_H (NJPD2_REG_BASE+NJPD_OFFSET(0x25)) 331 #define BK_NJPD2_MIU_HTABLE_SIZE (NJPD2_REG_BASE+NJPD_OFFSET(0x26)) 332 #define BK_NJPD2_SET_CHROMA_VALUE (NJPD2_REG_BASE+NJPD_OFFSET(0x27)) 333 #define BK_NJPD2_IBUF_READ_LENGTH (NJPD2_REG_BASE+NJPD_OFFSET(0x28)) 334 335 336 // Interrupt 337 #define BK_NJPD2_IRQ_CLEAR (NJPD2_REG_BASE+NJPD_OFFSET(0x29)) 338 #define BK_NJPD2_IRQ_FORCE (NJPD2_REG_BASE+NJPD_OFFSET(0x2a)) 339 #define BK_NJPD2_IRQ_MASK (NJPD2_REG_BASE+NJPD_OFFSET(0x2b)) 340 #define BK_NJPD2_IRQ_FINAL_S (NJPD2_REG_BASE+NJPD_OFFSET(0x2c)) 341 #define BK_NJPD2_IRQ_RAW_S (NJPD2_REG_BASE+NJPD_OFFSET(0x2d)) 342 343 // Sram Gated-Clock Control 344 #define BK_NJPD2_MIU_TLB (NJPD2_REG_BASE+NJPD_OFFSET(0x2f)+1) 345 346 347 // Debug 348 #define BK_NJPD2_ROW_IDEX (NJPD2_REG_BASE+NJPD_OFFSET(0x30)) 349 #define BK_NJPD2_COLUMN_IDEX (NJPD2_REG_BASE+NJPD_OFFSET(0x31)) 350 #define BK_NJPD2_DEBUG_BUS_SELECT (NJPD2_REG_BASE+NJPD_OFFSET(0x32)) 351 #define BK_NJPD2_DEBUG_BUS_H (NJPD2_REG_BASE+NJPD_OFFSET(0x33)) 352 #define BK_NJPD2_DEBUG_BUS_L (NJPD2_REG_BASE+NJPD_OFFSET(0x34)) 353 #define BK_NJPD2_IBUF_BYTE_COUNT_L (NJPD2_REG_BASE+NJPD_OFFSET(0x35)) 354 #define BK_NJPD2_IBUF_BYTE_COUNT_H (NJPD2_REG_BASE+NJPD_OFFSET(0x36)) 355 #define BK_NJPD2_VLD_BYTE_COUNT_L (NJPD2_REG_BASE+NJPD_OFFSET(0x37)) 356 #define BK_NJPD2_VLD_BYTE_COUNT_H (NJPD2_REG_BASE+NJPD_OFFSET(0x38)) 357 #define BK_NJPD2_VLD_DECODING_DATA_L (NJPD2_REG_BASE+NJPD_OFFSET(0x39)) 358 #define BK_NJPD2_VLD_DECODING_DATA_H (NJPD2_REG_BASE+NJPD_OFFSET(0x3a)) 359 #define BK_NJPD2_DEBUG_TRIG_CYCLE (NJPD2_REG_BASE+NJPD_OFFSET(0x3b)) 360 #define BK_NJPD2_DEBUG_TRIG_MBX (NJPD2_REG_BASE+NJPD_OFFSET(0x3c)) 361 #define BK_NJPD2_DEBUG_TRIG_MBY (NJPD2_REG_BASE+NJPD_OFFSET(0x3d)) 362 #define BK_NJPD2_DEBUG_TRIGGER (NJPD2_REG_BASE+NJPD_OFFSET(0x3e)) 363 364 365 // BIST 366 #define BK_NJPD2_BIST_FAIL (NJPD2_REG_BASE+NJPD_OFFSET(0x3f)) 367 368 369 // TBC RIU Interface 370 #define BK_NJPD2_TBC (NJPD2_REG_BASE+NJPD_OFFSET(0x40)) 371 #define BK_NJPD2_TBC_WDATA0 (NJPD2_REG_BASE+NJPD_OFFSET(0x41)) 372 #define BK_NJPD2_TBC_WDATA1 (NJPD2_REG_BASE+NJPD_OFFSET(0x42)) 373 #define BK_NJPD2_TBC_RDATA_L (NJPD2_REG_BASE+NJPD_OFFSET(0x43)) 374 #define BK_NJPD2_TBC_RDATA_H (NJPD2_REG_BASE+NJPD_OFFSET(0x44)) 375 376 377 // Max Huffman Table Address 378 #define BK_NJPD2_Y_MAX_HUFFTABLE_ADDRESS (NJPD2_REG_BASE+NJPD_OFFSET(0x45)) 379 #define BK_NJPD2_CB_MAX_HUFFTABLE_ADDRESS (NJPD2_REG_BASE+NJPD_OFFSET(0x46)) 380 #define BK_NJPD2_CR_MAX_HUFFTABLE_ADDRESS (NJPD2_REG_BASE+NJPD_OFFSET(0x47)) 381 382 383 // Spare 384 #define BK_NJPD2_SPARE00 (NJPD2_REG_BASE+NJPD_OFFSET(0x48)) 385 #define BK_NJPD2_SPARE01 (NJPD2_REG_BASE+NJPD_OFFSET(0x49)) 386 #define BK_NJPD2_SPARE02 (NJPD2_REG_BASE+NJPD_OFFSET(0x4a)) 387 #define BK_NJPD2_SPARE03 (NJPD2_REG_BASE+NJPD_OFFSET(0x4b)) 388 #define BK_NJPD2_SPARE04 (NJPD2_REG_BASE+NJPD_OFFSET(0x4c)) 389 #define BK_NJPD2_SPARE05 (NJPD2_REG_BASE+NJPD_OFFSET(0x4d)) 390 #define BK_NJPD2_SPARE06 (NJPD2_REG_BASE+NJPD_OFFSET(0x4e)) 391 #define BK_NJPD2_SPARE07 (NJPD2_REG_BASE+NJPD_OFFSET(0x4f)) 392 393 #define BK_NJPD2_SPARE07 (NJPD2_REG_BASE+NJPD_OFFSET(0x4f)) 394 395 #define BK_NJPD2_MARB_SETTING_00 (NJPD2_REG_BASE+NJPD_OFFSET(0x50)) 396 #define BK_NJPD2_MARB_SETTING_01 (NJPD2_REG_BASE+NJPD_OFFSET(0x51)) 397 #define BK_NJPD2_MARB_SETTING_02 (NJPD2_REG_BASE+NJPD_OFFSET(0x52)) 398 #define BK_NJPD2_MARB_SETTING_03 (NJPD2_REG_BASE+NJPD_OFFSET(0x53)) 399 #define BK_NJPD2_MARB_SETTING_04 (NJPD2_REG_BASE+NJPD_OFFSET(0x54)) 400 #define BK_NJPD2_MARB_SETTING_05 (NJPD2_REG_BASE+NJPD_OFFSET(0x55)) 401 #define BK_NJPD2_MARB_SETTING_06 (NJPD2_REG_BASE+NJPD_OFFSET(0x56)) 402 #define BK_NJPD2_MARB_SETTING_07 (NJPD2_REG_BASE+NJPD_OFFSET(0x57)) 403 404 #define BK_NJPD2_MARB_UBOUND_0_L (NJPD2_REG_BASE+NJPD_OFFSET(0x58)) 405 #define BK_NJPD2_MARB_UBOUND_0_H (NJPD2_REG_BASE+NJPD_OFFSET(0x59)) 406 #define BK_NJPD2_MARB_LBOUND_0_L (NJPD2_REG_BASE+NJPD_OFFSET(0x5a)) 407 #define BK_NJPD2_MARB_LBOUND_0_H (NJPD2_REG_BASE+NJPD_OFFSET(0x5b)) 408 409 410 #define BK_NJPD2_CRC_MODE (NJPD2_REG_BASE+NJPD_OFFSET(0x6d)) 411 412 // Miu Arbiter 413 // TODO: MIU Arbiter registers 414 415 416 #define BK_NJPD2_MARB_CRC_RESULT_0 (NJPD2_REG_BASE+NJPD_OFFSET(0x70)) 417 #define BK_NJPD2_MARB_CRC_RESULT_1 (NJPD2_REG_BASE+NJPD_OFFSET(0x71)) 418 #define BK_NJPD2_MARB_CRC_RESULT_2 (NJPD2_REG_BASE+NJPD_OFFSET(0x72)) 419 #define BK_NJPD2_MARB_CRC_RESULT_3 (NJPD2_REG_BASE+NJPD_OFFSET(0x73)) 420 #define BK_NJPD2_MARB_RESET (NJPD2_REG_BASE+NJPD_OFFSET(0x74)) 421 #define BK_NJPD2_HANDSHAKE_CNT (NJPD2_REG_BASE+NJPD_OFFSET(0x74)+1) 422 #define BK_NJPD2_SW_MB_ROW_CNT (NJPD2_REG_BASE+NJPD_OFFSET(0x75)) 423 #define BK_NJPD2_HANDSHAKE (NJPD2_REG_BASE+NJPD_OFFSET(0x75)+1) 424 #define BK_NJPD2_TOP_MARB_PORT_ENABLE (NJPD2_REG_BASE+NJPD_OFFSET(0x76)) 425 426 #define BK_NJPD2_GENERAL(x) (NJPD2_REG_BASE+NJPD_OFFSET(x)) 427 428 #define BK_MIU0_GENERAL(x) (NJPD_MIU0_BASE+NJPD_OFFSET(x)) 429 #define BK_MIU1_GENERAL(x) (NJPD_MIU1_BASE+NJPD_OFFSET(x)) 430 431 432 433 // CLKGEN0 434 // For Agate, we use bank 0x0B,offset 0x35 bit(8:11) to set reg_ckg_njpd 435 #define NJPD_CLOCK (NJPD_CLKGEN0_BASE+NJPD_OFFSET(0x35)) // Agate 436 //CLK_NJPD clock setting 437 //[0]: disable clock 438 //[1]: invert clock 439 //[3:2]: Select clock source 440 // 00: 144 MHz 441 // 01: 123 MHz 442 // 10: 108 MHz 443 // 11: 80 MHz 444 445 446 // MIU 447 #define NJPD_MIU0_BASE 0x1200 448 #define NJPD_MIU1_BASE 0x0600 449 // h0033 h0033 15 0 reg_rq1_mask 450 #define NJPD_MIU0_RQ1_MASK (NJPD_MIU0_BASE+NJPD_OFFSET(0x33)) 451 #define NJPD_MIU1_RQ1_MASK (NJPD_MIU1_BASE+NJPD_OFFSET(0x33)) 452 #define NJPD0_MIU0_CLIENT_NJPD NJPD_BIT(3) //bit3 of the first byte (bit 3) 453 #define NJPD0_MIU1_CLIENT_NJPD NJPD_BIT(3) //bit3 of the first byte (bit 3) 454 #define NJPD1_MIU0_CLIENT_NJPD NJPD_BIT(3) //bit3 of the first byte (bit 3) 455 #define NJPD1_MIU1_CLIENT_NJPD NJPD_BIT(3) //bit3 of the first byte (bit 3) 456 457 //h0079 h0079 15 0 reg_miu_sel1 458 #define NJPD0_MIU0_MIU_SEL1 (NJPD_MIU0_BASE+NJPD_OFFSET(0x79)) 459 #define NJPD0_MIU1_MIU_SEL1 (NJPD_MIU1_BASE+NJPD_OFFSET(0x79)) 460 #define NJPD1_MIU0_MIU_SEL1 (NJPD_MIU0_BASE+NJPD_OFFSET(0x79)) 461 #define NJPD1_MIU1_MIU_SEL1 (NJPD_MIU1_BASE+NJPD_OFFSET(0x79)) 462 463 464 #define NJPD_1608_BASE 0x60800 465 #define NJPD_160F_BASE 0x60F00 466 #define NJPD_1615_BASE 0x61500 467 #define NJPD_1620_BASE 0x62000 468 469 470 #define BK_1608_GENERAL(x) (NJPD_1608_BASE+NJPD_OFFSET(x)) 471 #define BK_160F_GENERAL(x) (NJPD_160F_BASE+NJPD_OFFSET(x)) 472 #define BK_1615_GENERAL(x) (NJPD_1615_BASE+NJPD_OFFSET(x)) 473 #define BK_1620_GENERAL(x) (NJPD_1620_BASE+NJPD_OFFSET(x)) 474 475 476 // TSP 477 #define NJPD_TSP_BASE 0x1500 478 #define REG_TSP_CTRL (NJPD_TSP_BASE + NJPD_OFFSET(0x7A)) 479 #define REG_TSP_CPU_ENABLE NJPD_BIT(0) 480 #define REG_TSP_SW_RSTZ NJPD_BIT(1) 481 #define REG_TSP_STC_L (NJPD_TSP_BASE + NJPD_OFFSET(0x30)) 482 #define REG_TSP_STC_H (NJPD_TSP_BASE + NJPD_OFFSET(0x31)) 483 484 485 // CHIPTOP 486 #define NJPD_CHIPTOP_BASE 0x1E00 487 #define NJPD_MIU_GROUP1_I64 (NJPD_CHIPTOP_BASE + NJPD_OFFSET(0x21)) 488 #define NJPD_MIU0_CLIENT_NJPD_CS3 NJPD_BIT(3) // bit3 of the first byte (bit 3) 489 490 // TZPC NON-PM 491 #define NJPD_TZPC_NONPM_BASE 0x23900 492 #define NJPD_NONPM_SECURE_20 (NJPD_TZPC_NONPM_BASE + NJPD_OFFSET(0x20)) 493 #define NJPD_NONPM_SECURE_21 (NJPD_TZPC_NONPM_BASE + NJPD_OFFSET(0x21)) 494 #define NJPD_NONPM_SECURE_22 (NJPD_TZPC_NONPM_BASE + NJPD_OFFSET(0x22)) 495 #define NJPD_NONPM_SECURE_23 (NJPD_TZPC_NONPM_BASE + NJPD_OFFSET(0x23)) 496 #define NJPD_NONPM_SECURE_24 (NJPD_TZPC_NONPM_BASE + NJPD_OFFSET(0x24)) 497 #define NJPD_NONPM_SECURE_25 (NJPD_TZPC_NONPM_BASE + NJPD_OFFSET(0x25)) 498 #define NJPD_NONPM_SECURE_26 (NJPD_TZPC_NONPM_BASE + NJPD_OFFSET(0x26)) 499 #define NJPD_NONPM_SECURE_27 (NJPD_TZPC_NONPM_BASE + NJPD_OFFSET(0x27)) 500 #define NJPD_NONPM_SECURE_28 (NJPD_TZPC_NONPM_BASE + NJPD_OFFSET(0x28)) 501 #define NJPD_NONPM_SECURE_29 (NJPD_TZPC_NONPM_BASE + NJPD_OFFSET(0x29)) 502 #define NJPD_NONPM_SECURE_2A (NJPD_TZPC_NONPM_BASE + NJPD_OFFSET(0x2A)) 503 #define NJPD_NONPM_SECURE_2B (NJPD_TZPC_NONPM_BASE + NJPD_OFFSET(0x2B)) 504 #define NJPD_NONPM_SECURE_2C (NJPD_TZPC_NONPM_BASE + NJPD_OFFSET(0x2C)) 505 #define NJPD_NONPM_SECURE_2D (NJPD_TZPC_NONPM_BASE + NJPD_OFFSET(0x2D)) 506 #define NJPD_NONPM_SECURE_2E (NJPD_TZPC_NONPM_BASE + NJPD_OFFSET(0x2E)) 507 #define NJPD_NONPM_SECURE_2F (NJPD_TZPC_NONPM_BASE + NJPD_OFFSET(0x2F)) 508 509 #define BK_TZPC_GENERAL(x) (NJPD_TZPC_NONPM_BASE+NJPD_OFFSET(x)) 510 511 #if 0 512 #define JPD_REG_BASE 0x1700 513 514 #define BK_JPD_SCONFIG (JPD_REG_BASE+NJPD_OFFSET(0x00)) 515 #define BK_JPD_MCONFIG (JPD_REG_BASE+NJPD_OFFSET(0x01)) 516 #define BK_JPD_RCSMADR_L (JPD_REG_BASE+NJPD_OFFSET(0x0B)) 517 #define BK_JPD_RCSMADR_H (JPD_REG_BASE+NJPD_OFFSET(0x0C)) 518 #define BK_JPD_RBUF_FLOOR_L (JPD_REG_BASE+NJPD_OFFSET(0x0D)) 519 #define BK_JPD_RBUF_FLOOR_H (JPD_REG_BASE+NJPD_OFFSET(0x0E)) 520 #define BK_JPD_RBUF_CEIL_L (JPD_REG_BASE+NJPD_OFFSET(0x0F)) 521 #define BK_JPD_RBUF_CEIL_H (JPD_REG_BASE+NJPD_OFFSET(0x10)) 522 #define BK_JPD_MWBF_SADR_L (JPD_REG_BASE+NJPD_OFFSET(0x11)) 523 #define BK_JPD_MWBF_SADR_H (JPD_REG_BASE+NJPD_OFFSET(0x12)) 524 #define BK_JPD_AUTO_PROTECT (JPD_REG_BASE+NJPD_OFFSET(0x1F)) 525 #define BK_JPD_MWBF_EADR_L (JPD_REG_BASE+NJPD_OFFSET(0x20)) 526 #define BK_JPD_MWBF_EADR_H (JPD_REG_BASE+NJPD_OFFSET(0x21)) 527 528 #define BK_JPD1_GENERAL(x) (JPD_REG_BASE+NJPD_OFFSET(x)) 529 #endif 530 531 #endif // _REG_NJPD_H_ 532 533 534