1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
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20 //
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
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91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #include "MsCommon.h"
101 #ifndef MSOS_TYPE_LINUX_KERNEL
102 #include <string.h>
103 #endif
104 #include "MsTypes.h"
105 #include "MsIRQ.h"
106 #include "MsOS.h"
107 #include "drvMVOP.h"
108 #include "drvMIU.h"
109
110 // Internal Definition
111 #include "regMVOP.h"
112 #include "halMVOP.h"
113
114 #ifndef ANDROID
115 #define MVOP_PRINTF printf
116 #else
117 #include <sys/mman.h>
118 #include <cutils/ashmem.h>
119 #include <cutils/log.h>
120
121 #define MVOP_PRINTF ALOGD
122 #endif
123
124 // Common
125 #ifdef MSOS_TYPE_LINUX_KERNEL
126 #include <asm/div64.h>
127 #else
128 #define do_div(x,y) ((x)/=(y))
129 #define do_mod(x,y) ((x)%=(y))
130 #endif
131 //-------------------------------------------------------------------------------------------------
132 // Driver Compiler Options
133 //-------------------------------------------------------------------------------------------------
134
135
136 //-------------------------------------------------------------------------------------------------
137 // Local Defines
138 //-------------------------------------------------------------------------------------------------
139 #define MPLL_CLOCK (432000000ULL)
140
141 #define BIT0 BIT(0)
142 #define BIT1 BIT(1)
143 #define BIT2 BIT(2)
144 #define BIT3 BIT(3)
145 #define BIT4 BIT(4)
146 #define BIT5 BIT(5)
147 #define BIT6 BIT(6)
148 #define BIT7 BIT(7)
149 #define BIT15 BIT(15)
150
151 #define ALIGN_UPTO_16(x) ((((x) + 15) >> 4) << 4)
152 #define ALIGN_UPTO_4(x) ((((x) + 3) >> 2) << 2)
153 #define ALIGN_UPTO_2(x) ((((x) + 1) >> 1) << 1)
154
155 #define MVOP_VBlank 45
156 #define MVOP_HBlank_SD 200
157 #define MVOP_HBlank_HD 300
158
159 #if 0
160 static MS_U32 u32RiuBaseAdd=0;
161 static MS_BOOL bMirrorModeVer = 0;
162 static MS_BOOL bMirrorModeHor = 0;
163 static MS_BOOL bMirrorMode=0;
164 static MS_BOOL bSubMirrorModeVer = 0;
165 static MS_BOOL bSubMirrorModeHor = 0;
166 static MS_BOOL bSubMirrorMode=0;
167 static MS_BOOL bEnableFreerunMode = FALSE;
168 static MS_BOOL bSubEnableFreerunMode = FALSE;
169 static MS_BOOL b3DLRMode=0; /// 3D L/R dual buffer mode
170 static MS_BOOL bSub3DLRMode=0;
171 static MS_BOOL b3DLRAltOutput = FALSE; /// 3D L/R line alternative output
172 static MS_BOOL bNewVSyncMode = FALSE;
173 static MVOP_RptFldMode eRepeatField = E_MVOP_RPTFLD_NONE; /// mvop output repeating fields for single field input.
174 static MVOP_RptFldMode eSubRepeatField = E_MVOP_RPTFLD_NONE; /// mvop output repeating fields for single field input.
175 static MVOP_RgbFormat eMainRgbFmt = E_MVOP_RGB_NONE;
176 static MVOP_RgbFormat eSubRgbFmt = E_MVOP_RGB_NONE;
177 #endif
178
179 typedef struct
180 {
181
182 MS_BOOL bMirrorModeVer;
183 MS_BOOL bMirrorModeHor;
184 MS_BOOL bMirrorMode;
185 MS_BOOL bEnableFreerunMode;
186 MS_BOOL b3DLRMode; /// 3D L/R dual buffer mode
187 MS_BOOL b3DLRAltOutput; /// 3D L/R line alternative output
188 MS_BOOL b3DLRAltSBSOutput; /// 3D L/R side by side output
189 MS_BOOL bNewVSyncMode;
190 MVOP_RptFldMode eRepeatField; /// mvop output repeating fields for single field input.
191 MVOP_RgbFormat eMainRgbFmt;
192 MS_BOOL bIsInit;
193 MS_BOOL bRptPreVsync;
194 MS_BOOL bIs422;
195 MS_BOOL bIsH265;
196 MS_BOOL bIsHS;
197 MS_U16 u16CropXStart;
198 MS_U16 u16CropYStart;
199 MS_U16 u16CropXSize;
200 MS_U16 u16CropYSize;
201 MS_BOOL bIsSetCrop;
202 MS_BOOL bIsXcTrig;
203 MS_U32 u32MVOPFixClk;
204 MS_BOOL bIsEnable;
205 MS_BOOL bIs2p;
206 MVOP_OutputImodeType eInterlaceType;
207 MS_U16 u16ECONum;
208 MS_BOOL bDramRdContd;
209 MS_BOOL bIsEnLSB;
210 MS_BOOL bIsMCUMfdec;
211 MS_U8 u8LumaMIU;
212 MS_U8 u8ChromaMIU;
213 #if MVOP_SUPPORT_SUB
214 MS_BOOL bSubMirrorModeVer;
215 MS_BOOL bSubMirrorModeHor;
216 MS_BOOL bSubMirrorMode;
217 MS_BOOL bSubEnableFreerunMode;
218 MS_BOOL bSub3DLRMode;
219 MS_BOOL bSubNewVSyncMode;
220 MVOP_RptFldMode eSubRepeatField; /// mvop output repeating fields for single field input.
221 MVOP_RgbFormat eSubRgbFmt;
222 MS_BOOL bSubIsInit;
223 MS_BOOL bSubRptPreVsync;
224 MS_BOOL bSubIs422;
225 MS_BOOL bSubIsH265;
226 MS_BOOL bSub3DLRAltOutput; /// 3D L/R line alternative output
227 MS_BOOL bSub3DLRAltSBSOutput;
228 MS_BOOL bSubIsHS;
229 MS_U16 u16SubCropXStart;
230 MS_U16 u16SubCropYStart;
231 MS_U16 u16SubCropXSize;
232 MS_U16 u16SubCropYSize;
233 MS_BOOL bSubIsSetCrop;
234 MS_BOOL bSubIsXcTrig;
235 MS_U32 u32SubMVOPFixClk;
236 MS_BOOL bIsSubEnable;
237 MS_BOOL bSubIs2p;
238 MVOP_OutputImodeType eSubInterlaceType;
239 MS_BOOL bSubDramRdContd;
240 MS_BOOL bSubIsEnLSB;
241 MS_BOOL bSubIsMCUMfdec;
242 MS_U8 u8SubLumaMIU;
243 MS_U8 u8SubChromaMIU;
244 #endif
245 }MVOP_CTX_HAL;
246
247 static MVOP_CTX_HAL *g_pHalMVOPCtx = NULL;
248 static MS_VIRT u32RiuBaseAdd=0;
249
250 #ifndef MSOS_TYPE_LINUX
251 MVOP_CTX_HAL g_stmvopHalCtx;
252 #endif
253 #define RIU_MAP u32RiuBaseAdd //obtained in init
254
255 #define RIU8 ((unsigned char volatile *) RIU_MAP)
256 #define RIU16 ((MS_U16 volatile *) RIU_MAP)
257 #define MST_MACRO_START do {
258 #define MST_MACRO_END } while (0)
259
260 #define HAL_WriteByte( u32Reg, u8Val ) \
261 MST_MACRO_START \
262 if ( __builtin_constant_p( u32Reg ) ) \
263 { \
264 RIU8[((u32Reg) * 2) - ((u32Reg) & 1)] = u8Val; \
265 } \
266 else \
267 { \
268 RIU8[(u32Reg << 1) - (u32Reg & 1)] = u8Val; \
269 } \
270 MST_MACRO_END
271
272 #define HAL_ReadByte( u32Reg ) \
273 (__builtin_constant_p( u32Reg ) ? \
274 (((u32Reg) & 0x01) ? RIU8[(u32Reg) * 2 - 1] : RIU8[(u32Reg) * 2]) : \
275 (RIU8[(u32Reg << 1) - (u32Reg & 1)]))
276
277 #define HAL_Read2Byte( u32Reg ) \
278 (RIU16[u32Reg])
279
280 #define HAL_ReadRegBit( u32Reg, u8Mask ) \
281 (RIU8[(u32Reg) * 2 - ((u32Reg) & 1)] & (u8Mask))
282
283 #define HAL_WriteRegBit( u32Reg, bEnable, u8Mask ) \
284 MST_MACRO_START \
285 MS_U32 u32Reg8 = ((u32Reg) * 2) - ((u32Reg) & 1); \
286 RIU8[u32Reg8] = (bEnable) ? (RIU8[u32Reg8] | (u8Mask)) : \
287 (RIU8[u32Reg8] & ~(u8Mask)); \
288 MST_MACRO_END
289
290 #define HAL_WriteByteMask( u32Reg, u8Val, u8Msk ) \
291 MST_MACRO_START \
292 MS_U32 u32Reg8 = ((u32Reg) * 2) - ((u32Reg) & 1); \
293 RIU8[u32Reg8] = (RIU8[u32Reg8] & ~(u8Msk)) | ((u8Val) & (u8Msk)); \
294 MST_MACRO_END
295
296 #define HAL_Write2Byte(u32Reg, u16Val) \
297 RIU16[u32Reg] = u16Val;
298
299 #define HAL_Write2ByteMask( u32Reg, u16Val, u16Msk ) \
300 MST_MACRO_START \
301 RIU16[u32Reg] = (RIU16[u32Reg] & ~(u16Msk)) | ((u16Val) & (u16Msk)); \
302 MST_MACRO_END
303 #define SUB_REG(x) (x-MVOP_REG_BASE+MVOP_SUB_REG_BASE)
304
305 #define _FUNC_NOT_USED() do {} while ( 0 )
306 #ifndef UNUSED
307 #define UNUSED(x) (void)(x)
308 #endif
309
310 #define LOWBYTE(u16) ((MS_U8)(u16))
311 #define HIGHBYTE(u16) ((MS_U8)((u16) >> 8))
312
313
314 #define VOP_ON_MIU1 ((HAL_ReadByte(0x12F9) & BIT2) == BIT2)
315 #define _MaskMiuReq_MVOP_R( m ) HAL_WriteRegBit(0x12C7, m, BIT2)
316 #define _MaskMiu1Req_MVOP_R( m ) HAL_WriteRegBit(0x06C7, m, BIT2)
317
318 #define HAL_MIU_SetReqMask( miu_clients, mask ) \
319 do { \
320 if (VOP_ON_MIU1 == 0) \
321 _MaskMiuReq_##miu_clients( mask ); \
322 else \
323 _MaskMiu1Req_##miu_clients( mask ); \
324 }while(0)
325
326 #define SUBVOP_ON_MIU1 ((HAL_ReadByte(0x12F9) & BIT2) == BIT2)
327 #define _MaskMiuReq_SUBMVOP_R( m ) HAL_WriteRegBit(0x12C7, m, BIT2)
328 #define _MaskMiu1Req_SUBMVOP_R( m ) HAL_WriteRegBit(0x06C7, m, BIT2)
329
330 #define HAL_MIU_SubSetReqMask( miu_clients, mask ) \
331 do { \
332 if (SUBVOP_ON_MIU1 == 0) \
333 _MaskMiuReq_##miu_clients( mask ); \
334 else \
335 _MaskMiu1Req_##miu_clients( mask ); \
336 }while(0)
337
338 #define MVOP_DBG_ENABLE 0
339 #if MVOP_DBG_ENABLE
340 #define MVOP_DBG(fmt, args...) MVOP_PRINTF(fmt, ##args)
341 #else
342 #define MVOP_DBG(fmt, args...) {}
343 #endif
344
345 typedef enum
346 {
347 E_MVOP_INIT_OK = 0,
348 E_MVOP_INIT_FAIL = 1,
349 E_MVOP_INIT_ALREADY_EXIST = 2
350 } MVOP_HalInitCtxResults;
351 //-------------------------------------------------------------------------------------------------
352 // Local Structures
353 //-------------------------------------------------------------------------------------------------
354
355
356 //-------------------------------------------------------------------------------------------------
357 // Global Variables
358 //-------------------------------------------------------------------------------------------------
359
360 #define Y_INFO 0
361 #define UV_INFO 1
362
363 //-------------------------------------------------------------------------------------------------
364 // Local Variables
365 //-------------------------------------------------------------------------------------------------
366
367
368 //-------------------------------------------------------------------------------------------------
369 // Debug Functions
370 //-------------------------------------------------------------------------------------------------
371
372
373 //-------------------------------------------------------------------------------------------------
374 // Local Functions
375 //-------------------------------------------------------------------------------------------------
376
377
378 //-------------------------------------------------------------------------------------------------
379 // Global Functions
380 //-------------------------------------------------------------------------------------------------
381
_HAL_MVOP_InitVarCtx(void)382 void _HAL_MVOP_InitVarCtx(void)
383 {
384 g_pHalMVOPCtx->bMirrorModeVer = 0;
385 g_pHalMVOPCtx->bMirrorModeHor = 0;
386 g_pHalMVOPCtx->bMirrorMode=0;
387 g_pHalMVOPCtx->bEnableFreerunMode = FALSE;
388 g_pHalMVOPCtx->b3DLRMode=0; /// 3D L/R dual buffer mode
389 g_pHalMVOPCtx->b3DLRAltOutput = FALSE; /// 3D L/R line alternative output
390 g_pHalMVOPCtx->b3DLRAltSBSOutput = FALSE;
391 g_pHalMVOPCtx->bNewVSyncMode = FALSE;
392 g_pHalMVOPCtx->eRepeatField = E_MVOP_RPTFLD_NONE; /// mvop output repeating fields for single field input.
393 g_pHalMVOPCtx->eMainRgbFmt = E_MVOP_RGB_NONE;
394 g_pHalMVOPCtx->bIsInit = 0;
395 g_pHalMVOPCtx->bRptPreVsync = 0;
396 g_pHalMVOPCtx->bIs422 = 0;
397 g_pHalMVOPCtx->bIsH265 = 0;
398 g_pHalMVOPCtx->bIsHS = FALSE;
399 g_pHalMVOPCtx->u16CropXStart = 0;
400 g_pHalMVOPCtx->u16CropYStart = 0;
401 g_pHalMVOPCtx->u16CropXSize = 0;
402 g_pHalMVOPCtx->u16CropYSize = 0;
403 g_pHalMVOPCtx->bIsSetCrop = FALSE;
404 g_pHalMVOPCtx->bIsXcTrig = TRUE;
405 g_pHalMVOPCtx->u32MVOPFixClk = 0;
406 g_pHalMVOPCtx->bIsEnable = 0;
407 g_pHalMVOPCtx->bIs2p = 0;
408 g_pHalMVOPCtx->eInterlaceType = E_MVOP_PRO;
409 g_pHalMVOPCtx->u16ECONum = 0;
410 g_pHalMVOPCtx->u8LumaMIU = 0;
411 g_pHalMVOPCtx->u8SubChromaMIU = 0;
412 }
413
_HAL_MVOP_SubInitVarCtx(void)414 void _HAL_MVOP_SubInitVarCtx(void)
415 {
416 #if MVOP_SUPPORT_SUB
417 g_pHalMVOPCtx->bSubMirrorModeVer = 0;
418 g_pHalMVOPCtx->bSubMirrorModeHor = 0;
419 g_pHalMVOPCtx->bSubMirrorMode=0;
420 g_pHalMVOPCtx->bSubEnableFreerunMode = FALSE;
421 g_pHalMVOPCtx->bSub3DLRMode=0;
422 g_pHalMVOPCtx->bSubNewVSyncMode = FALSE;
423 g_pHalMVOPCtx->eSubRepeatField = E_MVOP_RPTFLD_NONE; /// mvop output repeating fields for single field input.
424 g_pHalMVOPCtx->eSubRgbFmt = E_MVOP_RGB_NONE;
425 g_pHalMVOPCtx->bSubIsInit = 0;
426 g_pHalMVOPCtx->bSubRptPreVsync = 0;
427 g_pHalMVOPCtx->bSubIs422 = 0;
428 g_pHalMVOPCtx->bSubIsH265 = 0;
429 g_pHalMVOPCtx->bSub3DLRAltOutput = FALSE; /// 3D L/R line alternative output
430 g_pHalMVOPCtx->bSub3DLRAltSBSOutput = FALSE;
431 g_pHalMVOPCtx->bSubIsHS = FALSE;
432 g_pHalMVOPCtx->u16SubCropXStart = 0;
433 g_pHalMVOPCtx->u16SubCropYStart = 0;
434 g_pHalMVOPCtx->u16SubCropXSize = 0;
435 g_pHalMVOPCtx->u16SubCropYSize = 0;
436 g_pHalMVOPCtx->bSubIsSetCrop = FALSE;
437 g_pHalMVOPCtx->bSubIsXcTrig = TRUE;
438 g_pHalMVOPCtx->u32SubMVOPFixClk = 0;
439 g_pHalMVOPCtx->bIsSubEnable = 0;
440 g_pHalMVOPCtx->bSubIs2p = 0;
441 g_pHalMVOPCtx->eSubInterlaceType = E_MVOP_PRO;
442 g_pHalMVOPCtx->u8SubLumaMIU = 0;
443 g_pHalMVOPCtx->u8SubChromaMIU = 0;
444 #endif
445 }
446
_HAL_MVOP_InitContext(MS_BOOL * pbFirstDrvInstant)447 MVOP_HalInitCtxResults _HAL_MVOP_InitContext(MS_BOOL *pbFirstDrvInstant)
448 {
449 MS_BOOL bNeedInitShared = FALSE;
450
451 //check first init by MsOS_SHM_GetId / MSOS_SHM_QUERY
452 #if 0
453 if (g_pHalMVOPCtx)
454 {
455 // The context instance has been created already
456 // before somewhere sometime in the same process.
457 *pbFirstDrvInstant = bNeedInitShared;
458 //return E_MVOP_INIT_FAIL;
459 return E_MVOP_INIT_OK;
460 }
461 #endif
462
463 #if defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_LINUX_KERNEL)
464 MS_U32 u32ShmId;
465 MS_VIRT u32Addr;
466 MS_U32 u32BufSize;
467
468 //MsOS_SHM_Init(); init in msos_init
469 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux MVOP HAL driver", sizeof(MVOP_CTX_HAL), &u32ShmId, &u32Addr, &u32BufSize, MSOS_SHM_QUERY))
470 {
471 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux MVOP HAL driver", sizeof(MVOP_CTX_HAL), &u32ShmId, &u32Addr, &u32BufSize, MSOS_SHM_CREATE))
472 {
473 MVOP_DBG(MVOP_PRINTF("MVOP: SHM allocation failed!\n");)
474 return E_MVOP_INIT_FAIL;
475 }
476 MVOP_DBG(MVOP_PRINTF("MVOP: [%s][%d] This is first initial 0x%08lx\n", __FUNCTION__, __LINE__, u32Addr);)
477 memset( (MS_U8*)u32Addr, 0, sizeof(MVOP_CTX_HAL));
478 bNeedInitShared = TRUE;
479 g_pHalMVOPCtx = (MVOP_CTX_HAL*)u32Addr;
480 _HAL_MVOP_InitVarCtx();
481 #if MVOP_SUPPORT_SUB
482 _HAL_MVOP_SubInitVarCtx();
483 #endif
484 }
485 else
486 {
487 g_pHalMVOPCtx = (MVOP_CTX_HAL*)u32Addr;
488 bNeedInitShared = FALSE;
489 *pbFirstDrvInstant = bNeedInitShared;
490
491 return E_MVOP_INIT_ALREADY_EXIST;
492 }
493 #else
494 g_pHalMVOPCtx = &g_stmvopHalCtx;
495 bNeedInitShared = TRUE;
496 #endif
497 *pbFirstDrvInstant = bNeedInitShared;
498
499 if (bNeedInitShared)
500 {
501 memset(g_pHalMVOPCtx, 0, sizeof(*g_pHalMVOPCtx));
502 }
503
504 return E_MVOP_INIT_OK;
505 }
506
_HAL_MVOP_IsSupport4k2k2P(void)507 MS_BOOL _HAL_MVOP_IsSupport4k2k2P(void)
508 {
509 return TRUE;
510 }
511
HAL_MVOP_RegSetBase(MS_VIRT u32Base)512 void HAL_MVOP_RegSetBase(MS_VIRT u32Base)
513 {
514 u32RiuBaseAdd = u32Base;
515 }
516
HAL_MVOP_InitMirrorMode(MS_BOOL bMir)517 void HAL_MVOP_InitMirrorMode(MS_BOOL bMir)
518 {
519 //set bit[3:7] to support mirror mode
520 HAL_WriteRegBit(VOP_MIRROR_CFG, bMir, VOP_MIRROR_CFG_ENABLE);
521 }
522
HAL_MVOP_SetVerticalMirrorMode(MS_BOOL bEnable)523 void HAL_MVOP_SetVerticalMirrorMode(MS_BOOL bEnable)
524 {
525 if (g_pHalMVOPCtx == NULL)
526 {
527 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
528 return;
529 }
530
531 if (VOP_MIRROR_CFG_ENABLE != HAL_ReadRegBit(VOP_MIRROR_CFG, VOP_MIRROR_CFG_ENABLE))
532 {
533 //MVOP_PRINTF("Setup mirror mode\n");
534 HAL_MVOP_InitMirrorMode(TRUE);
535 }
536
537 HAL_WriteRegBit(VOP_MIRROR_CFG, bEnable, VOP_MIRROR_CFG_VEN);
538 g_pHalMVOPCtx->bMirrorModeVer = bEnable;
539 }
540
HAL_MVOP_SetHorizontallMirrorMode(MS_BOOL bEnable)541 void HAL_MVOP_SetHorizontallMirrorMode(MS_BOOL bEnable)
542 {
543 if (g_pHalMVOPCtx == NULL)
544 {
545 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
546 return;
547 }
548
549 if (VOP_MIRROR_CFG_ENABLE != HAL_ReadRegBit(VOP_MIRROR_CFG, VOP_MIRROR_CFG_ENABLE))
550 {
551 //MVOP_PRINTF("Setup mirror mode\n");
552 HAL_MVOP_InitMirrorMode(TRUE);
553 }
554
555 HAL_WriteRegBit(VOP_MIRROR_CFG, bEnable, VOP_MIRROR_CFG_HEN);
556 g_pHalMVOPCtx->bMirrorModeHor = bEnable;
557 }
558
HAL_MVOP_Init(void)559 void HAL_MVOP_Init(void)
560 {
561 MVOP_HalInitCtxResults eRet;
562 MS_BOOL pbFirstDrvInstant;
563
564 eRet = _HAL_MVOP_InitContext(&pbFirstDrvInstant);
565 if(eRet == E_MVOP_INIT_FAIL)
566 {
567 MVOP_DBG(MVOP_PRINTF("[%s] MVOP Context Init failed!\n",__FUNCTION__);)
568 return;
569 }
570 else if(eRet == E_MVOP_INIT_ALREADY_EXIST)
571 {
572 if(g_pHalMVOPCtx->bIsInit)
573 {
574 MVOP_DBG(MVOP_PRINTF("[%s] Main MVOP Context has Initialized!\n",__FUNCTION__);)
575 return;
576 }
577 }
578
579 HAL_MVOP_InitMirrorMode(TRUE);
580 //Enable dynamic clock gating
581 //Note: cannot enable VOP_GCLK_VCLK_ON, or hsync cannot be sent out.
582 HAL_WriteByteMask(VOP_GCLK, VOP_GCLK_MIU_ON, VOP_GCLK_MIU_ON|VOP_GCLK_VCLK_ON);
583 g_pHalMVOPCtx->bIsInit = 1;
584 }
585
HAL_MVOP_SetFieldInverse(MS_BOOL b2MVD,MS_BOOL b2IP)586 void HAL_MVOP_SetFieldInverse(MS_BOOL b2MVD, MS_BOOL b2IP)
587 {
588 // Set fld inv & ofld_inv
589 HAL_WriteRegBit(VOP_CTRL0+1, b2MVD, BIT3); //inverse the field to MVD
590 HAL_WriteRegBit(VOP_CTRL0+1, b2IP, BIT4); //inverse the field to IP
591 }
592
HAL_MVOP_SetChromaWeighting(MS_BOOL bEnable)593 void HAL_MVOP_SetChromaWeighting(MS_BOOL bEnable)
594 {
595 HAL_WriteRegBit(VOP_REG_WEIGHT_CTRL, bEnable, BIT1);
596 }
597
598 //load new value into active registers 0x20-0x26
HAL_MVOP_LoadReg(void)599 void HAL_MVOP_LoadReg(void)
600 {
601 HAL_WriteRegBit(VOP_REG_WR, 1, BIT0);
602 HAL_WriteRegBit(VOP_REG_WR, 0, BIT0);
603
604 HAL_WriteRegBit(VOP_REG_WR, 1, BIT4);
605 HAL_WriteRegBit(VOP_REG_WR, 0, BIT4);
606 }
607
608
HAL_MVOP_SetMIUReqMask(MS_BOOL bEnable)609 void HAL_MVOP_SetMIUReqMask(MS_BOOL bEnable)
610 {
611 #if 0 //[FIXME]
612 if (bEnable)
613 { // mask MVOP2MI to protect MIU
614 HAL_MIU_SetReqMask(MVOP_R, 1);
615 MsOS_DelayTask(1);
616 }
617 else
618 { // unmask MVOP2MI
619 MsOS_DelayTask(1);
620 HAL_MIU_SetReqMask(MVOP_R, 0);
621 }
622 #endif
623 MS_U8 u8Miu;
624
625 if(HAL_MVOP_GetIsOnlyMiuIPControl() == TRUE)
626 {
627 // mask msb mvop
628 u8Miu = (HAL_ReadByte(VOP_MIU_SEL) & VOP_MSB_BUF0_MIU_SEL) >> 4;
629 }
630 else
631 {
632 u8Miu = VOP_ON_MIU1;
633 }
634 eMIUClientID eClientID = MIU_CLIENT_MVOP_128BIT_R;
635 //MVOP_PRINTF("Enter %s bEnable=%x ReqMask=0x%x, 0x%x\n", __FUNCTION__, bEnable,
636 // HAL_ReadByte(0x1266), HAL_ReadByte(0x0666));
637 if (bEnable)
638 { // mask MVOP2MI to protect MIU
639 MDrv_MIU_MaskReq(u8Miu,eClientID);
640 MsOS_DelayTask(1);
641 }
642 else
643 { // unmask MVOP2MI
644 MsOS_DelayTask(1);
645 MDrv_MIU_UnMaskReq(u8Miu,eClientID);
646 }
647
648 //MVOP_PRINTF(">Exit %s bEnable=%x ReqMask=0x%x, 0x%x\n", __FUNCTION__, bEnable,
649 // HAL_ReadByte(0x1266), HAL_ReadByte(0x0666));
650 }
651
HAL_MVOP_Rst(void)652 void HAL_MVOP_Rst(void)
653 {
654 HAL_WriteRegBit(VOP_CTRL0, 0, BIT0);
655 HAL_WriteRegBit(VOP_CTRL0, 1, BIT0);
656
657 HAL_WriteRegBit(VOP_CTRL0, 0, BIT4);
658 HAL_WriteRegBit(VOP_CTRL0, 1, BIT4);
659
660 g_pHalMVOPCtx->bIsEnable = 1;
661 }
662
HAL_MVOP_Enable(MS_BOOL bEnable,MS_U8 u8Framerate)663 void HAL_MVOP_Enable(MS_BOOL bEnable, MS_U8 u8Framerate)
664 {
665 MS_U8 regval;
666
667 regval = HAL_ReadByte(VOP_CTRL0);
668
669 if ( bEnable )
670 {
671 regval |= 0x1;
672 }
673 else
674 {
675 regval &= ~0x1;
676 }
677
678 g_pHalMVOPCtx->bIsEnable = bEnable;
679
680 HAL_WriteByte(VOP_CTRL0, regval);
681 }
682
HAL_MVOP_GetEnableState(void)683 MS_BOOL HAL_MVOP_GetEnableState(void)
684 {
685 return (HAL_ReadRegBit(VOP_CTRL0, BIT0));
686 }
687
HAL_MVOP_GetMaxFreerunClk(void)688 HALMVOPFREQUENCY HAL_MVOP_GetMaxFreerunClk(void)
689 {
690 return HALMVOP_160MHZ;
691 }
692
HAL_MVOP_Get4k2kClk(void)693 HALMVOPFREQUENCY HAL_MVOP_Get4k2kClk(void)
694 {
695 return HALMVOP_320MHZ;
696 }
697
HAL_MVOP_SetFrequency(HALMVOPFREQUENCY enFrequency)698 void HAL_MVOP_SetFrequency(HALMVOPFREQUENCY enFrequency)
699 {
700 // clear
701 HAL_WriteByteMask(REG_CKG_DC0, 0, CKG_DC0_MASK);
702 switch(enFrequency)
703 {
704 case HALMVOP_SYNCMODE:
705 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK);
706 break;
707 case HALMVOP_FREERUNMODE:
708 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_FREERUN, CKG_DC0_MASK);
709 break;
710 case HALMVOP_320MHZ:
711 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_320MHZ, CKG_DC0_MASK);
712 break;
713 case HALMVOP_108MHZ:
714 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_108MHZ, CKG_DC0_MASK);
715 break;
716 case HALMVOP_123MHZ:
717 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_123MHZ, CKG_DC0_MASK);
718 break;
719 case HALMVOP_144MHZ:
720 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_144MHZ, CKG_DC0_MASK);
721 break;
722 case HALMVOP_160MHZ:
723 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK);
724 break;
725 case HALMVOP_192MHZ:
726 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_192MHZ, CKG_DC0_MASK);
727 break;
728 default:
729 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK);
730 MVOP_PRINTF("Attention! In HAL_MVOP_SetFrequency default 160MHz!\n");
731 break;
732 }
733 }
734
HAL_MVOP_GetMaximumClk(void)735 HALMVOPFREQUENCY HAL_MVOP_GetMaximumClk(void)
736 {
737 return HALMVOP_320MHZ;
738 }
739
HAL_MVOP_GetCurrentClk(void)740 HALMVOPFREQUENCY HAL_MVOP_GetCurrentClk(void)
741 {
742 MS_U8 u8DC0Clk;
743 HALMVOPFREQUENCY mvopFreq;
744
745 u8DC0Clk = HAL_ReadByte(REG_CKG_DC0)&CKG_DC0_MASK;
746
747 switch(u8DC0Clk)
748 {
749 case CKG_DC0_SYNCHRONOUS:
750 mvopFreq = HALMVOP_SYNCMODE;
751 break;
752 case CKG_DC0_FREERUN:
753 mvopFreq = HALMVOP_FREERUNMODE;
754 break;
755 case CKG_DC0_144MHZ:
756 mvopFreq = HALMVOP_144MHZ;
757 break;
758 case CKG_DC0_160MHZ:
759 mvopFreq = HALMVOP_160MHZ;
760 break;
761 case CKG_DC0_320MHZ:
762 mvopFreq = HALMVOP_320MHZ;
763 break;
764 default:
765 mvopFreq = 0;
766 break;
767 }
768 return mvopFreq;
769 }
770
HAL_MVOP_SetOutputInterlace(MS_BOOL bEnable,MS_U16 u16ECOVersion)771 void HAL_MVOP_SetOutputInterlace(MS_BOOL bEnable, MS_U16 u16ECOVersion)
772 {
773 MS_U8 regval;
774
775 regval = HAL_ReadByte(VOP_CTRL0);
776
777 if ( bEnable )
778 {
779 regval |= 0x80;
780 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
781 if(u16ECOVersion == 0)
782 {
783 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x4, CKG_DC0_SRAM);//Dc0 enable & dc0_mfdec_en =0 57[3:0]= 0x4, others 57[3:0]=0x0
784 }
785 }
786 else
787 {
788 regval &= ~0x80;
789 }
790 //Kano patch for GOP
791 HAL_WriteRegBit(VOP_TST_IMG, bEnable, VOP_SC_VS_INV);
792 HAL_WriteByte(VOP_CTRL0, regval);
793 }
794
HAL_MVOP_SetPattern(MVOP_Pattern enMVOPPattern)795 void HAL_MVOP_SetPattern(MVOP_Pattern enMVOPPattern)
796 {
797 HAL_WriteByteMask(VOP_TST_IMG, enMVOPPattern, BIT2 | BIT1 | BIT0);
798 }
799
HAL_MVOP_SetTileFormat(MVOP_TileFormat eTileFmt)800 MS_BOOL HAL_MVOP_SetTileFormat(MVOP_TileFormat eTileFmt)
801 {
802 if (eTileFmt == E_MVOP_TILE_8x32)
803 {
804 HAL_WriteRegBit(VOP_REG_WR, 0, BIT1);
805 return TRUE;
806 }
807 else if (eTileFmt == E_MVOP_TILE_16x32)
808 {
809 HAL_WriteRegBit(VOP_REG_WR, 1, BIT1);
810 return TRUE;
811 }
812 else if (eTileFmt == E_MVOP_TILE_32x16)
813 {
814 HAL_WriteRegBit(VOP_REG_WR, 0, BIT1);
815 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 1, EVD_ENABLE);
816 return TRUE;
817 }
818 else if (eTileFmt == E_MVOP_TILE_32x32)
819 {
820 HAL_WriteRegBit(VOP_REG_WR, 0, BIT1);
821 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, EVD_ENABLE);
822 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 1, VOP_TILE_32x32);
823 return TRUE;
824 }
825 else
826 {
827 return FALSE;
828 }
829 }
830
HAL_MVOP_GetSupportRgbFormat(MVOP_RgbFormat eRgbFmt)831 MS_BOOL HAL_MVOP_GetSupportRgbFormat(MVOP_RgbFormat eRgbFmt)
832 {
833 if ((eRgbFmt == E_MVOP_RGB_565) || (eRgbFmt == E_MVOP_RGB_888))
834 {
835 return TRUE;
836 }
837 return FALSE;
838 }
839
HAL_MVOP_SetRgbFormat(MVOP_RgbFormat eRgbFmt)840 MS_BOOL HAL_MVOP_SetRgbFormat(MVOP_RgbFormat eRgbFmt)
841 {
842 MS_BOOL bRet = FALSE;
843
844 if (g_pHalMVOPCtx == NULL)
845 {
846 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
847 return FALSE;
848 }
849
850 if (eRgbFmt == E_MVOP_RGB_NONE)
851 {
852 HAL_WriteByteMask(VOP_RGB_FMT, 0, VOP_RGB_FMT_SEL);
853 bRet = TRUE;
854 }
855 else if (eRgbFmt == E_MVOP_RGB_565)
856 {
857 HAL_WriteByteMask(VOP_RGB_FMT, VOP_RGB_FMT_565, VOP_RGB_FMT_SEL);
858 bRet = TRUE;
859 }
860 else if (eRgbFmt == E_MVOP_RGB_888)
861 {
862 HAL_WriteByteMask(VOP_RGB_FMT, VOP_RGB_FMT_888, VOP_RGB_FMT_SEL);
863 bRet = TRUE;
864 }
865
866 if (bRet == TRUE)
867 {
868 g_pHalMVOPCtx->eMainRgbFmt = eRgbFmt;
869 }
870 return bRet;
871 }
872
HAL_MVOP_SetBlackBG(void)873 void HAL_MVOP_SetBlackBG(void)
874 {
875 MS_U8 regval;
876
877 //set MVOP test pattern to black
878 HAL_WriteByte((VOP_TST_IMG + 1), 0x10);
879 HAL_WriteByte(VOP_U_PAT , 0x80);
880 HAL_WriteByte((VOP_U_PAT + 1), 0x80);
881
882 regval = HAL_ReadByte(VOP_TST_IMG);
883 HAL_WriteByteMask(VOP_TST_IMG, 0x02, BIT2 | BIT1 | BIT0);
884 HAL_WriteByteMask(VOP_TST_IMG, 0x00, BIT2 | BIT1 | BIT0);
885 HAL_WriteByteMask(VOP_TST_IMG, regval, BIT2 | BIT1 | BIT0);
886 }
887
HAL_MVOP_SetCropWindow(MVOP_InputCfg * pparam)888 void HAL_MVOP_SetCropWindow(MVOP_InputCfg *pparam)
889 {
890 #if 1
891 UNUSED(pparam);
892 #else // enable it when test code is ready
893 MS_U32 x, y;
894 MS_U32 u32offset;
895
896 if(!pparam)
897 {
898 return;
899 }
900 //set MVOP test pattern to black
901 HAL_MVOP_SetBlackBG();
902 #if 0
903 if((pparam->enVideoType == MVOP_H264) && (pparam->u16StripSize == 1920))
904 {
905 pparam->u16StripSize = 1952;
906 }
907 #endif
908 if((pparam->enVideoType == MVOP_MPG) || (pparam->enVideoType == MVOP_MPEG4))
909 {
910 pparam->u16CropX = (pparam->u16CropX >> 3) << 3; // 8 bytes align
911 pparam->u16CropY = (pparam->u16CropY >> 6) << 6; // 64 bytes align
912 }
913 else if((pparam->enVideoType == MVOP_H264) || (pparam->enVideoType == MVOP_RM))
914 {
915 pparam->u16CropX = (pparam->u16CropX >> 4) << 4; // 16 bytes align
916 pparam->u16CropY = (pparam->u16CropY >> 6) << 6; // 64 bytes align
917 }
918 else
919 {
920 MS_ASSERT(0);
921 }
922
923 x = (MS_U32)pparam->u16CropX;
924 y = (MS_U32)pparam->u16CropY;
925
926 // y offset
927 u32offset = ((y * pparam->u16StripSize + (x << 5)) >> 3);
928 HAL_WriteByte((VOP_JPG_YSTR0_L ), (MS_U8)(u32offset));
929 HAL_WriteByte((VOP_JPG_YSTR0_L + 1), (MS_U8)(u32offset >> 8));
930 HAL_WriteByte((VOP_JPG_YSTR0_H ), (MS_U8)(u32offset >> 16));
931 HAL_WriteByte((VOP_JPG_YSTR0_H + 1), (MS_U8)((u32offset >> 24) & VOP_YUV_STR_HIBITS));
932
933 // uv offset
934 u32offset = ((y >> 1) * pparam->u16StripSize + (x << 5)) >> 3;
935 HAL_WriteByte((VOP_JPG_UVSTR0_L ), (MS_U8)(u32offset));
936 HAL_WriteByte((VOP_JPG_UVSTR0_L + 1), (MS_U8)(u32offset >> 8));
937 HAL_WriteByte((VOP_JPG_UVSTR0_H ), (MS_U8)(u32offset >> 16));
938 HAL_WriteByte((VOP_JPG_UVSTR0_H + 1), (MS_U8)((u32offset >> 24) & VOP_YUV_STR_HIBITS));
939
940 pparam->u16CropWidth= (pparam->u16CropWidth >> 3) << 3;
941 // HSize, VSize
942 HAL_WriteByte((VOP_JPG_HSIZE ), LOWBYTE(pparam->u16CropWidth ));
943 HAL_WriteByte((VOP_JPG_HSIZE + 1), HIGHBYTE(pparam->u16CropWidth ));
944 HAL_WriteByte((VOP_JPG_VSIZE ), LOWBYTE(pparam->u16CropHeight));
945 HAL_WriteByte((VOP_JPG_VSIZE + 1), HIGHBYTE(pparam->u16CropHeight ));
946
947 HAL_WriteByteMask(VOP_MPG_JPG_SWITCH, BIT0, BIT1|BIT0);
948
949 // clear extend strip len bit by default
950 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
951 if((pparam->enVideoType == MVOP_MPG) || (pparam->enVideoType == MVOP_MPEG4))
952 {
953 // Disable H264 or RM Input
954 HAL_WriteRegBit(VOP_INPUT_SWITCH1, 0, BIT2|BIT3);
955 //8*32 tile format
956 HAL_WriteRegBit(VOP_REG_WR, 0, BIT1);
957 }
958 else if((pparam->enVideoType == MVOP_H264) || (pparam->enVideoType == MVOP_RM))
959 {
960 //16*32 tile format
961 HAL_WriteRegBit(VOP_REG_WR, 1, BIT1);
962 // SVD mode enable
963 HAL_WriteByteMask(VOP_INPUT_SWITCH1, BIT3, BIT2|BIT3);
964 // set mvop to 64bit interface
965 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
966 }
967 HAL_MVOP_LoadReg();
968 #endif
969 }
970
HAL_MVOP_SetRepeatField(MVOP_RptFldMode eMode)971 void HAL_MVOP_SetRepeatField(MVOP_RptFldMode eMode)
972 {
973 if (g_pHalMVOPCtx == NULL)
974 {
975 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
976 return;
977 }
978 g_pHalMVOPCtx->eRepeatField = eMode;
979 }
980
HAL_MVOP_SetFDMaskFromMVD(MS_BOOL bEnable)981 void HAL_MVOP_SetFDMaskFromMVD(MS_BOOL bEnable)
982 {
983 HAL_WriteRegBit(VOP_REG_FD_MASK_SEL, bEnable, BIT5); //FD MASK from MVD
984 }
985
HAL_MVOP_SetInputMode(VOPINPUTMODE mode,MVOP_InputCfg * pparam,MS_U16 u16ECOVersion)986 void HAL_MVOP_SetInputMode( VOPINPUTMODE mode, MVOP_InputCfg *pparam, MS_U16 u16ECOVersion)
987 {
988 MS_U8 regval;
989 MS_U16 u16strip, u16strip_lsb;
990
991 if (g_pHalMVOPCtx == NULL)
992 {
993 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
994 return;
995 }
996 #if 0
997 /*****************************************************/
998 // Reset MVOP setting
999 HAL_WriteByte(VOP_TST_IMG, 0x40); //reset test pattern or BG
1000 HAL_MVOP_Set3DLRAltOutput_VHalfScaling(DISABLE); //reset to default: disable 3D L/R alternative output.
1001 HAL_MVOP_Set3DLR2ndCfg(DISABLE); //reset to default: disable 3D L/R 2nd pitch.
1002 HAL_MVOP_SetRgbFormat(E_MVOP_RGB_NONE); //reset rgb format
1003 HAL_WriteRegBit(VOP_CTRL1, 0, VOP_MVD_VS_MD); //default use original vsync
1004 //stb series
1005 HAL_WriteRegBit(VOP_REG_422_OUT_EN, 1, BIT0);
1006 HAL_WriteRegBit(VOP_HANDSHAKE, 1, VOP_HANDSHAKE_MODE);
1007 HAL_MVOP_SetTimingFromXC(E_MVOP_DEV_0, TRUE);
1008
1009 //set MVOP test pattern to black
1010 HAL_MVOP_SetBlackBG();
1011
1012 // clear extend strip len bit by default
1013 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
1014
1015 // set mvop to 128bit_i128 interface
1016 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
1017
1018 // Disable H264 or RM Input
1019 HAL_WriteRegBit(VOP_INPUT_SWITCH1, 0, BIT2|BIT3);
1020 // Clear 422 Flag
1021 g_pHalMVOPCtx->bIs422 = 0;
1022 //8*32 tile format
1023 HAL_WriteRegBit(VOP_REG_WR, 0, BIT1);
1024 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD);
1025
1026 // EVD mode disable
1027 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, EVD_ENABLE);
1028 // Clear evd Flag for interlace mode setting
1029 g_pHalMVOPCtx->bIsH265 = 0;
1030 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_L, 1, BIT3);
1031 HAL_WriteRegBit(VOP_MIRROR_CFG, 1, BIT5);
1032 // EVD 10 bits disable
1033 HAL_WriteByteMask(VOP_REG_MASK, BIT1, VOP_LSB_REQ_MASK);
1034 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_Y_EN);
1035 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_UV_EN);
1036 HAL_WriteRegBit(VOP_UV_SHIFT, 1, VOP_GCLK_MIU_ON);
1037 // Disable 420 BW Saving mode
1038 HAL_WriteRegBit(VOP_REG_DUMMY, 0, VOP_420_BW_SAVE);
1039 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
1040 // Disable New Vsync Mode
1041 g_pHalMVOPCtx->bNewVSyncMode = FALSE;
1042 // Disable 2p mode
1043 HAL_MVOP_SetEnable4k2k2P(FALSE);
1044 /* only for STB DC */
1045 // Handshake mode chip need to set from MVD: Kappa (maybe fix in after project)
1046 HAL_MVOP_SetFDMaskFromMVD(ENABLE);
1047 // Use frame sync (CLK_DC1 domain) to reset CLK_DC0 and CLK_MIU domain every frame
1048 HAL_WriteRegBit(VOP_REG_FRAME_RST+1, 0, BIT7); // reg_frame_rst = 0
1049
1050 // Kappa do not need to invert DC2SC field; the inverse was setted in SC XC_BK02_33[3]=1
1051 HAL_MVOP_SetFieldInverse(ENABLE, DISABLE);
1052 // kappa U02 need to bypass field from mvd to xc for FCR.
1053 HAL_WriteRegBit(VOP_REG_DUMMY_3D_1, 1, VOP_RGB_FILED_BYPASS);
1054
1055 // Clippers temp patch: New diu interface, waiting for decoder adding diu setting.
1056 HAL_WriteByteMask(VOP_INFO_FROM_CODEC_H, 0, VOP_INFO_FROM_CODEC_MIU_BUF0_SEL | VOP_INFO_FROM_CODEC_MIU_BUF1_SEL | VOP_INFO_FROM_CODEC_10BIT);
1057
1058 //Change MIU BW Default Value to 0x241C (after Einstein)
1059 //FIFO threshold
1060 HAL_WriteByteMask(VOP_DMA0, 0x08, VOP_FORCE_HIGH|VOP_HI_TSH|VOP_BURST_EXT);
1061 //burst and priority
1062 HAL_WriteByteMask(VOP_DMA1, 0x22, VOP_FORCE_HIGH|VOP_HI_TSH|VOP_BURST_EXT);
1063 HAL_WriteByte(VOP_BURST_CTRL0, 0x02);
1064 HAL_WriteByte(VOP_BURST_CTRL1, 0x00);
1065 //// clippers crop sw patch /////
1066 HAL_WriteRegBit(VOP_REG_SINGLE_3D_L, 0, VOP_FORCE_SKIP);
1067 HAL_WriteByteMask(VOP_REG_SINGLE_3D_L, 0, VOP_SKIP_SIZE_LVIEW);
1068 HAL_WriteByteMask(VOP_REG_SINGLE_3D_H, 0, VOP_SKIP_SIZE_RVIEW);
1069 HAL_WriteRegBit(VOP_REG_ENABLE_SKIP, 0, VOP_SKIP_LVIEW);
1070 HAL_WriteRegBit(VOP_REG_ENABLE_SKIP, 0, VOP_SKIP_RVIEW);
1071 g_pHalMVOPCtx->g_u16SetStartX = 0;
1072 g_pHalMVOPCtx->g_u16SetStartY = 0;
1073 g_pHalMVOPCtx->g_u16SetXSize = 0;
1074 g_pHalMVOPCtx->g_u16SetYSize = 0;
1075 g_pHalMVOPCtx->g_bIsY4Align = FALSE;
1076 g_pHalMVOPCtx->g_bIsSetCrop = FALSE;
1077 g_pHalMVOPCtx->bIsXcTrig = FALSE;
1078 g_pHalMVOPCtx->bSubIsXcTrig = FALSE;
1079 /*****************************************************/
1080 #endif
1081
1082 //regval = HAL_ReadByte(VOP_MPG_JPG_SWITCH);
1083 regval = 0;
1084 regval |= ( mode & 0x3 );
1085
1086 if ( mode == VOPINPUT_HARDWIRE )
1087 {
1088 HAL_WriteByte(VOP_MPG_JPG_SWITCH, regval);
1089 }
1090 else if ( mode == VOPINPUT_HARDWIRECLIP )
1091 {
1092 HAL_WriteByte(VOP_MPG_JPG_SWITCH, regval);
1093
1094 // HSize, VSize
1095 HAL_WriteByte(VOP_JPG_HSIZE , LOWBYTE( pparam->u16HSize ));
1096 HAL_WriteByte((VOP_JPG_HSIZE + 1), HIGHBYTE( pparam->u16HSize ));
1097 HAL_WriteByte(VOP_JPG_VSIZE , LOWBYTE( pparam->u16VSize ));
1098 HAL_WriteByte((VOP_JPG_VSIZE + 1), HIGHBYTE( pparam->u16VSize ));
1099 }
1100 else if (mode == VOPINPUT_MCUCTRL)
1101 {
1102 g_pHalMVOPCtx->bMirrorMode = (g_pHalMVOPCtx->bMirrorModeVer||g_pHalMVOPCtx->bMirrorModeHor);
1103 if ( pparam->bProgressive )
1104 regval |= 0x4;
1105 else
1106 {
1107 regval &= ~0x4;
1108 regval |= 0x1; //reg_dc_md=b'11 for interlace input
1109 if (E_MVOP_RPTFLD_NONE == g_pHalMVOPCtx->eRepeatField)
1110 {
1111 MVOP_DBG("%s normal NOT repeat field %x\n", __FUNCTION__, g_pHalMVOPCtx->eRepeatField);
1112 //To support mcu mode interlace, need to set h'3B[9]=1,
1113 //h'11[12]=0, and Y1/UV1 address equal to Y0/UV0 address.
1114 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_REF_SELF_FLD);
1115 //HAL_MVOP_SetFieldInverse(ENABLE, DISABLE); //do not inverse in kano: mvop gen timing + hsk mode
1116 // mheg5, mcu mode for i mode, do not bypass, 0x11[6] = 0: mvop t/b toggle
1117 HAL_WriteRegBit(VOP_REG_DUMMY_3D_1, 0, VOP_RGB_FILED_BYPASS);
1118 HAL_WriteRegBit(VOP_CTRL0, 0, VOP_EXTFLD_EN);
1119 }
1120 }
1121 // disable from wb
1122 HAL_WriteRegBit(VOP_REG_MFDEC_2_L, 0, VOP_MF_FROM_WB);
1123 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, VOP_R2_WISHBONE);
1124 HAL_WriteRegBit(VOP_REG_DUMMY, 0, VOP_32x32_WB);
1125
1126 if ( pparam->bYUV422 )
1127 regval |= 0x10;
1128 else
1129 regval &= ~0x10;
1130
1131 if ( pparam->b422pack )
1132 regval |= 0x80;
1133
1134 if ( pparam->bDramRdContd == 1 )
1135 regval |= 0x20;
1136 else
1137 regval &= ~0x20;
1138
1139 // for backward compatable to saturn
1140 // [3] UV-7bit mode don't care
1141 // [5] dram_rd_md =0
1142 // [6] Fld don't care
1143 // [7] 422pack don'care
1144 HAL_WriteByte(VOP_MPG_JPG_SWITCH, regval);
1145 g_pHalMVOPCtx->bIs422 = pparam->bYUV422;
1146 HAL_WriteRegBit(VOP_REG_DUMMY, !(pparam->bYUV422), VOP_420_BW_SAVE);
1147 HAL_WriteRegBit(VOP_REG_BW_SAVE, !(pparam->bYUV422), VOP_420_BW_SAVE_EX);
1148
1149 if (pparam->u16StripSize == 0)
1150 {
1151 if (pparam->bSD)
1152 {
1153 u16strip = 720;
1154 u16strip_lsb = 720;
1155 }
1156 else
1157 {
1158 u16strip = 1920;
1159 u16strip_lsb = 1920;
1160 }
1161 }
1162 else
1163 {
1164 u16strip = pparam->u16StripSize;
1165 u16strip_lsb = pparam->u16StripSize;
1166 }
1167
1168 // set dc_strip[7:0]
1169 if ( pparam->bDramRdContd == 0 )
1170 {
1171 u16strip = (u16strip + 31) / 32 * 32; //need align for monaco
1172 u16strip = u16strip/8;
1173 u16strip_lsb = (u16strip_lsb+127)/128;
1174 u16strip_lsb *= 4;
1175
1176 MVOP_DBG(MVOP_PRINTF("[MVOP]%s enVideoType = 0x%x\n", __FUNCTION__,pparam->enVideoType);)
1177
1178 if(pparam->enVideoType == MVOP_H264)
1179 {
1180 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 1, VOP_TILE_32x32);//mantis:1144345 mustang h264 default 32x32.
1181 }
1182 else
1183 {
1184 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, VOP_TILE_32x32);//MVD can not 32x32.
1185 }
1186 }
1187 else
1188 {
1189 if ( pparam->b422pack )
1190 {
1191 if (E_MVOP_RGB_888 == g_pHalMVOPCtx->eMainRgbFmt)
1192 {
1193 u16strip *= 2; //4bytes/pixel (yuv422:2bytes/pixel)
1194 }
1195 //VOP_REG_STRIP_ALIGN and Mirror mode are mutually exclusive, after M10(support mirror), VOP_DC_STRIP_H
1196 //replace VOP_REG_STRIP_ALIGN, which supported maximun Hsize is 8188
1197 #if 0
1198 // [071016 Andy] support YUV422 pack mode
1199 if ((u16strip < 1024) || g_pHalMVOPCtx->bMirrorMode)
1200 {
1201 u16strip = u16strip/4;
1202 // dont extend strip len
1203 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
1204 }
1205 else
1206 {
1207 u16strip = u16strip/8;
1208 // extend strip len to 2048
1209 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 1, BIT0);
1210 }
1211 #endif
1212 u16strip = u16strip/4;
1213 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
1214 }
1215 else
1216 {
1217 u16strip = u16strip/8;
1218 }
1219 }
1220
1221 if (u16strip >= 256 )
1222 {
1223 HAL_WriteByte(VOP_DC_STRIP_H, (u16strip>>8));
1224 //reg_dc_strip_h[2:0] = reg_dc_strip[10:8]
1225 }
1226 else
1227 {
1228 HAL_WriteByteMask(VOP_DC_STRIP_H, 0, BIT0 | BIT1 | BIT2);
1229 }
1230
1231 regval = u16strip;
1232 HAL_WriteByte(VOP_DC_STRIP, regval);
1233 //LSB strip
1234 HAL_WriteByte(VOP_DC_STRIP_LSB, u16strip_lsb & 0x3ff);
1235
1236
1237 HAL_MVOP_SetYUVBaseAdd(pparam->u32YOffset, pparam->u32UVOffset,
1238 pparam->bProgressive, pparam->b422pack);
1239
1240 if (E_MVOP_RPTFLD_NONE != g_pHalMVOPCtx->eRepeatField)
1241 {
1242 MVOP_DBG("%s reset eRepeatField=%x ==>", __FUNCTION__, g_pHalMVOPCtx->eRepeatField);
1243 //To output the same field for single field input,
1244 //do NOT set h'3B[9]=1 and h'11[12]=0
1245 g_pHalMVOPCtx->eRepeatField = E_MVOP_RPTFLD_NONE; //reset the flag to repeat field
1246 MVOP_DBG(" %x\n", g_pHalMVOPCtx->eRepeatField);
1247 }
1248
1249 // HSize
1250 MS_U16 u16HSize = ALIGN_UPTO_16(pparam->u16HSize);
1251 if (u16HSize != pparam->u16HSize)
1252 {
1253 MVOP_DBG(MVOP_PRINTF("\n\n Change HSize %d to %d\n", pparam->u16HSize, u16HSize);)
1254 }
1255 HAL_WriteByte(VOP_JPG_HSIZE , LOWBYTE( u16HSize ));
1256 HAL_WriteByte((VOP_JPG_HSIZE + 1), HIGHBYTE( u16HSize ));
1257
1258 // VSize
1259 MS_U16 u16VSize = pparam->u16VSize;
1260 if (g_pHalMVOPCtx->bMirrorModeVer)
1261 {
1262 u16VSize = ALIGN_UPTO_4(pparam->u16VSize);
1263 MVOP_DBG(MVOP_PRINTF("\n\n Change VSize %d to %d\n", pparam->u16VSize, u16VSize);)
1264 }
1265 HAL_WriteByte(VOP_JPG_VSIZE , LOWBYTE( u16VSize ));
1266 HAL_WriteByte((VOP_JPG_VSIZE + 1), HIGHBYTE( u16VSize ));
1267 }
1268
1269 HAL_MVOP_LoadReg();
1270 }
1271
1272
HAL_MVOP_EnableUVShift(MS_BOOL bEnable)1273 void HAL_MVOP_EnableUVShift(MS_BOOL bEnable)
1274 {
1275 MS_U8 regval;
1276
1277 regval = HAL_ReadByte(VOP_MPG_JPG_SWITCH);
1278
1279 if (((regval & BIT4) == BIT4) && ((regval & 0x3)== 0x2))
1280 { // 422 with MCU control mode
1281 if (bEnable)
1282 {
1283 MS_ASSERT(0);
1284 }
1285 }
1286
1287 // output 420 and interlace
1288 //[IP - Sheet] : Main Page --- 420CUP
1289 //[Project] : Titania2
1290 //[Description]: Chroma artifacts when 420to422 is applied duplicate method.
1291 //[Root cause]: Apply 420to422 average algorithm to all DTV input cases.
1292 //The average algorithm must cooperate with MVOP.
1293 HAL_WriteByteMask(VOP_UV_SHIFT, (bEnable)?1:0, 0x3);
1294 }
1295
1296 static MS_BOOL _bEnable60P = false;
HAL_MVOP_SetEnable60P(MS_BOOL bEnable)1297 void HAL_MVOP_SetEnable60P(MS_BOOL bEnable)
1298 {
1299 _bEnable60P = bEnable;
1300 }
1301
1302 static MS_BOOL _bEnable4k2kClk = false;
HAL_MVOP_SetEnable4k2kClk(MS_BOOL bEnable)1303 void HAL_MVOP_SetEnable4k2kClk(MS_BOOL bEnable)
1304 {
1305 _bEnable4k2kClk = bEnable;
1306 }
1307
HAL_MVOP_SetEnable4k2k2P(MS_BOOL bEnable)1308 void HAL_MVOP_SetEnable4k2k2P(MS_BOOL bEnable)
1309 {
1310 g_pHalMVOPCtx->bIs2p = bEnable;
1311 HAL_WriteRegBit(VOP_REG_4K2K_2P, bEnable, VOP_4K2K_2P);
1312 HAL_MVOP_Set420BWSaveMode(bEnable);
1313 }
1314
HAL_MVOP_Get4k2k2PMode(MVOP_DevID eID)1315 MS_BOOL HAL_MVOP_Get4k2k2PMode(MVOP_DevID eID)
1316 {
1317 MS_BOOL bEnable4k2k2P = FALSE;
1318 switch(eID)
1319 {
1320 case E_MVOP_DEV_0:
1321 bEnable4k2k2P = g_pHalMVOPCtx->bIs2p;
1322 break;
1323 #if MVOP_SUPPORT_SUB
1324 case E_MVOP_DEV_1:
1325 bEnable4k2k2P = g_pHalMVOPCtx->bSubIs2p;
1326 break;
1327 #endif
1328 default:
1329 MVOP_PRINTF("Attention! %s Not support eID=%u yet\n", __FUNCTION__, eID);
1330 break;
1331 }
1332 return bEnable4k2k2P;
1333 }
1334
1335 static MS_BOOL _bEnableFixClk = false;
HAL_MVOP_SetEnableFixClk(MS_BOOL bEnable)1336 void HAL_MVOP_SetEnableFixClk(MS_BOOL bEnable)
1337 {
1338 _bEnableFixClk = bEnable;
1339 }
1340
HAL_MVOP_EnableFreerunMode(MS_BOOL bEnable)1341 void HAL_MVOP_EnableFreerunMode(MS_BOOL bEnable)
1342 {
1343 if (g_pHalMVOPCtx == NULL)
1344 {
1345 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1346 return;
1347 }
1348 g_pHalMVOPCtx->bEnableFreerunMode = bEnable;
1349 }
1350
HAL_MVOP_SetVSyncMode(MS_U8 u8Mode)1351 void HAL_MVOP_SetVSyncMode(MS_U8 u8Mode)
1352 {
1353 if (g_pHalMVOPCtx == NULL)
1354 {
1355 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1356 return;
1357 }
1358 if (1==u8Mode)
1359 {
1360 g_pHalMVOPCtx->bNewVSyncMode = TRUE;
1361 }
1362 else
1363 {
1364 g_pHalMVOPCtx->bNewVSyncMode = FALSE;
1365 }
1366 }
1367
HAL_MVOP_SetOutputTiming(MVOP_Timing * ptiming)1368 void HAL_MVOP_SetOutputTiming( MVOP_Timing *ptiming )
1369 {
1370 MS_U8 regval;
1371
1372 if (g_pHalMVOPCtx == NULL)
1373 {
1374 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1375 return;
1376 }
1377
1378 HAL_WriteByte(VOP_FRAME_VCOUNT , LOWBYTE( ptiming->u16V_TotalCount ));
1379 HAL_WriteByte((VOP_FRAME_VCOUNT + 1), HIGHBYTE( ptiming->u16V_TotalCount ));
1380 HAL_WriteByte(VOP_FRAME_HCOUNT , LOWBYTE( ptiming->u16H_TotalCount ));
1381 HAL_WriteByte((VOP_FRAME_HCOUNT + 1), HIGHBYTE( ptiming->u16H_TotalCount ));
1382
1383 HAL_WriteByte((VOP_VB0_STR ), LOWBYTE( ptiming->u16VBlank0_Start ));
1384 HAL_WriteByte((VOP_VB0_STR + 1), HIGHBYTE( ptiming->u16VBlank0_Start ));
1385 HAL_WriteByte((VOP_VB0_END ), LOWBYTE( ptiming->u16VBlank0_End ));
1386 HAL_WriteByte((VOP_VB0_END + 1), HIGHBYTE( ptiming->u16VBlank0_End ));
1387 HAL_WriteByte((VOP_VB1_STR ), LOWBYTE( ptiming->u16VBlank1_Start ));
1388 HAL_WriteByte((VOP_VB1_STR + 1), HIGHBYTE( ptiming->u16VBlank1_Start ));
1389 HAL_WriteByte((VOP_VB1_END ), LOWBYTE( ptiming->u16VBlank1_End ));
1390 HAL_WriteByte((VOP_VB1_END + 1), HIGHBYTE( ptiming->u16VBlank1_End ));
1391 HAL_WriteByte((VOP_TF_STR ), LOWBYTE( ptiming->u16TopField_Start ));
1392 HAL_WriteByte((VOP_TF_STR + 1), HIGHBYTE( ptiming->u16TopField_Start ));
1393 HAL_WriteByte((VOP_BF_STR ), LOWBYTE( ptiming->u16BottomField_Start ));
1394 HAL_WriteByte((VOP_BF_STR + 1), HIGHBYTE( ptiming->u16BottomField_Start ));
1395 HAL_WriteByte((VOP_HACT_STR ), LOWBYTE( ptiming->u16HActive_Start ));
1396 HAL_WriteByte((VOP_HACT_STR + 1), HIGHBYTE( ptiming->u16HActive_Start ));
1397
1398 HAL_WriteByte((VOP_TF_VS ), LOWBYTE( ptiming->u16TopField_VS ));
1399 HAL_WriteByte((VOP_TF_VS + 1), HIGHBYTE( ptiming->u16TopField_VS ));
1400 HAL_WriteByte((VOP_BF_VS ), LOWBYTE( ptiming->u16BottomField_VS ));
1401 HAL_WriteByte((VOP_BF_VS + 1), HIGHBYTE( ptiming->u16BottomField_VS ));
1402
1403 //if(((ptiming->u16V_TotalCount > 2160) || (ptiming->u16H_TotalCount > 3840)) && (ptiming->u8Framerate >= 30))
1404 if((!g_pHalMVOPCtx->bIsXcTrig) && (g_pHalMVOPCtx->bIsHS))
1405 {
1406 g_pHalMVOPCtx->bNewVSyncMode = TRUE;
1407 }
1408
1409 if (g_pHalMVOPCtx->bNewVSyncMode)
1410 {
1411 #define NEW_VSYNC_MODE_ADVANCE_LINECNT 30
1412 MVOP_DBG(MVOP_PRINTF("MVOP use new vync mode, forwarding %d lines\n",NEW_VSYNC_MODE_ADVANCE_LINECNT);)
1413
1414 MS_U16 u16BottomField_VS2MVD = ptiming->u16BottomField_VS - NEW_VSYNC_MODE_ADVANCE_LINECNT;
1415 MVOP_DBG(MVOP_PRINTF("BottomField VS ori=0x%x, new=0x%x\n", ptiming->u16BottomField_VS, u16BottomField_VS2MVD);)
1416 HAL_WriteByte((VOP_BF_VS_MVD ), LOWBYTE( u16BottomField_VS2MVD ));
1417 HAL_WriteByte((VOP_BF_VS_MVD + 1), HIGHBYTE( u16BottomField_VS2MVD ));
1418
1419 MS_U16 u16TopField_VS2MVD = ptiming->u16V_TotalCount - NEW_VSYNC_MODE_ADVANCE_LINECNT;
1420 MVOP_DBG(MVOP_PRINTF("TopField VS Vtt=0x%x, new=0x%x\n", ptiming->u16V_TotalCount, u16TopField_VS2MVD);)
1421 HAL_WriteByte((VOP_TF_VS_MVD ), LOWBYTE( u16TopField_VS2MVD ));
1422 HAL_WriteByte((VOP_TF_VS_MVD + 1), HIGHBYTE( u16TopField_VS2MVD ));
1423
1424 HAL_WriteRegBit(VOP_GCLK, 0, VOP_GCLK_MIU_ON);
1425
1426 HAL_WriteRegBit(VOP_CTRL1, 1, VOP_MVD_VS_MD); //Use new vsync
1427
1428 g_pHalMVOPCtx->bNewVSyncMode = FALSE; //restore to original mode
1429 }
1430 else
1431 {
1432 MS_U16 u16BottomField_VS2MVD = 0x200;
1433 HAL_WriteByte((VOP_BF_VS_MVD ), LOWBYTE( u16BottomField_VS2MVD ));
1434 HAL_WriteByte((VOP_BF_VS_MVD + 1), HIGHBYTE( u16BottomField_VS2MVD ));
1435
1436 MS_U16 u16TopField_VS2MVD = 0x200;
1437 HAL_WriteByte((VOP_TF_VS_MVD ), LOWBYTE( u16TopField_VS2MVD ));
1438 HAL_WriteByte((VOP_TF_VS_MVD + 1), HIGHBYTE( u16TopField_VS2MVD ));
1439 HAL_WriteRegBit(VOP_CTRL1, 0, VOP_MVD_VS_MD);
1440 }
1441
1442
1443 /* Clippers sw patch: sbs + handshake mode video not stable*/
1444 if(g_pHalMVOPCtx->b3DLRAltSBSOutput)
1445 {
1446 ptiming->u16VImg_Start0 = 0xfff;
1447 ptiming->u16VImg_Start1 = 0xfff;
1448 }
1449
1450 // + S3, set default IMG_HSTR, IMG_VSTR0, IMG_VSTR1
1451 #ifdef _SUPPORT_IMG_OFFSET_
1452 HAL_WriteByte((VOP_IMG_HSTR ), LOWBYTE( ptiming->u16HImg_Start));
1453 HAL_WriteByte((VOP_IMG_HSTR + 1), HIGHBYTE( ptiming->u16HImg_Start ));
1454 HAL_WriteByte((VOP_IMG_VSTR0 ), LOWBYTE( ptiming->u16VImg_Start0));
1455 HAL_WriteByte((VOP_IMG_VSTR0+ 1), HIGHBYTE( ptiming->u16VImg_Start0 ));
1456 HAL_WriteByte((VOP_IMG_VSTR1 ), LOWBYTE( ptiming->u16VImg_Start1 ));
1457 HAL_WriteByte((VOP_IMG_VSTR1+ 1), HIGHBYTE( ptiming->u16VImg_Start1 ));
1458 #else
1459 HAL_WriteByte((VOP_IMG_HSTR ), LOWBYTE( ptiming->u16HActive_Start ));
1460 HAL_WriteByte((VOP_IMG_HSTR + 1), HIGHBYTE( ptiming->u16HActive_Start ));
1461 HAL_WriteByte((VOP_IMG_VSTR0 ), LOWBYTE( ptiming->u16VBlank0_End ));
1462 HAL_WriteByte((VOP_IMG_VSTR0+ 1), HIGHBYTE( ptiming->u16VBlank0_End ));
1463 HAL_WriteByte((VOP_IMG_VSTR1 ), LOWBYTE( ptiming->u16VBlank1_End ));
1464 HAL_WriteByte((VOP_IMG_VSTR1+ 1), HIGHBYTE( ptiming->u16VBlank1_End ));
1465 #endif
1466 // select mvop output from frame color(black)
1467 HAL_WriteByte((VOP_TST_IMG + 1), 0x10);
1468 HAL_WriteByte((VOP_U_PAT ), 0x80);
1469 HAL_WriteByte((VOP_U_PAT + 1), 0x80);
1470 // set mvop src to test pattern
1471 regval = HAL_ReadByte(VOP_TST_IMG);
1472 HAL_WriteByteMask(VOP_TST_IMG, 0x02, BIT2 | BIT1 | BIT0);
1473 // make changed registers take effect
1474 HAL_MVOP_LoadReg();
1475
1476 HAL_MVOP_SetMIUReqMask(TRUE);
1477 // reset mvop to avoid timing change cause mvop hang-up
1478 HAL_MVOP_Rst();
1479 HAL_MVOP_SetMIUReqMask(FALSE);
1480
1481 // select mvop output from mvd
1482 HAL_WriteByteMask(VOP_TST_IMG, 0x00, BIT2 | BIT1 | BIT0);
1483 HAL_WriteByteMask(VOP_TST_IMG, regval, BIT2 | BIT1 | BIT0);
1484 HAL_WriteRegBit(VOP_CTRL0, ptiming->bHDuplicate, BIT2);// H pixel duplicate
1485
1486 #if 0
1487 MVOP_DBG(MVOP_PRINTF("\nMVOP SetOutputTiming\n");)
1488 MVOP_DBG(MVOP_PRINTF(" VTot=%u,\t",ptiming->u16V_TotalCount);)
1489 MVOP_DBG(MVOP_PRINTF(" HTot=%u,\t",ptiming->u16H_TotalCount);)
1490 MVOP_DBG(MVOP_PRINTF(" I/P=%u\n",ptiming->bInterlace);)
1491 MVOP_DBG(MVOP_PRINTF(" W=%u,\t",ptiming->u16Width);)
1492 MVOP_DBG(MVOP_PRINTF(" H=%u,\t",ptiming->u16Height);)
1493 MVOP_DBG(MVOP_PRINTF(" FRate=%u,\t",ptiming->u8Framerate);)
1494 MVOP_DBG(MVOP_PRINTF(" HFreq=%u\n",ptiming->u16H_Freq);)
1495 MVOP_DBG(MVOP_PRINTF(" Num=0x%x,\t",ptiming->u16Num);)
1496 MVOP_DBG(MVOP_PRINTF(" Den=0x%x,\t",ptiming->u16Den);)
1497 MVOP_DBG(MVOP_PRINTF(" u16ExpFRate=%u #\n\n", ptiming->u16ExpFrameRate);)
1498 #endif
1499 }
1500
HAL_MVOP_SetDCClk(MS_U8 clkNum,MS_BOOL bEnable)1501 void HAL_MVOP_SetDCClk(MS_U8 clkNum, MS_BOOL bEnable)
1502 {
1503 MS_ASSERT( (clkNum==0) || (clkNum==1) );
1504 if (clkNum==0)
1505 {
1506 HAL_WriteRegBit(REG_CKG_DC0, !bEnable, CKG_DC0_GATED);
1507 }
1508 }
1509
HAL_MVOP_SetDCSRAMClk(MS_U8 clkNum,MS_BOOL bEnable)1510 void HAL_MVOP_SetDCSRAMClk(MS_U8 clkNum, MS_BOOL bEnable)
1511 {
1512 MVOP_DBG(MVOP_PRINTF("[%s] eco num = %d\n",__FUNCTION__,g_pHalMVOPCtx->u16ECONum);)
1513 MS_ASSERT( (clkNum==0) || (clkNum==1) );
1514 if (clkNum==0)
1515 {
1516 if(bEnable)
1517 {
1518 if(g_pHalMVOPCtx->u16ECONum == 0)
1519 {
1520 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x4, CKG_DC0_SRAM);//Dc0 enable & dc0_mfdec_en =0 57[3:0]= 0x4, others 57[3:0]=0x0
1521 }
1522 else // k6 eco for mfdec sram clock switch.
1523 {
1524 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x0, CKG_DC0_SRAM);
1525 HAL_WriteByteMask(VOP_REG_DUMMY_5D, 0x0, VOP_SRAM_CLK_AUTO);
1526 HAL_MVOP_LoadReg();
1527 }
1528 }
1529 else
1530 {
1531 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x0, CKG_DC0_SRAM);
1532 }
1533 }
1534 }
1535
1536
HAL_MVOP_SetSynClk(MVOP_Timing * ptiming)1537 void HAL_MVOP_SetSynClk(MVOP_Timing *ptiming)
1538 {
1539 if (g_pHalMVOPCtx == NULL)
1540 {
1541 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1542 return;
1543 }
1544
1545 if(g_pHalMVOPCtx->u32MVOPFixClk != 0)
1546 {
1547 HAL_MVOP_SetFrequency(g_pHalMVOPCtx->u32MVOPFixClk);
1548 if(g_pHalMVOPCtx->b3DLRMode)//4k1k mvc
1549 {
1550 //burst and priority
1551 HAL_WriteByte(VOP_DMA1, 0x26);
1552 HAL_WriteByte(VOP_BURST_CTRL0, 0x05);
1553 HAL_WriteByte(VOP_BURST_CTRL1, 0x00);
1554 }
1555 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] Set Fix clock\n");)
1556 }
1557 else if(g_pHalMVOPCtx->bEnableFreerunMode)
1558 {
1559 MS_U64 u64mpll_clock = MPLL_CLOCK << 27 ;
1560 do_div(u64mpll_clock, ((MS_U32)ptiming->u16H_TotalCount * (MS_U32)ptiming->u16V_TotalCount * (MS_U32)ptiming->u8Framerate));
1561 MS_U32 u32FreerunClk = (MS_U32)u64mpll_clock;
1562 HAL_MVOP_SetFrequency(HALMVOP_FREERUNMODE);
1563 HAL_WriteByte((REG_DC0_FREERUN_CW_L ), LOWBYTE((MS_U16)u32FreerunClk));
1564 HAL_WriteByte((REG_DC0_FREERUN_CW_L+1), HIGHBYTE((MS_U16)u32FreerunClk));
1565 HAL_WriteByte((REG_DC0_FREERUN_CW_H ), LOWBYTE((MS_U16)(u32FreerunClk >> 16)));
1566 HAL_WriteByte((REG_DC0_FREERUN_CW_H+1), HIGHBYTE((MS_U16)(u32FreerunClk >> 16)));
1567 HAL_WriteRegBit(REG_UPDATE_DC0_CW, 1, UPDATE_DC0_FREERUN_CW);
1568 HAL_WriteRegBit(REG_UPDATE_DC0_CW, 0, UPDATE_DC0_FREERUN_CW);
1569 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] Set Freerun clock\n");)
1570 }
1571 else if (_bEnable60P)
1572 {
1573 HAL_MVOP_SetFrequency(HAL_MVOP_GetMaxFreerunClk());
1574
1575 HAL_WriteRegBit(VOP_REG_FRAME_RST, 0, BIT15); // reg_frame_rst = 0
1576
1577 HAL_WriteRegBit(VOP_CTRL0, DISABLE, VOP_FSYNC_EN); // frame sync disable
1578
1579 if(g_pHalMVOPCtx->b3DLRMode)//4k1k mvc
1580 {
1581 //burst and priority
1582 HAL_WriteByte(VOP_DMA1, 0x26);
1583 HAL_WriteByte(VOP_BURST_CTRL0, 0x05);
1584 HAL_WriteByte(VOP_BURST_CTRL1, 0x00);
1585 }
1586
1587 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] Set 160MHz clock\n");)
1588 }
1589 else if (_bEnable4k2kClk)
1590 {
1591 HAL_MVOP_SetFrequency(HAL_MVOP_Get4k2kClk());
1592
1593 HAL_WriteRegBit(VOP_REG_FRAME_RST, 0, BIT15); // reg_frame_rst = 0
1594
1595 HAL_WriteRegBit(VOP_CTRL0, DISABLE, VOP_FSYNC_EN); // frame sync disable
1596 // Clippers sync wz xc: 4k2k default 2p mode enable(xc output 50 or 60)
1597 HAL_MVOP_SetEnable4k2k2P(TRUE);
1598 //Change MIU BW Default Value to 0x241C (after Einstein)
1599 //FIFO threshold
1600 HAL_WriteByte(VOP_DMA0, 0x10);
1601 //burst and priority
1602 HAL_WriteByte(VOP_DMA1, 0x26);
1603 HAL_WriteByte(VOP_BURST_CTRL0, 0x05);
1604 HAL_WriteByte(VOP_BURST_CTRL1, 0x00);
1605 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] Set 4k2k clock\n");)
1606 }
1607 else
1608 {
1609 HAL_MVOP_SetFrequency(HALMVOP_SYNCMODE);
1610 HAL_WriteByte((REG_DC0_NUM ), LOWBYTE( ptiming->u16Num));
1611 HAL_WriteByte((REG_DC0_NUM+1), HIGHBYTE(ptiming->u16Num));
1612 HAL_WriteByte((REG_DC0_DEN ), LOWBYTE( ptiming->u16Den));
1613 HAL_WriteByte((REG_DC0_DEN+1), HIGHBYTE(ptiming->u16Den));
1614 HAL_WriteRegBit(REG_UPDATE_DC0_CW, 1, UPDATE_DC0_SYNC_CW);
1615 HAL_WriteRegBit(REG_UPDATE_DC0_CW, 0, UPDATE_DC0_SYNC_CW);
1616 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] Set Sync clock\n");)
1617 }
1618 }
1619
1620
HAL_MVOP_SetMonoMode(MS_BOOL bEnable)1621 void HAL_MVOP_SetMonoMode(MS_BOOL bEnable)
1622 {
1623 if(bEnable)
1624 {
1625 HAL_WriteByte(VOP_U_PAT , 0x80);
1626 HAL_WriteByte((VOP_U_PAT+1), 0x80);
1627
1628 HAL_WriteRegBit(VOP_INPUT_SWITCH1, 1, BIT1); // Mono mode enable
1629 }
1630 else
1631 {
1632 HAL_WriteRegBit(VOP_INPUT_SWITCH1, 0, BIT1); //Mono mode disable
1633 }
1634 }
1635
1636 /******************************************************************************/
1637 /// Set MVOP for H264 Hardwire Mode
1638 /******************************************************************************/
HAL_MVOP_SetH264HardwireMode(MS_U16 u16ECOVersion)1639 void HAL_MVOP_SetH264HardwireMode(MS_U16 u16ECOVersion)
1640 {
1641 // Hardwire mode
1642 HAL_WriteByte(VOP_MPG_JPG_SWITCH, 0x00);
1643
1644 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
1645
1646 //16*32 tile format
1647 HAL_WriteRegBit(VOP_REG_WR, 1, BIT1);
1648
1649 // SVD mode enable
1650 HAL_WriteByteMask(VOP_INPUT_SWITCH1, BIT3, BIT2|BIT3);
1651
1652 // set mvop to 128bit_i128 interface
1653 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
1654
1655 // Only for Monaco: Disable deciding bot by top address + 2
1656 HAL_WriteRegBit(VOP_MIRROR_CFG, 0, VOP_FIELD_FROM_ADDR);
1657
1658 HAL_WriteRegBit(VOP_REG_DUMMY, 1, VOP_32x32_WB); //32x32 from wb
1659 if(u16ECOVersion == 0)
1660 {
1661 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x0, CKG_DC0_SRAM);//Dc0 enable & dc0_mfdec_en =0 57[3:0]= 0x4, others 57[3:0]=0x0
1662 }
1663 // Write trigger
1664 HAL_MVOP_LoadReg();
1665 }
1666
1667 /******************************************************************************/
1668 /// Set MVOP for RM Hardwire Mode
1669 /******************************************************************************/
HAL_MVOP_SetRMHardwireMode(MS_U16 u16ECOVersion)1670 void HAL_MVOP_SetRMHardwireMode(MS_U16 u16ECOVersion)
1671 {
1672 HAL_MVOP_SetH264HardwireMode(u16ECOVersion);
1673 if(u16ECOVersion == 0)
1674 {
1675 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x4, CKG_DC0_SRAM);//Dc0 enable & dc0_mfdec_en =0 57[3:0]= 0x4, others 57[3:0]=0x0
1676 }
1677 }
1678
1679 /******************************************************************************/
1680 /// Set MVOP for JPEG Hardwire Mode
1681 /******************************************************************************/
HAL_MVOP_SetJpegHardwireMode(void)1682 void HAL_MVOP_SetJpegHardwireMode(void)
1683 {
1684 MS_U8 regval = 0x00;
1685
1686 regval |= 0x80; // packmode
1687 regval |= 0x20; // Dram Rd Contd
1688 HAL_WriteByte(VOP_MPG_JPG_SWITCH, regval);
1689 g_pHalMVOPCtx->bIs422 = 1;
1690 HAL_WriteRegBit(VOP_REG_DUMMY, 0, VOP_420_BW_SAVE);
1691 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
1692
1693 HAL_WriteByteMask(VOP_INFO_FROM_CODEC_H, 0x00, VOP_INFO_FROM_CODEC_MIU_BUF0_SEL|VOP_INFO_FROM_CODEC_MIU_BUF1_SEL);
1694
1695 // Write trigger
1696 HAL_MVOP_LoadReg();
1697 }
1698
1699 /******************************************************************************/
1700 /// Set MVOP for EVD Hardwire Mode
1701 /******************************************************************************/
HAL_MVOP_SetEVDHardwireMode(MS_U16 u16ECOVersion)1702 void HAL_MVOP_SetEVDHardwireMode(MS_U16 u16ECOVersion)
1703 {
1704 // Hardwire mode
1705 HAL_WriteByte(VOP_MPG_JPG_SWITCH, 0x00);
1706
1707 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
1708
1709 //16*32 tile format
1710 HAL_WriteRegBit(VOP_REG_WR, 1, BIT1);
1711
1712 // SVD mode enable
1713 // EVD use HVD interface
1714 //HAL_WriteByteMask(VOP_INPUT_SWITCH1, BIT3, BIT2|BIT3);
1715
1716 // EVD mode enable
1717 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 1, EVD_ENABLE);
1718
1719 // set mvop to 128bit_i128 interface
1720 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
1721
1722 // set evd flag for interlace mode setting
1723 g_pHalMVOPCtx->bIsH265 = 1;
1724
1725 // 10 bits from wb
1726 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_H, 1, VOP_INFO_FROM_CODEC_10BIT);
1727 HAL_WriteByteMask(VOP_REG_MASK, 0, VOP_LSB_REQ_MASK);
1728
1729 if(u16ECOVersion == 0)
1730 {
1731 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x0, CKG_DC0_SRAM);//Dc0 enable & dc0_mfdec_en =0 57[3:0]= 0x4, others 57[3:0]=0x0
1732 }
1733
1734
1735 // Write trigger
1736 HAL_MVOP_LoadReg();
1737 }
1738
1739 /******************************************************************************/
1740 /// Set MVOP for VP9 Hardwire Mode
1741 /// vp9 hw change in Manhathan: tile mode 16x32
1742 /******************************************************************************/
HAL_MVOP_SetVP9HardwireMode(MS_U16 u16ECOVersion)1743 void HAL_MVOP_SetVP9HardwireMode(MS_U16 u16ECOVersion)
1744 {
1745 HAL_MVOP_SetEVDHardwireMode(u16ECOVersion);
1746 }
1747
1748 /******************************************************************************/
1749 /// Set MVOP for EVD MCU Mode
1750 /******************************************************************************/
HAL_MVOP_SetEVDFeature(MVOP_DevID eID,MVOP_EVDFeature * stEVDInput)1751 void HAL_MVOP_SetEVDFeature(MVOP_DevID eID, MVOP_EVDFeature* stEVDInput)
1752 {
1753 switch(eID)
1754 {
1755 case E_MVOP_DEV_0:
1756
1757 HAL_WriteRegBit(VOP_INPUT_SWITCH0, stEVDInput->bEnableEVD, EVD_ENABLE);// 32x32 enable
1758
1759 switch(stEVDInput->eEVDBit[Y_INFO])
1760 {
1761 case E_MVOP_EVD_8BIT:
1762 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_Y_EN);
1763 break;
1764 case E_MVOP_EVD_10BIT:
1765 HAL_WriteRegBit(VOP_EVD_10B_EN, 1, VOP_EVD_10B_Y_EN);
1766 break;
1767 default:
1768 break;
1769 }
1770
1771 switch(stEVDInput->eEVDBit[UV_INFO])
1772 {
1773 case E_MVOP_EVD_8BIT:
1774 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_UV_EN);
1775 break;
1776 case E_MVOP_EVD_10BIT:
1777 HAL_WriteRegBit(VOP_EVD_10B_EN, 1, VOP_EVD_10B_UV_EN);
1778 break;
1779 default:
1780 break;
1781 }
1782
1783 //LSB BW Discard MASK
1784 if(stEVDInput->eEVDBit[Y_INFO] || stEVDInput->eEVDBit[UV_INFO])
1785 {
1786 HAL_WriteByteMask(VOP_REG_MASK, 0, VOP_LSB_REQ_MASK);
1787 HAL_WriteRegBit(VOP_UV_SHIFT, 0, VOP_GCLK_MIU_ON);
1788 MVOP_DBG(MVOP_PRINTF("[Debug] 10 bits display\n"););
1789 }
1790 else
1791 {
1792 HAL_WriteByteMask(VOP_REG_MASK, BIT1, VOP_LSB_REQ_MASK);
1793 }
1794
1795 // Write trigger
1796 HAL_MVOP_LoadReg();
1797 break;
1798 case E_MVOP_DEV_1:
1799 #if MVOP_SUPPORT_SUB
1800
1801 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), stEVDInput->bEnableEVD, EVD_ENABLE);// 32x32 enable
1802
1803 switch(stEVDInput->eEVDBit[Y_INFO])
1804 {
1805 case E_MVOP_EVD_8BIT:
1806 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 0, VOP_EVD_10B_Y_EN);
1807 break;
1808 case E_MVOP_EVD_10BIT:
1809 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 1, VOP_EVD_10B_Y_EN);
1810 break;
1811 default:
1812 break;
1813 }
1814
1815 switch(stEVDInput->eEVDBit[UV_INFO])
1816 {
1817 case E_MVOP_EVD_8BIT:
1818 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 0, VOP_EVD_10B_UV_EN);
1819 break;
1820 case E_MVOP_EVD_10BIT:
1821 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 1, VOP_EVD_10B_UV_EN);
1822 break;
1823 default:
1824 break;
1825 }
1826
1827 //LSB BW Discard MASK
1828 if(stEVDInput->eEVDBit[Y_INFO] || stEVDInput->eEVDBit[UV_INFO])
1829 {
1830 HAL_WriteByteMask(SUB_REG(VOP_REG_MASK), 0, VOP_LSB_REQ_MASK);
1831 HAL_WriteRegBit(SUB_REG(VOP_UV_SHIFT), 0, VOP_GCLK_MIU_ON);
1832 MVOP_DBG(MVOP_PRINTF("[Debug] 10 bits display\n"););
1833 }
1834 else
1835 {
1836 HAL_WriteByteMask(SUB_REG(VOP_REG_MASK), BIT1, VOP_LSB_REQ_MASK);
1837 }
1838 // Write trigger
1839 HAL_MVOP_SubLoadReg();
1840 #endif
1841 break;
1842 default:
1843 break;
1844 }
1845
1846 }
1847
1848
1849 ///Enable 3D L/R dual buffer mode
HAL_MVOP_Enable3DLR(MS_BOOL bEnable)1850 MS_BOOL HAL_MVOP_Enable3DLR(MS_BOOL bEnable)
1851 {
1852 if (g_pHalMVOPCtx == NULL)
1853 {
1854 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1855 return FALSE;
1856 }
1857 HAL_WriteRegBit(VOP_MULTI_WIN_CFG0, bEnable, VOP_LR_BUF_MODE);
1858 g_pHalMVOPCtx->b3DLRMode = bEnable;
1859 if(bEnable)
1860 {
1861 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
1862 }
1863 return TRUE;
1864 }
1865
1866 ///Get if 3D L/R mode is enabled
HAL_MVOP_Get3DLRMode(void)1867 MS_BOOL HAL_MVOP_Get3DLRMode(void)
1868 {
1869 if (g_pHalMVOPCtx == NULL)
1870 {
1871 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1872 return FALSE;
1873 }
1874 return g_pHalMVOPCtx->b3DLRMode;
1875 }
1876
HAL_MVOP_GetTimingInfoFromRegisters(MVOP_TimingInfo_FromRegisters * pMvopTimingInfo)1877 MS_BOOL HAL_MVOP_GetTimingInfoFromRegisters(MVOP_TimingInfo_FromRegisters *pMvopTimingInfo)
1878 {
1879 if(NULL == pMvopTimingInfo)
1880 {
1881 MVOP_PRINTF("HAL_MVOP_GetTimingInfoFromRegisters():pMvopTimingInfo is NULL\n");
1882 return FALSE;
1883 }
1884 if(HAL_MVOP_GetEnableState() == FALSE)
1885 {
1886 MVOP_PRINTF("MVOP is not enabled!\n");
1887 pMvopTimingInfo->bEnabled = FALSE;
1888 return FALSE;
1889 }
1890 pMvopTimingInfo->bEnabled = TRUE;
1891 pMvopTimingInfo->u16H_TotalCount = (HAL_ReadByte((VOP_FRAME_HCOUNT + 1))<< 8) | (HAL_ReadByte((VOP_FRAME_HCOUNT)));
1892 pMvopTimingInfo->u16V_TotalCount = (HAL_ReadByte((VOP_FRAME_VCOUNT + 1))<< 8) | (HAL_ReadByte((VOP_FRAME_VCOUNT)));
1893 pMvopTimingInfo->u16VBlank0_Start = (HAL_ReadByte((VOP_VB0_STR + 1))<< 8) | (HAL_ReadByte((VOP_VB0_STR)));
1894 pMvopTimingInfo->u16VBlank0_End = (HAL_ReadByte((VOP_VB0_END + 1))<< 8) | (HAL_ReadByte((VOP_VB0_END)));
1895 pMvopTimingInfo->u16VBlank1_Start = (HAL_ReadByte((VOP_VB1_STR + 1))<< 8) | (HAL_ReadByte((VOP_VB1_STR)));
1896 pMvopTimingInfo->u16VBlank1_End = (HAL_ReadByte((VOP_VB1_END + 1))<< 8) | (HAL_ReadByte((VOP_VB1_END)));
1897 pMvopTimingInfo->u16TopField_Start = (HAL_ReadByte((VOP_TF_STR + 1))<< 8) | (HAL_ReadByte((VOP_TF_STR)));
1898 pMvopTimingInfo->u16BottomField_Start = (HAL_ReadByte((VOP_BF_STR + 1))<< 8) | (HAL_ReadByte((VOP_BF_STR)));
1899 pMvopTimingInfo->u16HActive_Start = (HAL_ReadByte((VOP_HACT_STR + 1))<< 8) | (HAL_ReadByte((VOP_HACT_STR)));
1900 pMvopTimingInfo->u16TopField_VS = (HAL_ReadByte((VOP_TF_VS + 1))<< 8) | (HAL_ReadByte((VOP_TF_VS)));
1901 pMvopTimingInfo->u16BottomField_VS = (HAL_ReadByte((VOP_BF_VS + 1))<< 8) | (HAL_ReadByte((VOP_BF_VS)));
1902 pMvopTimingInfo->bInterlace = (HAL_ReadRegBit(VOP_CTRL0, BIT7) == BIT7);
1903 return TRUE;
1904 }
1905
HAL_MVOP_SetYUVBaseAdd(MS_PHY u32YOffset,MS_PHY u32UVOffset,MS_BOOL bProgressive,MS_BOOL b422pack)1906 void HAL_MVOP_SetYUVBaseAdd(MS_PHY u32YOffset, MS_PHY u32UVOffset, MS_BOOL bProgressive, MS_BOOL b422pack)
1907 {
1908 MS_PHY u64tmp = 0;
1909
1910 if (g_pHalMVOPCtx == NULL)
1911 {
1912 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1913 return;
1914 }
1915 // Y offset
1916 u64tmp = u32YOffset >> 3;
1917 if ( !bProgressive )
1918 { //Refine Y offset for interlace repeat bottom field
1919 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
1920 {
1921 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
1922 u64tmp += 2;
1923 }
1924 else
1925 {
1926 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
1927 }
1928 }
1929 HAL_WriteByte(VOP_JPG_YSTR0_L, u64tmp & 0xff);
1930 HAL_WriteByte((VOP_JPG_YSTR0_L+1), (u64tmp >> 8) & 0xff);
1931 HAL_WriteByte((VOP_JPG_YSTR0_L+2), (u64tmp >> 16) & 0xff);
1932 HAL_WriteByte((VOP_JPG_YSTR0_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
1933
1934 if (!bProgressive )
1935 { //Y offset of bottom field if interlace
1936 HAL_WriteByte(VOP_JPG_YSTR1_L, u64tmp & 0xff);
1937 HAL_WriteByte((VOP_JPG_YSTR1_L+1), (u64tmp >> 8) & 0xff);
1938 HAL_WriteByte((VOP_JPG_YSTR1_L+2), (u64tmp >> 16) & 0xff);
1939 HAL_WriteByte((VOP_JPG_YSTR1_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
1940 }
1941
1942 if (b422pack)
1943 {
1944 u32UVOffset = u32YOffset + 16; //add 16 for 128bit; add 8 for 64bit
1945 }
1946 // UV offset
1947 u64tmp = u32UVOffset >> 3;
1948 if( !bProgressive )
1949 { //Refine UV offset for interlace repeat bottom field
1950 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
1951 {
1952 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
1953 u64tmp += 2;
1954 }
1955 else
1956 {
1957 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
1958 }
1959 }
1960 HAL_WriteByte(VOP_JPG_UVSTR0_L, u64tmp & 0xff);
1961 HAL_WriteByte((VOP_JPG_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
1962 HAL_WriteByte((VOP_JPG_UVSTR0_L+2), (u64tmp >> 16) & 0xff);
1963 HAL_WriteByte((VOP_JPG_UVSTR0_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
1964
1965 if( !bProgressive )
1966 { //UV offset of bottom field if interlace
1967 HAL_WriteByte(VOP_JPG_UVSTR1_L, u64tmp & 0xff);
1968 HAL_WriteByte((VOP_JPG_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
1969 HAL_WriteByte((VOP_JPG_UVSTR1_L+2), (u64tmp >> 16) & 0xff);
1970 HAL_WriteByte((VOP_JPG_UVSTR1_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
1971 }
1972
1973 return;
1974 }
1975
HAL_MVOP_SetYUVBaseAddMultiView(MVOP_BaseAddInput * stBaseAddInfo)1976 MS_BOOL HAL_MVOP_SetYUVBaseAddMultiView(MVOP_BaseAddInput *stBaseAddInfo)
1977 {
1978 MS_PHY u64tmpY = 0;
1979 MS_PHY u64tmpUV = 0;
1980
1981 if (stBaseAddInfo == NULL)
1982 {
1983 MVOP_DBG(MVOP_PRINTF("%s stBaseAddInfo is NULL pointer\n", __FUNCTION__);)
1984 return FALSE;
1985 }
1986 // Y offset
1987 u64tmpY = (stBaseAddInfo->u32YOffset) >> 3;
1988 // UV offset
1989 u64tmpUV = (stBaseAddInfo->u32UVOffset) >> 3;
1990
1991 switch(stBaseAddInfo->eView)
1992 {
1993 case E_MVOP_MAIN_VIEW:
1994 // Y offset
1995 HAL_WriteByte(VOP_JPG_YSTR0_L, u64tmpY & 0xff);
1996 HAL_WriteByte((VOP_JPG_YSTR0_L+1), (u64tmpY >> 8) & 0xff);
1997 HAL_WriteByte((VOP_JPG_YSTR0_L+2), (u64tmpY >> 16) & 0xff);
1998 HAL_WriteByte((VOP_JPG_YSTR0_L+3), (u64tmpY >> 24) & VOP_YUV_STR_HIBITS);
1999
2000 // UV offset
2001 HAL_WriteByte(VOP_JPG_UVSTR0_L, u64tmpUV & 0xff);
2002 HAL_WriteByte((VOP_JPG_UVSTR0_L+1), (u64tmpUV >> 8) & 0xff);
2003 HAL_WriteByte((VOP_JPG_UVSTR0_L+2), (u64tmpUV >> 16) & 0xff);
2004 HAL_WriteByte((VOP_JPG_UVSTR0_L+3), (u64tmpUV >> 24) & VOP_YUV_STR_HIBITS);
2005 break;
2006 case E_MVOP_2ND_VIEW:
2007 // Y offset
2008 HAL_WriteByte(VOP_JPG_YSTR1_L, u64tmpY & 0xff);
2009 HAL_WriteByte((VOP_JPG_YSTR1_L+1), (u64tmpY >> 8) & 0xff);
2010 HAL_WriteByte((VOP_JPG_YSTR1_L+2), (u64tmpY >> 16) & 0xff);
2011 HAL_WriteByte((VOP_JPG_YSTR1_L+3), (u64tmpY >> 24) & VOP_YUV_STR_HIBITS);
2012
2013 //UV offset
2014 HAL_WriteByte(VOP_JPG_UVSTR1_L, u64tmpUV & 0xff);
2015 HAL_WriteByte((VOP_JPG_UVSTR1_L+1), (u64tmpUV >> 8) & 0xff);
2016 HAL_WriteByte((VOP_JPG_UVSTR1_L+2), (u64tmpUV >> 16) & 0xff);
2017 HAL_WriteByte((VOP_JPG_UVSTR1_L+3), (u64tmpUV >> 24) & VOP_YUV_STR_HIBITS);
2018 break;
2019 default:
2020 break;
2021 }
2022 return TRUE;
2023 }
2024
HAL_MVOP_GetYBaseAdd(void)2025 MS_PHY HAL_MVOP_GetYBaseAdd(void)
2026 {
2027 MS_PHY u64YOffset = 0;
2028 u64YOffset = HAL_ReadByte(VOP_JPG_YSTR0_L)&0xff;
2029 u64YOffset |=((HAL_ReadByte((VOP_JPG_YSTR0_L+1))<<8)&0xff00);
2030 u64YOffset |=((HAL_ReadByte((VOP_JPG_YSTR0_L+2))<<16)&0xff0000);
2031 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
2032 return u64YOffset;
2033 }
2034
HAL_MVOP_GetUVBaseAdd(void)2035 MS_PHY HAL_MVOP_GetUVBaseAdd(void)
2036 {
2037 MS_PHY u64UVOffset = 0;
2038 u64UVOffset = HAL_ReadByte(VOP_JPG_UVSTR0_L)&0xff;
2039 u64UVOffset |=((HAL_ReadByte((VOP_JPG_UVSTR0_L+1))<<8)&0xff00);
2040 u64UVOffset |=((HAL_ReadByte((VOP_JPG_UVSTR0_L+2))<<16)&0xff0000);
2041 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
2042 return u64UVOffset;
2043 }
2044
HAL_MVOP_GetYBaseAddMultiView(MVOP_3DView eView)2045 MS_PHY HAL_MVOP_GetYBaseAddMultiView(MVOP_3DView eView)
2046 {
2047 MS_PHY u64YOffset = 0;
2048 switch(eView)
2049 {
2050 case E_MVOP_MAIN_VIEW:
2051 u64YOffset = HAL_ReadByte(VOP_JPG_YSTR0_L)&0xff;
2052 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR0_L+1))<<8)&0xff00);
2053 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR0_L+2))<<16)&0xff0000);
2054 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
2055 break;
2056 case E_MVOP_2ND_VIEW:
2057 u64YOffset = HAL_ReadByte(VOP_JPG_YSTR1_L)&0xff;
2058 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR1_L+1))<<8)&0xff00);
2059 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR1_L+2))<<16)&0xff0000);
2060 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR1_L+3))<<24)&0x7000000);
2061 break;
2062 default:
2063 u64YOffset = 0;
2064 break;
2065 }
2066 return u64YOffset;
2067 }
2068
HAL_MVOP_GetUVBaseAddMultiView(MVOP_3DView eView)2069 MS_PHY HAL_MVOP_GetUVBaseAddMultiView(MVOP_3DView eView)
2070 {
2071 MS_PHY u64UVOffset = 0;
2072 switch(eView)
2073 {
2074 case E_MVOP_MAIN_VIEW:
2075 u64UVOffset = HAL_ReadByte(VOP_JPG_UVSTR0_L)&0xff;
2076 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR0_L+1))<<8)&0xff00);
2077 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR0_L+2))<<16)&0xff0000);
2078 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
2079 break;
2080 case E_MVOP_2ND_VIEW:
2081 u64UVOffset = HAL_ReadByte(VOP_JPG_UVSTR1_L)&0xff;
2082 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR1_L+1))<<8)&0xff00);
2083 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR1_L+2))<<16)&0xff0000);
2084 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR1_L+3))<<24)&0x7000000);
2085 break;
2086 default:
2087 u64UVOffset = 0;
2088 break;
2089 }
2090 return u64UVOffset;
2091 }
2092
HAL_MVOP_Set3DLRAltOutput_VHalfScaling(MS_BOOL bEnable)2093 MS_BOOL HAL_MVOP_Set3DLRAltOutput_VHalfScaling(MS_BOOL bEnable)
2094 {
2095 MS_BOOL bEnDualBuff = bEnable ? ENABLE : DISABLE; //enable dual buffer
2096 MS_BOOL bEnSWDualBuff = bEnable ? DISABLE : ENABLE; //buffer controlled by HK instead of FW
2097 MS_BOOL bEnMirrMaskBase = bEnable ? DISABLE : ENABLE; //do not mask LSB
2098 MS_BOOL bEnHwFldBase = bEnable ? DISABLE : ENABLE; //hardware calculate field jump base address
2099
2100 if (g_pHalMVOPCtx == NULL)
2101 {
2102 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2103 return FALSE;
2104 }
2105 //Set 0x27[2] = 1 (enable SW dual buffer mode)
2106 HAL_WriteRegBit(VOP_REG_WR, bEnDualBuff, VOP_BUF_DUAL);
2107
2108 //Set 0x38[8] = 0 (use SW dual buffer mode)
2109 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_H, bEnSWDualBuff, VOP_INFO_FROM_CODEC_DUAL_BUFF);
2110
2111 //Set 0x3b[7] = 0 (use MVD/HVD firmware send base)
2112 HAL_WriteRegBit(VOP_MIRROR_CFG, bEnMirrMaskBase, VOP_MASK_BASE_LSB);
2113
2114 //Set 0x3b[5] = 0 (hardware calculate field jump base address)
2115 HAL_WriteRegBit(VOP_MIRROR_CFG, bEnHwFldBase, VOP_HW_FLD_BASE);
2116
2117 g_pHalMVOPCtx->b3DLRAltOutput = bEnable;
2118 return TRUE;
2119 }
2120
HAL_MVOP_Set3DLRAltOutput(MS_BOOL bEnable)2121 MS_BOOL HAL_MVOP_Set3DLRAltOutput(MS_BOOL bEnable)
2122 {
2123 //Set 0x3C[2] = 1 (enable 3D L/R dual buffer line alternative output)
2124 //it works when 0x3C[0] = 1
2125 HAL_WriteRegBit(VOP_MULTI_WIN_CFG0, bEnable, VOP_LR_LA_OUT);
2126 // bw saving not support: LA/SBS
2127 HAL_WriteRegBit(VOP_REG_DUMMY, 0, VOP_420_BW_SAVE);
2128 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
2129 HAL_MVOP_LoadReg();
2130
2131 g_pHalMVOPCtx->b3DLRAltOutput = bEnable;
2132 return TRUE;
2133 }
2134
HAL_MVOP_Set3DLRAltSBSOutput(MS_BOOL bEnable)2135 MS_BOOL HAL_MVOP_Set3DLRAltSBSOutput(MS_BOOL bEnable)
2136 {
2137 //it works when 0x3C[0] = 1 and 0x3C[2] = 1
2138 //Set 0x3C[3] = 1 (3D L/R line alternative read, side-by-side output)
2139 HAL_WriteRegBit(VOP_MULTI_WIN_CFG0, bEnable, VOP_LR_LA2SBS_OUT);
2140 g_pHalMVOPCtx->b3DLRAltSBSOutput = bEnable;
2141 return TRUE;
2142 }
2143
HAL_MVOP_Get3DLRAltOutput(void)2144 MS_BOOL HAL_MVOP_Get3DLRAltOutput(void)
2145 {
2146 if (g_pHalMVOPCtx == NULL)
2147 {
2148 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2149 return FALSE;
2150 }
2151 return g_pHalMVOPCtx->b3DLRAltOutput;
2152 }
2153
HAL_MVOP_Get3DLRAltSBSOutput(void)2154 MS_BOOL HAL_MVOP_Get3DLRAltSBSOutput(void)
2155 {
2156 return g_pHalMVOPCtx->b3DLRAltSBSOutput;
2157 }
2158
HAL_MVOP_GetOutput3DType(void)2159 EN_MVOP_Output_3D_TYPE HAL_MVOP_GetOutput3DType(void)
2160 {
2161 EN_MVOP_Output_3D_TYPE en3DType = E_MVOP_OUTPUT_3D_NONE;
2162 if(g_pHalMVOPCtx->b3DLRMode)
2163 {
2164 if(g_pHalMVOPCtx->b3DLRAltSBSOutput)
2165 {
2166 en3DType = E_MVOP_OUTPUT_3D_SBS;
2167 }
2168 else
2169 {
2170 en3DType = E_MVOP_OUTPUT_3D_TB;
2171 }
2172 }
2173 else if(g_pHalMVOPCtx->b3DLRAltOutput)
2174 {
2175 en3DType = E_MVOP_OUTPUT_3D_LA;
2176 }
2177 return en3DType;
2178 }
2179
HAL_MVOP_Set3DLR2ndCfg(MS_BOOL bEnable)2180 MS_BOOL HAL_MVOP_Set3DLR2ndCfg(MS_BOOL bEnable)
2181 {
2182 //Set 0x3c[7] as 1 to enable
2183 HAL_WriteRegBit(VOP_MULTI_WIN_CFG0, bEnable, VOP_LR_DIFF_SIZE);
2184 return TRUE;
2185 }
2186
HAL_MVOP_Get3DLR2ndCfg(void)2187 MS_BOOL HAL_MVOP_Get3DLR2ndCfg(void)
2188 {
2189 MS_BOOL bEnable = FALSE;
2190 if (VOP_LR_DIFF_SIZE == (VOP_LR_DIFF_SIZE & HAL_ReadRegBit(VOP_MULTI_WIN_CFG0, VOP_LR_DIFF_SIZE)))
2191 {
2192 bEnable = TRUE;
2193 }
2194 return bEnable;
2195 }
2196
HAL_MVOP_GetMirrorMode(MVOP_DevID eID)2197 MVOP_DrvMirror HAL_MVOP_GetMirrorMode(MVOP_DevID eID)
2198 {
2199 MVOP_DrvMirror enMirror = E_VOPMIRROR_NONE;
2200 if (g_pHalMVOPCtx == NULL)
2201 {
2202 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2203 return FALSE;
2204 }
2205 switch(eID)
2206 {
2207 case E_MVOP_DEV_0:
2208 if(g_pHalMVOPCtx->bMirrorModeVer && g_pHalMVOPCtx->bMirrorModeHor)
2209 {
2210 enMirror = E_VOPMIRROR_HVBOTH;
2211 }
2212 else if(g_pHalMVOPCtx->bMirrorModeHor)
2213 {
2214 enMirror = E_VOPMIRROR_HORIZONTALL;
2215 }
2216 else if(g_pHalMVOPCtx->bMirrorModeVer)
2217 {
2218 enMirror = E_VOPMIRROR_VERTICAL;
2219 }
2220 break;
2221 case E_MVOP_DEV_1:
2222 #if MVOP_SUPPORT_SUB
2223 if(g_pHalMVOPCtx->bSubMirrorModeVer &&g_pHalMVOPCtx-> bSubMirrorModeHor)
2224 {
2225 enMirror = E_VOPMIRROR_HVBOTH;
2226 }
2227 else if(g_pHalMVOPCtx->bSubMirrorModeHor)
2228 {
2229 enMirror = E_VOPMIRROR_HORIZONTALL;
2230 }
2231 else if(g_pHalMVOPCtx->bSubMirrorModeVer)
2232 {
2233 enMirror = E_VOPMIRROR_VERTICAL;
2234 }
2235 #endif
2236 break;
2237 default:
2238 break;
2239 }
2240 return enMirror;
2241 }
2242
HAL_MVOP_SetVerDup(MS_BOOL bEnable)2243 MS_BOOL HAL_MVOP_SetVerDup(MS_BOOL bEnable)
2244 {
2245 HAL_WriteRegBit(VOP_CTRL0, bEnable, BIT3);// V line duplicate
2246 return TRUE;
2247 }
2248
HAL_MVOP_GetVerDup(void)2249 MS_BOOL HAL_MVOP_GetVerDup(void)
2250 {
2251 return (HAL_ReadRegBit(VOP_CTRL0, BIT3) == BIT3);
2252 }
2253
HAL_MVOP_SetVerx4Dup(MS_BOOL bEnable)2254 MS_BOOL HAL_MVOP_SetVerx4Dup(MS_BOOL bEnable)
2255 {
2256 HAL_WriteRegBit(VOP_CTRL0, bEnable, BIT3);// x4 duplicate should raise V line duplicate first
2257 HAL_WriteRegBit(VOP_RGB_FMT, bEnable, BIT3);// V line x4 duplicate
2258 return TRUE;
2259 }
2260
HAL_MVOP_SetHorx4Dup(MS_BOOL bEnable)2261 MS_BOOL HAL_MVOP_SetHorx4Dup(MS_BOOL bEnable)
2262 {
2263 HAL_WriteRegBit(VOP_CTRL0, bEnable, BIT2);// x4 duplicate should raise H pixel duplicate first
2264 HAL_WriteRegBit(VOP_RGB_FMT, bEnable, BIT2);// H line x4 duplicate
2265 return TRUE;
2266 }
2267
HAL_MVOP_GetVerx4Dup(void)2268 MS_BOOL HAL_MVOP_GetVerx4Dup(void)
2269 {
2270 return ((HAL_ReadRegBit(VOP_RGB_FMT, BIT3) & HAL_ReadRegBit(VOP_CTRL0, BIT3)) == BIT3);
2271 }
2272
HAL_MVOP_GetHorx4Dup(void)2273 MS_BOOL HAL_MVOP_GetHorx4Dup(void)
2274 {
2275 return ((HAL_ReadRegBit(VOP_RGB_FMT, BIT2) & HAL_ReadRegBit(VOP_CTRL0, BIT2)) == BIT2);
2276 }
2277
HAL_MVOP_GetTopVStart(MVOP_DevID eID)2278 MS_U16 HAL_MVOP_GetTopVStart(MVOP_DevID eID)
2279 {
2280 MS_U16 u16TopVStart = 0;
2281 switch(eID)
2282 {
2283 case E_MVOP_DEV_0:
2284 u16TopVStart = HAL_Read2Byte(VOP_IMG_VSTR0)&0x1fff;
2285 break;
2286 case E_MVOP_DEV_1:
2287 #if MVOP_SUPPORT_SUB
2288 u16TopVStart = HAL_Read2Byte(SUB_REG(VOP_IMG_VSTR0))&0x1fff;
2289 #endif
2290 break;
2291 default:
2292 break;
2293 }
2294 return u16TopVStart;
2295 }
2296
HAL_MVOP_GetBottomVStart(MVOP_DevID eID)2297 MS_U16 HAL_MVOP_GetBottomVStart(MVOP_DevID eID)
2298 {
2299 MS_U16 u16BotVStart = 0;
2300 switch(eID)
2301 {
2302 case E_MVOP_DEV_0:
2303 u16BotVStart = HAL_Read2Byte(VOP_IMG_VSTR1)&0x1fff;
2304 break;
2305 case E_MVOP_DEV_1:
2306 #if MVOP_SUPPORT_SUB
2307 u16BotVStart = HAL_Read2Byte(SUB_REG(VOP_IMG_VSTR1))&0x1fff;
2308 #endif
2309 break;
2310 default:
2311 break;
2312 }
2313 return u16BotVStart;
2314 }
2315
HAL_MVOP_GetVCount(MVOP_DevID eID)2316 MS_U16 HAL_MVOP_GetVCount(MVOP_DevID eID)
2317 {
2318 MS_U16 u16VCount = 0;
2319 switch(eID)
2320 {
2321 case E_MVOP_DEV_0:
2322 u16VCount = HAL_Read2Byte(VOP_DEBUG_2A)&0x1fff;
2323 break;
2324 case E_MVOP_DEV_1:
2325 #if MVOP_SUPPORT_SUB
2326 u16VCount = HAL_Read2Byte(SUB_REG(VOP_DEBUG_2A))&0x1fff;
2327 #endif
2328 break;
2329 default:
2330 break;
2331 }
2332 return u16VCount;
2333 }
2334
HAL_MVOP_SetVC1RangeMap(MVOP_DevID eID,MVOP_VC1RangeMapInfo * stVC1RangeMapInfo)2335 MS_BOOL HAL_MVOP_SetVC1RangeMap(MVOP_DevID eID, MVOP_VC1RangeMapInfo *stVC1RangeMapInfo)
2336 {
2337 MS_U32 u8Luma = 0;
2338 MS_U32 u8Chroma = 0;
2339
2340 if (stVC1RangeMapInfo == NULL)
2341 {
2342 MVOP_DBG(MVOP_PRINTF("%s stBaseAddInfo is NULL pointer\n", __FUNCTION__);)
2343 return FALSE;
2344 }
2345
2346 // Luma value
2347 u8Luma = stVC1RangeMapInfo->u8LumaValue;
2348 // Chroma value
2349 u8Chroma = stVC1RangeMapInfo->u8ChromaValue;
2350
2351 switch(eID)
2352 {
2353 case E_MVOP_DEV_0:
2354 //set VC1 Luma value
2355 if(stVC1RangeMapInfo->bIsEnableLuma)
2356 {
2357 HAL_WriteRegBit(VOP_RAMAP_LUMA, 1, BIT7);
2358 HAL_WriteByteMask(VOP_RAMAP_LUMA, u8Luma, VOP_RAMAP_LUMA_VAL);
2359 }
2360 else //disable
2361 {
2362 HAL_WriteRegBit(VOP_RAMAP_LUMA, 0, BIT7);
2363 }
2364
2365 //set VC1 Chroma value
2366 if(stVC1RangeMapInfo->bIsEnableChroma)
2367 {
2368 HAL_WriteRegBit(VOP_RAMAP_CHROMA, 1, BIT7);
2369 HAL_WriteByteMask(VOP_RAMAP_CHROMA, u8Chroma, VOP_RAMAP_CHROMA_VAL);
2370 }
2371 else
2372 {
2373 HAL_WriteRegBit(VOP_RAMAP_CHROMA, 0, BIT7);
2374 }
2375 break;
2376 case E_MVOP_DEV_1:
2377 #if MVOP_SUPPORT_SUB
2378 //set VC1 Luma value
2379 if(stVC1RangeMapInfo->bIsEnableLuma)
2380 {
2381 HAL_WriteRegBit(SUB_REG(VOP_RAMAP_LUMA), 1, BIT7);
2382 HAL_WriteByteMask(SUB_REG(VOP_RAMAP_LUMA), u8Luma, VOP_RAMAP_LUMA_VAL);
2383 }
2384 else //disable
2385 {
2386 HAL_WriteRegBit(SUB_REG(VOP_RAMAP_LUMA), 0, BIT7);
2387 }
2388
2389 //set VC1 Chroma value
2390 if(stVC1RangeMapInfo->bIsEnableChroma)
2391 {
2392 HAL_WriteRegBit(SUB_REG(VOP_RAMAP_CHROMA), 1, BIT7);
2393 HAL_WriteByteMask(SUB_REG(VOP_RAMAP_CHROMA), u8Chroma, VOP_RAMAP_CHROMA_VAL);
2394 }
2395 else
2396 {
2397 HAL_WriteRegBit(SUB_REG(VOP_RAMAP_CHROMA), 0, BIT7);
2398 }
2399 #endif
2400 break;
2401 default:
2402 break;
2403 }
2404 return TRUE;
2405 }
2406
2407 MS_U16 g_u16SetStartX = 0;
2408 MS_U16 g_u16SetStartY = 0;
2409 MS_BOOL g_bIsY4Align = 0;
2410
HAL_MVOP_SetStartX(MVOP_DevID eID,MS_U16 u16XPos)2411 void HAL_MVOP_SetStartX(MVOP_DevID eID, MS_U16 u16XPos)
2412 {
2413 switch(eID)
2414 {
2415 case E_MVOP_DEV_0:
2416 #if 0 //tv setting
2417 u16XPos = ALIGN_UPTO_2(u16XPos);
2418 HAL_WriteByte(VOP_REG_CROP_HSTART, u16XPos & 0xff);
2419 HAL_WriteByte((VOP_REG_CROP_HSTART + 1),((u16XPos) >> (8)) & (0x1f));
2420 if(0 == u16XPos)
2421 {
2422 g_pHalMVOPCtx->u16CropXStart = 0;
2423 }
2424 else
2425 {
2426 g_pHalMVOPCtx->u16CropXStart += u16XPos;
2427 }
2428 #endif
2429 if(g_pHalMVOPCtx == NULL)
2430 {
2431 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2432 return;
2433 }
2434 u16XPos = ALIGN_UPTO_2(u16XPos);
2435 g_pHalMVOPCtx->u16CropXStart = u16XPos;
2436 HAL_WriteByte(VOP_REG_CROP_HSTART, u16XPos);
2437 HAL_WriteByteMask((VOP_REG_CROP_HSTART + 1),((u16XPos) >> (8)) & (0x1f), 0x1f);
2438 // Write trigger
2439 HAL_MVOP_LoadReg();
2440 break;
2441 case E_MVOP_DEV_1:
2442 #if MVOP_SUPPORT_SUB
2443 #if 0 //tv setting
2444 u16XPos = ALIGN_UPTO_2(u16XPos);
2445 HAL_WriteByte(SUB_REG(VOP_REG_CROP_HSTART), u16XPos & 0xff);
2446 HAL_WriteByte(SUB_REG((VOP_REG_CROP_HSTART + 1)),((u16XPos) >> (8)) & (0x1f));
2447 if(0 == u16XPos)
2448 {
2449 g_pHalMVOPCtx->u16SubCropXStart = 0;
2450 }
2451 else
2452 {
2453 g_pHalMVOPCtx->u16SubCropXStart += u16XPos;
2454 }
2455 #endif
2456 u16XPos = ALIGN_UPTO_2(u16XPos);
2457 g_pHalMVOPCtx->u16SubCropXStart = u16XPos;
2458 HAL_WriteByte(SUB_REG(VOP_REG_CROP_HSTART), u16XPos);
2459 HAL_WriteByteMask(SUB_REG(VOP_REG_CROP_HSTART + 1),((u16XPos) >> (8)) & (0x1f), 0x1f);
2460 // Write trigger
2461 HAL_MVOP_SubLoadReg();
2462 #endif
2463 break;
2464 default:
2465 break;
2466 }
2467 }
2468
2469
HAL_MVOP_SetStartY(MVOP_DevID eID,MS_U16 u16YPos,MS_BOOL bIsInterlace)2470 void HAL_MVOP_SetStartY(MVOP_DevID eID, MS_U16 u16YPos, MS_BOOL bIsInterlace)
2471 {
2472 switch(eID)
2473 {
2474 case E_MVOP_DEV_0:
2475 #if 0
2476 HAL_WriteByteMask(VOP_REG_CROP_VSTART, u16YPos & 0xff, 0xff);
2477 HAL_WriteByteMask((VOP_REG_CROP_VSTART + 1), ((u16YPos) >> (8)) & (0x1f), 0x1f);
2478 if(0 == u16YPos)
2479 {
2480 g_pHalMVOPCtx->u16CropYStart = 0;
2481 }
2482 else
2483 {
2484 g_pHalMVOPCtx->u16CropYStart += u16YPos;
2485 }
2486 #endif
2487 if(g_pHalMVOPCtx == NULL)
2488 {
2489 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2490 return;
2491 }
2492 g_pHalMVOPCtx->u16CropYStart = u16YPos;
2493 if(u16YPos == 0)
2494 u16YPos |= 0x6000;
2495 else
2496 u16YPos |= 0x2000;
2497
2498 HAL_WriteByte(VOP_REG_CROP_VSTART, u16YPos);
2499 HAL_WriteByteMask((VOP_REG_CROP_VSTART + 1), ((u16YPos) >> (8)) & (0x7f), 0x7f);
2500 // Write trigger
2501 HAL_MVOP_LoadReg();
2502 break;
2503 case E_MVOP_DEV_1:
2504 #if MVOP_SUPPORT_SUB
2505 #if 0
2506 HAL_WriteByteMask(SUB_REG(VOP_REG_CROP_VSTART), u16YPos & 0xff, 0xff);
2507 HAL_WriteByteMask(SUB_REG((VOP_REG_CROP_VSTART + 1)), ((u16YPos) >> (8)) & (0x1f), 0x1f);
2508 if(0 == u16YPos)
2509 {
2510 g_pHalMVOPCtx->u16SubCropYStart = 0;
2511 }
2512 else
2513 {
2514 g_pHalMVOPCtx->u16SubCropYStart += u16YPos;
2515 }
2516 #endif
2517 if(g_pHalMVOPCtx == NULL)
2518 {
2519 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2520 return;
2521 }
2522 g_pHalMVOPCtx->u16SubCropYStart = u16YPos;
2523 if(u16YPos == 0)
2524 u16YPos |= 0x6000;
2525 else
2526 u16YPos |= 0x2000;
2527
2528 HAL_WriteByte(SUB_REG(VOP_REG_CROP_VSTART), u16YPos);
2529 HAL_WriteByteMask(SUB_REG(VOP_REG_CROP_VSTART + 1), ((u16YPos) >> (8)) & (0x7f), 0x7f);
2530 // Write trigger
2531 HAL_MVOP_SubLoadReg();
2532 #endif
2533 break;
2534 default:
2535 break;
2536 }
2537 }
2538
2539 //-----------------------------------------
2540 //STB chip set crop size is from image (0,0) ,
2541 //including startx,y
2542 //Kano hw crop before mirror
2543 //-----------------------------------------
HAL_MVOP_SetPicWidthMinus(MVOP_DevID eID,MS_U16 u16XSizes,MS_U16 u16Width)2544 void HAL_MVOP_SetPicWidthMinus(MVOP_DevID eID, MS_U16 u16XSizes, MS_U16 u16Width)
2545 {
2546 EN_MVOP_Output_3D_TYPE en3DType = E_MVOP_OUTPUT_3D_NONE;
2547
2548 switch(eID)
2549 {
2550 if(g_pHalMVOPCtx == NULL)
2551 {
2552 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2553 return;
2554 }
2555 case E_MVOP_DEV_0:
2556 if(0 == u16XSizes)
2557 {
2558 g_pHalMVOPCtx->u16CropXSize = 0;
2559 }
2560 else
2561 {
2562 u16XSizes = u16XSizes + 1 - g_pHalMVOPCtx->u16CropXStart ;
2563 u16XSizes = ALIGN_UPTO_2(u16XSizes);
2564 g_pHalMVOPCtx->u16CropXSize = u16XSizes;
2565 }
2566 en3DType = HAL_MVOP_GetOutput3DType();
2567 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] 3D FORMAT = %d\n",en3DType);)
2568 if(en3DType == E_MVOP_OUTPUT_3D_SBS)
2569 {
2570 u16XSizes = u16XSizes >> 1;
2571 }
2572 HAL_WriteByte(VOP_REG_CROP_HSIZE, u16XSizes);
2573 HAL_WriteByteMask((VOP_REG_CROP_HSIZE + 1), ((u16XSizes) >> (8)) & (0x1f), 0x1f);
2574 // Write trigger
2575 HAL_MVOP_LoadReg();
2576 break;
2577 case E_MVOP_DEV_1:
2578 #if MVOP_SUPPORT_SUB
2579
2580 if(0 == u16XSizes)
2581 {
2582 g_pHalMVOPCtx->u16SubCropXSize = 0;
2583 }
2584 else
2585 {
2586 u16XSizes = u16XSizes + 1 - g_pHalMVOPCtx->u16SubCropXStart ;
2587 u16XSizes = ALIGN_UPTO_2(u16XSizes);
2588 g_pHalMVOPCtx->u16SubCropXSize = u16XSizes;
2589 }
2590 en3DType = HAL_MVOP_SubGetOutput3DType();
2591 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] 3D FORMAT = %d\n",en3DType);)
2592 if(en3DType == E_MVOP_OUTPUT_3D_SBS)
2593 {
2594 u16XSizes = u16XSizes >> 1;
2595 }
2596 HAL_WriteByte(SUB_REG(VOP_REG_CROP_HSIZE), u16XSizes);
2597 HAL_WriteByteMask(SUB_REG(VOP_REG_CROP_HSIZE + 1), ((u16XSizes) >> (8)) & (0x1f), 0x1f);
2598 // Write trigger
2599 HAL_MVOP_SubLoadReg();
2600 #endif
2601 break;
2602 default:
2603 break;
2604 }
2605 }
2606
HAL_MVOP_SetPicHeightMinus(MVOP_DevID eID,MS_U16 u16YSizes,MS_U16 u16Height)2607 void HAL_MVOP_SetPicHeightMinus(MVOP_DevID eID, MS_U16 u16YSizes, MS_U16 u16Height)
2608 {
2609 EN_MVOP_Output_3D_TYPE en3DType = E_MVOP_OUTPUT_3D_NONE;
2610
2611 switch(eID)
2612 {
2613 if(g_pHalMVOPCtx == NULL)
2614 {
2615 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2616 return;
2617 }
2618 case E_MVOP_DEV_0:
2619 if(0 == u16YSizes)
2620 {
2621 g_pHalMVOPCtx->u16CropYSize = 0;
2622 }
2623 else
2624 {
2625 u16YSizes = u16YSizes + 1 - g_pHalMVOPCtx->u16CropYStart ;
2626 g_pHalMVOPCtx->u16CropYSize = u16YSizes;
2627 }
2628 en3DType = HAL_MVOP_GetOutput3DType();
2629 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] 3D FORMAT = %d\n",en3DType);)
2630 if((en3DType == E_MVOP_OUTPUT_3D_TB) || (en3DType == E_MVOP_OUTPUT_3D_LA))
2631 {
2632 u16YSizes = u16YSizes >> 1;
2633 }
2634 HAL_WriteByte(VOP_REG_CROP_VSIZE, u16YSizes);
2635 HAL_WriteByteMask((VOP_REG_CROP_VSIZE + 1), ((u16YSizes) >> (8)) & (0x1f), 0x1f);
2636 // Write trigger
2637 HAL_MVOP_LoadReg();
2638 break;
2639 case E_MVOP_DEV_1:
2640 #if MVOP_SUPPORT_SUB
2641 if(0 == u16YSizes)
2642 {
2643 g_pHalMVOPCtx->u16CropYSize = 0;
2644 }
2645 else
2646 {
2647 u16YSizes = u16YSizes + 1 - g_pHalMVOPCtx->u16CropYStart ;
2648 g_pHalMVOPCtx->u16CropYSize = u16YSizes;
2649 }
2650 en3DType = HAL_MVOP_SubGetOutput3DType();
2651 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] 3D FORMAT = %d\n",en3DType);)
2652 if((en3DType == E_MVOP_OUTPUT_3D_TB) || (en3DType == E_MVOP_OUTPUT_3D_LA))
2653 {
2654 u16YSizes = u16YSizes >> 1;
2655 }
2656 HAL_WriteByte(SUB_REG(VOP_REG_CROP_VSIZE), u16YSizes);
2657 HAL_WriteByteMask(SUB_REG(VOP_REG_CROP_VSIZE + 1), ((u16YSizes) >> (8)) & (0x1f), 0x1f);
2658 // Write trigger
2659 HAL_MVOP_SubLoadReg();
2660
2661 #endif
2662 break;
2663 default:
2664 break;
2665 }
2666 }
2667
2668
2669 /******************************************************************************/
2670 /// Set MVOP Saving BW Mode
2671 /// @ Napoli this command should be set after MDrv_MVOP_SetOutputCfg
2672 /******************************************************************************/
HAL_MVOP_Set420BWSaveMode(MS_BOOL bEnable)2673 MS_BOOL HAL_MVOP_Set420BWSaveMode(MS_BOOL bEnable)
2674 {
2675 MS_BOOL bValue = FALSE;
2676
2677 //hw limtation: 3DLA/3DSBS/422/p mode in, i mode out/i mode in, p mode out(only need to check in MCU mode)
2678 bValue = (g_pHalMVOPCtx->b3DLRAltSBSOutput || g_pHalMVOPCtx->b3DLRAltOutput /*|| g_pHalMVOPCtx->b3DLRMode*/ || g_pHalMVOPCtx->bIs422 );
2679
2680 if(bValue)
2681 {
2682 MVOP_DBG(MVOP_PRINTF("%s Hit the limitation of saving bw, disable BW Saving mode\n", __FUNCTION__);)
2683 HAL_WriteRegBit(VOP_REG_DUMMY, 0, VOP_420_BW_SAVE);
2684 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
2685 HAL_MVOP_LoadReg();
2686 return FALSE;
2687 }
2688 else
2689 {
2690 HAL_WriteRegBit(VOP_REG_DUMMY, bEnable, VOP_420_BW_SAVE);
2691 if( g_pHalMVOPCtx->b3DLRMode == FALSE)
2692 {
2693 HAL_WriteRegBit(VOP_REG_BW_SAVE, bEnable, VOP_420_BW_SAVE_EX);
2694 }
2695
2696 HAL_MVOP_LoadReg();
2697 return TRUE;
2698 }
2699 }
2700
HAL_MVOP_SetEVDYUVBaseAdd(MVOP_EVDBaseAddInput * stEVDBaseAddInfo)2701 MS_BOOL HAL_MVOP_SetEVDYUVBaseAdd(MVOP_EVDBaseAddInput *stEVDBaseAddInfo)
2702 {
2703 //----------------------------------------------------
2704 // Set MSB YUV Address
2705 //----------------------------------------------------
2706
2707 MS_PHY u64tmp = 0;
2708
2709 if (g_pHalMVOPCtx == NULL)
2710 {
2711 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2712 return FALSE;
2713 }
2714 // Y offset
2715 u64tmp = stEVDBaseAddInfo->u32MSBYOffset >> 3;
2716 if ( !stEVDBaseAddInfo->bProgressive)
2717 { //Refine Y offset for interlace repeat bottom field
2718 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
2719 {
2720 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2721 u64tmp += 2;
2722 }
2723 else
2724 {
2725 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2726 }
2727 }
2728 HAL_WriteByte(VOP_JPG_YSTR0_L, u64tmp & 0xff);
2729 HAL_WriteByte((VOP_JPG_YSTR0_L+1), (u64tmp >> 8) & 0xff);
2730 HAL_WriteByte((VOP_JPG_YSTR0_H), (u64tmp >> 16) & 0xff);
2731 HAL_WriteByte((VOP_JPG_YSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2732
2733 if (!stEVDBaseAddInfo->bProgressive )
2734 { //Y offset of bottom field if interlace
2735 HAL_WriteByte(VOP_JPG_YSTR1_L, u64tmp & 0xff);
2736 HAL_WriteByte((VOP_JPG_YSTR1_L+1), (u64tmp >> 8) & 0xff);
2737 HAL_WriteByte((VOP_JPG_YSTR1_H), (u64tmp >> 16) & 0xff);
2738 HAL_WriteByte((VOP_JPG_YSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2739 }
2740
2741 if (stEVDBaseAddInfo->b422Pack)
2742 {
2743 stEVDBaseAddInfo->u32MSBUVOffset = stEVDBaseAddInfo->u32MSBYOffset + 16; //add 16 for 128bit; add 8 for 64bit
2744 }
2745 // UV offset
2746 u64tmp = stEVDBaseAddInfo->u32MSBUVOffset >> 3;
2747 if( !stEVDBaseAddInfo->bProgressive )
2748 { //Refine UV offset for interlace repeat bottom field
2749 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
2750 {
2751 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2752 u64tmp += 2;
2753 }
2754 else
2755 {
2756 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2757 }
2758 }
2759 HAL_WriteByte(VOP_JPG_UVSTR0_L, u64tmp & 0xff);
2760 HAL_WriteByte((VOP_JPG_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
2761 HAL_WriteByte((VOP_JPG_UVSTR0_H), (u64tmp >> 16) & 0xff);
2762 HAL_WriteByte((VOP_JPG_UVSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2763
2764 if( !stEVDBaseAddInfo->bProgressive )
2765 { //UV offset of bottom field if interlace
2766 HAL_WriteByte(VOP_JPG_UVSTR1_L, u64tmp & 0xff);
2767 HAL_WriteByte((VOP_JPG_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
2768 HAL_WriteByte((VOP_JPG_UVSTR1_H), (u64tmp >> 16) & 0xff);
2769 HAL_WriteByte((VOP_JPG_UVSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2770 }
2771
2772 //----------------------------------------------------
2773 // Set MSB YUV Address
2774 //----------------------------------------------------
2775 if(stEVDBaseAddInfo->bEnLSB)
2776 {
2777 //Enable LSB
2778 HAL_WriteRegBit(VOP_EVD_10B_EN, 1, VOP_EVD_10B_Y_EN);
2779 HAL_WriteRegBit(VOP_EVD_10B_EN, 1, VOP_EVD_10B_UV_EN);
2780 HAL_WriteRegBit(VOP_REG_MASK, 0, VOP_LSB_REQ_MASK);
2781
2782 // Y offset
2783 u64tmp = stEVDBaseAddInfo->u32LSBYOffset >> 3;
2784 if ( !stEVDBaseAddInfo->bProgressive)
2785 { //Refine Y offset for interlace repeat bottom field
2786 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
2787 {
2788 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2789 u64tmp += 2;
2790 }
2791 else
2792 {
2793 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2794 }
2795 }
2796 HAL_WriteByte(VOP_LSB_YSTR0_L, u64tmp & 0xff);
2797 HAL_WriteByte((VOP_LSB_YSTR0_L+1), (u64tmp >> 8) & 0xff);
2798 HAL_WriteByte((VOP_LSB_YSTR0_L), (u64tmp >> 16) & 0xff);
2799 HAL_WriteByte((VOP_LSB_YSTR0_L+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2800
2801 if (!stEVDBaseAddInfo->bProgressive )
2802 { //Y offset of bottom field if interlace
2803 HAL_WriteByte(VOP_LSB_YSTR1_L, u64tmp & 0xff);
2804 HAL_WriteByte((VOP_LSB_YSTR1_L+1), (u64tmp >> 8) & 0xff);
2805 HAL_WriteByte((VOP_LSB_YSTR1_H), (u64tmp >> 16) & 0xff);
2806 HAL_WriteByte((VOP_LSB_YSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2807 }
2808
2809 if (stEVDBaseAddInfo->b422Pack)
2810 {
2811 stEVDBaseAddInfo->u32LSBUVOffset = stEVDBaseAddInfo->u32LSBYOffset + 16; //add 16 for 128bit; add 8 for 64bit
2812 }
2813 // UV offset
2814 u64tmp = stEVDBaseAddInfo->u32LSBUVOffset >> 3;
2815 if( !stEVDBaseAddInfo->bProgressive )
2816 { //Refine UV offset for interlace repeat bottom field
2817 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
2818 {
2819 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2820 u64tmp += 2;
2821 }
2822 else
2823 {
2824 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2825 }
2826 }
2827 HAL_WriteByte(VOP_LSB_UVSTR0_L, u64tmp & 0xff);
2828 HAL_WriteByte((VOP_LSB_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
2829 HAL_WriteByte((VOP_LSB_UVSTR0_H), (u64tmp >> 16) & 0xff);
2830 HAL_WriteByte((VOP_LSB_UVSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2831
2832 if( !stEVDBaseAddInfo->bProgressive )
2833 { //UV offset of bottom field if interlace
2834 HAL_WriteByte(VOP_LSB_UVSTR1_L, u64tmp & 0xff);
2835 HAL_WriteByte((VOP_LSB_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
2836 HAL_WriteByte((VOP_LSB_UVSTR1_H), (u64tmp >> 16) & 0xff);
2837 HAL_WriteByte((VOP_LSB_UVSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2838 }
2839 }
2840
2841 return TRUE;
2842 }
2843
2844 /******************************************************************************/
2845 /// Set MVOP repeat previous frame IF VDEC can not finish vsync.
2846 /// this command should be set disable as call VDEC Exit.
2847 /******************************************************************************/
HAL_MVOP_SetRptPreVsyncFrame(MVOP_DevID eID,MS_BOOL bEnable)2848 void HAL_MVOP_SetRptPreVsyncFrame(MVOP_DevID eID, MS_BOOL bEnable)
2849 {
2850 switch(eID)
2851 {
2852 case E_MVOP_DEV_0:
2853 {
2854 g_pHalMVOPCtx->bRptPreVsync = bEnable;
2855 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, BIT3);
2856 break;
2857 }
2858 case E_MVOP_DEV_1:
2859 {
2860 #if MVOP_SUPPORT_SUB
2861 g_pHalMVOPCtx->bSubRptPreVsync = bEnable;
2862 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, BIT3);
2863 #endif
2864 break;
2865 }
2866 default:
2867 MVOP_PRINTF("[Warning] MVOP_DevID not support!\n");
2868 break;
2869 }
2870 }
2871
HAL_MVOP_PowerStateSuspend(void)2872 void HAL_MVOP_PowerStateSuspend(void)
2873 {
2874 MS_BOOL bFirstDrvInstant = FALSE;
2875 MVOP_HalInitCtxResults eRet = _HAL_MVOP_InitContext(&bFirstDrvInstant);
2876 if(eRet == E_MVOP_INIT_FAIL)
2877 {
2878 MVOP_DBG(MVOP_PRINTF("[%s] MVOP Context Init failed!\n",__FUNCTION__);)
2879 return;
2880 }
2881 g_pHalMVOPCtx->bIsInit = 0;
2882 #if MVOP_SUPPORT_SUB
2883 g_pHalMVOPCtx->bSubIsInit = 0;
2884 #endif
2885 }
2886
HAL_MVOP_GetHandShakeMode(MVOP_DevID eID)2887 MVOP_HSMode HAL_MVOP_GetHandShakeMode(MVOP_DevID eID)
2888 {
2889 MVOP_HSMode eRet = E_MVOP_HS_NOT_SUPPORT;
2890
2891 switch(eID)
2892 {
2893 case E_MVOP_DEV_0:
2894 if(HAL_ReadRegBit(VOP_HANDSHAKE, BIT0))
2895 {
2896 eRet = E_MVOP_HS_ENABLE;
2897 }
2898 else
2899 {
2900 eRet = E_MVOP_HS_DISABLE;
2901 }
2902 break;
2903 case E_MVOP_DEV_1:
2904 #if MVOP_SUPPORT_SUB
2905 if(HAL_ReadRegBit(SUB_REG(VOP_HANDSHAKE), BIT0))
2906 {
2907 eRet = E_MVOP_HS_ENABLE;
2908 }
2909 else
2910 {
2911 eRet = E_MVOP_HS_DISABLE;
2912 }
2913 #endif
2914 break;
2915 default:
2916 eRet = E_MVOP_HS_INVALID_PARAM;
2917 break;
2918 }
2919 return eRet;
2920 }
2921
HAL_MVOP_CheckSTCCW(void)2922 MS_BOOL HAL_MVOP_CheckSTCCW(void)
2923 {
2924 MS_U16 u16STC_CW_L = 0;
2925 MS_U16 u16STC_CW_H = 0;
2926 MS_BOOL u16STC_CW_SEL = 0;
2927 MS_BOOL u16TSP_CLK_EN = 0;
2928
2929 u16STC_CW_L = HAL_Read2Byte(REG_STC0_CW_L)&0xffff;
2930 u16STC_CW_H = HAL_Read2Byte(REG_STC0_CW_H)&0xffff;
2931
2932 u16STC_CW_SEL = (HAL_ReadRegBit(REG_STC_CW_SLE_L, BIT1) == BIT1);
2933 u16TSP_CLK_EN = !(HAL_ReadRegBit(REG_TSP_CLK, BIT0) == BIT0);
2934
2935 if((((u16STC_CW_L || u16STC_CW_H) == 0) && (u16STC_CW_SEL == 0)) || ((u16STC_CW_SEL == 1) && (u16TSP_CLK_EN == 0)))
2936 return FALSE;
2937 else
2938 return TRUE;
2939
2940 }
2941
2942 #define MIU1_REG_BASE 0x0600
HAL_MVOP_GetIsMiuIPControl(HALMVOPMIUCLIENTINFO stInfo)2943 MS_BOOL HAL_MVOP_GetIsMiuIPControl(HALMVOPMIUCLIENTINFO stInfo)
2944 {
2945 MS_U32 u32RegMiu = 0;
2946 MS_U16 u16Mask = 0;
2947 MS_BOOL bRet = FALSE;
2948
2949 u32RegMiu = MIU1_REG_BASE + (0xF0+(stInfo.u8Gp * 2));
2950 if(stInfo.u8BitPos < 8)
2951 {
2952 u16Mask = 1<<stInfo.u8BitPos;
2953 }
2954 else
2955 {
2956 u16Mask = 1<<(stInfo.u8BitPos-8);
2957 u32RegMiu += 1;
2958 }
2959 MVOP_DBG(MVOP_PRINTF("[%s] u32RegMiu = 0x%lx, u16Mask = 0x%x\n",__FUNCTION__, u32RegMiu,u16Mask);)
2960 if(HAL_ReadRegBit(u32RegMiu, u16Mask))
2961 {
2962 bRet = TRUE;
2963 }
2964
2965 return bRet;
2966 }
2967
HAL_MVOP_SelMIU(MVOP_DevID eDevID,HALMVOPMIUSEL eMiuMSB0,HALMVOPMIUSEL eMiuMSB1,HALMVOPMIUSEL eMiuLSB0,HALMVOPMIUSEL eMiuLSB1)2968 void HAL_MVOP_SelMIU(MVOP_DevID eDevID, HALMVOPMIUSEL eMiuMSB0, HALMVOPMIUSEL eMiuMSB1, HALMVOPMIUSEL eMiuLSB0, HALMVOPMIUSEL eMiuLSB1)
2969 {
2970 MS_U8 u8MSBVlue = 0;
2971 MS_U8 u8LSBVlue = 0;
2972
2973 if(eMiuMSB0 != eMiuMSB1)
2974 HAL_WriteRegBit(VOP_MIU_SEL, TRUE, BIT0);
2975 else
2976 HAL_WriteRegBit(VOP_MIU_SEL, FALSE, BIT0);
2977
2978 if(eMiuLSB0 != eMiuLSB1)
2979 HAL_WriteRegBit(VOP_MIU_SEL, TRUE, BIT1);
2980 else
2981 HAL_WriteRegBit(VOP_MIU_SEL, FALSE, BIT1);
2982
2983 u8MSBVlue |= (eMiuMSB0 << 4);
2984 u8MSBVlue |= (eMiuMSB1 << 6);
2985
2986 u8LSBVlue |= (eMiuLSB0 << 4);
2987 u8LSBVlue |= (eMiuLSB1 << 6);
2988
2989 switch(eDevID)
2990 {
2991 case E_MVOP_DEV_0:
2992 {
2993 // MSB
2994 HAL_WriteByteMask(VOP_MIU_SEL, u8MSBVlue, VOP_MSB_BUF0_MIU_SEL | VOP_MSB_BUF1_MIU_SEL);
2995 // LSB
2996 HAL_WriteByteMask(VOP_MIU_SEL_LSB, u8LSBVlue, VOP_LSB_BUF0_MIU_SEL | VOP_LSB_BUF1_MIU_SEL);
2997 g_pHalMVOPCtx->u8LumaMIU = eMiuMSB0;
2998 g_pHalMVOPCtx->u8ChromaMIU = eMiuMSB1;
2999 break;
3000 }
3001 #if MVOP_SUPPORT_SUB
3002 case E_MVOP_DEV_1:
3003 {
3004 // MSB
3005 HAL_WriteByteMask(SUB_REG(VOP_MIU_SEL), u8MSBVlue, VOP_MSB_BUF0_MIU_SEL | VOP_MSB_BUF1_MIU_SEL);
3006 // LSB
3007 HAL_WriteByteMask(SUB_REG(VOP_MIU_SEL_LSB), u8LSBVlue, VOP_LSB_BUF0_MIU_SEL | VOP_LSB_BUF1_MIU_SEL);
3008 g_pHalMVOPCtx->u8SubLumaMIU = eMiuMSB0;
3009 g_pHalMVOPCtx->u8SubChromaMIU = eMiuMSB1;
3010 break;
3011 }
3012 #endif
3013 default:
3014 break;
3015 }
3016 }
3017
HAL_MVOP_GetIsOnlyMiuIPControl(void)3018 MS_BOOL HAL_MVOP_GetIsOnlyMiuIPControl(void)
3019 {
3020 return TRUE;
3021 }
3022
HAL_MVOP_SetDefaultClk(MVOP_DevID eDevID)3023 HALMVOPFREQUENCY HAL_MVOP_SetDefaultClk(MVOP_DevID eDevID)
3024 {
3025 HALMVOPFREQUENCY eRet = HALMVOP_160MHZ;
3026 switch(eDevID)
3027 {
3028 case E_MVOP_DEV_0:
3029 {
3030 if(g_pHalMVOPCtx->bIsXcTrig == FALSE)
3031 {
3032 MVOP_PRINTF("[%s] HALMVOP_SYNCMODE\n",__FUNCTION__);
3033 eRet = HALMVOP_SYNCMODE;
3034 }
3035 break;
3036 }
3037 #if MVOP_SUPPORT_SUB
3038 case E_MVOP_DEV_1:
3039 {
3040 if(g_pHalMVOPCtx->bSubIsXcTrig == FALSE)
3041 {
3042 MVOP_PRINTF("[%s] HALMVOP_SYNCMODE\n",__FUNCTION__);
3043 eRet = HALMVOP_SYNCMODE;
3044 }
3045 break;
3046 }
3047 #endif
3048 default:
3049 break;
3050 }
3051
3052 MVOP_PRINTF("[%s] clock = %d\n",__FUNCTION__,eRet);
3053 return eRet;
3054 }
3055
HAL_MVOP_GetMaxFramerate(MVOP_DevID eDevID,MVOP_GetMaxFps * stStreamInfo)3056 void HAL_MVOP_GetMaxFramerate(MVOP_DevID eDevID, MVOP_GetMaxFps* stStreamInfo)
3057 {
3058 MS_U64 u64MaxClk = 0;
3059 MS_U16 u16HsizeTiming = 0;
3060 MS_U16 u16VsizeTiming = 0;
3061
3062 if(NULL == stStreamInfo)
3063 {
3064 MVOP_PRINTF("[%s] Input parameter is NULL!\n",__FUNCTION__);
3065 return;
3066 }
3067
3068 switch(eDevID)
3069 {
3070 case E_MVOP_DEV_0:
3071 #if MVOP_SUPPORT_SUB
3072 case E_MVOP_DEV_1:
3073 #endif
3074 {
3075 if(_HAL_MVOP_IsSupport4k2k2P())
3076 {
3077 u16HsizeTiming = stStreamInfo->u16HSize >> 1;
3078 }
3079 else
3080 {
3081 u16HsizeTiming = stStreamInfo->u16HSize;
3082 u16HsizeTiming = ALIGN_UPTO_2(u16HsizeTiming);
3083 }
3084 if(stStreamInfo->b3DSBS)
3085 {
3086 u16HsizeTiming *= 2;
3087 }
3088 if(stStreamInfo->u16HSize > 720)
3089 {
3090 u16HsizeTiming += MVOP_HBlank_HD;
3091 }
3092 else
3093 {
3094 u16HsizeTiming += MVOP_HBlank_SD;
3095 }
3096
3097 u64MaxClk = HAL_MVOP_GetMaximumClk();
3098 if(stStreamInfo->b3DTB)
3099 {
3100 u16VsizeTiming = stStreamInfo->u16VSize*2 + MVOP_VBlank;
3101 }
3102 else
3103 {
3104 u16VsizeTiming = stStreamInfo->u16VSize + MVOP_VBlank;
3105 }
3106
3107 stStreamInfo->u32Framerate = (u64MaxClk / u16HsizeTiming / u16VsizeTiming)*1000;
3108 }
3109 break;
3110 default:
3111 break;
3112 }
3113
3114 }
3115
HAL_MVOP_GetIsSendingData(MVOP_DevID eDevID)3116 MS_BOOL HAL_MVOP_GetIsSendingData(MVOP_DevID eDevID)
3117 {
3118 MS_U8 u8IsSend = 0;
3119
3120 if(eDevID == E_MVOP_DEV_0)
3121 {
3122 u8IsSend = HAL_ReadByte(VOP_DEBUG_2D_H) & VOP_DMA_STATUS;
3123 if(u8IsSend)
3124 return TRUE;
3125 else
3126 return FALSE;
3127 }
3128 else
3129 {
3130 MVOP_PRINTF("[Warning] not support device %d\n",eDevID);
3131 return FALSE;
3132 }
3133 }
3134
3135 /******************************************************************************/
3136 /// Set MVOP Handshake Mode, XC should be synchronous with MVOP.
3137 /// this command should be before mvop enable.(before 1st frame)
3138 /******************************************************************************/
HAL_MVOP_SetTimingFromXC(MVOP_DevID eID,MS_BOOL bEnable)3139 void HAL_MVOP_SetTimingFromXC(MVOP_DevID eID, MS_BOOL bEnable)
3140 {
3141 switch(eID)
3142 {
3143 MVOP_DBG(MVOP_PRINTF("[MVOP] HAL_MVOP_SetTimingFromXC = %d\n",bEnable);)
3144 case E_MVOP_DEV_0:
3145 {
3146 g_pHalMVOPCtx->bIsXcTrig = bEnable;
3147 if(bEnable)
3148 {
3149 HAL_WriteByteMask(VOP_HANDSHAKE, 0x06, VOP_TRIG_FROM_XC|VOP_VSUNC_FROM_XC);
3150 //HAL_WriteRegBit(VOP_CTRL1, 0, BIT4); // disable inverse the field to IP - not in kano
3151
3152 }
3153 else
3154 {
3155 HAL_WriteByteMask(VOP_HANDSHAKE, 0x00, VOP_TRIG_FROM_XC|VOP_VSUNC_FROM_XC);
3156 //HAL_WriteRegBit(VOP_CTRL1, 1, BIT4); // inverse the field to IP - not in kano
3157 }
3158 HAL_MVOP_LoadReg();
3159 break;
3160 }
3161 case E_MVOP_DEV_1:
3162 {
3163 #if MVOP_SUPPORT_SUB
3164 g_pHalMVOPCtx->bSubIsXcTrig = bEnable;
3165 if(bEnable)
3166 {
3167 HAL_WriteByteMask(SUB_REG(VOP_HANDSHAKE), 0x06, VOP_TRIG_FROM_XC|VOP_VSUNC_FROM_XC);
3168 }
3169 else
3170 {
3171 HAL_WriteByteMask(SUB_REG(VOP_HANDSHAKE), 0x00, VOP_TRIG_FROM_XC|VOP_VSUNC_FROM_XC);
3172 }
3173 HAL_MVOP_SubLoadReg();
3174 #endif
3175 break;
3176 }
3177 default:
3178 MVOP_PRINTF("[Warning] MVOP_DevID not support!\n");
3179 break;
3180 }
3181 }
3182
HAL_MVOP_ResetReg(MVOP_DevID eDevID,MS_U16 u16ECONumber)3183 void HAL_MVOP_ResetReg(MVOP_DevID eDevID, MS_U16 u16ECONumber)
3184 {
3185
3186 switch(eDevID)
3187 {
3188 case E_MVOP_DEV_0:
3189 {
3190 #if ENABLE_3D_LR_MODE
3191 HAL_MVOP_Enable3DLR(DISABLE);
3192 #endif
3193 #if SUPPORT_3DLR_ALT_SBS
3194 HAL_MVOP_Set3DLRAltOutput(DISABLE);
3195 HAL_MVOP_Set3DLRAltSBSOutput(DISABLE);
3196 #endif
3197
3198 /*****************************************************/
3199 // Reset MVOP setting
3200 HAL_WriteByteMask(VOP_TST_IMG, 0x00, BIT2 | BIT1 | BIT0);//reset test pattern or BG
3201 HAL_WriteRegBit(VOP_TST_IMG, BIT6, BIT6);//reset test pattern or BG
3202 HAL_MVOP_Set3DLRAltOutput_VHalfScaling(DISABLE); //reset to default: disable 3D L/R alternative output.
3203 HAL_MVOP_Set3DLR2ndCfg(DISABLE); //reset to default: disable 3D L/R 2nd pitch.
3204 HAL_MVOP_SetRgbFormat(E_MVOP_RGB_NONE); //reset rgb format
3205 HAL_WriteRegBit(VOP_CTRL1, 0, VOP_MVD_VS_MD); //default use original vsync
3206 //stb series: default hsk
3207 //HAL_WriteRegBit(VOP_REG_422_OUT_EN, 1, BIT0); //kano ip2 444
3208 //apple for debug
3209 HAL_WriteRegBit(VOP_HANDSHAKE, 1, VOP_HANDSHAKE_MODE);
3210 g_pHalMVOPCtx->bIsHS = TRUE;
3211 HAL_MVOP_SetTimingFromXC(E_MVOP_DEV_0, TRUE);
3212 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, ENABLE, VOP_HK_MASK); //default hsk mode bk background
3213
3214 // Kano hsk default 2p
3215 HAL_MVOP_SetEnable4k2k2P(TRUE);
3216
3217 HAL_MVOP_SetBlackBG();//set MVOP test pattern to black
3218 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);// clear extend strip len bit by default
3219 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);// set mvop to 128bit_i128 interface
3220 HAL_WriteRegBit(VOP_INPUT_SWITCH1, 0, BIT2|BIT3);// Disable H264 or RM Input
3221
3222 HAL_WriteRegBit(VOP_REG_WR, 0, BIT1);//8*32 tile format
3223 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD);
3224
3225 g_pHalMVOPCtx->bIs422 = 0;// Clear 422 Flag
3226 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, EVD_ENABLE);// EVD mode disable
3227 g_pHalMVOPCtx->bIsH265 = 0;
3228 HAL_WriteRegBit(VOP_INT_TYPE, 0, VOP_EVD_INT_SEP);// Clear evd Flag for interlace mode setting
3229
3230
3231 HAL_WriteRegBit(VOP_REG_MASK, 0, VOP_LSB_REQ_MASK);// EVD 10 bits disable
3232 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_Y_EN);
3233 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_UV_EN);
3234 HAL_WriteRegBit(VOP_UV_SHIFT, 1, VOP_GCLK_MIU_ON);
3235
3236 HAL_WriteRegBit(VOP_REG_DUMMY, 1, VOP_420_BW_SAVE);
3237 HAL_WriteRegBit(VOP_REG_BW_SAVE, 1, VOP_420_BW_SAVE_EX);
3238 HAL_MVOP_LoadReg(); //kano patch, mantis: 0997677
3239 g_pHalMVOPCtx->bNewVSyncMode = FALSE;// Disable New Vsync Mode
3240
3241 /* only for STB DC */
3242 // Handshake mode chip need to set from MVD: Kappa (maybe fix in after project)
3243 HAL_MVOP_SetFDMaskFromMVD(ENABLE);
3244 // Use frame sync (CLK_DC1 domain) to reset CLK_DC0 and CLK_MIU domain every frame
3245 HAL_WriteRegBit(VOP_REG_FRAME_RST+1, 0, BIT7); // reg_frame_rst = 0
3246
3247 // Warning: set from tv, clippers HAL_MVOP_SetFieldInverse(ENABLE, DISABLE);
3248 HAL_MVOP_SetFieldInverse(ENABLE, ENABLE);
3249 // Warning: kappa U02 need to bypass field from mvd to xc for FCR.
3250 HAL_WriteRegBit(VOP_REG_DUMMY_3D_1, 1, VOP_RGB_FILED_BYPASS);
3251
3252 //Change MIU BW Default Value to 0x241C (after Einstein)
3253 //FIFO threshold
3254 HAL_WriteByte(VOP_DMA0, 0x08);
3255 //burst and priority
3256 HAL_WriteByte(VOP_DMA1, 0x22);
3257 HAL_WriteByte(VOP_BURST_CTRL0, 0x02);
3258 HAL_WriteByte(VOP_BURST_CTRL1, 0x00);
3259 HAL_WriteByteMask(VOP_REG_MFDEC_0_L, 0x70, VOP_MF1_BURST|VOP_MF0_BURST|VOP_MFDEC_EN);// Setting MF burst len
3260 // Only for monaco: Disable mfdec setting from wb
3261 HAL_WriteRegBit(VOP_REG_MFDEC_2_L, 1, VOP_MF_FROM_WB);
3262 // All codec use WISHBONE(R2) interface in muji
3263 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 1, VOP_R2_WISHBONE);
3264 // Disable 10 bits from codec
3265 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_H, 0, VOP_INFO_FROM_CODEC_10BIT);
3266 //// clippers crop sw patch /////
3267 HAL_WriteRegBit(VOP_REG_SINGLE_3D_L, 0, VOP_FORCE_SKIP);
3268 HAL_WriteByteMask(VOP_REG_SINGLE_3D_L, 0, VOP_SKIP_SIZE_LVIEW);
3269 HAL_WriteByteMask(VOP_REG_SINGLE_3D_H, 0, VOP_SKIP_SIZE_RVIEW);
3270 HAL_WriteRegBit(VOP_REG_ENABLE_SKIP, 0, VOP_SKIP_LVIEW);
3271 HAL_WriteRegBit(VOP_REG_ENABLE_SKIP, 0, VOP_SKIP_RVIEW);
3272 g_pHalMVOPCtx->u16CropXStart = 0;
3273 g_pHalMVOPCtx->u16CropYStart = 0;
3274 g_pHalMVOPCtx->u16CropXSize = 0;
3275 g_pHalMVOPCtx->u16CropYSize = 0;
3276 g_pHalMVOPCtx->bIsSetCrop = FALSE;
3277 g_pHalMVOPCtx->u32MVOPFixClk = 0;
3278 // MIU select from WB
3279 HAL_WriteByteMask(VOP_INFO_FROM_CODEC_H, 0x30, VOP_INFO_FROM_CODEC_MIU_BUF0_SEL|VOP_INFO_FROM_CODEC_MIU_BUF1_SEL);
3280 HAL_WriteRegBit(VOP_UV_SHIFT, 0, VOP_GCLK_MIU_ON);// yc seperate can not enable
3281 g_pHalMVOPCtx->eInterlaceType = E_MVOP_PRO;
3282 HAL_WriteByte(VOP_REG_BLK_VCNT_L, 0x00);//mantis: 0986938
3283 HAL_WriteByteMask(VOP_REG_BLK_VCNT_H, 0x01, BIT0);
3284 HAL_WriteByteMask(REG_CKG_FBDEC, 0x0, VOP_SEL_CLK_432); //default disable mfdec clock.
3285 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, VOP_TILE_32x32);
3286 HAL_MVOP_LoadReg();
3287 /*****************************************************/
3288 break;
3289 }
3290 #if MVOP_SUPPORT_SUB
3291 case E_MVOP_DEV_1:
3292 {
3293 #if ENABLE_3D_LR_MODE
3294 HAL_MVOP_SubEnable3DLR(DISABLE);
3295 #endif
3296 #if SUPPORT_3DLR_ALT_SBS
3297 HAL_MVOP_SubSet3DLRAltOutput(DISABLE);
3298 HAL_MVOP_SubSet3DLRAltSBSOutput(DISABLE);
3299 #endif
3300 HAL_MVOP_SubEnableMVDInterface(FALSE);
3301
3302 /*****************************************************/
3303 // Reset MVOP setting
3304 HAL_WriteByteMask(SUB_REG(VOP_TST_IMG), 0x00, BIT2 | BIT1 | BIT0);//reset test pattern or BG
3305 HAL_WriteRegBit(SUB_REG(VOP_TST_IMG), BIT6, BIT6);//reset test pattern or BG
3306 HAL_MVOP_SubSetRgbFormat(E_MVOP_RGB_NONE);
3307 HAL_WriteRegBit(SUB_REG(VOP_CTRL1), 0, VOP_MVD_VS_MD); //default use original vsync
3308 //stb series: default hsk
3309 //HAL_WriteRegBit(SUB_REG(VOP_REG_422_OUT_EN), 1, BIT0); //kano ip2 444
3310 HAL_WriteRegBit(SUB_REG(VOP_HANDSHAKE), 1, VOP_HANDSHAKE_MODE);
3311 g_pHalMVOPCtx->bSubIsHS = TRUE;
3312 HAL_MVOP_SetTimingFromXC(E_MVOP_DEV_1, TRUE);
3313 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), ENABLE, VOP_HK_MASK); //default hsk mode bk background
3314 // Kano hsk default 2p
3315 HAL_MVOP_SubSetEnable4k2k2P(TRUE);
3316
3317 // Only for Monaco: Enable deciding bot by top address + 2
3318 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), 1, VOP_FIELD_FROM_ADDR);
3319 HAL_MVOP_SubSetMonoMode(FALSE);// Reset Mono mode
3320 HAL_MVOP_SubSetBlackBG();//set MVOP test pattern to black
3321 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);// clear extend strip len bit by default
3322 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);// set mvop to 128bit_i128 interface
3323 /* only for STB DC */
3324 HAL_MVOP_SubSetFDMaskFromMVD(ENABLE);
3325 // Use frame sync (CLK_DC1 domain) to reset CLK_DC0 and CLK_MIU domain every frame
3326 HAL_WriteRegBit(SUB_REG(VOP_REG_FRAME_RST+1), 0, BIT7); // reg_frame_rst = 0
3327
3328 // Warning: set from tv, clippers HAL_MVOP_SetFieldInverse(ENABLE, DISABLE);
3329 HAL_MVOP_SubSetFieldInverse(ENABLE, ENABLE);
3330 // Warning: kappa U02 need to bypass field from mvd to xc for FCR.
3331 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY_3D_1), 1, VOP_RGB_FILED_BYPASS);
3332
3333 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH1), 0, BIT2|BIT3);// Disable H264 or RM Input
3334 g_pHalMVOPCtx->bSubIs422 = 0;// Clear 422 Flag
3335 g_pHalMVOPCtx->bSubIsH265 = 0;// Clear evd Flag for interlace mode setting
3336 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, EVD_ENABLE);
3337 HAL_WriteRegBit(SUB_REG(VOP_INT_TYPE), 0, VOP_EVD_INT_SEP);
3338
3339 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT1);//8*32 tile format
3340 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD);
3341
3342 HAL_WriteRegBit(SUB_REG(VOP_REG_MASK), 0, VOP_LSB_REQ_MASK);// EVD 10 bits
3343 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 0, VOP_EVD_10B_Y_EN);
3344 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 0, VOP_EVD_10B_UV_EN);
3345 // Disable 420 BW Saving mode
3346 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 1, VOP_420_BW_SAVE);
3347 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 1, VOP_420_BW_SAVE_EX);
3348 HAL_MVOP_SubLoadReg(); //kano patch, mantis: 0997677
3349 // VP9 MODE disable
3350 //HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, VOP_R2_WISHBONE);
3351 HAL_WriteRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), 0, VOP_DRAM_RD_MODE);
3352
3353 g_pHalMVOPCtx->bSubNewVSyncMode = FALSE;// Disable New Vsync Mode
3354 HAL_WriteRegBit(SUB_REG(VOP_INFO_FROM_CODEC_H), 1, VOP_INFO_FROM_CODEC_DS_IDX);// Sub mvop ds idx from DIU
3355 HAL_WriteByteMask(SUB_REG(VOP_REG_MFDEC_0_L), 0x70, VOP_MF1_BURST|VOP_MF0_BURST|VOP_MFDEC_EN);// Setting MF burst len
3356 // Only for monaco: Disable mfdec setting from wb
3357 HAL_WriteRegBit(SUB_REG(VOP_REG_MFDEC_2_L), 1, VOP_MF_FROM_WB);
3358 // All codec use WISHBONE(R2) interface in muji
3359 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 1, VOP_R2_WISHBONE);
3360 // Disable 10 bits from codec
3361 HAL_WriteRegBit(SUB_REG(VOP_INFO_FROM_CODEC_H), 0, VOP_INFO_FROM_CODEC_10BIT);
3362 g_pHalMVOPCtx->u16SubCropXStart = 0;
3363 g_pHalMVOPCtx->u16CropYStart = 0;
3364 g_pHalMVOPCtx->u16CropXSize = 0;
3365 g_pHalMVOPCtx->u16CropYSize = 0;
3366 g_pHalMVOPCtx->bSubIsSetCrop = FALSE;
3367 g_pHalMVOPCtx->u32SubMVOPFixClk = 0;
3368 // MIU select from WB
3369 HAL_WriteByteMask(SUB_REG(VOP_INFO_FROM_CODEC_H), 0x30, VOP_INFO_FROM_CODEC_MIU_BUF0_SEL|VOP_INFO_FROM_CODEC_MIU_BUF1_SEL);
3370 HAL_WriteRegBit(SUB_REG(VOP_UV_SHIFT), 0, VOP_GCLK_MIU_ON);// yc seperate can not enable
3371 g_pHalMVOPCtx->eSubInterlaceType = E_MVOP_PRO;
3372 HAL_WriteByte(SUB_REG(VOP_REG_BLK_VCNT_L), 0x00);//mantis: 0986938
3373 HAL_WriteByteMask(SUB_REG(VOP_REG_BLK_VCNT_H), 0x01, BIT0);
3374 HAL_WriteByteMask(SUB_REG(REG_CKG_FBDEC), 0x0, VOP_SEL_CLK_432); //default disable mfdec clock.
3375 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, VOP_TILE_32x32);
3376 HAL_MVOP_SubLoadReg();
3377 /*****************************************************/
3378 break;
3379 }
3380 #endif
3381 default:
3382 MVOP_PRINTF("[%s] Input Device ID is Error!\n",__FUNCTION__);
3383 break;
3384 }
3385 }
3386
3387 /******************************************************************************/
3388 /// Set MVOP Handshake Mode, XC should be synchronous with MVOP.
3389 /// this command should be before mvop enable.(before 1st frame)
3390 /// kano hsk disable, xc gen timing need to disable.
3391 /******************************************************************************/
HAL_MVOP_SetHandShakeMode(MVOP_DevID eID,MS_BOOL bEnable,MS_U8 u8Framerate)3392 void HAL_MVOP_SetHandShakeMode(MVOP_DevID eID, MS_BOOL bEnable, MS_U8 u8Framerate)
3393 {
3394 switch(eID)
3395 {
3396 case E_MVOP_DEV_0:
3397 {
3398 if(!((bEnable == FALSE) && (g_pHalMVOPCtx->bIsHS == FALSE))) //prevent switch VOP_CTRL0 (mvop enable), for MHEG5 verify
3399 {
3400 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] HAL_MVOP_SetHandShakeMode = %d\n",bEnable);)
3401 HAL_WriteRegBit(VOP_CTRL0, 0, BIT0);
3402 g_pHalMVOPCtx->bIsHS = bEnable;
3403 HAL_WriteRegBit(VOP_HANDSHAKE, bEnable, VOP_HANDSHAKE_MODE);
3404 if(bEnable == FALSE)
3405 {
3406 HAL_MVOP_SetTimingFromXC(E_MVOP_DEV_0, FALSE);
3407 }
3408 HAL_WriteRegBit(VOP_CTRL0, bEnable, BIT4);
3409 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background
3410 HAL_WriteRegBit(VOP_CTRL0, 1, BIT0);
3411 HAL_MVOP_LoadReg();
3412 }
3413 break;
3414 }
3415 case E_MVOP_DEV_1:
3416 {
3417 #if MVOP_SUPPORT_SUB
3418 if(!((bEnable == FALSE) && (g_pHalMVOPCtx->bSubIsHS == FALSE))) //prevent switch VOP_CTRL0 (mvop enable), for MHEG5 verify
3419 {
3420 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 0, BIT0);
3421 g_pHalMVOPCtx->bSubIsHS = bEnable;
3422 HAL_WriteRegBit(SUB_REG(VOP_HANDSHAKE), bEnable, VOP_HANDSHAKE_MODE);
3423 if(bEnable == FALSE)
3424 {
3425 HAL_MVOP_SetTimingFromXC(E_MVOP_DEV_1, FALSE);
3426 }
3427 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), bEnable, BIT4);
3428 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, VOP_HK_MASK); //bk background
3429 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 1, BIT0);
3430 HAL_MVOP_SubLoadReg();
3431 }
3432 #endif
3433 break;
3434 }
3435 default:
3436 MVOP_PRINTF("[Warning] MVOP_DevID not support!\n");
3437 break;
3438 }
3439 }
3440
HAL_MVOP_SetCropforXC(MVOP_DevID eID,MVOP_XCGetCrop * stXCCrop,MS_U16 u16Width,MS_U16 u16Height)3441 void HAL_MVOP_SetCropforXC(MVOP_DevID eID, MVOP_XCGetCrop* stXCCrop, MS_U16 u16Width, MS_U16 u16Height)
3442 {
3443 MVOP_DBG(MVOP_PRINTF("%s [crop info] xst: 0x%x yst: 0x%x xsize: 0x%x ysize: 0x%x Width: 0x%x Height: 0x%x\n", __FUNCTION__,
3444 stXCCrop->u16XStart, stXCCrop->u16XSize, stXCCrop->u16YStart, stXCCrop->u16YSize, u16Width, u16Height);)
3445
3446 EN_MVOP_Output_3D_TYPE en3DType = E_MVOP_OUTPUT_3D_NONE;
3447
3448 switch(eID)
3449 {
3450 case E_MVOP_DEV_0:
3451 {
3452 if((stXCCrop->u16XStart + stXCCrop->u16XSize) > u16Width)
3453 {
3454 MVOP_PRINTF("[Warning] crop x size or start out of boundary.");
3455 return;
3456 }
3457
3458 if((stXCCrop->u16YStart + stXCCrop->u16YSize) > u16Height)
3459 {
3460 MVOP_PRINTF("[Warning] crop y size or start out of boundary.");
3461 return;
3462 }
3463
3464 g_pHalMVOPCtx->u16CropXStart = stXCCrop->u16XStart;
3465 en3DType = HAL_MVOP_GetOutput3DType();
3466 MVOP_DBG(MVOP_PRINTF("%s 3D FORMAT = %d\n", __FUNCTION__, en3DType);)
3467 if(en3DType == E_MVOP_OUTPUT_3D_SBS)
3468 {
3469 stXCCrop->u16XSize = stXCCrop->u16XSize >> 1;
3470 }
3471 g_pHalMVOPCtx->u16CropXSize = stXCCrop->u16XSize;
3472 g_pHalMVOPCtx->u16CropYStart = stXCCrop->u16YStart;
3473 if(stXCCrop->u16YStart == 0)
3474 stXCCrop->u16YStart |= 0x6000;
3475 else
3476 stXCCrop->u16YStart |= 0x2000;
3477
3478 if((en3DType == E_MVOP_OUTPUT_3D_TB) || (en3DType == E_MVOP_OUTPUT_3D_LA))
3479 {
3480 stXCCrop->u16YSize = stXCCrop->u16YSize >> 1;
3481 }
3482 g_pHalMVOPCtx->u16CropYSize = stXCCrop->u16YSize;
3483 break;
3484 }
3485 case E_MVOP_DEV_1:
3486 {
3487 #if MVOP_SUPPORT_SUB
3488
3489 if((stXCCrop->u16XStart + stXCCrop->u16XSize) > u16Width)
3490 {
3491 MVOP_PRINTF("[Warning] crop x size or start out of boundary.");
3492 return;
3493 }
3494
3495 if((stXCCrop->u16YStart + stXCCrop->u16YSize) > u16Height)
3496 {
3497 MVOP_PRINTF("[Warning] crop y size or start out of boundary.");
3498 return;
3499 }
3500
3501 g_pHalMVOPCtx->u16SubCropXStart = stXCCrop->u16XStart;
3502 en3DType = HAL_MVOP_SubGetOutput3DType();
3503 MVOP_DBG(MVOP_PRINTF("%s 3D FORMAT = %d\n", __FUNCTION__, en3DType);)
3504 if(en3DType == E_MVOP_OUTPUT_3D_SBS)
3505 {
3506 stXCCrop->u16XSize = stXCCrop->u16XSize >> 1;
3507 }
3508 g_pHalMVOPCtx->u16SubCropXSize = stXCCrop->u16XSize;
3509 g_pHalMVOPCtx->u16SubCropYStart = stXCCrop->u16YStart;
3510 if(stXCCrop->u16YStart == 0)
3511 stXCCrop->u16YStart |= 0x6000;
3512 else
3513 stXCCrop->u16YStart |= 0x2000;
3514
3515 if((en3DType == E_MVOP_OUTPUT_3D_TB) || (en3DType == E_MVOP_OUTPUT_3D_LA))
3516 {
3517 stXCCrop->u16YSize = stXCCrop->u16YSize >> 1;
3518 }
3519 g_pHalMVOPCtx->u16SubCropYSize = stXCCrop->u16YSize;
3520 #endif
3521 break;
3522 }
3523 default:
3524 MVOP_PRINTF("[Warning] MVOP_DevID not support!\n");
3525 break;
3526 }
3527 MVOP_PRINTF("[Debug][Crop to XC] xsize = %d, ysize = %d, xstart = %d, ystart=%d\n",stXCCrop->u16XSize,stXCCrop->u16YSize,stXCCrop->u16XStart,stXCCrop->u16YStart);
3528 return;
3529 }
3530
3531
3532
HAL_MVOP_SupportFRCOutputFPS(MVOP_DevID eID)3533 MS_BOOL HAL_MVOP_SupportFRCOutputFPS(MVOP_DevID eID)
3534 {
3535 MS_BOOL bRet = FALSE;
3536 switch(eID)
3537 {
3538 case E_MVOP_DEV_0:
3539 bRet = TRUE;
3540 break;
3541 #if MVOP_SUPPORT_SUB
3542 case E_MVOP_DEV_1:
3543 bRet = TRUE;
3544 break;
3545 #endif
3546 default:
3547 break;
3548 }
3549 return bRet;
3550 }
3551
HAL_MVOP_GetIsCurrentHSK(MVOP_DevID eID)3552 MS_BOOL HAL_MVOP_GetIsCurrentHSK(MVOP_DevID eID)
3553 {
3554 MS_BOOL bRet = FALSE;
3555 switch(eID)
3556 {
3557 case E_MVOP_DEV_0:
3558 bRet = g_pHalMVOPCtx->bIsHS;
3559 break;
3560 case E_MVOP_DEV_1:
3561 #if MVOP_SUPPORT_SUB
3562 bRet = g_pHalMVOPCtx->bSubIsHS;
3563 #endif
3564 break;
3565 default:
3566 bRet = E_MVOP_HS_INVALID_PARAM;
3567 break;
3568 }
3569 return bRet;
3570 }
3571
3572
HAL_MVOP_GetIsCurrentXCGenTiming(MVOP_DevID eID)3573 MS_BOOL HAL_MVOP_GetIsCurrentXCGenTiming(MVOP_DevID eID)
3574 {
3575 MS_BOOL bRet = FALSE;
3576 switch(eID)
3577 {
3578 case E_MVOP_DEV_0:
3579 bRet = g_pHalMVOPCtx->bIsXcTrig;
3580 break;
3581 case E_MVOP_DEV_1:
3582 #if MVOP_SUPPORT_SUB
3583 bRet = g_pHalMVOPCtx->bSubIsXcTrig;
3584 #endif
3585 break;
3586 default:
3587 bRet = E_MVOP_HS_INVALID_PARAM;
3588 break;
3589 }
3590 return bRet;
3591 }
3592
HAL_MVOP_SetFixClk(MVOP_DevID eID,MS_U32 u32MVOPClk)3593 HALMVOPFREQUENCY HAL_MVOP_SetFixClk(MVOP_DevID eID, MS_U32 u32MVOPClk)
3594 {
3595 HALMVOPFREQUENCY eRet = HALMVOP_160MHZ;
3596
3597 if(u32MVOPClk > HALMVOP_320MHZ*2)
3598 {
3599 MVOP_PRINTF("[Warning] MVOP clock out of spec(640MHz), set freerun mode.\n");
3600 eRet = HALMVOP_FREERUNMODE;
3601 }
3602 else if(u32MVOPClk <= HALMVOP_320MHZ*2 && u32MVOPClk > HALMVOP_320MHZ)
3603 {
3604 eRet = u32MVOPClk;
3605 }
3606 else if(u32MVOPClk <= HALMVOP_320MHZ && u32MVOPClk > HALMVOP_192MHZ)
3607 {
3608 eRet = u32MVOPClk;
3609 }
3610 else if(u32MVOPClk <= HALMVOP_192MHZ && u32MVOPClk > HALMVOP_160MHZ)
3611 {
3612 eRet = HALMVOP_192MHZ;
3613 }
3614 else if(u32MVOPClk <= HALMVOP_160MHZ && u32MVOPClk > HALMVOP_144MHZ)
3615 {
3616 eRet = HALMVOP_160MHZ;
3617 }
3618 else if(u32MVOPClk <= HALMVOP_144MHZ && u32MVOPClk > HALMVOP_123MHZ)
3619 {
3620 eRet = HALMVOP_144MHZ;
3621 }
3622 else if(u32MVOPClk <= HALMVOP_123MHZ && u32MVOPClk > HALMVOP_108MHZ)
3623 {
3624 eRet = HALMVOP_123MHZ;
3625 }
3626 else
3627 {
3628 eRet = HALMVOP_108MHZ;
3629 }
3630
3631 MVOP_DBG(MVOP_PRINTF("[MVOP] MVOP clock set as %ld\n",eRet););
3632 if(eID == E_MVOP_DEV_0)
3633 {
3634 if(eRet > HALMVOP_192MHZ)
3635 {
3636 g_pHalMVOPCtx->u32MVOPFixClk = HALMVOP_320MHZ;
3637 }
3638 else
3639 {
3640 g_pHalMVOPCtx->u32MVOPFixClk = eRet;
3641 }
3642 }
3643 #if MVOP_SUPPORT_SUB
3644 else if(eID == E_MVOP_DEV_1)
3645 {
3646 if(eRet > HALMVOP_192MHZ)
3647 {
3648 g_pHalMVOPCtx->u32SubMVOPFixClk = HALMVOP_320MHZ;
3649 }
3650 else
3651 {
3652 g_pHalMVOPCtx->u32SubMVOPFixClk = eRet;
3653 }
3654 }
3655 #endif
3656 return eRet;
3657 }
3658
3659
3660 #if 0
3661 void HAL_SetSCFEMIUIPSel(MVOP_SCIPSel *stIPSel)
3662 {
3663 if(NULL == stIPSel)
3664 {
3665 HAL_WriteRegBit(REG_MIU_SEL_FROM_IP, 1, MVOP_MIU_IP_SEL); //mvop
3666 HAL_WriteRegBit(REG_MIU_SEL_FROM_IP, 1, MFDEC0_MIU_IP_SEL); //mfdec0
3667 HAL_WriteRegBit(REG_MIU_SEL_FROM_IP, 1, MFDEC1_MIU_IP_SEL); //mfdec1
3668 }
3669 else
3670 {
3671 HAL_WriteRegBit(REG_MIU_SEL_FROM_IP, stIPSel->bMVOP0, MVOP_MIU_IP_SEL); //mvop
3672 HAL_WriteRegBit(REG_MIU_SEL_FROM_IP, stIPSel->bMFDEC0, MFDEC0_MIU_IP_SEL); //mfdec0
3673 HAL_WriteRegBit(REG_MIU_SEL_FROM_IP, stIPSel->bMFDEC1, MFDEC1_MIU_IP_SEL); //mfdec1
3674 }
3675
3676 }
3677 #endif
3678
HAL_MVOP_SetInterlaceType(MVOP_DevID eDevID,MS_U16 u16ECONumber,MS_U8 u8Interlace)3679 void HAL_MVOP_SetInterlaceType(MVOP_DevID eDevID, MS_U16 u16ECONumber, MS_U8 u8Interlace)
3680 {
3681 MVOP_DBG(MVOP_PRINTF("%s u8Interlace = %d\n", __FUNCTION__ ,u8Interlace);)
3682 switch(u8Interlace)
3683 {
3684 case 0:
3685 g_pHalMVOPCtx->eInterlaceType = E_MVOP_PRO;
3686 break;
3687 case 0x1:
3688 if(g_pHalMVOPCtx->bIsH265)
3689 {
3690 g_pHalMVOPCtx->eInterlaceType = E_MVOP_INT_TB_SEP_FRAME;
3691 }
3692 else
3693 {
3694 g_pHalMVOPCtx->eInterlaceType = E_MVOP_INT_TB_ONE_FRAME;
3695 }
3696 break;
3697 case 0x2:
3698 if(g_pHalMVOPCtx->bIsH265)
3699 {
3700 g_pHalMVOPCtx->eInterlaceType = E_MVOP_INT_TB_ONE_FRAME;
3701 }
3702 else
3703 {
3704 g_pHalMVOPCtx->eInterlaceType = E_MVOP_INT_TB_SEP_FRAME;
3705 }
3706 break;
3707 default:
3708 g_pHalMVOPCtx->eInterlaceType = E_MVOP_PRO;
3709 break;
3710 }
3711
3712 switch(eDevID)
3713 {
3714 case E_MVOP_DEV_0:
3715 if((g_pHalMVOPCtx->eInterlaceType == E_MVOP_INT_TB_SEP_FRAME) && (g_pHalMVOPCtx->bIsH265))
3716 {
3717 HAL_WriteRegBit(VOP_INT_TYPE, 1, VOP_EVD_INT_SEP);
3718 }
3719 else if((g_pHalMVOPCtx->eInterlaceType == E_MVOP_INT_TB_ONE_FRAME) && (g_pHalMVOPCtx->bIsH265))
3720 {
3721 HAL_WriteRegBit(VOP_INT_TYPE, 0, VOP_EVD_INT_SEP);
3722 HAL_WriteRegBit(VOP_MIRROR_CFG, 0, VOP_FIELD_FROM_ADDR);
3723 }
3724 HAL_MVOP_LoadReg();
3725 break;
3726 #if MVOP_SUPPORT_SUB
3727 case E_MVOP_DEV_1:
3728 if((g_pHalMVOPCtx->eSubInterlaceType == E_MVOP_INT_TB_SEP_FRAME) && (g_pHalMVOPCtx->bSubIsH265))
3729 {
3730 HAL_WriteRegBit(SUB_REG(VOP_INT_TYPE), 1, VOP_EVD_INT_SEP);
3731 }
3732 else if((g_pHalMVOPCtx->eSubInterlaceType == E_MVOP_INT_TB_ONE_FRAME) && (g_pHalMVOPCtx->bSubIsH265))
3733 {
3734 HAL_WriteRegBit(SUB_REG(VOP_INT_TYPE), 0, VOP_EVD_INT_SEP);
3735 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), 0, VOP_FIELD_FROM_ADDR);
3736 }
3737 HAL_MVOP_SubLoadReg();
3738 break;
3739 #endif
3740 default:
3741 MVOP_PRINTF("[Warning][%s] MVOP_DevID not support\n",__FUNCTION__);
3742 break;
3743 }
3744 }
3745
3746 #ifdef UFO_MVOP_GET_IS_MVOP_AUTO_GEN_BLACK
HAL_MVOP_GetIsMVOPSupportBLKBackground(MVOP_DevID eID)3747 MS_BOOL HAL_MVOP_GetIsMVOPSupportBLKBackground(MVOP_DevID eID)
3748 {
3749 MS_BOOL bRet = FALSE;
3750 switch(eID)
3751 {
3752 case E_MVOP_DEV_0:
3753 bRet = FALSE;
3754 break;
3755 case E_MVOP_DEV_1:
3756 #if MVOP_SUPPORT_SUB
3757 bRet = FALSE;
3758 #endif
3759 break;
3760 default:
3761 bRet = E_MVOP_HS_INVALID_PARAM;
3762 break;
3763 }
3764 return bRet;
3765 }
3766 #endif
3767
HAL_MVOP_ReadBank(MVOP_DevID eID,MS_U16 u16Length)3768 MS_U16 HAL_MVOP_ReadBank(MVOP_DevID eID ,MS_U16 u16Length)
3769 {
3770 MS_U16 u16Reg = 0;
3771 if(eID == E_MVOP_DEV_0)
3772 {
3773 u16Reg = HAL_Read2Byte(MVOP_REG_BASE + (u16Length << 1));
3774 }
3775 #ifdef MVOP_SUPPORT_SUB
3776 else if(eID == E_MVOP_DEV_1)
3777 {
3778 u16Reg = HAL_Read2Byte(SUB_REG(MVOP_REG_BASE + (u16Length << 1)));
3779 }
3780 #endif
3781 return u16Reg;
3782 }
3783
HAL_MVOP_WriteBank(MVOP_DevID eID,MS_U16 u16Length,MS_U16 u16Data)3784 void HAL_MVOP_WriteBank(MVOP_DevID eID ,MS_U16 u16Length,MS_U16 u16Data)
3785 {
3786 if(eID == E_MVOP_DEV_0)
3787 {
3788 HAL_Write2Byte(MVOP_REG_BASE + (u16Length << 1),u16Data);
3789 }
3790 #ifdef MVOP_SUPPORT_SUB
3791 else if(eID == E_MVOP_DEV_1)
3792 {
3793 HAL_Write2Byte(SUB_REG(MVOP_REG_BASE + (u16Length << 1)),u16Data);
3794 }
3795 #endif
3796 }
3797
HAL_MVOP_ReadClkBank(MS_U16 u16Length)3798 MS_U16 HAL_MVOP_ReadClkBank(MS_U16 u16Length)
3799 {
3800 MS_U16 u16Reg = 0;
3801
3802 if(u16Length < 3) // stc cw
3803 {
3804 u16Reg = HAL_Read2Byte(REG_STC_CW_SLE_L + (u16Length << 1));
3805
3806 }
3807 else if(u16Length < 7) // dc clk
3808 {
3809 u16Length -= 3;
3810 u16Reg = HAL_Read2Byte(REG_CKG_DC0 + (u16Length << 1)); // main/sub sram
3811 }
3812 else // freerun/sync clk
3813 {
3814 u16Length -= 7;
3815 u16Reg = HAL_Read2Byte(REG_UPDATE_DC0_CW + (u16Length << 1));
3816 }
3817
3818 //printk("[read][%x] u16Reg = 0x%x\n",u16Length,u16Reg);
3819 return u16Reg;
3820 }
3821
HAL_MVOP_WriteClkBank(MS_U16 u16Length,MS_U16 u16Data)3822 void HAL_MVOP_WriteClkBank(MS_U16 u16Length,MS_U16 u16Data)
3823 {
3824
3825 //printk("[write][%x] u16Reg = 0x%x\n",u16Length,u16Data);
3826
3827 if(u16Length < 3) // stc cw
3828 {
3829 HAL_Write2Byte(REG_STC_CW_SLE_L + (u16Length << 1), u16Data);
3830 }
3831 else if(u16Length < 7) // dc clk
3832 {
3833 u16Length -= 3;
3834 HAL_Write2Byte(REG_CKG_DC0 + (u16Length << 1), u16Data);
3835 }
3836 else // freerun/sync clk
3837 {
3838 u16Length -= 7;
3839 HAL_Write2Byte(REG_UPDATE_DC0_CW + (u16Length << 1), u16Data);
3840 }
3841 HAL_WriteRegBit(REG_UPDATE_DC0_CW, TRUE, UPDATE_DC0_SYNC_CW);
3842 HAL_WriteRegBit(REG_UPDATE_DC0_CW, FALSE, UPDATE_DC0_SYNC_CW);
3843
3844 }
3845
HAL_MVOP_SetSramPower(MVOP_DevID eID,MS_BOOL bEnable)3846 void HAL_MVOP_SetSramPower(MVOP_DevID eID ,MS_BOOL bEnable)
3847 {
3848 switch(eID)
3849 {
3850 case E_MVOP_DEV_0:
3851 #if MVOP_SUPPORT_SUB
3852 if((bEnable== FALSE) && (g_pHalMVOPCtx->bIsSubEnable == FALSE)) //check sub disable -> mfdec sram disable
3853 {
3854 HAL_WriteRegBit(VOP_DC_STRIP_H, 1, MFDEC_SRAM_SD_MASK);
3855 HAL_WriteRegBit(VOP_DC_STRIP_H, 1, VOP_SRAM_SD_MASK);
3856 }
3857 else
3858 {
3859 HAL_WriteRegBit(VOP_DC_STRIP_H, 0, MFDEC_SRAM_SD_MASK);
3860 HAL_WriteRegBit(VOP_DC_STRIP_H, 0, VOP_SRAM_SD_MASK);
3861 }
3862 #else
3863 HAL_WriteRegBit(VOP_DC_STRIP_H, !bEnable, VOP_SRAM_SD_MASK);
3864 #endif
3865 break;
3866 #if MVOP_SUPPORT_SUB
3867 case E_MVOP_DEV_1:
3868 if((bEnable== FALSE) && (g_pHalMVOPCtx->bIsEnable == FALSE))
3869 {
3870 HAL_WriteRegBit(VOP_DC_STRIP_H, 1, MFDEC_SRAM_SD_MASK);
3871 HAL_WriteRegBit(VOP_DC_STRIP_H, 1, VOP_SRAM_SD_MASK);
3872 HAL_WriteRegBit(SUB_REG(VOP_DC_STRIP_H), 1, VOP_SRAM_SD_MASK);
3873 }
3874 else
3875 {
3876 HAL_WriteRegBit(VOP_DC_STRIP_H, 0, MFDEC_SRAM_SD_MASK);
3877 HAL_WriteRegBit(VOP_DC_STRIP_H, 0, VOP_SRAM_SD_MASK); //main need to enable, if sub enable.
3878 HAL_WriteRegBit(SUB_REG(VOP_DC_STRIP_H), 0, VOP_SRAM_SD_MASK);
3879 }
3880 break;
3881 #endif
3882 default:
3883 break;
3884 }
3885 return;
3886 }
3887
HAL_MVOP_Exit(MVOP_DevID eID)3888 void HAL_MVOP_Exit(MVOP_DevID eID)
3889 {
3890 switch(eID)
3891 {
3892 case E_MVOP_DEV_0:
3893 g_pHalMVOPCtx->bIsInit = 0;
3894 break;
3895 #if MVOP_SUPPORT_SUB
3896 case E_MVOP_DEV_1:
3897 g_pHalMVOPCtx->bSubIsInit = 0;
3898 break;
3899 #endif
3900 default:
3901 break;
3902 }
3903 return;
3904 }
3905
HAL_MVOP_UVSwapEnable(MVOP_DevID eID,MS_BOOL bEnable)3906 void HAL_MVOP_UVSwapEnable(MVOP_DevID eID, MS_BOOL bEnable)
3907 {
3908 switch(eID)
3909 {
3910 case E_MVOP_DEV_0:
3911 HAL_WriteRegBit(VOP_TST_IMG, bEnable, VOP_UV_SWAP);
3912 break;
3913 #if MVOP_SUPPORT_SUB
3914 case E_MVOP_DEV_1:
3915 HAL_WriteRegBit(SUB_REG(VOP_TST_IMG), bEnable, VOP_UV_SWAP);
3916 break;
3917 #endif
3918 default:
3919 break;
3920 }
3921 return;
3922 }
3923
HAL_MVOP_SetECONumber(MS_U16 u16ECOVersion)3924 void HAL_MVOP_SetECONumber(MS_U16 u16ECOVersion)
3925 {
3926 if (g_pHalMVOPCtx == NULL)
3927 {
3928 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
3929 return;
3930 }
3931 g_pHalMVOPCtx->u16ECONum = u16ECOVersion;
3932 MVOP_DBG(MVOP_PRINTF("[%s] version num = %d\n",__FUNCTION__);)
3933 }
3934
HAL_MVOP_SetMFDECInfo(MVOP_DevID eID,HALMVOPMFDECINFO * pMFDECInfo)3935 void HAL_MVOP_SetMFDECInfo(MVOP_DevID eID, HALMVOPMFDECINFO *pMFDECInfo)
3936 {
3937 MS_PHY u64tmp = 0;
3938 MS_U16 u16Hszie, u16Vsize;
3939
3940 switch(eID)
3941 {
3942 case E_MVOP_DEV_0:
3943 {
3944 #if 1
3945 g_pHalMVOPCtx->bIsMCUMfdec = pMFDECInfo->bMFDEC_EN;
3946 if(pMFDECInfo->bMFDEC_EN)
3947 {
3948 HAL_WriteRegBit(VOP_REG_MFDEC_0_L, TRUE, VOP_MFDEC_EN); // enable mfdec
3949 HAL_WriteRegBit(REG_MF_BASIC_L, TRUE, MF_MFDEC_EN); // enable mfdec
3950 HAL_WriteByteMask(REG_MF_BASIC_H, 0x30, (MF_RIU_MODE|MF_RIU1_MODE));
3951
3952 u16Hszie = HAL_Read2Byte(VOP_JPG_HSIZE);
3953 u16Vsize = HAL_Read2Byte(VOP_JPG_VSIZE);
3954 if(pMFDECInfo->u8MFDEC_ID >= HAL_MFDEC_MODULE_CNT)
3955 {
3956 MVOP_PRINTF("[MVOP][ERR] not support mfdec id: %d\n",pMFDECInfo->u8MFDEC_ID);
3957 }
3958 else
3959 {
3960 HAL_WriteRegBit(VOP_REG_MFDEC_0_L, pMFDECInfo->u8MFDEC_ID, VOP_MFDEC_SEL); //select 0/1 mfdec
3961 }
3962 HAL_MVOP_LOAD_MFDEC_TABLE(pMFDECInfo->u8MFDEC_ID);//k6 mcu mode need to use 0x1122 bank
3963 u64tmp = pMFDECInfo->u32BITLEN_FB_ADDR >> 3;
3964 #if 0
3965 HAL_WriteByteMask(VOP_REG_MFDEC_2_L, (pMFDECInfo->u32UNCOMPRESS_MODE << 4), VOP_UNCOMP_MODE);
3966 HAL_Write2Byte(VOP_REG_BITLEN_ADD_L, u64tmp & 0xffff);
3967 HAL_Write2Byte(VOP_REG_BITLEN_ADD_H, (u64tmp >> 16) & 0x3ff);
3968 HAL_WriteByteMask(VOP_REG_MFDEC_2_L, (pMFDECInfo->u8BITLEN_FB_MIU << 2), VOP_BIT_MIU_SEL);
3969 HAL_WriteByte(VOP_REG_MFDEC_BIT_PITCH, pMFDECInfo->u32BITLEN_FB_PITCH);
3970 #endif
3971 HAL_WriteByteMask(REG_MF_BASIC_L, (pMFDECInfo->u32UNCOMPRESS_MODE << 5), MF_UNCOMP_MODE);
3972 HAL_Write2Byte(REG_MF_BT_ADDR_L, u64tmp & 0xffff);
3973 HAL_Write2Byte(REG_MF_BT_ADDR_H, (u64tmp >> 16) & 0x3ff);
3974 HAL_Write2Byte(REG_MF_FB_WIDTH, u16Hszie>>4);
3975 HAL_Write2Byte(REG_MF_FB_HEIGHT, u16Vsize);
3976 HAL_Write2Byte(REG_MF_FB_PITCH, u16Hszie>>3);
3977
3978 HAL_WriteByteMask(REG_MF_MIU, (pMFDECInfo->u8BITLEN_FB_MIU << 4), MF_BITLEN_MIU);
3979 HAL_WriteByteMask(REG_MF_MIU, g_pHalMVOPCtx->u8LumaMIU, MF_LUMA_MIU);
3980 HAL_WriteByteMask(REG_MF_MIU, g_pHalMVOPCtx->u8ChromaMIU<<2, MF_CHROMA_MIU);
3981 HAL_WriteByte(REG_MF_BT_PITCH, pMFDECInfo->u32BITLEN_FB_PITCH);
3982 HAL_WriteRegBit(VOP_REG_MFDEC_5E, pMFDECInfo->bBITLEN_SHT_8, VOP_BITLEN_SHT);
3983 }
3984 else
3985 {
3986 HAL_WriteRegBit(VOP_REG_MFDEC_0_L, FALSE, VOP_MFDEC_EN); // disable mfdec
3987 }
3988 #endif
3989 HAL_MVOP_LoadReg();
3990 }
3991 break;
3992 #if MVOP_SUPPORT_SUB
3993 case E_MVOP_DEV_1:
3994 {
3995 g_pHalMVOPCtx->bSubIsMCUMfdec = pMFDECInfo->bMFDEC_EN;
3996 if(pMFDECInfo->bMFDEC_EN)
3997 {
3998 HAL_WriteRegBit(SUB_REG(VOP_REG_MFDEC_0_L), TRUE, VOP_MFDEC_EN); // enable mfdec
3999 if(pMFDECInfo->u8MFDEC_ID >= HAL_MFDEC_MODULE_CNT)
4000 {
4001 MVOP_PRINTF("[MVOP][ERR] not support mfdec id: %d\n",pMFDECInfo->u8MFDEC_ID);
4002 }
4003 else
4004 {
4005 HAL_WriteRegBit(SUB_REG(VOP_REG_MFDEC_0_L), pMFDECInfo->u8MFDEC_ID, VOP_MFDEC_SEL); //select 0/1 mfdec
4006 }
4007 u64tmp = pMFDECInfo->u32BITLEN_FB_ADDR >> 3;
4008 HAL_WriteByteMask(SUB_REG(VOP_REG_MFDEC_2_L), (pMFDECInfo->u32UNCOMPRESS_MODE << 4), VOP_UNCOMP_MODE);
4009 HAL_Write2Byte(SUB_REG(VOP_REG_BITLEN_ADD_L), u64tmp);
4010 HAL_Write2Byte(SUB_REG(VOP_REG_BITLEN_ADD_H), u64tmp >> 16);
4011 HAL_WriteByteMask(SUB_REG(VOP_REG_MFDEC_2_L), (pMFDECInfo->u8BITLEN_FB_MIU << 2), VOP_BIT_MIU_SEL);
4012 HAL_WriteByte(SUB_REG(VOP_REG_MFDEC_BIT_PITCH), pMFDECInfo->u32BITLEN_FB_PITCH);
4013 HAL_WriteRegBit(SUB_REG(VOP_REG_MFDEC_5E), pMFDECInfo->bBITLEN_SHT_8, VOP_BITLEN_SHT);
4014 }
4015 else
4016 {
4017 HAL_WriteRegBit(SUB_REG(VOP_REG_MFDEC_0_L), FALSE, VOP_MFDEC_EN); // disable mfdec
4018 }
4019 HAL_MVOP_SubLoadReg();
4020 }
4021 break;
4022 #endif
4023 default:
4024 break;
4025 }
4026 return;
4027 }
4028 MS_U16 MFDec_HUFF_Table[MFEDC_TABLE_INDEX_NUM][4] =
4029 {
4030 {0x0000,0x0000,0x0000,0x8080},
4031 {0x0000,0x0000,0x0101,0x8081},
4032 {0x0000,0x0000,0x0000,0x8082},
4033 {0x0000,0x0000,0x0000,0x8083},
4034 {0x0002,0x0002,0x0101,0x8180},
4035 {0x0002,0x0002,0x0000,0x8181},
4036 {0x0000,0x0002,0x0200,0x8182},
4037 {0x0000,0x0001,0x0100,0x8183},
4038 {0x0006,0x0007,0x0302,0x8280},
4039 {0x0006,0x0006,0x0202,0x8281},
4040 {0x0006,0x0006,0x0303,0x8282},
4041 {0x0004,0x0005,0x0302,0x8283},
4042 {0x0000,0x0000,0x0000,0x8380},
4043 {0x000E,0x000E,0x0303,0x8381},
4044 {0x000E,0x000E,0x0404,0x8382},
4045 {0x000C,0x000D,0x0504,0x8383},
4046 {0x0000,0x0000,0x0000,0x8480},
4047 {0x001E,0x001E,0x0404,0x8481},
4048 {0x001E,0x001E,0x0505,0x8482},
4049 {0x001C,0x001D,0x0706,0x8483},
4050 {0x0000,0x0000,0x0000,0x8580},
4051 {0x003E,0x003E,0x0505,0x8581},
4052 {0x003E,0x003E,0x0606,0x8582},
4053 {0x003C,0x003D,0x0908,0x8583},
4054 {0x0000,0x0000,0x0000,0x8680},
4055 {0x007E,0x007F,0x0706,0x8681},
4056 {0x007E,0x007E,0x0707,0x8682},
4057 {0x007C,0x007D,0x0B0A,0x8683},
4058 {0x0000,0x0000,0x0000,0x8780},
4059 {0x0000,0x0000,0x0000,0x8781},
4060 {0x00FE,0x00FE,0x0808,0x8782},
4061 {0x00FC,0x00FD,0x0D0C,0x8783},
4062 {0x0000,0x0000,0x0000,0x8880},
4063 {0x0000,0x0000,0x0000,0x8881},
4064 {0x01FE,0x01FE,0x0909,0x8882},
4065 {0x01FC,0x01FD,0x0F0E,0x8883},
4066 {0x0000,0x0000,0x0000,0x8980},
4067 {0x0000,0x0000,0x0000,0x8981},
4068 {0x0000,0x0000,0x0D00,0x8982},
4069 {0x0000,0x0000,0x0000,0x8983},
4070 {0x0000,0x0000,0x0000,0x8A80},
4071 {0x0000,0x0000,0x0000,0x8A81},
4072 {0x07FC,0x07FD,0x0B0A,0x8A82},
4073 {0x0000,0x0000,0x0000,0x8A83},
4074 {0x0000,0x0000,0x0000,0x8B80},
4075 {0x0000,0x0000,0x0000,0x8B81},
4076 {0x0FFC,0x0FFF,0x0F0C,0x8B82},
4077 {0x0FF0,0x0FFF,0x1F10,0x8B83},
4078 };
HAL_MVOP_LOAD_MFDEC_TABLE(MS_U8 mfdec_id)4079 void HAL_MVOP_LOAD_MFDEC_TABLE(MS_U8 mfdec_id)
4080 {
4081 MS_U8 u8index=0;
4082
4083 //MVOP_PRINTF("[apple] HAL_MVOP_LOAD_MFDEC_TABLE\n");
4084
4085 //HAL_Write2ByteMask(REG_MF_BASIC_H, 0x3000 , BMASK(15:0));
4086 HAL_Write2ByteMask(REG_MF_CW_LEN2(mfdec_id), 0x0007 , BMASK(11:0));
4087 HAL_Write2ByteMask(REG_MF_CW_LEN3(mfdec_id), 0x007F , BMASK(11:0));
4088 HAL_Write2ByteMask(REG_MF_CW_LEN4(mfdec_id), 0x0DFE , BMASK(11:0));
4089 HAL_Write2ByteMask(REG_MF_CW_LEN5(mfdec_id), 0x09FE , BMASK(11:0));
4090
4091 for (u8index=0;u8index< MFEDC_TABLE_INDEX_NUM; u8index++)
4092 {
4093 HAL_Write2ByteMask(REG_MF_CW_BASE(mfdec_id), MFDec_HUFF_Table[u8index][0] , BMASK(15:0));
4094 HAL_Write2ByteMask(REG_MF_CW_MAX(mfdec_id), MFDec_HUFF_Table[u8index][1] , BMASK(15:0));
4095 HAL_Write2ByteMask(REG_MF_SYMB_BASE(mfdec_id), MFDec_HUFF_Table[u8index][2] , BMASK(15:0));
4096 HAL_Write2ByteMask(REG_MF_HUF_TAB(mfdec_id), MFDec_HUFF_Table[u8index][3] , BMASK(15:0));
4097 }
4098 //HAL_Write2ByteMask(REG_MF_BASIC_H, 0x0000 , BMASK(15:0));
4099 }
4100
4101 /////////////////////// Sub MVOP ////////////////////////
4102 #if MVOP_SUPPORT_SUB
HAL_MVOP_SubRegSetBase(MS_VIRT u32Base)4103 void HAL_MVOP_SubRegSetBase(MS_VIRT u32Base)
4104 {
4105 u32RiuBaseAdd = u32Base;
4106 }
4107
HAL_MVOP_SubInitMirrorMode(MS_BOOL bMir)4108 void HAL_MVOP_SubInitMirrorMode(MS_BOOL bMir)
4109 {
4110 //set bit[3:7] to support mirror mode
4111 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bMir, VOP_MIRROR_CFG_ENABLE);
4112 }
4113
HAL_MVOP_SubInit(void)4114 void HAL_MVOP_SubInit(void)
4115 {
4116 MVOP_HalInitCtxResults eRet;
4117 MS_BOOL pbFirstDrvInstant;
4118
4119 eRet = _HAL_MVOP_InitContext(&pbFirstDrvInstant);
4120 if(eRet == E_MVOP_INIT_FAIL)
4121 {
4122 MVOP_DBG(MVOP_PRINTF("[%s] MVOP Context Init failed!\n",__FUNCTION__);)
4123 return;
4124 }
4125 else if(eRet == E_MVOP_INIT_ALREADY_EXIST)
4126 {
4127 if(g_pHalMVOPCtx->bSubIsInit)
4128 {
4129 MVOP_DBG(MVOP_PRINTF("[%s] Sub MVOP Context has Initialized!\n",__FUNCTION__);)
4130 return;
4131 }
4132 }
4133 HAL_MVOP_SubInitMirrorMode(TRUE);
4134 //Enable dynamic clock gating
4135 //Note: cannot enable VOP_GCLK_VCLK_ON, or hsync cannot be sent out.
4136 HAL_WriteByteMask(SUB_REG(VOP_GCLK), VOP_GCLK_MIU_ON, VOP_GCLK_MIU_ON|VOP_GCLK_VCLK_ON);
4137 g_pHalMVOPCtx->bSubIsInit = 1;
4138 }
4139
HAL_MVOP_SubSetVerticalMirrorMode(MS_BOOL bEnable)4140 void HAL_MVOP_SubSetVerticalMirrorMode(MS_BOOL bEnable)
4141 {
4142 if (g_pHalMVOPCtx == NULL)
4143 {
4144 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4145 return;
4146 }
4147 if (VOP_MIRROR_CFG_ENABLE != HAL_ReadRegBit(SUB_REG(VOP_MIRROR_CFG), VOP_MIRROR_CFG_ENABLE))
4148 {
4149 //MVOP_PRINTF("Setup mirror mode\n");
4150 HAL_MVOP_SubInitMirrorMode(TRUE);
4151 }
4152
4153 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bEnable, VOP_MIRROR_CFG_VEN);
4154 g_pHalMVOPCtx->bSubMirrorModeVer = bEnable;
4155 }
4156
HAL_MVOP_SubSetHorizontallMirrorMode(MS_BOOL bEnable)4157 void HAL_MVOP_SubSetHorizontallMirrorMode(MS_BOOL bEnable)
4158 {
4159 if (g_pHalMVOPCtx == NULL)
4160 {
4161 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4162 return;
4163 }
4164 if (VOP_MIRROR_CFG_ENABLE != HAL_ReadRegBit(SUB_REG(VOP_MIRROR_CFG), VOP_MIRROR_CFG_ENABLE))
4165 {
4166 //MVOP_PRINTF("Setup mirror mode\n");
4167 HAL_MVOP_SubInitMirrorMode(TRUE);
4168 }
4169
4170 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bEnable, VOP_MIRROR_CFG_HEN);
4171 g_pHalMVOPCtx->bSubMirrorModeHor = bEnable;
4172 }
4173
HAL_MVOP_SubSetFieldInverse(MS_BOOL b2MVD,MS_BOOL b2IP)4174 void HAL_MVOP_SubSetFieldInverse(MS_BOOL b2MVD, MS_BOOL b2IP)
4175 {
4176 // Set fld inv & ofld_inv
4177 HAL_WriteRegBit(SUB_REG(VOP_CTRL0+1), b2MVD, BIT3); //inverse the field to MVD
4178 HAL_WriteRegBit(SUB_REG(VOP_CTRL0+1), b2IP, BIT4); //inverse the field to IP
4179 }
4180
HAL_MVOP_SubSetChromaWeighting(MS_BOOL bEnable)4181 void HAL_MVOP_SubSetChromaWeighting(MS_BOOL bEnable)
4182 {
4183 HAL_WriteRegBit(SUB_REG(VOP_REG_WEIGHT_CTRL), bEnable, BIT1);
4184 }
4185
4186 //load new value into active registers 0x20-0x26
HAL_MVOP_SubLoadReg(void)4187 void HAL_MVOP_SubLoadReg(void)
4188 {
4189 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT0);
4190 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT0);
4191
4192 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT4);
4193 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT4);
4194 }
4195
HAL_MVOP_SubSetMIUReqMask(MS_BOOL bEnable)4196 void HAL_MVOP_SubSetMIUReqMask(MS_BOOL bEnable)
4197 {
4198 #if 0
4199 if (bEnable)
4200 { // mask MVOP2MI to protect MIU
4201 HAL_MIU_SubSetReqMask(SUBMVOP_R, 1);
4202 MsOS_DelayTask(1);
4203 }
4204 else
4205 { // unmask MVOP2MI
4206 MsOS_DelayTask(1);
4207 HAL_MIU_SubSetReqMask(SUBMVOP_R, 0);
4208 }
4209 #endif
4210 MS_U8 u8Miu;
4211 if(HAL_MVOP_GetIsOnlyMiuIPControl() == TRUE)
4212 {
4213 // mask msb mvop
4214 u8Miu = (HAL_ReadByte(SUB_REG(VOP_MIU_SEL)) & VOP_MSB_BUF0_MIU_SEL) >> 4;
4215 }
4216 else
4217 {
4218 u8Miu = SUBVOP_ON_MIU1;
4219 }
4220 eMIUClientID eClientID = MIU_CLIENT_MVOP1_R;
4221 //MVOP_PRINTF("Enter %s bEnable=%x ReqMask=0x%x, 0x%x, u8Miu=%x\n", __FUNCTION__, bEnable,
4222 // HAL_ReadByte(0x1266), HAL_ReadByte(0x0666), u8Miu);
4223
4224 if (bEnable)
4225 { // mask MVOP2MI to protect MIU
4226 MDrv_MIU_MaskReq(u8Miu, eClientID);
4227 MsOS_DelayTask(1);
4228 }
4229 else
4230 { // unmask MVOP2MI
4231 MsOS_DelayTask(1);
4232 MDrv_MIU_UnMaskReq(u8Miu, eClientID);
4233 }
4234
4235 //MVOP_PRINTF(">Exit %s bEnable=%x ReqMask=0x%x, 0x%x, u8Miu=%x\n", __FUNCTION__, bEnable,
4236 // HAL_ReadByte(0x1266), HAL_ReadByte(0x0666), u8Miu);
4237 }
4238
HAL_MVOP_SubRst(void)4239 void HAL_MVOP_SubRst(void)
4240 {
4241 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 0, BIT0);
4242 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 1, BIT0);
4243
4244 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 0, BIT4);
4245 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 1, BIT4);
4246
4247 g_pHalMVOPCtx->bIsSubEnable = 1;
4248 }
4249
HAL_MVOP_SubEnable(MS_BOOL bEnable,MS_U8 u8Framerate)4250 void HAL_MVOP_SubEnable(MS_BOOL bEnable, MS_U8 u8Framerate)
4251 {
4252 MS_U8 regval;
4253
4254 regval = HAL_ReadByte(SUB_REG(VOP_CTRL0));
4255
4256 if ( bEnable )
4257 {
4258 regval |= 0x1;
4259 }
4260 else
4261 {
4262 regval &= ~0x1;
4263 }
4264
4265 g_pHalMVOPCtx->bIsSubEnable = bEnable;
4266
4267 HAL_WriteByte(SUB_REG(VOP_CTRL0), regval);
4268 }
4269
HAL_MVOP_SubGetEnableState(void)4270 MS_BOOL HAL_MVOP_SubGetEnableState(void)
4271 {
4272 return (HAL_ReadRegBit(SUB_REG(VOP_CTRL0), BIT0));
4273 }
4274
HAL_MVOP_SubGetMaxFreerunClk()4275 HALMVOPFREQUENCY HAL_MVOP_SubGetMaxFreerunClk()
4276 {
4277 return HALMVOP_160MHZ;
4278 }
4279
HAL_MVOP_SubGet4k2kClk()4280 HALMVOPFREQUENCY HAL_MVOP_SubGet4k2kClk()
4281 {
4282 return HALMVOP_320MHZ;
4283 }
4284
4285 //FIXME
HAL_MVOP_SubSetFrequency(HALMVOPFREQUENCY enFrequency)4286 void HAL_MVOP_SubSetFrequency(HALMVOPFREQUENCY enFrequency)
4287 {
4288 // clear
4289 HAL_WriteByteMask(REG_CKG_SUB_DC0, 0, CKG_SUB_DC0_MASK);
4290 switch(enFrequency)
4291 {
4292 case HALMVOP_SYNCMODE:
4293 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_SYNCHRONOUS, CKG_SUB_DC0_MASK);
4294 break;
4295 case HALMVOP_FREERUNMODE:
4296 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_FREERUN, CKG_SUB_DC0_MASK);
4297 break;
4298 case HALMVOP_320MHZ:
4299 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_320MHZ, CKG_SUB_DC0_MASK);
4300 break;
4301 case HALMVOP_108MHZ:
4302 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_108MHZ, CKG_SUB_DC0_MASK);
4303 break;
4304 case HALMVOP_123MHZ:
4305 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_123MHZ, CKG_SUB_DC0_MASK);
4306 break;
4307 case HALMVOP_144MHZ:
4308 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_144MHZ, CKG_SUB_DC0_MASK);
4309 break;
4310 case HALMVOP_160MHZ:
4311 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_160MHZ, CKG_SUB_DC0_MASK);
4312 break;
4313 case HALMVOP_192MHZ:
4314 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_192MHZ, CKG_SUB_DC0_MASK);
4315 break;
4316 default:
4317 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_160MHZ, CKG_SUB_DC0_MASK);
4318 MVOP_PRINTF("Attention! In HAL_MVOP_SetFrequency default 160MHz!\n");
4319 break;
4320 }
4321 }
4322
HAL_MVOP_SubSetOutputInterlace(MS_BOOL bEnable,MS_U16 u16ECOVersion)4323 void HAL_MVOP_SubSetOutputInterlace(MS_BOOL bEnable, MS_U16 u16ECOVersion)
4324 {
4325 MS_U8 regval;
4326
4327 regval = HAL_ReadByte(SUB_REG(VOP_CTRL0));
4328
4329 if ( bEnable )
4330 {
4331 regval |= 0x80;
4332 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
4333 if(u16ECOVersion == 0)
4334 {
4335 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x40, CKG_DC1_SRAM);//Dc0 enable & dc0_mfdec_en =0 57[3:0]= 0x4, others 57[3:0]=0x0
4336 }
4337 }
4338 else
4339 {
4340 regval &= ~0x80;
4341 }
4342
4343 //Kano patch for GOP
4344 HAL_WriteRegBit(SUB_REG(VOP_TST_IMG), bEnable, VOP_SC_VS_INV);
4345 HAL_WriteByte(SUB_REG(VOP_CTRL0), regval);
4346 }
4347
HAL_MVOP_SubSetPattern(MVOP_Pattern enMVOPPattern)4348 void HAL_MVOP_SubSetPattern(MVOP_Pattern enMVOPPattern)
4349 {
4350 HAL_WriteByteMask(SUB_REG(VOP_TST_IMG), enMVOPPattern, BIT2 | BIT1 | BIT0);
4351 }
4352
HAL_MVOP_SubSetTileFormat(MVOP_TileFormat eTileFmt)4353 MS_BOOL HAL_MVOP_SubSetTileFormat(MVOP_TileFormat eTileFmt)
4354 {
4355 if (eTileFmt == E_MVOP_TILE_8x32)
4356 {
4357 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT1);
4358 return TRUE;
4359 }
4360 else if (eTileFmt == E_MVOP_TILE_16x32)
4361 {
4362 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT1);
4363 return TRUE;
4364 }
4365 else if (eTileFmt == E_MVOP_TILE_32x16)
4366 {
4367 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT1);
4368 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 1, EVD_ENABLE);
4369 return TRUE;
4370 }
4371 else if (eTileFmt == E_MVOP_TILE_32x32)
4372 {
4373 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT1);
4374 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, EVD_ENABLE);
4375 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 1, VOP_TILE_32x32);
4376 return TRUE;
4377 }
4378 else
4379 {
4380 return FALSE;
4381 }
4382 }
4383
HAL_MVOP_SubSetRgbFormat(MVOP_RgbFormat eRgbFmt)4384 MS_BOOL HAL_MVOP_SubSetRgbFormat(MVOP_RgbFormat eRgbFmt)
4385 {
4386 MS_BOOL bRet = FALSE;
4387
4388 if (g_pHalMVOPCtx == NULL)
4389 {
4390 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4391 return FALSE;
4392 }
4393 if (eRgbFmt == E_MVOP_RGB_NONE)
4394 {
4395 HAL_WriteByteMask(SUB_REG(VOP_RGB_FMT), 0, VOP_RGB_FMT_SEL);
4396 bRet = TRUE;
4397 }
4398 else if (eRgbFmt == E_MVOP_RGB_565)
4399 {
4400 HAL_WriteByteMask(SUB_REG(VOP_RGB_FMT), VOP_RGB_FMT_565, VOP_RGB_FMT_SEL);
4401 bRet = TRUE;
4402 }
4403 else if (eRgbFmt == E_MVOP_RGB_888)
4404 {
4405 HAL_WriteByteMask(SUB_REG(VOP_RGB_FMT), VOP_RGB_FMT_888, VOP_RGB_FMT_SEL);
4406 bRet = TRUE;
4407 }
4408
4409 if (bRet == TRUE)
4410 {
4411 g_pHalMVOPCtx->eSubRgbFmt = eRgbFmt;
4412 }
4413 return bRet;
4414 }
4415
HAL_MVOP_SubSetBlackBG(void)4416 void HAL_MVOP_SubSetBlackBG(void)
4417 {
4418 MS_U8 regval;
4419
4420 //set MVOP test pattern to black
4421 HAL_WriteByte(SUB_REG(VOP_TST_IMG + 1), 0x10);
4422 HAL_WriteByte(SUB_REG(VOP_U_PAT ), 0x80);
4423 HAL_WriteByte(SUB_REG(VOP_U_PAT + 1), 0x80);
4424
4425 regval = HAL_ReadByte(SUB_REG(VOP_TST_IMG));
4426 HAL_WriteByteMask(SUB_REG(VOP_TST_IMG), 0x02, BIT2 | BIT1 | BIT0);
4427 HAL_WriteByteMask(SUB_REG(VOP_TST_IMG), 0x00, BIT2 | BIT1 | BIT0);
4428 HAL_WriteByteMask(SUB_REG(VOP_TST_IMG), regval, BIT2 | BIT1 | BIT0);
4429 }
4430
HAL_MVOP_SubSetCropWindow(MVOP_InputCfg * pparam)4431 void HAL_MVOP_SubSetCropWindow(MVOP_InputCfg *pparam)
4432 {
4433 #if 1
4434 UNUSED(pparam);
4435 #else // enable it when test code is ready
4436 MS_U32 x, y;
4437 MS_U32 u32offset;
4438
4439 if(!pparam)
4440 {
4441 return;
4442 }
4443 //set MVOP test pattern to black
4444 HAL_MVOP_SubSetBlackBG();
4445 #if 0
4446 if((pparam->enVideoType == MVOP_H264) && (pparam->u16StripSize == 1920))
4447 {
4448 pparam->u16StripSize = 1952;
4449 }
4450 #endif
4451 if((pparam->enVideoType == MVOP_MPG) || (pparam->enVideoType == MVOP_MPEG4))
4452 {
4453 pparam->u16CropX = (pparam->u16CropX >> 3) << 3; // 8 bytes align
4454 pparam->u16CropY = (pparam->u16CropY >> 6) << 6; // 64 bytes align
4455 }
4456 else if((pparam->enVideoType == MVOP_H264) || (pparam->enVideoType == MVOP_RM))
4457 {
4458 pparam->u16CropX = (pparam->u16CropX >> 4) << 4; // 16 bytes align
4459 pparam->u16CropY = (pparam->u16CropY >> 6) << 6; // 64 bytes align
4460 }
4461 else
4462 {
4463 MS_ASSERT(0);
4464 }
4465
4466 x = (MS_U32)pparam->u16CropX;
4467 y = (MS_U32)pparam->u16CropY;
4468
4469 // y offset
4470 u32offset = ((y * pparam->u16StripSize + (x << 5)) >> 3);
4471 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L ), (MS_U8)(u32offset));
4472 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L + 1), (MS_U8)(u32offset >> 8));
4473 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_H ), (MS_U8)(u32offset >> 16));
4474 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_H + 1), (MS_U8)((u32offset >> 24) & VOP_YUV_STR_HIBITS));
4475
4476 // uv offset
4477 u32offset = ((y >> 1) * pparam->u16StripSize + (x << 5)) >> 3;
4478 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L ), (MS_U8)(u32offset));
4479 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L + 1), (MS_U8)(u32offset >> 8));
4480 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_H ), (MS_U8)(u32offset >> 16));
4481 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_H + 1), (MS_U8)((u32offset >> 24) & VOP_YUV_STR_HIBITS));
4482
4483 pparam->u16CropWidth= (pparam->u16CropWidth >> 3) << 3;
4484 // HSize, VSize
4485 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE ), LOWBYTE(pparam->u16CropWidth ));
4486 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE + 1), HIGHBYTE(pparam->u16CropWidth ));
4487 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE ), LOWBYTE(pparam->u16CropHeight));
4488 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE + 1), HIGHBYTE(pparam->u16CropHeight ));
4489
4490 HAL_WriteByteMask(SUB_REG(VOP_MPG_JPG_SWITCH), BIT0, BIT1|BIT0);
4491
4492 // clear extend strip len bit by default
4493 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
4494 if((pparam->enVideoType == MVOP_MPG) || (pparam->enVideoType == MVOP_MPEG4))
4495 {
4496 // Disable H264 or RM Input
4497 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH), 0, BIT2|BIT3);
4498 //8*32 tile format
4499 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT1);
4500 }
4501 else if((pparam->enVideoType == MVOP_H264) || (pparam->enVideoType == MVOP_RM))
4502 {
4503 //16*32 tile format
4504 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT1);
4505 // SVD mode enable
4506 HAL_WriteByteMask(SUB_REG(VOP_INPUT_SWITCH), BIT3, BIT2|BIT3);
4507 // set mvop to 128bit_i128 interface
4508 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
4509 }
4510 HAL_MVOP_SubLoadReg();
4511 #endif
4512 }
4513
HAL_MVOP_SubSetRepeatField(MVOP_RptFldMode eMode)4514 void HAL_MVOP_SubSetRepeatField(MVOP_RptFldMode eMode)
4515 {
4516 if (g_pHalMVOPCtx == NULL)
4517 {
4518 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4519 return;
4520 }
4521 g_pHalMVOPCtx->eSubRepeatField = eMode;
4522 }
4523
HAL_MVOP_SubSetFDMaskFromMVD(MS_BOOL bEnable)4524 void HAL_MVOP_SubSetFDMaskFromMVD(MS_BOOL bEnable)
4525 {
4526 HAL_WriteRegBit(SUB_REG(VOP_REG_FD_MASK_SEL), bEnable, BIT5); //FD MASK from MVD
4527 }
4528
HAL_MVOP_SubSetInputMode(VOPINPUTMODE mode,MVOP_InputCfg * pparam,MS_U16 u16ECOVersion)4529 void HAL_MVOP_SubSetInputMode( VOPINPUTMODE mode, MVOP_InputCfg *pparam, MS_U16 u16ECOVersion )
4530 {
4531 MS_U8 regval;
4532 MS_U16 u16strip, u16strip_lsb;
4533
4534 if (g_pHalMVOPCtx == NULL)
4535 {
4536 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4537 return;
4538 }
4539
4540 #if 0
4541 /*****************************************************/
4542 // Reset MVOP setting
4543 HAL_WriteByte(SUB_REG(VOP_TST_IMG), 0x40);
4544 HAL_MVOP_SubSetRgbFormat(E_MVOP_RGB_NONE);
4545 HAL_WriteRegBit(SUB_REG(VOP_CTRL1), 0, VOP_MVD_VS_MD); //default use original vsync
4546 // Only for Monaco: Enable deciding bot by top address + 2
4547 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), 1, VOP_FIELD_FROM_ADDR);
4548
4549 //set MVOP test pattern to black
4550 HAL_MVOP_SubSetBlackBG();
4551
4552 //regval = HAL_ReadByte(SUB_REG(VOP_MPG_JPG_SWITCH);
4553 regval = 0;
4554 regval |= ( mode & 0x3 );
4555
4556 // clear extend strip len bit by default
4557 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
4558
4559 // set mvop to 128bit_i128 interface
4560 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
4561
4562 // Disable H264 or RM Input
4563 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH), 0, BIT2|BIT3);
4564 //8*32 tile format
4565 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT1);
4566 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD);
4567 HAL_MVOP_SubSetFieldInverse(ENABLE, ENABLE);
4568 #endif
4569 regval = 0;
4570 regval |= ( mode & 0x3 );
4571
4572 if ( mode == VOPINPUT_HARDWIRE )
4573 {
4574 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), regval);
4575 }
4576 else if ( mode == VOPINPUT_HARDWIRECLIP )
4577 {
4578 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), regval);
4579
4580 // HSize, VSize
4581 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE ), LOWBYTE( pparam->u16HSize ));
4582 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE + 1), HIGHBYTE( pparam->u16HSize ));
4583 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE ), LOWBYTE( pparam->u16VSize ));
4584 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE + 1), HIGHBYTE( pparam->u16VSize ));
4585 }
4586 else if (mode == VOPINPUT_MCUCTRL)
4587 {
4588 g_pHalMVOPCtx->bSubMirrorMode = (g_pHalMVOPCtx->bSubMirrorModeVer||g_pHalMVOPCtx->bSubMirrorModeHor);
4589 if ( pparam->bProgressive )
4590 regval |= 0x4;
4591 else
4592 {
4593 regval &= ~0x4;
4594 regval |= 0x1; //reg_dc_md=b'11 for interlace input
4595 if (E_MVOP_RPTFLD_NONE == g_pHalMVOPCtx->eSubRepeatField)
4596 {
4597 MVOP_DBG("%s normal NOT repeat field %x\n", __FUNCTION__, g_pHalMVOPCtx->eSubRepeatField);
4598 //To support mcu mode interlace, need to set h'3B[9]=1,
4599 //h'11[12]=0, and Y1/UV1 address equal to Y0/UV0 address.
4600 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 1, VOP_REF_SELF_FLD);
4601 //HAL_MVOP_SubSetFieldInverse(ENABLE, DISABLE); //do not inverse in kano: mvop gen timing + hsk mode
4602 // mheg5, mcu mode for i mode, do not bypass, 0x11[6] = 0: mvop t/b toggle
4603 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY_3D_1), 0, VOP_RGB_FILED_BYPASS);
4604 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 0, VOP_EXTFLD_EN);
4605 }
4606 }
4607 // disable from wb
4608 HAL_WriteRegBit(SUB_REG(VOP_REG_MFDEC_2_L), 0, VOP_MF_FROM_WB);
4609 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, VOP_R2_WISHBONE);
4610 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 0, VOP_32x32_WB);
4611
4612 if ( pparam->bYUV422 )
4613 regval |= 0x10;
4614 else
4615 regval &= ~0x10;
4616
4617 if ( pparam->b422pack )
4618 regval |= 0x80;
4619
4620 if ( pparam->bDramRdContd == 1 )
4621 regval |= 0x20;
4622 else
4623 regval &= ~0x20;
4624
4625 // for backward compatable to saturn
4626 // [3] UV-7bit mode don't care
4627 // [5] dram_rd_md =0
4628 // [6] Fld don't care
4629 // [7] 422pack don'care
4630 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), regval);
4631 g_pHalMVOPCtx->bSubIs422 = pparam->bYUV422;
4632 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), !pparam->bYUV422, VOP_420_BW_SAVE);
4633 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), !pparam->bYUV422, VOP_420_BW_SAVE_EX);
4634
4635 if (pparam->u16StripSize == 0)
4636 {
4637 if (pparam->bSD)
4638 {
4639 u16strip = 720;
4640 u16strip_lsb = 720;
4641 }
4642 else
4643 {
4644 u16strip = 1920;
4645 u16strip_lsb = 1920;
4646 }
4647 }
4648 else
4649 {
4650 u16strip = pparam->u16StripSize;
4651 u16strip_lsb = pparam->u16StripSize;
4652 }
4653
4654 // set dc_strip[7:0]
4655 if (pparam->bDramRdContd == 0)
4656 {
4657 u16strip = (u16strip + 31) / 32 * 32; //need align for monaco
4658 u16strip = u16strip/8;
4659 u16strip_lsb = (u16strip_lsb+127)/128;
4660 u16strip_lsb *= 4;
4661
4662 MVOP_DBG(MVOP_PRINTF("[MVOP]%s enVideoType = 0x%x\n", __FUNCTION__,pparam->enVideoType);)
4663
4664 if(pparam->enVideoType == MVOP_H264)
4665 {
4666 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 1, VOP_TILE_32x32);//mantis:1144345 mustang h264 default 32x32.
4667 }
4668 else
4669 {
4670 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, VOP_TILE_32x32);//MVD can not 32x32.
4671 }
4672 }
4673 else
4674 {
4675 if ( pparam->b422pack )
4676 {
4677 if (E_MVOP_RGB_888 == g_pHalMVOPCtx->eSubRgbFmt)
4678 {
4679 u16strip *= 2;
4680 }
4681
4682 if ((u16strip < 1024) || g_pHalMVOPCtx->bSubMirrorMode)
4683 {
4684 u16strip = u16strip/4;
4685 // dont extend strip len
4686 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
4687 }
4688 else
4689 {
4690 u16strip = u16strip/8;
4691 // extend strip len to 2048
4692 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 1, BIT0);
4693 }
4694 }
4695 else
4696 {
4697 u16strip = u16strip/8;
4698 }
4699 }
4700
4701 if (u16strip >= 256 )
4702 {
4703 HAL_WriteByte(SUB_REG(VOP_DC_STRIP_H), (u16strip>>8));
4704 //reg_dc_strip_h[2:0] = reg_dc_strip[10:8]
4705 }
4706 else
4707 {
4708 HAL_WriteByteMask(SUB_REG(VOP_DC_STRIP_H), 0, BIT0 | BIT1 | BIT2);
4709 }
4710
4711 regval = u16strip;
4712 HAL_WriteByte(SUB_REG(VOP_DC_STRIP), regval);
4713 //LSB strip
4714 HAL_WriteByte(SUB_REG(VOP_DC_STRIP_LSB), u16strip_lsb & 0x3ff);
4715
4716 HAL_MVOP_SubSetYUVBaseAdd(pparam->u32YOffset, pparam->u32UVOffset,
4717 pparam->bProgressive, pparam->b422pack);
4718
4719 if (E_MVOP_RPTFLD_NONE != g_pHalMVOPCtx->eSubRepeatField)
4720 {
4721 MVOP_DBG("%s reset eRepeatField=%x ==>", __FUNCTION__, g_pHalMVOPCtx->eSubRepeatField);
4722 //To output the same field for single field input,
4723 //do NOT set h'3B[9]=1 and h'11[12]=0
4724 g_pHalMVOPCtx->eSubRepeatField = E_MVOP_RPTFLD_NONE; //reset the flag to repeat field
4725 MVOP_DBG(" %x\n", g_pHalMVOPCtx->eSubRepeatField);
4726 }
4727
4728 // HSize
4729 MS_U16 u16HSize = ALIGN_UPTO_16(pparam->u16HSize);
4730 if (u16HSize != pparam->u16HSize)
4731 {
4732 MVOP_DBG(MVOP_PRINTF("\n\n Change HSize %d to %d\n", pparam->u16HSize, u16HSize);)
4733 }
4734 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE ), LOWBYTE( u16HSize ));
4735 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE + 1), HIGHBYTE( u16HSize ));
4736
4737 // VSize
4738 MS_U16 u16VSize = pparam->u16VSize;
4739 if (g_pHalMVOPCtx->bSubMirrorModeVer)
4740 {
4741 u16VSize = ALIGN_UPTO_4(pparam->u16VSize);
4742 MVOP_DBG(MVOP_PRINTF("\n\n Change VSize %d to %d\n", pparam->u16VSize, u16VSize);)
4743 }
4744 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE ), LOWBYTE( u16VSize ));
4745 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE + 1), HIGHBYTE( u16VSize ));
4746 }
4747
4748 HAL_MVOP_SubLoadReg();
4749 }
4750
4751
HAL_MVOP_SubEnableUVShift(MS_BOOL bEnable)4752 void HAL_MVOP_SubEnableUVShift(MS_BOOL bEnable)
4753 {
4754 MS_U8 regval;
4755
4756 regval = HAL_ReadByte(SUB_REG(VOP_MPG_JPG_SWITCH));
4757
4758 if (((regval & BIT4) == BIT4) && ((regval & 0x3)== 0x2))
4759 { // 422 with MCU control mode
4760 if (bEnable)
4761 {
4762 MS_ASSERT(0);
4763 }
4764 }
4765
4766 // output 420 and interlace
4767 //[IP - Sheet] : Main Page --- 420CUP
4768 //[Project] : Titania2
4769 //[Description]: Chroma artifacts when 420to422 is applied duplicate method.
4770 //[Root cause]: Apply 420to422 average algorithm to all DTV input cases.
4771 //The average algorithm must cooperate with MVOP.
4772 HAL_WriteByteMask(SUB_REG(VOP_UV_SHIFT), (bEnable)?1:0, 0x3);
4773 }
4774
4775 static MS_BOOL _bSubEnable60P = false;
HAL_MVOP_SubSetEnable60P(MS_BOOL bEnable)4776 void HAL_MVOP_SubSetEnable60P(MS_BOOL bEnable)
4777 {
4778 _bSubEnable60P = bEnable;
4779 }
4780
4781 static MS_BOOL _bSubEnable4k2kClk = false;
HAL_MVOP_SubSetEnable4k2kClk(MS_BOOL bEnable)4782 void HAL_MVOP_SubSetEnable4k2kClk(MS_BOOL bEnable)
4783 {
4784 _bSubEnable4k2kClk = bEnable;
4785 }
4786
4787
HAL_MVOP_SubSetEnable4k2k2P(MS_BOOL bEnable)4788 void HAL_MVOP_SubSetEnable4k2k2P(MS_BOOL bEnable)
4789 {
4790 g_pHalMVOPCtx->bSubIs2p = bEnable;
4791 HAL_WriteRegBit(SUB_REG(VOP_REG_4K2K_2P), bEnable, VOP_4K2K_2P);
4792
4793 }
4794
HAL_MVOP_SubEnableFreerunMode(MS_BOOL bEnable)4795 void HAL_MVOP_SubEnableFreerunMode(MS_BOOL bEnable)
4796 {
4797 if (g_pHalMVOPCtx == NULL)
4798 {
4799 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4800 return;
4801 }
4802 g_pHalMVOPCtx->bSubEnableFreerunMode = bEnable;
4803 }
4804
HAL_MVOP_SubSetOutputTiming(MVOP_Timing * ptiming)4805 void HAL_MVOP_SubSetOutputTiming( MVOP_Timing *ptiming )
4806 {
4807 MS_U8 regval;
4808
4809 HAL_WriteByte(SUB_REG(VOP_FRAME_VCOUNT ), LOWBYTE( ptiming->u16V_TotalCount ));
4810 HAL_WriteByte(SUB_REG(VOP_FRAME_VCOUNT + 1), HIGHBYTE( ptiming->u16V_TotalCount ));
4811 HAL_WriteByte(SUB_REG(VOP_FRAME_HCOUNT ), LOWBYTE( ptiming->u16H_TotalCount ));
4812 HAL_WriteByte(SUB_REG(VOP_FRAME_HCOUNT + 1), HIGHBYTE( ptiming->u16H_TotalCount ));
4813
4814 HAL_WriteByte(SUB_REG(VOP_VB0_STR ), LOWBYTE( ptiming->u16VBlank0_Start ));
4815 HAL_WriteByte(SUB_REG(VOP_VB0_STR + 1), HIGHBYTE( ptiming->u16VBlank0_Start ));
4816 HAL_WriteByte(SUB_REG(VOP_VB0_END ), LOWBYTE( ptiming->u16VBlank0_End ));
4817 HAL_WriteByte(SUB_REG(VOP_VB0_END + 1), HIGHBYTE( ptiming->u16VBlank0_End ));
4818 HAL_WriteByte(SUB_REG(VOP_VB1_STR ), LOWBYTE( ptiming->u16VBlank1_Start ));
4819 HAL_WriteByte(SUB_REG(VOP_VB1_STR + 1), HIGHBYTE( ptiming->u16VBlank1_Start ));
4820 HAL_WriteByte(SUB_REG(VOP_VB1_END ), LOWBYTE( ptiming->u16VBlank1_End ));
4821 HAL_WriteByte(SUB_REG(VOP_VB1_END + 1), HIGHBYTE( ptiming->u16VBlank1_End ));
4822 HAL_WriteByte(SUB_REG(VOP_TF_STR ), LOWBYTE( ptiming->u16TopField_Start ));
4823 HAL_WriteByte(SUB_REG(VOP_TF_STR + 1), HIGHBYTE( ptiming->u16TopField_Start ));
4824 HAL_WriteByte(SUB_REG(VOP_BF_STR ), LOWBYTE( ptiming->u16BottomField_Start ));
4825 HAL_WriteByte(SUB_REG(VOP_BF_STR + 1), HIGHBYTE( ptiming->u16BottomField_Start ));
4826 HAL_WriteByte(SUB_REG(VOP_HACT_STR ), LOWBYTE( ptiming->u16HActive_Start ));
4827 HAL_WriteByte(SUB_REG(VOP_HACT_STR + 1), HIGHBYTE( ptiming->u16HActive_Start ));
4828
4829 HAL_WriteByte(SUB_REG(VOP_TF_VS ), LOWBYTE( ptiming->u16TopField_VS ));
4830 HAL_WriteByte(SUB_REG(VOP_TF_VS + 1), HIGHBYTE( ptiming->u16TopField_VS ));
4831 HAL_WriteByte(SUB_REG(VOP_BF_VS ), LOWBYTE( ptiming->u16BottomField_VS ));
4832 HAL_WriteByte(SUB_REG(VOP_BF_VS + 1), HIGHBYTE( ptiming->u16BottomField_VS ));
4833
4834 //if(((ptiming->u16V_TotalCount > 2160) || (ptiming->u16H_TotalCount > 3840)) && (ptiming->u8Framerate >= 30))
4835 if((!g_pHalMVOPCtx->bSubIsXcTrig) && (g_pHalMVOPCtx->bSubIsHS))
4836 {
4837 g_pHalMVOPCtx->bSubNewVSyncMode = TRUE;
4838 }
4839
4840 if (g_pHalMVOPCtx->bSubNewVSyncMode)
4841 {
4842 #define SUB_NEW_VSYNC_MODE_ADVANCE_LINECNT 30
4843 MVOP_DBG(MVOP_PRINTF("MVOP use new vync mode, forwarding %d lines\n",SUB_NEW_VSYNC_MODE_ADVANCE_LINECNT);)
4844
4845 MS_U16 u16BottomField_VS2MVD = ptiming->u16BottomField_VS - SUB_NEW_VSYNC_MODE_ADVANCE_LINECNT;
4846 MVOP_DBG(MVOP_PRINTF("BottomField VS ori=0x%x, new=0x%x\n", ptiming->u16BottomField_VS, u16BottomField_VS2MVD);)
4847 HAL_WriteByte(SUB_REG(VOP_BF_VS_MVD), LOWBYTE( u16BottomField_VS2MVD ));
4848 HAL_WriteByte(SUB_REG((VOP_BF_VS_MVD + 1)), HIGHBYTE( u16BottomField_VS2MVD ));
4849
4850 MS_U16 u16TopField_VS2MVD = ptiming->u16V_TotalCount - SUB_NEW_VSYNC_MODE_ADVANCE_LINECNT;
4851 MVOP_DBG(MVOP_PRINTF("TopField VS Vtt=0x%x, new=0x%x\n", ptiming->u16V_TotalCount, u16TopField_VS2MVD);)
4852 HAL_WriteByte(SUB_REG(VOP_TF_VS_MVD), LOWBYTE( u16TopField_VS2MVD ));
4853 HAL_WriteByte(SUB_REG((VOP_TF_VS_MVD + 1)), HIGHBYTE( u16TopField_VS2MVD ));
4854
4855 HAL_WriteRegBit(SUB_REG(VOP_GCLK), 0, VOP_GCLK_MIU_ON);
4856
4857 HAL_WriteRegBit(SUB_REG(VOP_CTRL1), 1, VOP_MVD_VS_MD); //Use new vsync
4858
4859 g_pHalMVOPCtx->bSubNewVSyncMode = FALSE; //restore to original mode
4860 }
4861
4862
4863 // + S3, set default IMG_HSTR, IMG_VSTR0, IMG_VSTR1
4864 #ifdef _SUPPORT_IMG_OFFSET_
4865 HAL_WriteByte(SUB_REG(VOP_IMG_HSTR ), LOWBYTE( ptiming->u16HImg_Start));
4866 HAL_WriteByte(SUB_REG(VOP_IMG_HSTR + 1), HIGHBYTE( ptiming->u16HImg_Start ));
4867 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR0 ), LOWBYTE( ptiming->u16VImg_Start0));
4868 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR0+ 1), HIGHBYTE( ptiming->u16VImg_Start0 ));
4869 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR1 ), LOWBYTE( ptiming->u16VImg_Start1 ));
4870 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR1+ 1), HIGHBYTE( ptiming->u16VImg_Start1 ));
4871 #else
4872 HAL_WriteByte(SUB_REG(VOP_IMG_HSTR ), LOWBYTE( ptiming->u16HActive_Start ));
4873 HAL_WriteByte(SUB_REG(VOP_IMG_HSTR + 1), HIGHBYTE( ptiming->u16HActive_Start ));
4874 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR0 ), LOWBYTE( ptiming->u16VBlank0_End ));
4875 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR0+ 1), HIGHBYTE( ptiming->u16VBlank0_End ));
4876 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR1 ), LOWBYTE( ptiming->u16VBlank1_End ));
4877 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR1+ 1), HIGHBYTE( ptiming->u16VBlank1_End ));
4878 #endif
4879 // select mvop output from frame color(black)
4880 HAL_WriteByte(SUB_REG(VOP_TST_IMG + 1), 0x10);
4881 HAL_WriteByte(SUB_REG(VOP_U_PAT ), 0x80);
4882 HAL_WriteByte(SUB_REG(VOP_U_PAT + 1), 0x80);
4883 // set mvop src to test pattern
4884 regval = HAL_ReadByte(SUB_REG(VOP_TST_IMG));
4885 HAL_WriteByteMask(SUB_REG(VOP_TST_IMG), 0x02, BIT2 | BIT1 | BIT0);
4886 // make changed registers take effect
4887 HAL_MVOP_SubLoadReg();
4888
4889 HAL_MVOP_SubSetMIUReqMask(TRUE);
4890 // reset mvop to avoid timing change cause mvop hang-up
4891 HAL_MVOP_SubRst();
4892 HAL_MVOP_SubSetMIUReqMask(FALSE);
4893
4894 // select mvop output from mvd
4895 HAL_WriteByteMask(SUB_REG(VOP_TST_IMG), 0x00, BIT2 | BIT1 | BIT0);
4896 HAL_WriteByteMask(SUB_REG(VOP_TST_IMG), regval, BIT2 | BIT1 | BIT0);
4897 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), ptiming->bHDuplicate, BIT2);// H pixel duplicate
4898
4899 #if 0
4900 MVOP_DBG(MVOP_PRINTF("\nMVOP SetOutputTiming\n");)
4901 MVOP_DBG(MVOP_PRINTF(" VTot=%u,\t",ptiming->u16V_TotalCount);)
4902 MVOP_DBG(MVOP_PRINTF(" HTot=%u,\t",ptiming->u16H_TotalCount);)
4903 MVOP_DBG(MVOP_PRINTF(" I/P=%u\n",ptiming->bInterlace);)
4904 MVOP_DBG(MVOP_PRINTF(" W=%u,\t",ptiming->u16Width);)
4905 MVOP_DBG(MVOP_PRINTF(" H=%u,\t",ptiming->u16Height);)
4906 MVOP_DBG(MVOP_PRINTF(" FRate=%u,\t",ptiming->u8Framerate);)
4907 MVOP_DBG(MVOP_PRINTF(" HFreq=%u\n",ptiming->u16H_Freq);)
4908 MVOP_DBG(MVOP_PRINTF(" Num=0x%x,\t",ptiming->u16Num);)
4909 MVOP_DBG(MVOP_PRINTF(" Den=0x%x,\t",ptiming->u16Den);)
4910 MVOP_DBG(MVOP_PRINTF(" u16ExpFRate=%u #\n\n", ptiming->u16ExpFrameRate);)
4911 #endif
4912 }
4913
HAL_MVOP_SubSetDCClk(MS_U8 clkNum,MS_BOOL bEnable)4914 void HAL_MVOP_SubSetDCClk(MS_U8 clkNum, MS_BOOL bEnable)
4915 {
4916 MS_ASSERT( (clkNum==0) || (clkNum==1) );
4917 if (clkNum==0)
4918 {
4919 HAL_WriteRegBit(REG_CKG_SUB_DC0, !bEnable, CKG_SUB_DC0_GATED);
4920 }
4921 }
4922
HAL_MVOP_SubSetDCSRAMClk(MS_U8 clkNum,MS_BOOL bEnable)4923 void HAL_MVOP_SubSetDCSRAMClk(MS_U8 clkNum, MS_BOOL bEnable)
4924 {
4925 MS_ASSERT( (clkNum==0) || (clkNum==1) );
4926 if (clkNum==0)
4927 {
4928 if(bEnable)
4929 {
4930 if(g_pHalMVOPCtx->u16ECONum == 0)
4931 {
4932 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x4, CKG_DC1_SRAM);//Dc0 enable & dc0_mfdec_en =0 57[3:0]= 0x4, others 57[3:0]=0x0
4933 }
4934 else
4935 {
4936 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x0, CKG_DC1_SRAM);
4937 HAL_WriteByteMask(SUB_REG(VOP_REG_DUMMY_5D), 0x0, VOP_SRAM_CLK_AUTO);
4938 HAL_MVOP_SubLoadReg();
4939 }
4940 }
4941 else
4942 {
4943 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x0, CKG_DC1_SRAM);
4944 }
4945 }
4946 }
4947
HAL_MVOP_SubSetSynClk(MVOP_Timing * ptiming)4948 void HAL_MVOP_SubSetSynClk(MVOP_Timing *ptiming)
4949 {
4950 if (g_pHalMVOPCtx == NULL)
4951 {
4952 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4953 return;
4954 }
4955 if(g_pHalMVOPCtx->u32SubMVOPFixClk != 0)
4956 {
4957 HAL_MVOP_SubSetFrequency(g_pHalMVOPCtx->u32SubMVOPFixClk);
4958 if(g_pHalMVOPCtx->bSub3DLRMode)//4k1k mvc
4959 {
4960 //burst and priority
4961 HAL_WriteByte(SUB_REG(VOP_DMA1), 0x26);
4962 HAL_WriteByte(SUB_REG(VOP_BURST_CTRL0), 0x05);
4963 HAL_WriteByte(SUB_REG(VOP_BURST_CTRL1), 0x00);
4964 }
4965 }
4966 else if(g_pHalMVOPCtx->bSubEnableFreerunMode)
4967 {
4968 MS_U64 u64mpll_clock = MPLL_CLOCK << 27 ;
4969 do_div(u64mpll_clock, ((MS_U32)ptiming->u16H_TotalCount * (MS_U32)ptiming->u16V_TotalCount * (MS_U32)ptiming->u8Framerate));
4970 MS_U32 u32FreerunClk = (MS_U32)u64mpll_clock;
4971 HAL_MVOP_SubSetFrequency(HALMVOP_FREERUNMODE);
4972 HAL_WriteByte((REG_DC1_FREERUN_CW_L ), LOWBYTE((MS_U16)u32FreerunClk));
4973 HAL_WriteByte((REG_DC1_FREERUN_CW_L+1), HIGHBYTE((MS_U16)u32FreerunClk));
4974 HAL_WriteByte((REG_DC1_FREERUN_CW_H ), LOWBYTE((MS_U16)(u32FreerunClk >> 16)));
4975 HAL_WriteByte((REG_DC1_FREERUN_CW_H+1), HIGHBYTE((MS_U16)(u32FreerunClk >> 16)));
4976 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_FREERUN_CW);
4977 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_FREERUN_CW);
4978 }
4979 else if (_bSubEnable60P)
4980 {
4981 HAL_MVOP_SubSetFrequency(HAL_MVOP_SubGetMaxFreerunClk());
4982 HAL_WriteRegBit(SUB_REG(VOP_REG_FRAME_RST), 0, BIT15); // reg_frame_rst = 0
4983
4984 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), DISABLE, VOP_FSYNC_EN); // frame sync disable
4985
4986 if(g_pHalMVOPCtx->bSub3DLRMode)//4k1k mvc
4987 {
4988 //burst and priority
4989 HAL_WriteByte(SUB_REG(VOP_DMA1), 0x26);
4990 HAL_WriteByte(SUB_REG(VOP_BURST_CTRL0), 0x05);
4991 HAL_WriteByte(SUB_REG(VOP_BURST_CTRL1), 0x00);
4992 }
4993 }
4994 else if (_bSubEnable4k2kClk)
4995 {
4996 HAL_MVOP_SubSetFrequency(HAL_MVOP_SubGet4k2kClk());
4997
4998 HAL_WriteRegBit(SUB_REG(VOP_REG_FRAME_RST), 0, BIT15); // reg_frame_rst = 0
4999
5000 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), DISABLE, VOP_FSYNC_EN); // frame sync disable
5001 }
5002 else
5003 {
5004 HAL_MVOP_SubSetFrequency(HALMVOP_SYNCMODE);
5005 HAL_WriteByte((REG_DC1_NUM ), LOWBYTE( ptiming->u16Num));
5006 HAL_WriteByte((REG_DC1_NUM+1), HIGHBYTE(ptiming->u16Num));
5007 HAL_WriteByte((REG_DC1_DEN ), LOWBYTE( ptiming->u16Den));
5008 HAL_WriteByte((REG_DC1_DEN+1), HIGHBYTE(ptiming->u16Den));
5009 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_SYNC_CW);
5010 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_SYNC_CW);
5011 }
5012 }
5013
5014
HAL_MVOP_SubSetMonoMode(MS_BOOL bEnable)5015 void HAL_MVOP_SubSetMonoMode(MS_BOOL bEnable)
5016 {
5017 if(bEnable)
5018 {
5019 HAL_WriteByte(SUB_REG(VOP_U_PAT ), 0x80);
5020 HAL_WriteByte(SUB_REG(VOP_U_PAT+1), 0x80);
5021
5022 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH1), 1, BIT1); // Mono mode enable
5023 }
5024 else
5025 {
5026 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH1), 0, BIT1); //Mono mode disable
5027 }
5028 }
5029
5030 /******************************************************************************/
5031 /// Set MVOP for H264 Hardwire Mode
5032 /******************************************************************************/
HAL_MVOP_SubSetH264HardwireMode(MS_U16 u16ECOVersion)5033 void HAL_MVOP_SubSetH264HardwireMode(MS_U16 u16ECOVersion)
5034 {
5035 // Hardwire mode
5036 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), 0x00);
5037
5038 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
5039
5040 //16*32 tile format
5041 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT1);
5042
5043 // SVD mode enable
5044 HAL_WriteByteMask(SUB_REG(VOP_INPUT_SWITCH1), BIT3, BIT2|BIT3);
5045
5046
5047 // set mvop to 64bit interface
5048 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
5049 // Only for Monaco: Disable deciding bot by top address + 2
5050 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), 0, VOP_FIELD_FROM_ADDR);
5051
5052 // Enable mfdec setting from wb from Manhattan
5053 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 1, VOP_32x32_WB); //32x32 from wb
5054
5055 if(u16ECOVersion == 0)
5056 {
5057 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x0, CKG_DC1_SRAM);//Dc0 enable & dc0_mfdec_en =0 57[3:0]= 0x4, others 57[3:0]=0x0
5058 }
5059
5060 // Write trigger
5061 HAL_MVOP_SubLoadReg();
5062 }
5063
HAL_MVOP_SubEnableMVDInterface(MS_BOOL bEnable)5064 void HAL_MVOP_SubEnableMVDInterface(MS_BOOL bEnable)
5065 {
5066 MS_BOOL bMVOPMain2MVD = TRUE;
5067 bMVOPMain2MVD = (bEnable) ? FALSE : TRUE;
5068
5069 //This bit is only valid in main mvop bank.
5070 //Select which mvop interrupt that mvd f/w recieve: 1 for main; 0 for sub.
5071 HAL_WriteByteMask(VOP_INPUT_SWITCH1, bMVOPMain2MVD, VOP_MVD_EN);
5072
5073 //No need to "Write trigger" since HAL_MVOP_SubSetInputMode() will do it later.
5074 //HAL_MVOP_SubLoadReg();
5075 }
5076
5077 /******************************************************************************/
5078 /// Set MVOP for RM Hardwire Mode
5079 /******************************************************************************/
HAL_MVOP_SubSetRMHardwireMode(MS_U16 u16ECOVersion)5080 void HAL_MVOP_SubSetRMHardwireMode(MS_U16 u16ECOVersion)
5081 {
5082 HAL_MVOP_SubSetH264HardwireMode(u16ECOVersion);
5083 if(u16ECOVersion == 0)
5084 {
5085 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x40, CKG_DC1_SRAM);//Dc0 enable & dc0_mfdec_en =0 57[3:0]= 0x4, others 57[3:0]=0x0
5086 }
5087 }
5088
5089 /******************************************************************************/
5090 /// Set MVOP for JPEG Hardwire Mode
5091 /******************************************************************************/
HAL_MVOP_SubSetJpegHardwireMode(MS_U16 u16ECOVersion)5092 void HAL_MVOP_SubSetJpegHardwireMode(MS_U16 u16ECOVersion)
5093 {
5094 MS_U8 regval = 0x00;
5095
5096 //Hardwire mode//
5097 //Use HVD interface//
5098 HAL_MVOP_SubSetH264HardwireMode(u16ECOVersion);
5099
5100 regval |= 0x80; // packmode
5101 regval |= 0x20; // Dram Rd Contd
5102 regval |= 0x10; // reg_img422
5103 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), regval);
5104 /* There is no hardwire:mvd2dc_img422/hvd2dc_img422 0x20[4] in sub mvop*/
5105 HAL_WriteByteMask(SUB_REG(VOP_INFO_FROM_CODEC_L), 0, VOP_INFO_FROM_CODEC_422_FMT);
5106 g_pHalMVOPCtx->bSubIs422 = 1;
5107 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 0, VOP_420_BW_SAVE);
5108 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
5109 HAL_WriteByteMask(SUB_REG(VOP_INFO_FROM_CODEC_H), 0x00, VOP_INFO_FROM_CODEC_MIU_BUF0_SEL|VOP_INFO_FROM_CODEC_MIU_BUF1_SEL);
5110
5111 // Write trigger
5112 HAL_MVOP_SubLoadReg();
5113 }
5114 /******************************************************************************/
5115 /// Set MVOP for EVD Hardwire Mode
5116 /******************************************************************************/
HAL_MVOP_SubSetEVDHardwireMode(MS_U16 u16ECOVersion)5117 void HAL_MVOP_SubSetEVDHardwireMode(MS_U16 u16ECOVersion)
5118 {
5119 // Hardwire mode
5120 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), 0x00);
5121
5122 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
5123
5124 //16*32 tile format
5125 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT1);
5126
5127 // EVD use HVD interface
5128 //HAL_WriteByteMask(SUB_REG(VOP_INPUT_SWITCH1), BIT3, BIT2|BIT3);
5129
5130 // EVD mode enable
5131 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 1, EVD_ENABLE);
5132
5133 // set mvop to 128bit_i128 interface
5134 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
5135
5136 // set evd flag for interlace mode setting
5137 g_pHalMVOPCtx->bSubIsH265 = 1;
5138
5139 // 10 bits from wb
5140 HAL_WriteRegBit(SUB_REG(VOP_INFO_FROM_CODEC_H), 1, VOP_INFO_FROM_CODEC_10BIT);
5141 HAL_WriteByteMask(SUB_REG(VOP_REG_MASK), 0, VOP_LSB_REQ_MASK);
5142
5143 if(u16ECOVersion == 0)
5144 {
5145 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x0, CKG_DC1_SRAM);//Dc0 enable & dc0_mfdec_en =0 57[3:0]= 0x4, others 57[3:0]=0x0
5146 }
5147
5148 // Write trigger
5149 HAL_MVOP_SubLoadReg();
5150 }
5151
5152 /******************************************************************************/
5153 /// Set MVOP for VP9 Hardwire Mode
5154 /******************************************************************************/
HAL_MVOP_SubSetVP9HardwireMode(MS_U16 u16ECOVersion)5155 void HAL_MVOP_SubSetVP9HardwireMode(MS_U16 u16ECOVersion)
5156 {
5157 HAL_MVOP_SubSetEVDHardwireMode(u16ECOVersion);
5158 }
5159
5160
5161 ///Enable 3D L/R dual buffer mode
HAL_MVOP_SubEnable3DLR(MS_BOOL bEnable)5162 MS_BOOL HAL_MVOP_SubEnable3DLR(MS_BOOL bEnable)
5163 {
5164 if (g_pHalMVOPCtx == NULL)
5165 {
5166 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5167 return FALSE;
5168 }
5169 HAL_WriteRegBit(SUB_REG(VOP_MULTI_WIN_CFG0), bEnable, VOP_LR_BUF_MODE);
5170 g_pHalMVOPCtx->bSub3DLRMode = bEnable;
5171 if(bEnable)
5172 {
5173 //only for monaco: do not wait for data ready.
5174 HAL_WriteByteMask(SUB_REG(VOP_NOT_WAIT_READ_DATA), 2, VOP_NOT_WAIT_RDLAT);
5175 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
5176 }
5177 else
5178 {
5179 HAL_WriteByteMask(SUB_REG(VOP_NOT_WAIT_READ_DATA), 0, VOP_NOT_WAIT_RDLAT);
5180 }
5181 return TRUE;
5182 }
5183
5184 ///Get if 3D L/R mode is enabled
HAL_MVOP_SubGet3DLRMode(void)5185 MS_BOOL HAL_MVOP_SubGet3DLRMode(void)
5186 {
5187 if (g_pHalMVOPCtx == NULL)
5188 {
5189 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5190 return FALSE;
5191 }
5192 return g_pHalMVOPCtx->bSub3DLRMode;
5193 }
5194
HAL_MVOP_SubGetTimingInfoFromRegisters(MVOP_TimingInfo_FromRegisters * pMvopTimingInfo)5195 MS_BOOL HAL_MVOP_SubGetTimingInfoFromRegisters(MVOP_TimingInfo_FromRegisters *pMvopTimingInfo)
5196 {
5197 if(NULL == pMvopTimingInfo)
5198 {
5199 MVOP_PRINTF("HAL_MVOP_SubGetTimingInfoFromRegisters():pMvopTimingInfo is NULL\n");
5200 return FALSE;
5201 }
5202 if(HAL_MVOP_SubGetEnableState() == FALSE)
5203 {
5204 MVOP_PRINTF("MVOP is not enabled!\n");
5205 pMvopTimingInfo->bEnabled = FALSE;
5206 return FALSE;
5207 }
5208 pMvopTimingInfo->bEnabled = TRUE;
5209 pMvopTimingInfo->u16H_TotalCount = (HAL_ReadByte(SUB_REG(VOP_FRAME_HCOUNT + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_FRAME_HCOUNT)));
5210 pMvopTimingInfo->u16V_TotalCount = (HAL_ReadByte(SUB_REG(VOP_FRAME_VCOUNT + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_FRAME_VCOUNT)));
5211 pMvopTimingInfo->u16VBlank0_Start = (HAL_ReadByte(SUB_REG(VOP_VB0_STR + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_VB0_STR)));
5212 pMvopTimingInfo->u16VBlank0_End = (HAL_ReadByte(SUB_REG(VOP_VB0_END + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_VB0_END)));
5213 pMvopTimingInfo->u16VBlank1_Start = (HAL_ReadByte(SUB_REG(VOP_VB1_STR + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_VB1_STR)));
5214 pMvopTimingInfo->u16VBlank1_End = (HAL_ReadByte(SUB_REG(VOP_VB1_END + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_VB1_END)));
5215 pMvopTimingInfo->u16TopField_Start = (HAL_ReadByte(SUB_REG(VOP_TF_STR + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_TF_STR)));
5216 pMvopTimingInfo->u16BottomField_Start = (HAL_ReadByte(SUB_REG(VOP_BF_STR + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_BF_STR)));
5217 pMvopTimingInfo->u16HActive_Start = (HAL_ReadByte(SUB_REG(VOP_HACT_STR + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_HACT_STR)));
5218 pMvopTimingInfo->u16TopField_VS = (HAL_ReadByte(SUB_REG(VOP_TF_VS + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_TF_VS)));
5219 pMvopTimingInfo->u16BottomField_VS = (HAL_ReadByte(SUB_REG(VOP_BF_VS + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_BF_VS)));
5220 pMvopTimingInfo->bInterlace = (HAL_ReadRegBit(SUB_REG(VOP_CTRL0), BIT7) == BIT7);
5221 return TRUE;
5222 }
5223
HAL_MVOP_SubSetYUVBaseAdd(MS_PHY u32YOffset,MS_PHY u32UVOffset,MS_BOOL bProgressive,MS_BOOL b422pack)5224 void HAL_MVOP_SubSetYUVBaseAdd(MS_PHY u32YOffset, MS_PHY u32UVOffset, MS_BOOL bProgressive, MS_BOOL b422pack)
5225 {
5226 MS_PHY u64tmp = 0;
5227
5228 if (g_pHalMVOPCtx == NULL)
5229 {
5230 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5231 return;
5232 }
5233 // Y offset
5234 u64tmp = u32YOffset >> 3;
5235 if ( !bProgressive )
5236 { //Refine Y offset for interlace repeat bottom field
5237 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eSubRepeatField)
5238 {
5239 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eSubRepeatField);
5240 u64tmp += 2;
5241 }
5242 else
5243 {
5244 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eSubRepeatField);
5245 }
5246 }
5247 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L), u64tmp & 0xff);
5248 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L+1), (u64tmp >> 8) & 0xff);
5249 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L+2), (u64tmp >> 16) & 0xff);
5250 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5251
5252 if (!bProgressive )
5253 { //Y offset of bottom field if interlace
5254 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L), u64tmp & 0xff);
5255 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L+1), (u64tmp >> 8) & 0xff);
5256 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L+2), (u64tmp >> 16) & 0xff);
5257 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5258 }
5259
5260 if (b422pack)
5261 {
5262 if (HAL_ReadRegBit(SUB_REG(VOP_MIU_IF), VOP_MIU_128B_I64) != VOP_MIU_128B_I64) //128-bit
5263 {
5264 u32UVOffset = u32YOffset + 16; //add 16 for 128bit; add 8 for 64bit
5265 }
5266 else //64-bit
5267 {
5268 u32UVOffset = u32YOffset + 8; //add 16 for 128bit; add 8 for 64bit
5269 }
5270 }
5271 // UV offset
5272 u64tmp = u32UVOffset >> 3;
5273 if( !bProgressive )
5274 { //Refine UV offset for interlace repeat bottom field
5275 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eSubRepeatField)
5276 {
5277 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eSubRepeatField);
5278 u64tmp += 2;
5279 }
5280 else
5281 {
5282 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eSubRepeatField);
5283 }
5284 }
5285 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L), u64tmp & 0xff);
5286 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
5287 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L+2), (u64tmp >> 16) & 0xff);
5288 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5289
5290 if( !bProgressive )
5291 { //UV offset of bottom field if interlace
5292 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L), u64tmp & 0xff);
5293 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
5294 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L+2), (u64tmp >> 16) & 0xff);
5295 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5296 }
5297
5298 return;
5299 }
5300
HAL_MVOP_SubGetYBaseAdd(void)5301 MS_PHY HAL_MVOP_SubGetYBaseAdd(void)
5302 {
5303 MS_PHY u64YOffset;
5304 u64YOffset = HAL_ReadByte(SUB_REG(VOP_JPG_YSTR0_L))&0xff;
5305 u64YOffset |=((HAL_ReadByte(SUB_REG(VOP_JPG_YSTR0_L+1))<<8)&0xff00);
5306 u64YOffset |=((HAL_ReadByte(SUB_REG(VOP_JPG_YSTR0_L+2))<<16)&0xff0000);
5307 u64YOffset |= ((HAL_ReadByte(SUB_REG(VOP_JPG_YSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
5308 return u64YOffset;
5309 }
5310
HAL_MVOP_SubGetUVBaseAdd(void)5311 MS_PHY HAL_MVOP_SubGetUVBaseAdd(void)
5312 {
5313 MS_PHY u64UVOffset;
5314 u64UVOffset = HAL_ReadByte(SUB_REG(VOP_JPG_UVSTR0_L))&0xff;
5315 u64UVOffset |=((HAL_ReadByte(SUB_REG(VOP_JPG_UVSTR0_L+1))<<8)&0xff00);
5316 u64UVOffset |=((HAL_ReadByte(SUB_REG(VOP_JPG_UVSTR0_L+2))<<16)&0xff0000);
5317 u64UVOffset |= ((HAL_ReadByte(SUB_REG(VOP_JPG_UVSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
5318 return u64UVOffset;
5319 }
5320
5321 /******************************************************************************/
5322 /// Set MVOP Saving BW Mode
5323 /// @ Napoli this command should be set after MDrv_MVOP_SubSetOutputCfg
5324 /******************************************************************************/
HAL_MVOP_SubSet420BWSaveMode(MS_BOOL bEnable,MS_U16 u16ECOVersion)5325 MS_BOOL HAL_MVOP_SubSet420BWSaveMode(MS_BOOL bEnable, MS_U16 u16ECOVersion)
5326 {
5327 UNUSED(u16ECOVersion);
5328 MS_BOOL bValue = FALSE;
5329
5330 //hw limtation: 3DLA/3DSBS/422/p mode in, i mode out/i mode in, p mode out(only need to check in MCU mode)
5331 bValue = (g_pHalMVOPCtx->bSub3DLRAltSBSOutput || g_pHalMVOPCtx->bSub3DLRAltOutput/* || g_pHalMVOPCtx->bSub3DLRMode */|| g_pHalMVOPCtx->bSubIs422 );
5332
5333 if(bValue)
5334 {
5335 MVOP_DBG(MVOP_PRINTF("%s Hit the limitation of saving bw, disable BW Saving mode\n", __FUNCTION__);)
5336 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 0, VOP_420_BW_SAVE);
5337 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
5338 HAL_MVOP_SubLoadReg();
5339 return FALSE;
5340 }
5341 else
5342 {
5343 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), bEnable, VOP_420_BW_SAVE);
5344 if( g_pHalMVOPCtx->bSub3DLRMode == FALSE)
5345 {
5346 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), bEnable, VOP_420_BW_SAVE_EX);
5347 }
5348 HAL_MVOP_SubLoadReg();
5349 return TRUE;
5350 }
5351 }
5352
HAL_MVOP_SubSetEVDYUVBaseAdd(MVOP_EVDBaseAddInput * stEVDBaseAddInfo)5353 MS_BOOL HAL_MVOP_SubSetEVDYUVBaseAdd(MVOP_EVDBaseAddInput *stEVDBaseAddInfo)
5354 {
5355 //----------------------------------------------------
5356 // Set MSB YUV Address
5357 //----------------------------------------------------
5358
5359 MS_PHY u64tmp = 0;
5360
5361 if (g_pHalMVOPCtx == NULL)
5362 {
5363 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5364 return FALSE;
5365 }
5366 // Y offset
5367 u64tmp = stEVDBaseAddInfo->u32MSBYOffset >> 3;
5368 if ( !stEVDBaseAddInfo->bProgressive)
5369 { //Refine Y offset for interlace repeat bottom field
5370 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
5371 {
5372 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5373 u64tmp += 2;
5374 }
5375 else
5376 {
5377 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5378 }
5379 }
5380 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L), u64tmp & 0xff);
5381 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L+1), (u64tmp >> 8) & 0xff);
5382 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_H), (u64tmp >> 16) & 0xff);
5383 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5384
5385 if (!stEVDBaseAddInfo->bProgressive )
5386 { //Y offset of bottom field if interlace
5387 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L), u64tmp & 0xff);
5388 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L+1), (u64tmp >> 8) & 0xff);
5389 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_H), (u64tmp >> 16) & 0xff);
5390 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5391 }
5392
5393 if (stEVDBaseAddInfo->b422Pack)
5394 {
5395 stEVDBaseAddInfo->u32MSBUVOffset = stEVDBaseAddInfo->u32MSBYOffset + 16; //add 16 for 128bit; add 8 for 64bit
5396 }
5397 // UV offset
5398 u64tmp = stEVDBaseAddInfo->u32MSBUVOffset >> 3;
5399 if( !stEVDBaseAddInfo->bProgressive )
5400 { //Refine UV offset for interlace repeat bottom field
5401 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
5402 {
5403 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5404 u64tmp += 2;
5405 }
5406 else
5407 {
5408 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5409 }
5410 }
5411 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L), u64tmp & 0xff);
5412 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
5413 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_H), (u64tmp >> 16) & 0xff);
5414 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5415
5416 if( !stEVDBaseAddInfo->bProgressive )
5417 { //UV offset of bottom field if interlace
5418 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L), u64tmp & 0xff);
5419 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
5420 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_H), (u64tmp >> 16) & 0xff);
5421 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5422 }
5423
5424 //----------------------------------------------------
5425 // Set MSB YUV Address
5426 //----------------------------------------------------
5427 if(stEVDBaseAddInfo->bEnLSB)
5428 {
5429 //Enable LSB
5430 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 1, VOP_EVD_10B_Y_EN);
5431 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 1, VOP_EVD_10B_UV_EN);
5432 HAL_WriteRegBit(SUB_REG(VOP_REG_MASK), 0, VOP_LSB_REQ_MASK);
5433
5434 // Y offset
5435 u64tmp = stEVDBaseAddInfo->u32LSBYOffset >> 3;
5436 if ( !stEVDBaseAddInfo->bProgressive)
5437 { //Refine Y offset for interlace repeat bottom field
5438 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
5439 {
5440 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5441 u64tmp += 2;
5442 }
5443 else
5444 {
5445 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5446 }
5447 }
5448 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR0_L), u64tmp & 0xff);
5449 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR0_L+1), (u64tmp >> 8) & 0xff);
5450 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR0_L), (u64tmp >> 16) & 0xff);
5451 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR0_L+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5452
5453 if (!stEVDBaseAddInfo->bProgressive )
5454 { //Y offset of bottom field if interlace
5455 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR1_L), u64tmp & 0xff);
5456 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR1_L+1), (u64tmp >> 8) & 0xff);
5457 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR1_H), (u64tmp >> 16) & 0xff);
5458 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5459 }
5460
5461 if (stEVDBaseAddInfo->b422Pack)
5462 {
5463 stEVDBaseAddInfo->u32LSBUVOffset = stEVDBaseAddInfo->u32LSBYOffset + 16; //add 16 for 128bit; add 8 for 64bit
5464 }
5465 // UV offset
5466 u64tmp = stEVDBaseAddInfo->u32LSBUVOffset >> 3;
5467 if( !stEVDBaseAddInfo->bProgressive )
5468 { //Refine UV offset for interlace repeat bottom field
5469 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
5470 {
5471 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5472 u64tmp += 2;
5473 }
5474 else
5475 {
5476 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5477 }
5478 }
5479 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR0_L), u64tmp & 0xff);
5480 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
5481 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR0_H), (u64tmp >> 16) & 0xff);
5482 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5483
5484 if( !stEVDBaseAddInfo->bProgressive )
5485 { //UV offset of bottom field if interlace
5486 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR1_L), u64tmp & 0xff);
5487 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
5488 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR1_H), (u64tmp >> 16) & 0xff);
5489 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5490 }
5491 }
5492
5493 return TRUE;
5494 }
5495
HAL_MVOP_SubCheckSTCCW(void)5496 MS_BOOL HAL_MVOP_SubCheckSTCCW(void)
5497 {
5498 MS_U16 u16STC_CW_L = 0;
5499 MS_U16 u16STC_CW_H = 0;
5500
5501 MS_BOOL u16STC_CW_SEL = 0;
5502 MS_BOOL u16TSP_CLK_EN = 0;
5503
5504 u16STC_CW_L = HAL_Read2Byte(REG_STC1_CW_L)&0xffff;
5505 u16STC_CW_H = HAL_Read2Byte(REG_STC1_CW_H)&0xffff;
5506
5507 u16STC_CW_SEL = (HAL_ReadRegBit(REG_STC_CW_SLE_H, BIT1) == BIT1);
5508 u16TSP_CLK_EN = !(HAL_ReadRegBit(REG_TSP_CLK, BIT0) == BIT0);
5509
5510 if((((u16STC_CW_L || u16STC_CW_H) == 0) && (u16STC_CW_SEL == 0)) || ((u16STC_CW_SEL == 1) && (u16TSP_CLK_EN == 0)))
5511 return FALSE;
5512 else
5513 return TRUE;
5514
5515 }
5516
HAL_MVOP_SubSetVSyncMode(MS_U8 u8Mode)5517 void HAL_MVOP_SubSetVSyncMode(MS_U8 u8Mode)
5518 {
5519 if (g_pHalMVOPCtx == NULL)
5520 {
5521 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5522 return;
5523 }
5524 if (1==u8Mode)
5525 {
5526 g_pHalMVOPCtx->bSubNewVSyncMode = TRUE;
5527 }
5528 else
5529 {
5530 g_pHalMVOPCtx->bSubNewVSyncMode = FALSE;
5531 }
5532 }
5533
HAL_MVOP_SubSet3DLRAltOutput_VHalfScaling(MS_BOOL bEnable)5534 MS_BOOL HAL_MVOP_SubSet3DLRAltOutput_VHalfScaling(MS_BOOL bEnable)
5535 {
5536 MS_BOOL bEnDualBuff = bEnable ? ENABLE : DISABLE; //enable dual buffer
5537 MS_BOOL bEnSWDualBuff = bEnable ? DISABLE : ENABLE; //buffer controlled by HK instead of FW
5538 MS_BOOL bEnMirrMaskBase = bEnable ? DISABLE : ENABLE; //do not mask LSB
5539 MS_BOOL bEnHwFldBase = bEnable ? DISABLE : ENABLE; //hardware calculate field jump base address
5540 if (g_pHalMVOPCtx == NULL)
5541 {
5542 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5543 return FALSE;
5544 }
5545 //Set 0x27[2] = 1 (enable SW dual buffer mode)
5546 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), bEnDualBuff, VOP_BUF_DUAL);
5547
5548 //Set 0x38[8] = 0 (use SW dual buffer mode)
5549 HAL_WriteRegBit(SUB_REG(VOP_INFO_FROM_CODEC_H), bEnSWDualBuff, VOP_INFO_FROM_CODEC_DUAL_BUFF);
5550
5551 //Set 0x3b[7] = 0 (use MVD/HVD firmware send base)
5552 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bEnMirrMaskBase, VOP_MASK_BASE_LSB);
5553
5554 //Set 0x3b[5] = 0 (hardware calculate field jump base address)
5555 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bEnHwFldBase, VOP_HW_FLD_BASE);
5556 g_pHalMVOPCtx->bSub3DLRAltOutput = bEnable;
5557 return TRUE;
5558 }
5559
HAL_MVOP_SubSet3DLRAltOutput(MS_BOOL bEnable)5560 MS_BOOL HAL_MVOP_SubSet3DLRAltOutput(MS_BOOL bEnable)
5561 {
5562 //Set 0x3C[2] = 1 (enable 3D L/R dual buffer line alternative output)
5563 //it works when 0x3C[0] = 1
5564 HAL_WriteRegBit(SUB_REG(VOP_MULTI_WIN_CFG0), bEnable, VOP_LR_LA_OUT);
5565 // bw saving not support: LA/SBS
5566 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 0, VOP_420_BW_SAVE);
5567 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
5568 HAL_MVOP_LoadReg();
5569
5570 g_pHalMVOPCtx->bSub3DLRAltOutput = bEnable;
5571 return TRUE;
5572 }
5573
HAL_MVOP_SubSet3DLRAltSBSOutput(MS_BOOL bEnable)5574 MS_BOOL HAL_MVOP_SubSet3DLRAltSBSOutput(MS_BOOL bEnable)
5575 {
5576 //it works when 0x3C[0] = 1 and 0x3C[2] = 1
5577 //Set 0x3C[3] = 1 (3D L/R line alternative read, side-by-side output)
5578 HAL_WriteRegBit(SUB_REG(VOP_MULTI_WIN_CFG0), bEnable, VOP_LR_LA2SBS_OUT);
5579 g_pHalMVOPCtx->bSub3DLRAltSBSOutput = bEnable;
5580 return TRUE;
5581 }
5582
HAL_MVOP_SubGet3DLRAltOutput(void)5583 MS_BOOL HAL_MVOP_SubGet3DLRAltOutput(void)
5584 {
5585 if (g_pHalMVOPCtx == NULL)
5586 {
5587 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5588 return FALSE;
5589 }
5590 return g_pHalMVOPCtx->bSub3DLRAltOutput;
5591 }
5592
HAL_MVOP_SubGet3DLRAltSBSOutput(void)5593 MS_BOOL HAL_MVOP_SubGet3DLRAltSBSOutput(void)
5594 {
5595 return g_pHalMVOPCtx->bSub3DLRAltSBSOutput;
5596 }
5597
HAL_MVOP_SubGetOutput3DType(void)5598 EN_MVOP_Output_3D_TYPE HAL_MVOP_SubGetOutput3DType(void)
5599 {
5600 EN_MVOP_Output_3D_TYPE en3DType = E_MVOP_OUTPUT_3D_NONE;
5601 if(g_pHalMVOPCtx->bSub3DLRMode)
5602 {
5603 if(g_pHalMVOPCtx->bSub3DLRAltSBSOutput)
5604 {
5605 en3DType = E_MVOP_OUTPUT_3D_SBS;
5606 }
5607 else
5608 {
5609 en3DType = E_MVOP_OUTPUT_3D_TB;
5610 }
5611 }
5612 else if(g_pHalMVOPCtx->bSub3DLRAltOutput)
5613 {
5614 en3DType = E_MVOP_OUTPUT_3D_LA;
5615 }
5616 return en3DType;
5617 }
5618
5619
5620 #endif
5621
5622
5623 #define MVOP_INT_UF BIT0
5624 #define MVOP_INT_OF BIT1
5625 #define MVOP_INT_VSYNC BIT2
5626 #define MVOP_INT_HSYNC BIT3
5627 #define MVOP_INT_RDY BIT4
5628 #define MVOP_INT_FLD BIT5
5629 #define MVOP_INT_ALL (BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
5630
5631 const MS_U16 u16MvopRegBase[2] = { MVOP_REG_BASE, MVOP_SUB_REG_BASE};
5632 #define MAP_REG(_id, _reg) ((_reg) - MVOP_REG_BASE + u16MvopRegBase[(_id)])
5633
HAL_MVOP_IntEnableMask(MVOP_DevID eID,MS_U8 eIntType)5634 MS_BOOL HAL_MVOP_IntEnableMask(MVOP_DevID eID, MS_U8 eIntType)
5635 {
5636 MS_BOOL bRet = TRUE;
5637 MS_U16 u16Reg = MAP_REG( eID, VOP_INT_MASK);
5638 MS_U8 u8Mask = 0;
5639
5640 u8Mask = HAL_ReadByte(u16Reg);
5641
5642 if (E_MVOP_INT_NONE != eIntType)
5643 {
5644 u8Mask = (E_MVOP_INT_VSYNC == (eIntType&E_MVOP_INT_VSYNC)) ?
5645 (u8Mask & ~MVOP_INT_VSYNC) : (u8Mask);
5646 u8Mask = (E_MVOP_INT_HSYNC == (eIntType&E_MVOP_INT_HSYNC)) ?
5647 (u8Mask & ~MVOP_INT_HSYNC) : (u8Mask);
5648 u8Mask = (E_MVOP_INT_FDCHNG == (eIntType&E_MVOP_INT_FDCHNG)) ?
5649 (u8Mask & ~MVOP_INT_FLD) : (u8Mask);
5650 u8Mask = (E_MVOP_INT_RDY == (eIntType&E_MVOP_INT_RDY)) ?
5651 (u8Mask & ~MVOP_INT_RDY) : (u8Mask);
5652 u8Mask = (E_MVOP_INT_BUFF_UF == (eIntType&E_MVOP_INT_BUFF_UF)) ?
5653 (u8Mask & ~MVOP_INT_UF) : (u8Mask);
5654 u8Mask = (E_MVOP_INT_BUFF_OF == (eIntType&E_MVOP_INT_BUFF_OF)) ?
5655 (u8Mask & ~MVOP_INT_OF) : (u8Mask);
5656 }
5657 else //mask all
5658 {
5659 u8Mask |= MVOP_INT_ALL;
5660 }
5661
5662 //MVOP_PRINTF("u8Mask %x ", u8Mask);
5663 HAL_WriteByteMask(u16Reg, u8Mask, MVOP_INT_ALL);
5664 //u8Mask = HAL_ReadByte(u16Reg);
5665 //MVOP_PRINTF("==> %x \n", u8Mask);
5666 return bRet;
5667 }
5668
HAL_MVOP_IntGetStatus(MVOP_DevID eID)5669 MS_U8 HAL_MVOP_IntGetStatus(MVOP_DevID eID)
5670 {
5671 MS_U8 u8IntVal = 0;
5672 MS_U8 u8IntType = E_MVOP_INT_NONE;
5673 MS_U16 u16Reg = MAP_REG(eID, (VOP_INT_MASK+1));
5674
5675 u8IntVal = HAL_ReadByte(u16Reg) & MVOP_INT_ALL;
5676 //MVOP_PRINTF("u8IntVal %x\n", u8IntVal);
5677 if ((u8IntVal & MVOP_INT_VSYNC) == MVOP_INT_VSYNC)
5678 {
5679 u8IntType |= E_MVOP_INT_VSYNC;
5680 }
5681 if ((u8IntVal & MVOP_INT_HSYNC) == MVOP_INT_HSYNC)
5682 {
5683 u8IntType |= E_MVOP_INT_HSYNC;
5684 }
5685 if ((u8IntVal & MVOP_INT_FLD) == MVOP_INT_FLD)
5686 {
5687 u8IntType |= E_MVOP_INT_FDCHNG;
5688 }
5689 if ((u8IntVal & MVOP_INT_RDY) == MVOP_INT_RDY)
5690 {
5691 u8IntType |= E_MVOP_INT_RDY;
5692 }
5693 if ((u8IntVal & MVOP_INT_UF) == MVOP_INT_UF)
5694 {
5695 u8IntType |= E_MVOP_INT_BUFF_UF;
5696 }
5697 if ((u8IntVal & MVOP_INT_OF) == MVOP_INT_OF)
5698 {
5699 u8IntType |= E_MVOP_INT_BUFF_OF;
5700 }
5701 return u8IntType;
5702 }
5703
5704 #if 0
5705 void HAL_MVOP_SetStartX(MS_U16 u16Length)
5706 {
5707 if(g_pHalMVOPCtx == NULL)
5708 {
5709 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5710 return;
5711 }
5712 g_pHalMVOPCtx->g_u16SetStartX = u16Length;
5713 HAL_WriteByte(VOP_REG_CROP_HSTART, u16Length & 0xff);
5714 HAL_WriteByte((VOP_REG_CROP_HSTART + 1),((u16Length) >> (8)) & (0x1f));
5715 // Write trigger
5716 HAL_MVOP_LoadReg();
5717 }
5718
5719
5720 void HAL_MVOP_SetStartY(MS_U16 u16Length, MS_BOOL bIs4Align)
5721 {
5722 if(g_pHalMVOPCtx == NULL)
5723 {
5724 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5725 return;
5726 }
5727 g_pHalMVOPCtx->g_u16SetStartY = u16Length;
5728 g_pHalMVOPCtx->g_bIsY4Align = bIs4Align;
5729 HAL_WriteByte(VOP_REG_CROP_VSTART, u16Length & 0xff);
5730 HAL_WriteByte((VOP_REG_CROP_VSTART + 1), ((u16Length) >> (8)) & (0x1f));
5731 // Write trigger
5732 HAL_MVOP_LoadReg();
5733 }
5734
5735
5736 void HAL_MVOP_SetPicWidthMinus(MS_U16 u16Sizes)
5737 {
5738 if(g_pHalMVOPCtx == NULL)
5739 {
5740 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5741 return;
5742 }
5743 if(u16Sizes == 0)
5744 {
5745 HAL_WriteByte(VOP_REG_CROP_HSIZE, u16Sizes);
5746 HAL_WriteByte((VOP_REG_CROP_HSIZE + 1), u16Sizes);
5747 }
5748 else
5749 {
5750 u16Sizes = u16Sizes + 1 - g_pHalMVOPCtx->g_u16SetStartX ;
5751 HAL_WriteByte(VOP_REG_CROP_HSIZE, u16Sizes & 0xff);
5752 HAL_WriteByte((VOP_REG_CROP_HSIZE + 1), ((u16Sizes) >> (8)) & (0x1f));
5753 }
5754 g_pHalMVOPCtx->g_u16SetXSize= u16Sizes;
5755 // Write trigger
5756 HAL_MVOP_LoadReg();
5757 }
5758
5759 void HAL_MVOP_SetPicHeightMinus(MS_U16 u16Sizes)
5760 {
5761 MS_U32 u32YOffset=0;
5762 MS_U32 u32UVOffset=0;
5763 MS_BOOL bIsInterlace = 0;
5764
5765 if(g_pHalMVOPCtx == NULL)
5766 {
5767 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5768 return;
5769 }
5770
5771 if(u16Sizes == 0)
5772 {
5773 HAL_WriteByte(VOP_REG_CROP_VSIZE, u16Sizes);
5774 HAL_WriteByte((VOP_REG_CROP_VSIZE + 1), u16Sizes);
5775 }
5776 else
5777 {
5778 u16Sizes = u16Sizes + 1 - g_pHalMVOPCtx->g_u16SetStartY ;
5779 if(g_pHalMVOPCtx->g_bIsY4Align)
5780 u16Sizes -= 2;
5781
5782 HAL_WriteByte(VOP_REG_CROP_VSIZE, (u16Sizes) & 0xff);
5783 HAL_WriteByte((VOP_REG_CROP_VSIZE + 1), ((u16Sizes) >> (8)) & (0x1f));
5784 }
5785 g_pHalMVOPCtx->g_u16SetYSize= u16Sizes;
5786 //***********************************************************************************//
5787 //@clippers crop sw patch
5788 // Synchronization: video broken, looks like pitch incorrect.
5789 // Hit condition: (g_pHalMVOPCtx->g_u16SetStartX%16)+(g_pHalMVOPCtx->g_u16SetXSize%16) > 16
5790 // Fix: after monet
5791 // Limitation: have to set MDrv_MVOP_SetImageWidthHight after:
5792 // MDrv_MVOP_SetInputCfg / MDrv_MVOP_SetOutputCfg / MDrv_MVOP_SetBaseAdd / MDrv_MVOP_SetStartPos
5793 //***********************************************************************************//
5794 if((g_pHalMVOPCtx->g_u16SetXSize == 0) && (g_pHalMVOPCtx->g_u16SetYSize == 0))
5795 {
5796 HAL_WriteRegBit(VOP_REG_SINGLE_3D_L, 0, VOP_FORCE_SKIP);
5797 HAL_WriteByteMask(VOP_REG_SINGLE_3D_L, 0, VOP_SKIP_SIZE_LVIEW);
5798 HAL_WriteByteMask(VOP_REG_SINGLE_3D_H, 0, VOP_SKIP_SIZE_RVIEW);
5799 HAL_WriteRegBit(VOP_REG_ENABLE_SKIP, 0, VOP_SKIP_LVIEW);
5800 HAL_WriteRegBit(VOP_REG_ENABLE_SKIP, 0, VOP_SKIP_RVIEW);
5801 if(g_pHalMVOPCtx->g_bIsSetCrop == TRUE)
5802 {
5803 u32YOffset = HAL_MVOP_GetYBaseAdd() +4;
5804 u32UVOffset = HAL_MVOP_GetUVBaseAdd() +4;
5805 bIsInterlace = HAL_ReadRegBit(VOP_CTRL0, BIT7);
5806 HAL_MVOP_SetYUVBaseAdd(u32YOffset<<3, u32UVOffset<<3, !bIsInterlace,g_pHalMVOPCtx->bIs422);
5807 g_pHalMVOPCtx->g_bIsSetCrop = FALSE;
5808 }
5809 HAL_MVOP_LoadReg();
5810 return;
5811 }
5812 MVOP_DBG("[Warning] clippers crop may hit hw bug: g_u16SetStartX = %d, g_u16SetXSize = %d\n",g_pHalMVOPCtx->g_u16SetStartX,g_pHalMVOPCtx->g_u16SetXSize);
5813 if(((g_pHalMVOPCtx->g_u16SetStartX%16)+(g_pHalMVOPCtx->g_u16SetXSize%16) > 16) && (g_pHalMVOPCtx->bIs422))
5814 {
5815 HAL_WriteRegBit(VOP_REG_SINGLE_3D_L, 1, VOP_FORCE_SKIP);
5816 HAL_WriteByteMask(VOP_REG_SINGLE_3D_L, (g_pHalMVOPCtx->g_u16SetStartX%16), VOP_SKIP_SIZE_LVIEW);
5817 HAL_WriteByteMask(VOP_REG_SINGLE_3D_H, (g_pHalMVOPCtx->g_u16SetStartX%16), VOP_SKIP_SIZE_RVIEW);
5818 HAL_WriteRegBit(VOP_REG_ENABLE_SKIP, 1, VOP_SKIP_LVIEW);
5819 HAL_WriteRegBit(VOP_REG_ENABLE_SKIP, 1, VOP_SKIP_RVIEW);
5820 if(g_pHalMVOPCtx->g_bIsSetCrop == FALSE)
5821 {
5822 u32YOffset = HAL_MVOP_GetYBaseAdd();
5823 u32UVOffset = HAL_MVOP_GetUVBaseAdd();
5824 if((u32YOffset < 4) || (u32UVOffset < 4))
5825 return;
5826
5827 u32YOffset -= 4;
5828 u32UVOffset -= 4;
5829 bIsInterlace = HAL_ReadRegBit(VOP_CTRL0, BIT7);
5830 HAL_MVOP_SetYUVBaseAdd(u32YOffset<<3, u32UVOffset<<3, !bIsInterlace,g_pHalMVOPCtx->bIs422);
5831 g_pHalMVOPCtx->g_bIsSetCrop = TRUE;
5832 }
5833 }
5834 // Write trigger
5835 HAL_MVOP_LoadReg();
5836 }
5837 #endif
HAL_MVOP_MaskDBRegCtrl(MVOP_DevID eID,MS_BOOL bEnable,MVOPMSAKDBREGCTRL eModeCtrl)5838 void HAL_MVOP_MaskDBRegCtrl(MVOP_DevID eID, MS_BOOL bEnable ,MVOPMSAKDBREGCTRL eModeCtrl)
5839 {
5840 MS_U8 regval;
5841 MS_U8 u8Arg;
5842
5843 if (eModeCtrl> E_MVOP_INV_OP_VS)
5844 {
5845 return;
5846 }
5847 #if 0
5848 else if (eModeCtrl >= E_MVOP_CHKSUM_422_SWAP)
5849 {
5850 regval = HAL_ReadByte(MVOP_MASK_DB_REG1);
5851 }
5852 else
5853 {
5854 regval = HAL_ReadByte(MVOP_MASK_DB_REG0);
5855 }
5856 #endif
5857
5858 switch(eID)
5859 {
5860 case E_MVOP_DEV_0:
5861 {
5862 switch(eModeCtrl)
5863 {
5864 case E_MVOP_MASK_DB_REG:
5865 //u8Arg = MVOP_MASK_DB_REG;
5866 break;
5867 case E_MVOP_EN_DB_REG:
5868 //u8Arg = MVOP_EN_DB_REG;
5869 break;
5870 case E_MVOP_DEBUG_SEL:
5871 //u8Arg = MVOP_DEBUG_SEL;
5872 break;
5873 case E_MVOP_UPDATE_SEL:
5874 //u8Arg = MVOP_UPDATE_SEL;
5875 break;
5876 case E_MVOP_RST_START_SEL:
5877 //u8Arg = MVOP_RST_START_SEL;
5878 break;
5879 case E_MVOP_SC_VSYNC_SEL:
5880 //u8Arg = MVOP_SC_VSYNC_SEL;
5881 break;
5882 case E_MVOP_READ_IP_BASE_SEL:
5883 //u8Arg = MVOP_READ_IP_BASE_SEL;
5884 break;
5885 case E_MVOP_CHKSUM_422_SWAP:
5886 //u8Arg = MVOP_CHKSUM_422_SWAP;
5887 break;
5888 case E_MVOP_CHKSUM_FULL_C:
5889 //u8Arg = MVOP_CHKSUM_FULL_C;
5890 break;
5891 case E_MVOP_OFF_LATCH_CRC:
5892 //u8Arg = MVOP_OFF_LATCH_CRC;
5893 break;
5894 case E_MVOP_SEL_OP_FIELD:
5895 {
5896 u8Arg = VOP_MVD_VS_MD;
5897 regval = HAL_ReadByte(VOP_CTRL0);
5898 if ( bEnable )
5899 {
5900 regval &= ~u8Arg;
5901 }
5902 else
5903 {
5904 regval |= u8Arg;
5905 }
5906 HAL_WriteByte(VOP_CTRL0, regval);
5907
5908 u8Arg = VOP_RGB_FILED_BYPASS;
5909 regval = HAL_ReadByte(VOP_REG_DUMMY_3D_1);
5910 if ( bEnable )
5911 {
5912 regval &= ~u8Arg;
5913 }
5914 else
5915 {
5916 regval |= u8Arg;
5917 }
5918 HAL_WriteByte(VOP_REG_DUMMY_3D_1, regval);
5919 //xc use bob mode(only use one field de-interlace)
5920 // xc receive top/bot toggle signal, but only one field
5921 #if 0
5922 // xc receive top/bot toggle signal, but only one field
5923 u8Arg = VOP_REF_SELF_FLD;
5924 regval = HAL_ReadByte(VOP_MIRROR_CFG_HI);
5925 if ( bEnable )
5926 {
5927 regval |= u8Arg;
5928 }
5929 else
5930 {
5931 regval &= ~u8Arg;
5932 }
5933 HAL_WriteByte(VOP_MIRROR_CFG_HI, regval);
5934 //if hardwired mode
5935 if(BIT2 != HAL_ReadRegBit(VOP_MPG_JPG_SWITCH, BIT2))
5936 {
5937 if ( bEnable )
5938 {
5939 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_L, 0, VOP_INFO_FROM_CODEC_FIELD);
5940 }
5941 else
5942 {
5943 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_L, 1, VOP_INFO_FROM_CODEC_FIELD);
5944 }
5945 }
5946 #endif
5947 HAL_MVOP_LoadReg();
5948 break;
5949 }
5950 case E_MVOP_INV_OP_FIELD:
5951 //u8Arg = MVOP_INV_OP_FIELD;
5952 break;
5953 case E_MVOP_INV_OP_VS:
5954 //u8Arg = MVOP_INV_OP_VS;
5955 break;
5956 default:
5957 //u8Arg = 0x0;
5958 break;
5959
5960 }
5961 break;
5962 }
5963 #if MVOP_SUPPORT_SUB
5964 case E_MVOP_DEV_1:
5965 {
5966 switch(eModeCtrl)
5967 {
5968 case E_MVOP_MASK_DB_REG:
5969 //u8Arg = MVOP_MASK_DB_REG;
5970 break;
5971 case E_MVOP_EN_DB_REG:
5972 //u8Arg = MVOP_EN_DB_REG;
5973 break;
5974 case E_MVOP_DEBUG_SEL:
5975 //u8Arg = MVOP_DEBUG_SEL;
5976 break;
5977 case E_MVOP_UPDATE_SEL:
5978 //u8Arg = MVOP_UPDATE_SEL;
5979 break;
5980 case E_MVOP_RST_START_SEL:
5981 //u8Arg = MVOP_RST_START_SEL;
5982 break;
5983 case E_MVOP_SC_VSYNC_SEL:
5984 //u8Arg = MVOP_SC_VSYNC_SEL;
5985 break;
5986 case E_MVOP_READ_IP_BASE_SEL:
5987 //u8Arg = MVOP_READ_IP_BASE_SEL;
5988 break;
5989 case E_MVOP_CHKSUM_422_SWAP:
5990 //u8Arg = MVOP_CHKSUM_422_SWAP;
5991 break;
5992 case E_MVOP_CHKSUM_FULL_C:
5993 //u8Arg = MVOP_CHKSUM_FULL_C;
5994 break;
5995 case E_MVOP_OFF_LATCH_CRC:
5996 //u8Arg = MVOP_OFF_LATCH_CRC;
5997 break;
5998 case E_MVOP_SEL_OP_FIELD:
5999 {
6000 u8Arg = VOP_MVD_VS_MD;
6001 regval = HAL_ReadByte(SUB_REG(VOP_CTRL0));
6002 if ( bEnable )
6003 {
6004 regval &= ~u8Arg;
6005 }
6006 else
6007 {
6008 regval |= u8Arg;
6009 }
6010 HAL_WriteByte(SUB_REG(VOP_CTRL0), regval);
6011
6012 u8Arg = VOP_RGB_FILED_BYPASS;
6013 regval = HAL_ReadByte(SUB_REG(VOP_REG_DUMMY_3D_1));
6014 if ( bEnable )
6015 {
6016 regval &= ~u8Arg;
6017 }
6018 else
6019 {
6020 regval |= u8Arg;
6021 }
6022 HAL_WriteByte(SUB_REG(VOP_REG_DUMMY_3D_1), regval);
6023 //xc use bob mode(only use one field de-interlace)
6024 // xc receive top/bot toggle signal, but only one field
6025 #if 0
6026 // xc receive top/bot toggle signal, but only one field
6027 u8Arg = VOP_REF_SELF_FLD;
6028 regval = HAL_ReadByte(VOP_MIRROR_CFG_HI);
6029 if ( bEnable )
6030 {
6031 regval |= u8Arg;
6032 }
6033 else
6034 {
6035 regval &= ~u8Arg;
6036 }
6037 HAL_WriteByte(VOP_MIRROR_CFG_HI, regval);
6038 //if hardwired mode
6039 if(BIT2 != HAL_ReadRegBit(VOP_MPG_JPG_SWITCH, BIT2))
6040 {
6041 if ( bEnable )
6042 {
6043 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_L, 0, VOP_INFO_FROM_CODEC_FIELD);
6044 }
6045 else
6046 {
6047 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_L, 1, VOP_INFO_FROM_CODEC_FIELD);
6048 }
6049 }
6050 #endif
6051 HAL_MVOP_SubLoadReg();
6052 break;
6053 }
6054 case E_MVOP_INV_OP_FIELD:
6055 //u8Arg = MVOP_INV_OP_FIELD;
6056 break;
6057 case E_MVOP_INV_OP_VS:
6058 //u8Arg = MVOP_INV_OP_VS;
6059 break;
6060 default:
6061 //u8Arg = 0x0;
6062 break;
6063
6064 }
6065 break;
6066 }
6067 #endif
6068 default:
6069 break;
6070 }
6071 #if 0
6072 if ( bEnable )
6073 {
6074 regval |= u8Arg;
6075 }
6076 else
6077 {
6078 regval &= ~u8Arg;
6079 }
6080 if (eModeCtrl >= E_MVOP_CHKSUM_422_SWAP)
6081 {
6082 HAL_WriteByte(MVOP_MASK_DB_REG1, regval);
6083 }
6084 else
6085 {
6086 HAL_WriteByte(MVOP_MASK_DB_REG0, regval);
6087 }
6088 #endif
6089
6090
6091 }
6092
6093
6094 //patch for Kappa
HAL_MVOP_SetDeb2MVDFrameModeCtrl(MVOP_DevID eID,MS_BOOL bEnable,MVOPDEB2MVDFRAMECTRL eModeCtrl)6095 void HAL_MVOP_SetDeb2MVDFrameModeCtrl(MVOP_DevID eID, MS_BOOL bEnable, MVOPDEB2MVDFRAMECTRL eModeCtrl)
6096 {
6097 MS_U8 regval;
6098 MS_U8 u8Arg;
6099
6100 switch(eID)
6101 {
6102 case E_MVOP_DEV_0:
6103 {
6104 regval = HAL_ReadByte(VOP_INFO_FROM_CODEC_L);
6105 switch (eModeCtrl)
6106 {
6107 case E_MVOP_DEB2MVD_FRAME_MODE:
6108 u8Arg = 0x0;
6109 break;
6110 case E_MVOP_DEB2MVD_FIELD_INV:
6111 u8Arg = 0x0;
6112 break;
6113 case E_MVOP_SIZE_FROM_MVD:
6114 u8Arg = VOP_INFO_FROM_CODEC_SIZE;
6115 if (bEnable)
6116 {
6117 //crop = 0, then size could be from vdec.
6118 HAL_MVOP_SetPicWidthMinus(E_MVOP_DEV_0, 0, 0);
6119 HAL_MVOP_SetPicHeightMinus(E_MVOP_DEV_0, 0, 0);
6120 }
6121 break;
6122 case E_MVOP_SEQ_FROM_MVD:
6123 u8Arg = 0x0;
6124 break;
6125 default:
6126 u8Arg = 0x0;
6127 break;
6128 }
6129
6130 if (bEnable)
6131 {
6132 regval |= u8Arg;
6133 }
6134 else
6135 {
6136 regval &= ~u8Arg;
6137 }
6138
6139 HAL_WriteByte(VOP_INFO_FROM_CODEC_L, regval);
6140
6141 // Write trigger
6142 HAL_MVOP_LoadReg();
6143 }
6144 break;
6145 #if MVOP_SUPPORT_SUB
6146 case E_MVOP_DEV_1:
6147 {
6148 regval = HAL_ReadByte(SUB_REG(VOP_INFO_FROM_CODEC_L));
6149 switch (eModeCtrl)
6150 {
6151 case E_MVOP_DEB2MVD_FRAME_MODE:
6152 u8Arg = 0x0;
6153 break;
6154 case E_MVOP_DEB2MVD_FIELD_INV:
6155 u8Arg = 0x0;
6156 break;
6157 case E_MVOP_SIZE_FROM_MVD:
6158 u8Arg = VOP_INFO_FROM_CODEC_SIZE;
6159 if (bEnable)
6160 {
6161 //crop = 0, then size could be from vdec.
6162 HAL_MVOP_SetPicWidthMinus(SUB_REG(E_MVOP_DEV_0), 0, 0);
6163 HAL_MVOP_SetPicHeightMinus(SUB_REG(E_MVOP_DEV_0), 0, 0);
6164 }
6165 break;
6166 case E_MVOP_SEQ_FROM_MVD:
6167 u8Arg = 0x0;
6168 break;
6169 default:
6170 u8Arg = 0x0;
6171 break;
6172 }
6173
6174 if (bEnable)
6175 {
6176 regval |= u8Arg;
6177 }
6178 else
6179 {
6180 regval &= ~u8Arg;
6181 }
6182
6183 HAL_WriteByte(SUB_REG(VOP_INFO_FROM_CODEC_L), regval);
6184
6185 // Write trigger
6186 HAL_MVOP_SubLoadReg();
6187 }
6188 break;
6189 #endif
6190 default:
6191 break;
6192 }
6193
6194 }
6195
6196 // for kappa
HAL_MVOP_BaseFromIPCtrl(MVOP_DevID eID,MS_BOOL bEnable,MVOPBASEFROMIPCTRL eModeCtrl)6197 void HAL_MVOP_BaseFromIPCtrl(MVOP_DevID eID, MS_BOOL bEnable ,MVOPBASEFROMIPCTRL eModeCtrl )
6198 {
6199 MS_U8 regval;
6200 MS_U8 u8Arg;
6201
6202 if ( eModeCtrl>
6203 #if NO_MVOP_PATCH
6204 E_MVOP_FD_MASK_INV)
6205 #else
6206 E_MVOP_SIZE_FROM_MVD_PATCH)
6207 #endif
6208 {
6209 return;
6210 }
6211 else if (eModeCtrl >= E_MVOP_FMT_FROM_MVD)
6212 {
6213 regval = HAL_ReadByte(VOP_FD_MASK); // ox30
6214 }
6215 else
6216 {
6217 regval = HAL_ReadByte(VOP_INFO_FROM_CODEC_L); //0x38
6218 }
6219
6220 switch(eModeCtrl)
6221 {
6222 case E_MVOP_BASE_FROM_IP:
6223 u8Arg = 0x0;
6224 break;
6225 case E_MVOP_SRC_FROM_MVD:
6226 u8Arg = 0x0;
6227 break;
6228 case E_MVOP_FIELD_FROM_MVD:
6229 u8Arg = 0x0;
6230 break;
6231 case E_MVOP_FIELD_FROM_MVD_INV:
6232 u8Arg = 0x0;
6233 break;
6234 case E_MVOP_PITCH_FROM_IP:
6235 u8Arg = 0x0;
6236 break;
6237 case E_MVOP_FMT_FROM_MVD:
6238 u8Arg = 0x0;
6239 break;
6240 case E_MVOP_FD_MASK_CLR:
6241 u8Arg = VOP_FD_MASK_CLR;
6242 break;
6243 case E_MVOP_FD_MASK_INV:
6244 u8Arg = VOP_FD_MASK_INV;
6245 break;
6246 #if (NO_MVOP_PATCH == 0)
6247 case E_MVOP_SIZE_FROM_MVD_PATCH:
6248 u8Arg = 0x0;
6249 break;
6250 case E_MVOP_SEQ_FROM_MVD_PATCH:
6251 u8Arg = 0x0;
6252 break;
6253 #endif
6254 default:
6255 u8Arg = 0x0;
6256 break;
6257
6258 }
6259 if ( bEnable )
6260 {
6261 regval |= u8Arg;
6262 }
6263 else
6264 {
6265 regval &= ~u8Arg;
6266 }
6267 if (eModeCtrl >= E_MVOP_FMT_FROM_MVD)
6268 {
6269 HAL_WriteByte(VOP_FD_MASK, regval);
6270 }
6271 else
6272 {
6273 HAL_WriteByte(VOP_INFO_FROM_CODEC_L, regval);
6274 }
6275
6276
6277 }
6278