1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
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20 //
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // ("MStar Confidential Information") by the recipient.
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90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #include "MsCommon.h"
101 #ifndef MSOS_TYPE_LINUX_KERNEL
102 #include <string.h>
103 #endif
104 #include "MsTypes.h"
105 #include "MsIRQ.h"
106 #include "MsOS.h"
107 #include "drvMVOP.h"
108 #include "drvMIU.h"
109
110 // Internal Definition
111 #include "regMVOP.h"
112 #include "halMVOP.h"
113
114 #ifndef ANDROID
115 #define MVOP_PRINTF printf
116 #else
117 #include <sys/mman.h>
118 #include <cutils/ashmem.h>
119 #include <cutils/log.h>
120
121 #define MVOP_PRINTF ALOGD
122 #endif
123
124 // Common
125 #ifdef MSOS_TYPE_LINUX_KERNEL
126 #include <asm/div64.h>
127 #else
128 #define do_div(x,y) ((x)/=(y))
129 #define do_mod(x,y) ((x)%=(y))
130 #endif
131 //-------------------------------------------------------------------------------------------------
132 // Driver Compiler Options
133 //-------------------------------------------------------------------------------------------------
134
135
136 //-------------------------------------------------------------------------------------------------
137 // Local Defines
138 //-------------------------------------------------------------------------------------------------
139 #define MPLL_CLOCK_216 (216000000ULL)
140 #define MPLL_CLOCK_432 (432000000ULL)
141
142 #define BIT0 BIT(0)
143 #define BIT1 BIT(1)
144 #define BIT2 BIT(2)
145 #define BIT3 BIT(3)
146 #define BIT4 BIT(4)
147 #define BIT5 BIT(5)
148 #define BIT6 BIT(6)
149 #define BIT7 BIT(7)
150 #define BIT15 BIT(15)
151
152 #define ALIGN_UPTO_16(x) ((((x) + 15) >> 4) << 4)
153 #define ALIGN_UPTO_4(x) ((((x) + 3) >> 2) << 2)
154 #define ALIGN_UPTO_2(x) ((((x) + 1) >> 1) << 1)
155
156 #define MVOP_VBlank 45
157 #define MVOP_HBlank_SD 200
158 #define MVOP_HBlank_HD 300
159 #if 0
160 static MS_U32 u32RiuBaseAdd=0;
161 static MS_BOOL bMirrorModeVer = 0;
162 static MS_BOOL bMirrorModeHor = 0;
163 static MS_BOOL bMirrorMode=0;
164 static MS_BOOL bSubMirrorModeVer = 0;
165 static MS_BOOL bSubMirrorModeHor = 0;
166 static MS_BOOL bSubMirrorMode=0;
167 static MS_BOOL bEnableFreerunMode = FALSE;
168 static MS_BOOL bSubEnableFreerunMode = FALSE;
169 static MS_BOOL b3DLRMode=0; /// 3D L/R dual buffer mode
170 static MS_BOOL bSub3DLRMode=0;
171 static MS_BOOL b3DLRAltOutput = FALSE; /// 3D L/R line alternative output
172 static MS_BOOL bNewVSyncMode = FALSE;
173 static MVOP_RptFldMode eRepeatField = E_MVOP_RPTFLD_NONE; /// mvop output repeating fields for single field input.
174 static MVOP_RptFldMode eSubRepeatField = E_MVOP_RPTFLD_NONE; /// mvop output repeating fields for single field input.
175 static MVOP_RgbFormat eMainRgbFmt = E_MVOP_RGB_NONE;
176 static MVOP_RgbFormat eSubRgbFmt = E_MVOP_RGB_NONE;
177 #endif
178
179 typedef struct
180 {
181 MS_BOOL bMirrorModeVer;
182 MS_BOOL bMirrorModeHor;
183 MS_BOOL bMirrorMode;
184 MS_BOOL bEnableFreerunMode;
185
186 MS_BOOL b3DLRMode; /// 3D L/R dual buffer mode
187
188 MS_BOOL b3DLRAltOutput; /// 3D L/R line alternative output
189 MS_BOOL b3DLRAltSBSOutput; /// 3D L/R side by side output
190 MS_BOOL bNewVSyncMode;
191 MVOP_RptFldMode eRepeatField; /// mvop output repeating fields for single field input.
192 MVOP_RgbFormat eMainRgbFmt;
193 MS_BOOL bIsInit;
194 MS_BOOL bRptPreVsync;
195 MS_BOOL bIs422;
196 MS_BOOL bIsH265;
197 MS_BOOL bIsHS;
198 MS_U16 u16CropXStart;
199 MS_U16 u16CropYStart;
200 MS_U16 u16CropXSize;
201 MS_U16 u16CropYSize;
202 MS_BOOL bIs2p;
203 MS_BOOL bIsEnable;
204 MS_U16 u16VsyncLines;
205 MVOP_OutputImodeType eInterlaceType;
206 MS_BOOL bIs265DV;
207 #if MVOP_SUPPORT_SUB
208 MS_BOOL bSubMirrorModeVer;
209 MS_BOOL bSubMirrorModeHor;
210 MS_BOOL bSubMirrorMode;
211 MS_BOOL bSubEnableFreerunMode;
212 MS_BOOL bSub3DLRMode;
213 MS_BOOL bSubNewVSyncMode;
214 MVOP_RptFldMode eSubRepeatField; /// mvop output repeating fields for single field input.
215 MVOP_RgbFormat eSubRgbFmt;
216 MS_BOOL bSubIsInit;
217 MS_BOOL bSubRptPreVsync;
218 MS_BOOL bSubIs422;
219 MS_BOOL bSubIsH265;
220 MS_BOOL bSub3DLRAltOutput; /// 3D L/R line alternative output
221 MS_BOOL bSub3DLRAltSBSOutput;
222 MS_BOOL bSubIsHS;
223 MS_U16 u16SubCropXStart;
224 MS_U16 u16SubCropYStart;
225 MS_U16 u16SubCropXSize;
226 MS_U16 u16SubCropYSize;
227 MS_BOOL bSubIs2p;
228 MS_BOOL bSubIsEnable;
229 MS_U16 u16SubVsyncLines;
230 MVOP_OutputImodeType eSubInterlaceType;
231 #endif
232 }MVOP_CTX_HAL;
233
234 static MVOP_CTX_HAL *g_pHalMVOPCtx = NULL;
235 static MS_VIRT u32RiuBaseAdd=0;
236
237 #ifndef MSOS_TYPE_LINUX
238 MVOP_CTX_HAL g_stmvopHalCtx;
239 #endif
240 #if defined(SUPPORT_X_MODEL_FEATURE)
241 MVOP_CTX_HAL g_stmvopHalCtx;
242 #endif
243 #define RIU_MAP u32RiuBaseAdd //obtained in init
244
245 #define RIU8 ((unsigned char volatile *) RIU_MAP)
246 #define RIU16 ((MS_U16 volatile *) RIU_MAP)
247 #define MST_MACRO_START do {
248 #define MST_MACRO_END } while (0)
249
250 #define HAL_WriteByte( u32Reg, u8Val ) \
251 MST_MACRO_START \
252 if ( __builtin_constant_p( u32Reg ) ) \
253 { \
254 RIU8[((u32Reg) * 2) - ((u32Reg) & 1)] = u8Val; \
255 } \
256 else \
257 { \
258 RIU8[(u32Reg << 1) - (u32Reg & 1)] = u8Val; \
259 } \
260 MST_MACRO_END
261
262 #define HAL_ReadByte( u32Reg ) \
263 (__builtin_constant_p( u32Reg ) ? \
264 (((u32Reg) & 0x01) ? RIU8[(u32Reg) * 2 - 1] : RIU8[(u32Reg) * 2]) : \
265 (RIU8[(u32Reg << 1) - (u32Reg & 1)]))
266
267 #define HAL_Read2Byte( u32Reg ) \
268 (RIU16[u32Reg])
269
270 #define HAL_ReadRegBit( u32Reg, u8Mask ) \
271 (RIU8[(u32Reg) * 2 - ((u32Reg) & 1)] & (u8Mask))
272
273 #define HAL_WriteRegBit( u32Reg, bEnable, u8Mask ) \
274 MST_MACRO_START \
275 MS_U32 u32Reg8 = ((u32Reg) * 2) - ((u32Reg) & 1); \
276 RIU8[u32Reg8] = (bEnable) ? (RIU8[u32Reg8] | (u8Mask)) : \
277 (RIU8[u32Reg8] & ~(u8Mask)); \
278 MST_MACRO_END
279
280 #define HAL_WriteByteMask( u32Reg, u8Val, u8Msk ) \
281 MST_MACRO_START \
282 MS_U32 u32Reg8 = ((u32Reg) * 2) - ((u32Reg) & 1); \
283 RIU8[u32Reg8] = (RIU8[u32Reg8] & ~(u8Msk)) | ((u8Val) & (u8Msk)); \
284 MST_MACRO_END
285
286 #define HAL_Write2Byte(u32Reg, u16Val) \
287 RIU16[u32Reg] = u16Val;
288
289 #define SUB_REG(x) (x-MVOP_REG_BASE+MVOP_SUB_REG_BASE)
290
291 #define _FUNC_NOT_USED() do {} while ( 0 )
292 #ifndef UNUSED
293 #define UNUSED(x) (void)(x)
294 #endif
295
296 #define LOWBYTE(u16) ((MS_U8)(u16))
297 #define HIGHBYTE(u16) ((MS_U8)((u16) >> 8))
298
299
300 #define VOP_ON_MIU1 ((HAL_ReadByte(0x12F9) & BIT2) == BIT2)
301 #define _MaskMiuReq_MVOP_R( m ) HAL_WriteRegBit(0x12C7, m, BIT2)
302 #define _MaskMiu1Req_MVOP_R( m ) HAL_WriteRegBit(0x06C7, m, BIT2)
303
304 #define HAL_MIU_SetReqMask( miu_clients, mask ) \
305 do { \
306 if (VOP_ON_MIU1 == 0) \
307 _MaskMiuReq_##miu_clients( mask ); \
308 else \
309 _MaskMiu1Req_##miu_clients( mask ); \
310 }while(0)
311
312 #define SUBVOP_ON_MIU1 ((HAL_ReadByte(0x12F9) & BIT2) == BIT2)
313 #define _MaskMiuReq_SUBMVOP_R( m ) HAL_WriteRegBit(0x12C7, m, BIT2)
314 #define _MaskMiu1Req_SUBMVOP_R( m ) HAL_WriteRegBit(0x06C7, m, BIT2)
315
316 #define HAL_MIU_SubSetReqMask( miu_clients, mask ) \
317 do { \
318 if (SUBVOP_ON_MIU1 == 0) \
319 _MaskMiuReq_##miu_clients( mask ); \
320 else \
321 _MaskMiu1Req_##miu_clients( mask ); \
322 }while(0)
323
324 #define MVOP_DBG_ENABLE 0
325 #if MVOP_DBG_ENABLE
326 #define MVOP_DBG(fmt, args...) MVOP_PRINTF(fmt, ##args)
327 #else
328 #define MVOP_DBG(fmt, args...) {}
329 #endif
330
331 typedef enum
332 {
333 E_MVOP_INIT_OK = 0,
334 E_MVOP_INIT_FAIL = 1,
335 E_MVOP_INIT_ALREADY_EXIST = 2
336 } MVOP_HalInitCtxResults;
337 //-------------------------------------------------------------------------------------------------
338 // Local Structures
339 //-------------------------------------------------------------------------------------------------
340
341
342 //-------------------------------------------------------------------------------------------------
343 // Global Variables
344 //-------------------------------------------------------------------------------------------------
345
346 #define Y_INFO 0
347 #define UV_INFO 1
348
349 //-------------------------------------------------------------------------------------------------
350 // Local Variables
351 //-------------------------------------------------------------------------------------------------
352
353
354 //-------------------------------------------------------------------------------------------------
355 // Debug Functions
356 //-------------------------------------------------------------------------------------------------
357
358
359 //-------------------------------------------------------------------------------------------------
360 // Local Functions
361 //-------------------------------------------------------------------------------------------------
362
363
364 //-------------------------------------------------------------------------------------------------
365 // Global Functions
366 //-------------------------------------------------------------------------------------------------
367
_HAL_MVOP_InitVarCtx(void)368 void _HAL_MVOP_InitVarCtx(void)
369 {
370 g_pHalMVOPCtx->bMirrorModeVer = 0;
371 g_pHalMVOPCtx->bMirrorModeHor = 0;
372 g_pHalMVOPCtx->bMirrorMode=0;
373 g_pHalMVOPCtx->bEnableFreerunMode = FALSE;
374 g_pHalMVOPCtx->b3DLRMode=0; /// 3D L/R dual buffer mode
375 g_pHalMVOPCtx->b3DLRAltOutput = FALSE; /// 3D L/R line alternative output
376 g_pHalMVOPCtx->b3DLRAltSBSOutput = FALSE;
377 g_pHalMVOPCtx->bNewVSyncMode = FALSE;
378 g_pHalMVOPCtx->eRepeatField = E_MVOP_RPTFLD_NONE; /// mvop output repeating fields for single field input.
379 g_pHalMVOPCtx->eMainRgbFmt = E_MVOP_RGB_NONE;
380 g_pHalMVOPCtx->bIsInit = 0;
381 g_pHalMVOPCtx->bRptPreVsync = 0;
382 g_pHalMVOPCtx->bIs422 = 0;
383 g_pHalMVOPCtx->bIsH265 = 0;
384 g_pHalMVOPCtx->bIsHS = FALSE;
385 g_pHalMVOPCtx->u16CropXStart = 0;
386 g_pHalMVOPCtx->u16CropYStart = 0;
387 g_pHalMVOPCtx->u16CropXSize = 0;
388 g_pHalMVOPCtx->u16CropYSize = 0;
389 g_pHalMVOPCtx->bIs2p = FALSE;
390 g_pHalMVOPCtx->bIsEnable = 0;
391 g_pHalMVOPCtx->u16VsyncLines = 0;
392 g_pHalMVOPCtx->eInterlaceType = E_MVOP_PRO;
393 g_pHalMVOPCtx->bIs265DV = 0;
394 }
395
_HAL_MVOP_SubInitVarCtx(void)396 void _HAL_MVOP_SubInitVarCtx(void)
397 {
398 #if MVOP_SUPPORT_SUB
399 g_pHalMVOPCtx->bSubMirrorModeVer = 0;
400 g_pHalMVOPCtx->bSubMirrorModeHor = 0;
401 g_pHalMVOPCtx->bSubMirrorMode=0;
402 g_pHalMVOPCtx->bSubEnableFreerunMode = FALSE;
403 g_pHalMVOPCtx->bSub3DLRMode=0;
404 g_pHalMVOPCtx->bSubNewVSyncMode = FALSE;
405 g_pHalMVOPCtx->eSubRepeatField = E_MVOP_RPTFLD_NONE; /// mvop output repeating fields for single field input.
406 g_pHalMVOPCtx->eSubRgbFmt = E_MVOP_RGB_NONE;
407 g_pHalMVOPCtx->bSubIsInit = 0;
408 g_pHalMVOPCtx->bSubRptPreVsync = 0;
409 g_pHalMVOPCtx->bSubIs422 = 0;
410 g_pHalMVOPCtx->bSubIsH265 = 0;
411 g_pHalMVOPCtx->bSub3DLRAltOutput = FALSE; /// 3D L/R line alternative output
412 g_pHalMVOPCtx->bSub3DLRAltSBSOutput = FALSE;
413 g_pHalMVOPCtx->bSubIsHS = FALSE;
414 g_pHalMVOPCtx->u16SubCropXStart = 0;
415 g_pHalMVOPCtx->u16SubCropYStart = 0;
416 g_pHalMVOPCtx->u16SubCropXSize = 0;
417 g_pHalMVOPCtx->u16SubCropYSize = 0;
418 g_pHalMVOPCtx->bSubIs2p = FALSE;
419 g_pHalMVOPCtx->bSubIsEnable = 0;
420 g_pHalMVOPCtx->u16SubVsyncLines = 0;
421 g_pHalMVOPCtx->eSubInterlaceType = E_MVOP_PRO;
422 #endif
423 }
424
_HAL_MVOP_InitContext(MS_BOOL * pbFirstDrvInstant)425 MVOP_HalInitCtxResults _HAL_MVOP_InitContext(MS_BOOL *pbFirstDrvInstant)
426 {
427 MS_BOOL bNeedInitShared = FALSE;
428
429 //check first init by MsOS_SHM_GetId / MSOS_SHM_QUERY
430 #if 0
431 if (g_pHalMVOPCtx)
432 {
433 // The context instance has been created already
434 // before somewhere sometime in the same process.
435 *pbFirstDrvInstant = bNeedInitShared;
436 //return E_MVOP_INIT_FAIL;
437 return E_MVOP_INIT_OK;
438 }
439 #endif
440
441 #if defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_LINUX_KERNEL)
442 #if !defined(SUPPORT_X_MODEL_FEATURE)
443 MS_U32 u32ShmId;
444 MS_VIRT u32Addr;
445 MS_U32 u32BufSize;
446
447 //MsOS_SHM_Init(); init in msos_init
448 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux MVOP HAL driver", sizeof(MVOP_CTX_HAL), &u32ShmId, &u32Addr, &u32BufSize, MSOS_SHM_QUERY))
449 {
450 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux MVOP HAL driver", sizeof(MVOP_CTX_HAL), &u32ShmId, &u32Addr, &u32BufSize, MSOS_SHM_CREATE))
451 {
452 MVOP_DBG(MVOP_PRINTF("MVOP: SHM allocation failed!\n");)
453 return E_MVOP_INIT_FAIL;
454 }
455 MVOP_DBG(MVOP_PRINTF("MVOP: [%s][%d] This is first initial 0x%08lx\n", __FUNCTION__, __LINE__, u32Addr);)
456 memset( (MS_U8*)u32Addr, 0, sizeof(MVOP_CTX_HAL));
457 bNeedInitShared = TRUE;
458 g_pHalMVOPCtx = (MVOP_CTX_HAL*)u32Addr;
459 _HAL_MVOP_InitVarCtx();
460 }
461 else
462 {
463 g_pHalMVOPCtx = (MVOP_CTX_HAL*)u32Addr;
464 bNeedInitShared = FALSE;
465 *pbFirstDrvInstant = bNeedInitShared;
466
467 return E_MVOP_INIT_ALREADY_EXIST;
468 }
469 #else
470 g_pHalMVOPCtx = &g_stmvopHalCtx;
471 bNeedInitShared = TRUE;
472 #endif
473 #else
474 g_pHalMVOPCtx = &g_stmvopHalCtx;
475 bNeedInitShared = TRUE;
476 #endif
477 *pbFirstDrvInstant = bNeedInitShared;
478
479 if (bNeedInitShared)
480 {
481 memset(g_pHalMVOPCtx, 0, sizeof(*g_pHalMVOPCtx));
482 }
483
484 return E_MVOP_INIT_OK;
485 }
486
_HAL_MVOP_IsSupport4k2k2P(void)487 MS_BOOL _HAL_MVOP_IsSupport4k2k2P(void)
488 {
489 return TRUE;
490 }
491
HAL_MVOP_RegSetBase(MS_VIRT u32Base)492 void HAL_MVOP_RegSetBase(MS_VIRT u32Base)
493 {
494 u32RiuBaseAdd = u32Base;
495 }
496
HAL_MVOP_InitMirrorMode(MS_BOOL bMir)497 void HAL_MVOP_InitMirrorMode(MS_BOOL bMir)
498 {
499 //set bit[3:7] to support mirror mode
500 HAL_WriteRegBit(VOP_MIRROR_CFG, bMir, VOP_MIRROR_CFG_ENABLE);
501 }
502
HAL_MVOP_SetVerticalMirrorMode(MS_BOOL bEnable)503 void HAL_MVOP_SetVerticalMirrorMode(MS_BOOL bEnable)
504 {
505 if (g_pHalMVOPCtx == NULL)
506 {
507 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
508 return;
509 }
510
511 if (VOP_MIRROR_CFG_ENABLE != HAL_ReadRegBit(VOP_MIRROR_CFG, VOP_MIRROR_CFG_ENABLE))
512 {
513 //MVOP_PRINTF("Setup mirror mode\n");
514 HAL_MVOP_InitMirrorMode(TRUE);
515 }
516
517 HAL_WriteRegBit(VOP_MIRROR_CFG, bEnable, VOP_MIRROR_CFG_VEN);
518 g_pHalMVOPCtx->bMirrorModeVer = bEnable;
519 if(g_pHalMVOPCtx->bIs265DV)
520 {
521 #if MVOP_SUPPORT_SUB
522 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bEnable, VOP_MIRROR_CFG_VEN);
523 g_pHalMVOPCtx->bSubMirrorModeVer = bEnable;
524 #endif
525 }
526 }
527
HAL_MVOP_SetHorizontallMirrorMode(MS_BOOL bEnable)528 void HAL_MVOP_SetHorizontallMirrorMode(MS_BOOL bEnable)
529 {
530 if (g_pHalMVOPCtx == NULL)
531 {
532 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
533 return;
534 }
535
536 if (VOP_MIRROR_CFG_ENABLE != HAL_ReadRegBit(VOP_MIRROR_CFG, VOP_MIRROR_CFG_ENABLE))
537 {
538 //MVOP_PRINTF("Setup mirror mode\n");
539 HAL_MVOP_InitMirrorMode(TRUE);
540 }
541
542 HAL_WriteRegBit(VOP_MIRROR_CFG, bEnable, VOP_MIRROR_CFG_HEN);
543 g_pHalMVOPCtx->bMirrorModeHor = bEnable;
544 if(g_pHalMVOPCtx->bIs265DV)
545 {
546 #if MVOP_SUPPORT_SUB
547 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bEnable, VOP_MIRROR_CFG_HEN);
548 g_pHalMVOPCtx->bSubMirrorModeHor = bEnable;
549 #endif
550 }
551 }
552
HAL_MVOP_Init(void)553 void HAL_MVOP_Init(void)
554 {
555 MVOP_HalInitCtxResults eRet;
556 MS_BOOL pbFirstDrvInstant;
557
558 eRet = _HAL_MVOP_InitContext(&pbFirstDrvInstant);
559 if(eRet == E_MVOP_INIT_FAIL)
560 {
561 MVOP_DBG(MVOP_PRINTF("[%s] MVOP Context Init failed!\n",__FUNCTION__);)
562 return;
563 }
564 else if(eRet == E_MVOP_INIT_ALREADY_EXIST)
565 {
566 if(g_pHalMVOPCtx->bIsInit)
567 {
568 MVOP_DBG(MVOP_PRINTF("[%s] Main MVOP Context has Initialized!\n",__FUNCTION__);)
569 return;
570 }
571 }
572
573 HAL_MVOP_InitMirrorMode(TRUE);
574 //Enable dynamic clock gating
575 //Note: cannot enable VOP_GCLK_VCLK_ON, or hsync cannot be sent out.
576 HAL_WriteByteMask(VOP_GCLK, VOP_GCLK_MIU_ON, VOP_GCLK_MIU_ON|VOP_GCLK_VCLK_ON);
577 g_pHalMVOPCtx->bIsInit = 1;
578 }
579
HAL_MVOP_SetFieldInverse(MS_BOOL b2MVD,MS_BOOL b2IP)580 void HAL_MVOP_SetFieldInverse(MS_BOOL b2MVD, MS_BOOL b2IP)
581 {
582 // Set fld inv & ofld_inv
583 HAL_WriteRegBit(VOP_CTRL0+1, b2MVD, BIT3); //inverse the field to MVD
584 HAL_WriteRegBit(VOP_CTRL0+1, b2IP, BIT4); //inverse the field to IP
585 }
586
HAL_MVOP_SetChromaWeighting(MS_BOOL bEnable)587 void HAL_MVOP_SetChromaWeighting(MS_BOOL bEnable)
588 {
589 HAL_WriteRegBit(VOP_REG_WEIGHT_CTRL, bEnable, BIT1);
590 }
591
592 //load new value into active registers 0x20-0x26
HAL_MVOP_LoadReg(void)593 void HAL_MVOP_LoadReg(void)
594 {
595 HAL_WriteRegBit(VOP_REG_WR, 1, BIT0);
596 HAL_WriteRegBit(VOP_REG_WR, 0, BIT0);
597
598 HAL_WriteRegBit(VOP_REG_WR, 1, BIT4);
599 HAL_WriteRegBit(VOP_REG_WR, 0, BIT4);
600 }
601
602
HAL_MVOP_SetMIUReqMask(MS_BOOL bEnable)603 void HAL_MVOP_SetMIUReqMask(MS_BOOL bEnable)
604 {
605 #if 0 //[FIXME]
606 if (bEnable)
607 { // mask MVOP2MI to protect MIU
608 HAL_MIU_SetReqMask(MVOP_R, 1);
609 MsOS_DelayTask(1);
610 }
611 else
612 { // unmask MVOP2MI
613 MsOS_DelayTask(1);
614 HAL_MIU_SetReqMask(MVOP_R, 0);
615 }
616 #endif
617 MS_U8 u8Miu;
618
619 if(HAL_MVOP_GetIsOnlyMiuIPControl() == TRUE)
620 {
621 // mask msb mvop
622 u8Miu = (HAL_ReadByte(VOP_MIU_SEL) & VOP_MSB_BUF0_MIU_SEL) >> 4;
623 }
624 else
625 {
626 u8Miu = VOP_ON_MIU1;
627 }
628 eMIUClientID eClientID = MIU_CLIENT_MVOP_128BIT_R;
629 //MVOP_PRINTF("Enter %s bEnable=%x ReqMask=0x%x, 0x%x\n", __FUNCTION__, bEnable,
630 // HAL_ReadByte(0x1266), HAL_ReadByte(0x0666));
631 if (bEnable)
632 { // mask MVOP2MI to protect MIU
633 MDrv_MIU_MaskReq(u8Miu,eClientID);
634 MsOS_DelayTask(1);
635 }
636 else
637 { // unmask MVOP2MI
638 MsOS_DelayTask(1);
639 MDrv_MIU_UnMaskReq(u8Miu,eClientID);
640 }
641
642 //MVOP_PRINTF(">Exit %s bEnable=%x ReqMask=0x%x, 0x%x\n", __FUNCTION__, bEnable,
643 // HAL_ReadByte(0x1266), HAL_ReadByte(0x0666));
644 }
645
HAL_MVOP_Rst(void)646 void HAL_MVOP_Rst(void)
647 {
648 #if 0
649 MS_BOOL bMCU = FALSE;
650
651 bMCU = HAL_ReadRegBit(VOP_MPG_JPG_SWITCH, BIT1);
652 #endif
653 HAL_WriteRegBit(VOP_CTRL0, 0, BIT0);
654 HAL_WriteRegBit(VOP_CTRL0, 1, BIT0);
655
656 g_pHalMVOPCtx->bIsEnable = 1;
657 #if 0
658 // sw patch: for mvop hsk mode, switching mvop enable/disable may cause video was stuck.
659 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] HAL_MVOP_Enable patch \n");)
660 HAL_MVOP_SetBlackBG();
661 HAL_MVOP_SetPattern(MVOP_PATTERN_FRAMECOLOR);
662 HAL_WriteRegBit(VOP_REG_WR, 1, BIT4);
663 HAL_WriteRegBit(VOP_MPG_JPG_SWITCH, 1, BIT1);
664 MsOS_DelayTask(40);
665 if(bMCU == FALSE)
666 {
667 HAL_WriteRegBit(VOP_MPG_JPG_SWITCH, 0, BIT1);
668 }
669 HAL_MVOP_SetPattern(MVOP_PATTERN_NORMAL);
670 HAL_WriteRegBit(VOP_REG_WR, 0, BIT4);
671 #endif
672 }
673
HAL_MVOP_Enable(MS_BOOL bEnable,MS_U8 u8Framerate)674 void HAL_MVOP_Enable(MS_BOOL bEnable, MS_U8 u8Framerate)
675 {
676 MS_U8 regval;
677 #if 0 //remove patch
678 MS_U8 u8FrmDur = 40;
679 MS_BOOL bMCU = FALSE;
680
681 bMCU = HAL_ReadRegBit(VOP_MPG_JPG_SWITCH, BIT1);
682
683 if(u8Framerate != 0)
684 {
685 u8FrmDur = 1000/u8Framerate; //time of one frame(ms).
686 }
687 #endif
688
689 regval = HAL_ReadByte(VOP_CTRL0);
690
691 if ( bEnable )
692 {
693 regval |= 0x1;
694 }
695 else
696 {
697 regval &= ~0x1;
698 HAL_Write2Byte(VOP_BF_VS_MVD, 0x200);
699 HAL_Write2Byte(VOP_TF_VS_MVD, 0x200);
700 }
701 #if 0
702 // sw patch: for mvop hsk mode, switching mvop enable/disable may cause video was stuck.
703 if( bEnable && (g_pHalMVOPCtx->bIsEnable == FALSE)) // need patch only from off to on
704 {
705 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] HAL_MVOP_Enable patch \n");)
706 HAL_MVOP_SetBlackBG();
707 HAL_MVOP_SetPattern(MVOP_PATTERN_FRAMECOLOR);
708 HAL_WriteRegBit(VOP_REG_WR, 1, BIT4);
709 HAL_WriteRegBit(VOP_MPG_JPG_SWITCH, 1, BIT1);
710 MsOS_DelayTask(u8FrmDur);
711 if(bMCU == FALSE)
712 {
713 HAL_WriteRegBit(VOP_MPG_JPG_SWITCH, 0, BIT1);
714 }
715 HAL_MVOP_SetPattern(MVOP_PATTERN_NORMAL);
716 HAL_WriteRegBit(VOP_REG_WR, 0, BIT4);
717 }
718 #endif
719 g_pHalMVOPCtx->bIsEnable = bEnable;
720
721 HAL_WriteByte(VOP_CTRL0, regval);
722 }
723
HAL_MVOP_GetEnableState(void)724 MS_BOOL HAL_MVOP_GetEnableState(void)
725 {
726 return (HAL_ReadRegBit(VOP_CTRL0, BIT0));
727 }
728
HAL_MVOP_GetMaxFreerunClk(void)729 HALMVOPFREQUENCY HAL_MVOP_GetMaxFreerunClk(void)
730 {
731 return HALMVOP_160MHZ;
732 }
733
HAL_MVOP_Get4k2kClk(void)734 HALMVOPFREQUENCY HAL_MVOP_Get4k2kClk(void)
735 {
736 return HALMVOP_320MHZ;
737 }
738
HAL_MVOP_SetFrequency(HALMVOPFREQUENCY enFrequency)739 void HAL_MVOP_SetFrequency(HALMVOPFREQUENCY enFrequency)
740 {
741 // clear
742 HAL_WriteByteMask(REG_CKG_DC0, 0, CKG_DC0_MASK);
743 switch(enFrequency)
744 {
745 case HALMVOP_SYNCMODE:
746 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK);
747 break;
748 case HALMVOP_FREERUNMODE:
749 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_FREERUN, CKG_DC0_MASK);
750 break;
751 case HALMVOP_160MHZ:
752 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK);
753 break;
754 case HALMVOP_144MHZ:
755 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_144MHZ, CKG_DC0_MASK);
756 break;
757 case HALMVOP_320MHZ:
758 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_320MHZ, CKG_DC0_MASK);
759 break;
760 default:
761 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK);
762 MVOP_PRINTF("Attention! In HAL_MVOP_SetFrequency default path!\n");
763 break;
764 }
765 }
766
HAL_MVOP_GetMaximumClk(void)767 HALMVOPFREQUENCY HAL_MVOP_GetMaximumClk(void)
768 {
769 return HALMVOP_320MHZ;
770 }
771
HAL_MVOP_GetCurrentClk(void)772 HALMVOPFREQUENCY HAL_MVOP_GetCurrentClk(void)
773 {
774 (MVOP_DBG("%s err: HAL_MVOP_GetCurrentClk=NULL\n", __FUNCTION__));
775 return 0;
776 }
777
HAL_MVOP_SetOutputInterlace(MS_BOOL bEnable,MS_U16 u16ECOVersion)778 void HAL_MVOP_SetOutputInterlace(MS_BOOL bEnable, MS_U16 u16ECOVersion)
779 {
780 UNUSED(u16ECOVersion);
781 MS_U8 regval;
782
783 regval = HAL_ReadByte(VOP_CTRL0);
784
785 if ( bEnable )
786 {
787 regval |= 0x80;
788 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
789 }
790 else
791 {
792 regval &= ~0x80;
793 }
794
795 HAL_WriteByte(VOP_CTRL0, regval);
796 }
797
HAL_MVOP_SetPattern(MVOP_Pattern enMVOPPattern)798 void HAL_MVOP_SetPattern(MVOP_Pattern enMVOPPattern)
799 {
800 HAL_WriteByteMask(VOP_TST_IMG, enMVOPPattern, BIT2 | BIT1 | BIT0);
801 }
802
HAL_MVOP_SetTileFormat(MVOP_TileFormat eTileFmt)803 MS_BOOL HAL_MVOP_SetTileFormat(MVOP_TileFormat eTileFmt)
804 {
805 if (eTileFmt == E_MVOP_TILE_8x32)
806 {
807 HAL_WriteRegBit(VOP_REG_WR, 0, BIT1);
808 return TRUE;
809 }
810 else if (eTileFmt == E_MVOP_TILE_16x32)
811 {
812 HAL_WriteRegBit(VOP_REG_WR, 1, BIT1);
813 return TRUE;
814 }
815 else if (eTileFmt == E_MVOP_TILE_32x16)
816 {
817 HAL_WriteRegBit(VOP_REG_WR, 0, BIT1);
818 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 1, EVD_ENABLE);
819 return TRUE;
820 }
821 else if (eTileFmt == E_MVOP_TILE_32x32)
822 {
823 HAL_WriteRegBit(VOP_REG_WR, 0, BIT1);
824 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, EVD_ENABLE);
825 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 1, VOP_TILE_32x32);
826 return TRUE;
827 }
828 else
829 {
830 return FALSE;
831 }
832 }
833
HAL_MVOP_GetSupportRgbFormat(MVOP_RgbFormat eRgbFmt)834 MS_BOOL HAL_MVOP_GetSupportRgbFormat(MVOP_RgbFormat eRgbFmt)
835 {
836 if ((eRgbFmt == E_MVOP_RGB_565) || (eRgbFmt == E_MVOP_RGB_888))
837 {
838 return TRUE;
839 }
840 return FALSE;
841 }
842
HAL_MVOP_SetRgbFormat(MVOP_RgbFormat eRgbFmt)843 MS_BOOL HAL_MVOP_SetRgbFormat(MVOP_RgbFormat eRgbFmt)
844 {
845 MS_BOOL bRet = FALSE;
846
847 if (g_pHalMVOPCtx == NULL)
848 {
849 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
850 return FALSE;
851 }
852
853 if (eRgbFmt == E_MVOP_RGB_NONE)
854 {
855 HAL_WriteByteMask(VOP_RGB_FMT, 0, VOP_RGB_FMT_SEL);
856 bRet = TRUE;
857 }
858 else if (eRgbFmt == E_MVOP_RGB_565)
859 {
860 HAL_WriteByteMask(VOP_RGB_FMT, VOP_RGB_FMT_565, VOP_RGB_FMT_SEL);
861 bRet = TRUE;
862 }
863 else if (eRgbFmt == E_MVOP_RGB_888)
864 {
865 HAL_WriteByteMask(VOP_RGB_FMT, VOP_RGB_FMT_888, VOP_RGB_FMT_SEL);
866 bRet = TRUE;
867 }
868
869 if (bRet == TRUE)
870 {
871 g_pHalMVOPCtx->eMainRgbFmt = eRgbFmt;
872 }
873 return bRet;
874 }
875
HAL_MVOP_SetBlackBG(void)876 void HAL_MVOP_SetBlackBG(void)
877 {
878 MS_U8 regval;
879
880 //set MVOP test pattern to black
881 HAL_WriteByte((VOP_TST_IMG + 1), 0x10);
882 HAL_WriteByte(VOP_U_PAT , 0x80);
883 HAL_WriteByte((VOP_U_PAT + 1), 0x80);
884
885 regval = HAL_ReadByte(VOP_TST_IMG);
886 HAL_WriteByte(VOP_TST_IMG, 0x02);
887 HAL_WriteByte(VOP_TST_IMG, 0x00);
888 HAL_WriteByte(VOP_TST_IMG, regval);
889 }
890
HAL_MVOP_SetCropWindow(MVOP_InputCfg * pparam)891 void HAL_MVOP_SetCropWindow(MVOP_InputCfg *pparam)
892 {
893 #if 1
894 UNUSED(pparam);
895 #else // enable it when test code is ready
896 MS_U32 x, y;
897 MS_U32 u32offset;
898
899 if(!pparam)
900 {
901 return;
902 }
903 //set MVOP test pattern to black
904 HAL_MVOP_SetBlackBG();
905 #if 0
906 if((pparam->enVideoType == MVOP_H264) && (pparam->u16StripSize == 1920))
907 {
908 pparam->u16StripSize = 1952;
909 }
910 #endif
911 if((pparam->enVideoType == MVOP_MPG) || (pparam->enVideoType == MVOP_MPEG4))
912 {
913 pparam->u16CropX = (pparam->u16CropX >> 3) << 3; // 8 bytes align
914 pparam->u16CropY = (pparam->u16CropY >> 6) << 6; // 64 bytes align
915 }
916 else if((pparam->enVideoType == MVOP_H264) || (pparam->enVideoType == MVOP_RM))
917 {
918 pparam->u16CropX = (pparam->u16CropX >> 4) << 4; // 16 bytes align
919 pparam->u16CropY = (pparam->u16CropY >> 6) << 6; // 64 bytes align
920 }
921 else
922 {
923 MS_ASSERT(0);
924 }
925
926 x = (MS_U32)pparam->u16CropX;
927 y = (MS_U32)pparam->u16CropY;
928
929 // y offset
930 u32offset = ((y * pparam->u16StripSize + (x << 5)) >> 3);
931 HAL_WriteByte((VOP_JPG_YSTR0_L ), (MS_U8)(u32offset));
932 HAL_WriteByte((VOP_JPG_YSTR0_L + 1), (MS_U8)(u32offset >> 8));
933 HAL_WriteByte((VOP_JPG_YSTR0_H ), (MS_U8)(u32offset >> 16));
934 HAL_WriteByte((VOP_JPG_YSTR0_H + 1), (MS_U8)((u32offset >> 24) & VOP_YUV_STR_HIBITS));
935
936 // uv offset
937 u32offset = ((y >> 1) * pparam->u16StripSize + (x << 5)) >> 3;
938 HAL_WriteByte((VOP_JPG_UVSTR0_L ), (MS_U8)(u32offset));
939 HAL_WriteByte((VOP_JPG_UVSTR0_L + 1), (MS_U8)(u32offset >> 8));
940 HAL_WriteByte((VOP_JPG_UVSTR0_H ), (MS_U8)(u32offset >> 16));
941 HAL_WriteByte((VOP_JPG_UVSTR0_H + 1), (MS_U8)((u32offset >> 24) & VOP_YUV_STR_HIBITS));
942
943 pparam->u16CropWidth= (pparam->u16CropWidth >> 3) << 3;
944 // HSize, VSize
945 HAL_WriteByte((VOP_JPG_HSIZE ), LOWBYTE(pparam->u16CropWidth ));
946 HAL_WriteByte((VOP_JPG_HSIZE + 1), HIGHBYTE(pparam->u16CropWidth ));
947 HAL_WriteByte((VOP_JPG_VSIZE ), LOWBYTE(pparam->u16CropHeight));
948 HAL_WriteByte((VOP_JPG_VSIZE + 1), HIGHBYTE(pparam->u16CropHeight ));
949
950 HAL_WriteByteMask(VOP_MPG_JPG_SWITCH, BIT0, BIT1|BIT0);
951
952 // clear extend strip len bit by default
953 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
954 if((pparam->enVideoType == MVOP_MPG) || (pparam->enVideoType == MVOP_MPEG4))
955 {
956 // Disable H264 or RM Input
957 HAL_WriteRegBit(VOP_INPUT_SWITCH1, 0, BIT2|BIT3);
958 //8*32 tile format
959 HAL_WriteRegBit(VOP_REG_WR, 0, BIT1);
960 }
961 else if((pparam->enVideoType == MVOP_H264) || (pparam->enVideoType == MVOP_RM))
962 {
963 //16*32 tile format
964 HAL_WriteRegBit(VOP_REG_WR, 1, BIT1);
965 // SVD mode enable
966 HAL_WriteByteMask(VOP_INPUT_SWITCH1, BIT3, BIT2|BIT3);
967 // set mvop to 64bit interface
968 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
969 }
970 HAL_MVOP_LoadReg();
971 #endif
972 }
973
HAL_MVOP_SetRepeatField(MVOP_RptFldMode eMode)974 void HAL_MVOP_SetRepeatField(MVOP_RptFldMode eMode)
975 {
976 if (g_pHalMVOPCtx == NULL)
977 {
978 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
979 return;
980 }
981 g_pHalMVOPCtx->eRepeatField = eMode;
982 }
983
HAL_MVOP_SetInputMode(VOPINPUTMODE mode,MVOP_InputCfg * pparam,MS_U16 u16ECOVersion)984 void HAL_MVOP_SetInputMode( VOPINPUTMODE mode, MVOP_InputCfg *pparam, MS_U16 u16ECOVersion )
985 {
986 MS_U8 regval;
987 MS_U16 u16strip, u16strip_lsb;
988
989 if (g_pHalMVOPCtx == NULL)
990 {
991 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
992 return;
993 }
994 #if 0
995 /*****************************************************/
996 // Reset MVOP setting
997 HAL_WriteByte(VOP_TST_IMG, 0x40); //reset test pattern or BG
998 HAL_MVOP_Set3DLRAltOutput_VHalfScaling(DISABLE); //reset to default: disable 3D L/R alternative output.
999 HAL_MVOP_Set3DLR2ndCfg(DISABLE); //reset to default: disable 3D L/R 2nd pitch.
1000 HAL_MVOP_SetRgbFormat(E_MVOP_RGB_NONE); //reset rgb format
1001 HAL_WriteRegBit(VOP_CTRL1, 0, VOP_MVD_VS_MD); //default use original vsync
1002 // Only for Monaco: Enable deciding bot by top address + 2
1003 HAL_WriteRegBit(VOP_MIRROR_CFG, 1, VOP_FIELD_FROM_ADDR);
1004
1005 //set MVOP test pattern to black
1006 HAL_MVOP_SetBlackBG();
1007
1008 // clear extend strip len bit by default
1009 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
1010
1011 // set mvop to 128bit_i128 interface
1012 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
1013
1014 // Disable H264 or RM Input
1015 HAL_WriteRegBit(VOP_INPUT_SWITCH1, 0, BIT2|BIT3);
1016 // Clear 422 Flag
1017 g_pHalMVOPCtx->bIs422 = 0;
1018 // Clear evd Flag for interlace mode setting
1019 g_pHalMVOPCtx->bIsH265 = 0;
1020 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_L, 1, BIT3);
1021 HAL_WriteRegBit(VOP_MIRROR_CFG, 1, BIT5);
1022 //8*32 tile format
1023 HAL_WriteRegBit(VOP_REG_WR, 0, BIT1);
1024 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD);
1025 HAL_MVOP_SetFieldInverse(ENABLE, ENABLE);
1026 // EVD mode disable
1027 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, EVD_ENABLE);
1028 // EVD 10 bits disable
1029 HAL_WriteByteMask(VOP_REG_MASK, BIT1, VOP_LSB_REQ_MASK);
1030 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_Y_EN);
1031 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_UV_EN);
1032 HAL_WriteRegBit(VOP_UV_SHIFT, 1, VOP_GCLK_MIU_ON);
1033 // Disable 420 BW Saving mode
1034 HAL_WriteRegBit(VOP_REG_DUMMY, 0, VOP_420_BW_SAVE);
1035 // Disable New Vsync Mode
1036 g_pHalMVOPCtx->bNewVSyncMode = FALSE;
1037 // VP9 MODE disable
1038 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, VOP_R2_WISHBONE);
1039 HAL_WriteRegBit(VOP_MPG_JPG_SWITCH, 0, VOP_DRAM_RD_MODE);
1040 // Disable 2p mode
1041 HAL_MVOP_SetEnable4k2k2P(FALSE);
1042 /*****************************************************/
1043 #endif
1044 regval = 0;
1045 regval |= ( mode & 0x3 );
1046
1047 if ( mode == VOPINPUT_HARDWIRE )
1048 {
1049 HAL_WriteByte(VOP_MPG_JPG_SWITCH, regval);
1050 }
1051 else if ( mode == VOPINPUT_HARDWIRECLIP )
1052 {
1053 HAL_WriteByte(VOP_MPG_JPG_SWITCH, regval);
1054
1055 // HSize, VSize
1056 HAL_WriteByte(VOP_JPG_HSIZE , LOWBYTE( pparam->u16HSize ));
1057 HAL_WriteByte((VOP_JPG_HSIZE + 1), HIGHBYTE( pparam->u16HSize ));
1058 HAL_WriteByte(VOP_JPG_VSIZE , LOWBYTE( pparam->u16VSize ));
1059 HAL_WriteByte((VOP_JPG_VSIZE + 1), HIGHBYTE( pparam->u16VSize ));
1060 }
1061 else if (mode == VOPINPUT_MCUCTRL)
1062 {
1063 // disable from wb
1064 HAL_WriteRegBit(VOP_REG_MFDEC_2_L, 0, VOP_MF_FROM_WB);
1065 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, VOP_R2_WISHBONE);
1066 g_pHalMVOPCtx->bMirrorMode = (g_pHalMVOPCtx->bMirrorModeVer||g_pHalMVOPCtx->bMirrorModeHor);
1067 if ( pparam->bProgressive )
1068 regval |= 0x4;
1069 else
1070 {
1071 regval &= ~0x4;
1072 regval |= 0x1; //reg_dc_md=b'11 for interlace input
1073 if (E_MVOP_RPTFLD_NONE == g_pHalMVOPCtx->eRepeatField)
1074 {
1075 MVOP_DBG("%s normal NOT repeat field %x\n", __FUNCTION__, g_pHalMVOPCtx->eRepeatField);
1076 //To support mcu mode interlace, need to set h'3B[9]=1,
1077 //h'11[12]=0, and Y1/UV1 address equal to Y0/UV0 address.
1078 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_REF_SELF_FLD);
1079 HAL_MVOP_SetFieldInverse(ENABLE, DISABLE);
1080 }
1081 }
1082
1083 if ( pparam->bYUV422 )
1084 regval |= 0x10;
1085 else
1086 regval &= ~0x10;
1087
1088 if ( pparam->b422pack )
1089 regval |= 0x80;
1090
1091 if ( pparam->bDramRdContd == 1 )
1092 regval |= 0x20;
1093 else
1094 regval &= ~0x20;
1095
1096 // for backward compatable to saturn
1097 // [3] UV-7bit mode don't care
1098 // [5] dram_rd_md =0
1099 // [6] Fld don't care
1100 // [7] 422pack don'care
1101 HAL_WriteByte(VOP_MPG_JPG_SWITCH, regval);
1102 g_pHalMVOPCtx->bIs422 = pparam->bYUV422;
1103 HAL_WriteRegBit(VOP_REG_DUMMY, !(pparam->bYUV422), VOP_420_BW_SAVE);
1104 HAL_WriteRegBit(VOP_REG_BW_SAVE, !(pparam->bYUV422), VOP_420_BW_SAVE_EX);
1105
1106 if (pparam->u16StripSize == 0)
1107 {
1108 if (pparam->bSD)
1109 {
1110 u16strip = 720;
1111 u16strip_lsb = 720;
1112 }
1113 else
1114 {
1115 u16strip = 1920;
1116 u16strip_lsb = 1920;
1117 }
1118 }
1119 else
1120 {
1121 u16strip = pparam->u16StripSize;
1122 u16strip_lsb = pparam->u16StripSize;
1123 }
1124
1125 // set dc_strip[7:0]
1126 if ( pparam->bDramRdContd == 0 )
1127 {
1128 u16strip = (u16strip + 31) / 32 * 32; //need align for monaco
1129 u16strip = u16strip/8;
1130 u16strip_lsb = (u16strip_lsb+127)/128;
1131 u16strip_lsb *= 4;
1132 }
1133 else
1134 {
1135 if ( pparam->b422pack )
1136 {
1137 if (E_MVOP_RGB_888 == g_pHalMVOPCtx->eMainRgbFmt)
1138 {
1139 u16strip *= 2; //4bytes/pixel (yuv422:2bytes/pixel)
1140 }
1141 //VOP_REG_STRIP_ALIGN and Mirror mode are mutually exclusive, after M10(support mirror), VOP_DC_STRIP_H
1142 //replace VOP_REG_STRIP_ALIGN, which supported maximun Hsize is 8188
1143 #if 0
1144 // [071016 Andy] support YUV422 pack mode
1145 if ((u16strip < 1024) || g_pHalMVOPCtx->bMirrorMode)
1146 {
1147 u16strip = u16strip/4;
1148 // dont extend strip len
1149 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
1150 }
1151 else
1152 {
1153 u16strip = u16strip/8;
1154 // extend strip len to 2048
1155 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 1, BIT0);
1156 }
1157 #endif
1158 u16strip = u16strip/4;
1159 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
1160 }
1161 else
1162 {
1163 u16strip = u16strip/8;
1164 }
1165 }
1166
1167 if (u16strip >= 256 )
1168 {
1169 HAL_WriteByte(VOP_DC_STRIP_H, (u16strip>>8));
1170 //reg_dc_strip_h[2:0] = reg_dc_strip[10:8]
1171 }
1172 else
1173 {
1174 HAL_WriteByteMask(VOP_DC_STRIP_H, 0, BIT0 | BIT1 | BIT2);
1175 }
1176
1177 regval = u16strip;
1178 HAL_WriteByte(VOP_DC_STRIP, regval);
1179 //LSB strip
1180 HAL_WriteByte(VOP_DC_STRIP_LSB, u16strip_lsb & 0x3ff);
1181
1182
1183 HAL_MVOP_SetYUVBaseAdd(pparam->u32YOffset, pparam->u32UVOffset,
1184 pparam->bProgressive, pparam->b422pack);
1185
1186 if (E_MVOP_RPTFLD_NONE != g_pHalMVOPCtx->eRepeatField)
1187 {
1188 MVOP_DBG("%s reset eRepeatField=%x ==>", __FUNCTION__, g_pHalMVOPCtx->eRepeatField);
1189 //To output the same field for single field input,
1190 //do NOT set h'3B[9]=1 and h'11[12]=0
1191 g_pHalMVOPCtx->eRepeatField = E_MVOP_RPTFLD_NONE; //reset the flag to repeat field
1192 MVOP_DBG(" %x\n", g_pHalMVOPCtx->eRepeatField);
1193 }
1194
1195 // HSize
1196 MS_U16 u16HSize = ALIGN_UPTO_16(pparam->u16HSize);
1197 if (u16HSize != pparam->u16HSize)
1198 {
1199 MVOP_DBG(MVOP_PRINTF("\n\n Change HSize %d to %d\n", pparam->u16HSize, u16HSize);)
1200 }
1201 HAL_WriteByte(VOP_JPG_HSIZE , LOWBYTE( u16HSize ));
1202 HAL_WriteByte((VOP_JPG_HSIZE + 1), HIGHBYTE( u16HSize ));
1203
1204 // VSize
1205 MS_U16 u16VSize = pparam->u16VSize;
1206 if (g_pHalMVOPCtx->bMirrorModeVer)
1207 {
1208 u16VSize = ALIGN_UPTO_4(pparam->u16VSize);
1209 MVOP_DBG(MVOP_PRINTF("\n\n Change VSize %d to %d\n", pparam->u16VSize, u16VSize);)
1210 }
1211 HAL_WriteByte(VOP_JPG_VSIZE , LOWBYTE( u16VSize ));
1212 HAL_WriteByte((VOP_JPG_VSIZE + 1), HIGHBYTE( u16VSize ));
1213 }
1214
1215 HAL_MVOP_LoadReg();
1216 }
1217
1218
HAL_MVOP_EnableUVShift(MS_BOOL bEnable)1219 void HAL_MVOP_EnableUVShift(MS_BOOL bEnable)
1220 {
1221 MS_U8 regval;
1222
1223 regval = HAL_ReadByte(VOP_MPG_JPG_SWITCH);
1224
1225 if (((regval & BIT4) == BIT4) && ((regval & 0x3)== 0x2))
1226 { // 422 with MCU control mode
1227 if (bEnable)
1228 {
1229 MS_ASSERT(0);
1230 }
1231 }
1232
1233 // output 420 and interlace
1234 //[IP - Sheet] : Main Page --- 420CUP
1235 //[Project] : Titania2
1236 //[Description]: Chroma artifacts when 420to422 is applied duplicate method.
1237 //[Root cause]: Apply 420to422 average algorithm to all DTV input cases.
1238 //The average algorithm must cooperate with MVOP.
1239 HAL_WriteByteMask(VOP_UV_SHIFT, (bEnable)?1:0, 0x3);
1240 }
1241
1242 static MS_BOOL _bEnable60P = false;
HAL_MVOP_SetEnable60P(MS_BOOL bEnable)1243 void HAL_MVOP_SetEnable60P(MS_BOOL bEnable)
1244 {
1245 _bEnable60P = bEnable;
1246 }
1247
1248 static MS_BOOL _bEnable4k2kClk = false;
HAL_MVOP_SetEnable4k2kClk(MS_BOOL bEnable)1249 void HAL_MVOP_SetEnable4k2kClk(MS_BOOL bEnable)
1250 {
1251 _bEnable4k2kClk = bEnable;
1252 }
1253
HAL_MVOP_SetEnable4k2k2P(MS_BOOL bEnable)1254 void HAL_MVOP_SetEnable4k2k2P(MS_BOOL bEnable)
1255 {
1256 g_pHalMVOPCtx->bIs2p = bEnable;
1257 HAL_WriteRegBit(VOP_REG_4K2K_2P, bEnable, VOP_4K2K_2P);
1258
1259 }
1260
HAL_MVOP_EnableFreerunMode(MS_BOOL bEnable)1261 void HAL_MVOP_EnableFreerunMode(MS_BOOL bEnable)
1262 {
1263 if (g_pHalMVOPCtx == NULL)
1264 {
1265 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1266 return;
1267 }
1268 g_pHalMVOPCtx->bEnableFreerunMode = bEnable;
1269 }
1270
HAL_MVOP_SetVSyncMode(MS_U8 u8Mode)1271 void HAL_MVOP_SetVSyncMode(MS_U8 u8Mode)
1272 {
1273 if (g_pHalMVOPCtx == NULL)
1274 {
1275 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1276 return;
1277 }
1278 if (1==u8Mode)
1279 {
1280 g_pHalMVOPCtx->bNewVSyncMode = TRUE;
1281 }
1282 else
1283 {
1284 g_pHalMVOPCtx->bNewVSyncMode = FALSE;
1285 }
1286 }
1287
HAL_MVOP_SetOutputTiming(MVOP_Timing * ptiming)1288 void HAL_MVOP_SetOutputTiming( MVOP_Timing *ptiming )
1289 {
1290 MS_U8 regval;
1291
1292 if (g_pHalMVOPCtx == NULL)
1293 {
1294 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1295 return;
1296 }
1297
1298 HAL_WriteByte(VOP_FRAME_VCOUNT , LOWBYTE( ptiming->u16V_TotalCount ));
1299 HAL_WriteByte((VOP_FRAME_VCOUNT + 1), HIGHBYTE( ptiming->u16V_TotalCount ));
1300 HAL_WriteByte(VOP_FRAME_HCOUNT , LOWBYTE( ptiming->u16H_TotalCount ));
1301 HAL_WriteByte((VOP_FRAME_HCOUNT + 1), HIGHBYTE( ptiming->u16H_TotalCount ));
1302
1303 HAL_WriteByte((VOP_VB0_STR ), LOWBYTE( ptiming->u16VBlank0_Start ));
1304 HAL_WriteByte((VOP_VB0_STR + 1), HIGHBYTE( ptiming->u16VBlank0_Start ));
1305 HAL_WriteByte((VOP_VB0_END ), LOWBYTE( ptiming->u16VBlank0_End ));
1306 HAL_WriteByte((VOP_VB0_END + 1), HIGHBYTE( ptiming->u16VBlank0_End ));
1307 HAL_WriteByte((VOP_VB1_STR ), LOWBYTE( ptiming->u16VBlank1_Start ));
1308 HAL_WriteByte((VOP_VB1_STR + 1), HIGHBYTE( ptiming->u16VBlank1_Start ));
1309 HAL_WriteByte((VOP_VB1_END ), LOWBYTE( ptiming->u16VBlank1_End ));
1310 HAL_WriteByte((VOP_VB1_END + 1), HIGHBYTE( ptiming->u16VBlank1_End ));
1311 HAL_WriteByte((VOP_TF_STR ), LOWBYTE( ptiming->u16TopField_Start ));
1312 HAL_WriteByte((VOP_TF_STR + 1), HIGHBYTE( ptiming->u16TopField_Start ));
1313 HAL_WriteByte((VOP_BF_STR ), LOWBYTE( ptiming->u16BottomField_Start ));
1314 HAL_WriteByte((VOP_BF_STR + 1), HIGHBYTE( ptiming->u16BottomField_Start ));
1315 HAL_WriteByte((VOP_HACT_STR ), LOWBYTE( ptiming->u16HActive_Start ));
1316 HAL_WriteByte((VOP_HACT_STR + 1), HIGHBYTE( ptiming->u16HActive_Start ));
1317
1318 HAL_WriteByte((VOP_TF_VS ), LOWBYTE( ptiming->u16TopField_VS ));
1319 HAL_WriteByte((VOP_TF_VS + 1), HIGHBYTE( ptiming->u16TopField_VS ));
1320 HAL_WriteByte((VOP_BF_VS ), LOWBYTE( ptiming->u16BottomField_VS ));
1321 HAL_WriteByte((VOP_BF_VS + 1), HIGHBYTE( ptiming->u16BottomField_VS ));
1322
1323 if(((((ptiming->u16V_TotalCount >= 2160) && (ptiming->u16H_TotalCount >= 3840)) || ((ptiming->u16V_TotalCount >= 2160) && (ptiming->u16H_TotalCount >= 1920) && g_pHalMVOPCtx->bIs2p))
1324 && (ptiming->u8Framerate > 15)) || g_pHalMVOPCtx->bIs265DV)
1325 {
1326 g_pHalMVOPCtx->bNewVSyncMode = TRUE;
1327 if(g_pHalMVOPCtx->bIs265DV)
1328 {
1329 if(ptiming->u8Framerate > 30) //for 4k60
1330 {
1331 g_pHalMVOPCtx->u16VsyncLines = 0x10D; //0x9d->0x10d for 120Hz trick mode.
1332 }
1333 else
1334 {
1335 g_pHalMVOPCtx->u16VsyncLines = 0x60;//mantis 1205202
1336 }
1337 HAL_WriteByte(VOP_DMA0, 0x18);
1338 HAL_WriteByteMask(VOP_DMA1, 0x01, VOP_BURST_EXT);
1339 }
1340 else
1341 {
1342 if(ptiming->u8Framerate > 30) //for 4k60
1343 {
1344 g_pHalMVOPCtx->u16VsyncLines = 0;
1345 HAL_WriteByte(VOP_DMA0, 0x08);
1346 HAL_WriteByteMask(VOP_DMA1, 0x02, VOP_BURST_EXT);
1347 }
1348 else
1349 {
1350 g_pHalMVOPCtx->u16VsyncLines = 0;
1351 HAL_WriteByte(VOP_DMA0, 0x08);
1352 HAL_WriteByteMask(VOP_DMA1, 0x02, VOP_BURST_EXT);
1353 g_pHalMVOPCtx->bNewVSyncMode = 0;
1354 HAL_WriteRegBit(VOP_CTRL1, 1, VOP_MVD_VS_SEL); //4k 30 only 4 lines forwarding: mantis 1185981
1355 }
1356 }
1357
1358 }
1359 // patch for manhattan + FRC
1360 else if(((ptiming->u16V_TotalCount >= 1080) && (ptiming->u16H_TotalCount >= 1440)) && (ptiming->u8Framerate >= 24) && (ptiming->bInterlace == 1))
1361 {
1362 if(g_pHalMVOPCtx->bMirrorModeVer)
1363 {
1364 g_pHalMVOPCtx->bNewVSyncMode = FALSE;
1365 HAL_WriteRegBit(VOP_CTRL1, 1, VOP_MVD_VS_SEL); // 4 lins forwarding; Mantis ID:1074519
1366 }
1367 else
1368 {
1369 g_pHalMVOPCtx->bNewVSyncMode = TRUE;
1370 HAL_MVOP_SetFieldInverse(DISABLE, ENABLE);
1371 g_pHalMVOPCtx->u16VsyncLines = 0x40;
1372 HAL_WriteByte(VOP_DMA0, 0x18);
1373 HAL_WriteByteMask(VOP_DMA1, 0x01, VOP_BURST_EXT);
1374 }
1375 }
1376 else
1377 {
1378 g_pHalMVOPCtx->u16VsyncLines = 0;
1379 HAL_WriteByte(VOP_DMA0, 0x08);
1380 HAL_WriteByteMask(VOP_DMA1, 0x02, VOP_BURST_EXT);
1381 }
1382
1383 if(g_pHalMVOPCtx->bNewVSyncMode)
1384 {
1385 #define NEW_VSYNC_MODE_ADVANCE_LINECNT 30
1386 MS_U16 u16BottomField_VS2MVD;
1387 MS_U16 u16TopField_VS2MVD;
1388 MVOP_DBG(MVOP_PRINTF("MVOP use new vync mode, forwarding %d lines\n",NEW_VSYNC_MODE_ADVANCE_LINECNT);)
1389
1390 if(g_pHalMVOPCtx->u16VsyncLines == 0)
1391 u16BottomField_VS2MVD = ptiming->u16BottomField_VS - NEW_VSYNC_MODE_ADVANCE_LINECNT;
1392 else
1393 u16BottomField_VS2MVD = ptiming->u16BottomField_VS - g_pHalMVOPCtx->u16VsyncLines;
1394
1395 MVOP_DBG(MVOP_PRINTF("BottomField VS ori=0x%x, new=0x%x\n", ptiming->u16BottomField_VS, u16BottomField_VS2MVD);)
1396 HAL_WriteByte((VOP_BF_VS_MVD ), LOWBYTE( u16BottomField_VS2MVD ));
1397 HAL_WriteByte((VOP_BF_VS_MVD + 1), HIGHBYTE( u16BottomField_VS2MVD ));
1398
1399 if(g_pHalMVOPCtx->u16VsyncLines == 0)
1400 u16TopField_VS2MVD = ptiming->u16V_TotalCount - NEW_VSYNC_MODE_ADVANCE_LINECNT;
1401 else
1402 u16TopField_VS2MVD = ptiming->u16V_TotalCount - g_pHalMVOPCtx->u16VsyncLines;
1403
1404 MVOP_DBG(MVOP_PRINTF("TopField VS Vtt=0x%x, new=0x%x\n", ptiming->u16V_TotalCount, u16TopField_VS2MVD);)
1405 HAL_WriteByte((VOP_TF_VS_MVD ), LOWBYTE( u16TopField_VS2MVD ));
1406 HAL_WriteByte((VOP_TF_VS_MVD + 1), HIGHBYTE( u16TopField_VS2MVD ));
1407
1408 HAL_WriteRegBit(VOP_GCLK, 0, VOP_GCLK_MIU_ON);
1409
1410 HAL_WriteRegBit(VOP_CTRL1, 1, VOP_MVD_VS_MD); //Use new vsync
1411
1412 g_pHalMVOPCtx->bNewVSyncMode = FALSE; //restore to original mode
1413 }
1414 else
1415 {
1416 MS_U16 u16BottomField_VS2MVD = 0x200;
1417 HAL_WriteByte((VOP_BF_VS_MVD ), LOWBYTE( u16BottomField_VS2MVD ));
1418 HAL_WriteByte((VOP_BF_VS_MVD + 1), HIGHBYTE( u16BottomField_VS2MVD ));
1419
1420 MS_U16 u16TopField_VS2MVD = 0x200;
1421 HAL_WriteByte((VOP_TF_VS_MVD ), LOWBYTE( u16TopField_VS2MVD ));
1422 HAL_WriteByte((VOP_TF_VS_MVD + 1), HIGHBYTE( u16TopField_VS2MVD ));
1423 HAL_WriteRegBit(VOP_CTRL1, 0, VOP_MVD_VS_MD);
1424 }
1425
1426 // + S3, set default IMG_HSTR, IMG_VSTR0, IMG_VSTR1
1427 #ifdef _SUPPORT_IMG_OFFSET_
1428 HAL_WriteByte((VOP_IMG_HSTR ), LOWBYTE( ptiming->u16HImg_Start));
1429 HAL_WriteByte((VOP_IMG_HSTR + 1), HIGHBYTE( ptiming->u16HImg_Start ));
1430 HAL_WriteByte((VOP_IMG_VSTR0 ), LOWBYTE( ptiming->u16VImg_Start0));
1431 HAL_WriteByte((VOP_IMG_VSTR0+ 1), HIGHBYTE( ptiming->u16VImg_Start0 ));
1432 HAL_WriteByte((VOP_IMG_VSTR1 ), LOWBYTE( ptiming->u16VImg_Start1 ));
1433 HAL_WriteByte((VOP_IMG_VSTR1+ 1), HIGHBYTE( ptiming->u16VImg_Start1 ));
1434 #else
1435 HAL_WriteByte((VOP_IMG_HSTR ), LOWBYTE( ptiming->u16HActive_Start ));
1436 HAL_WriteByte((VOP_IMG_HSTR + 1), HIGHBYTE( ptiming->u16HActive_Start ));
1437 HAL_WriteByte((VOP_IMG_VSTR0 ), LOWBYTE( ptiming->u16VBlank0_End ));
1438 HAL_WriteByte((VOP_IMG_VSTR0+ 1), HIGHBYTE( ptiming->u16VBlank0_End ));
1439 HAL_WriteByte((VOP_IMG_VSTR1 ), LOWBYTE( ptiming->u16VBlank1_End ));
1440 HAL_WriteByte((VOP_IMG_VSTR1+ 1), HIGHBYTE( ptiming->u16VBlank1_End ));
1441 #endif
1442 // select mvop output from frame color(black)
1443 HAL_WriteByte((VOP_TST_IMG + 1), 0x10);
1444 HAL_WriteByte((VOP_U_PAT ), 0x80);
1445 HAL_WriteByte((VOP_U_PAT + 1), 0x80);
1446 // set mvop src to test pattern
1447 regval = HAL_ReadByte(VOP_TST_IMG);
1448 HAL_WriteByte(VOP_TST_IMG, 0x02);
1449 // make changed registers take effect
1450 HAL_MVOP_LoadReg();
1451
1452 HAL_MVOP_SetMIUReqMask(TRUE);
1453 // reset mvop to avoid timing change cause mvop hang-up
1454 HAL_MVOP_Rst();
1455 HAL_MVOP_SetMIUReqMask(FALSE);
1456
1457 // select mvop output from mvd
1458 HAL_WriteByte(VOP_TST_IMG, 0x00);
1459 HAL_WriteByte(VOP_TST_IMG, regval);
1460 HAL_WriteRegBit(VOP_CTRL0, ptiming->bHDuplicate, BIT2);// H pixel duplicate
1461
1462 #if 0
1463 MVOP_DBG(MVOP_PRINTF("\nMVOP SetOutputTiming\n");)
1464 MVOP_DBG(MVOP_PRINTF(" VTot=%u,\t",ptiming->u16V_TotalCount);)
1465 MVOP_DBG(MVOP_PRINTF(" HTot=%u,\t",ptiming->u16H_TotalCount);)
1466 MVOP_DBG(MVOP_PRINTF(" I/P=%u\n",ptiming->bInterlace);)
1467 MVOP_DBG(MVOP_PRINTF(" W=%u,\t",ptiming->u16Width);)
1468 MVOP_DBG(MVOP_PRINTF(" H=%u,\t",ptiming->u16Height);)
1469 MVOP_DBG(MVOP_PRINTF(" FRate=%u,\t",ptiming->u8Framerate);)
1470 MVOP_DBG(MVOP_PRINTF(" HFreq=%u\n",ptiming->u16H_Freq);)
1471 MVOP_DBG(MVOP_PRINTF(" Num=0x%x,\t",ptiming->u16Num);)
1472 MVOP_DBG(MVOP_PRINTF(" Den=0x%x,\t",ptiming->u16Den);)
1473 MVOP_DBG(MVOP_PRINTF(" u16ExpFRate=%u #\n\n", ptiming->u16ExpFrameRate);)
1474 #endif
1475 }
1476
HAL_MVOP_SetDCClk(MS_U8 clkNum,MS_BOOL bEnable)1477 void HAL_MVOP_SetDCClk(MS_U8 clkNum, MS_BOOL bEnable)
1478 {
1479 MS_ASSERT( (clkNum==0) || (clkNum==1) );
1480 if (clkNum==0)
1481 {
1482 HAL_WriteRegBit(REG_CKG_DC0, !bEnable, CKG_DC0_GATED);
1483 }
1484 }
1485
HAL_MVOP_SetDCSRAMClk(MS_U8 clkNum,MS_BOOL bEnable)1486 void HAL_MVOP_SetDCSRAMClk(MS_U8 clkNum, MS_BOOL bEnable)
1487 {
1488 MS_ASSERT( (clkNum==0) || (clkNum==1) );
1489 if (clkNum==0)
1490 {
1491 HAL_WriteRegBit(REG_CKG_DC_SRAM, !bEnable, CKG_DC0_SRAM);
1492 }
1493 }
1494
1495
HAL_MVOP_SetSynClk(MVOP_Timing * ptiming)1496 void HAL_MVOP_SetSynClk(MVOP_Timing *ptiming)
1497 {
1498 if (g_pHalMVOPCtx == NULL)
1499 {
1500 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1501 return;
1502 }
1503 if(g_pHalMVOPCtx->bEnableFreerunMode)
1504 {
1505 MS_U64 u64mpll_clock = MPLL_CLOCK_216 << 27 ; //mvop hw bug, tsp default use 216MHz mpll clock @ maserati
1506 if(HAL_ReadRegBit(REG_CLK_SYN_STC, BIT0) == BIT0) //check stc1 clock use 432 or 216
1507 {
1508 u64mpll_clock = MPLL_CLOCK_432 << 27 ;
1509 }
1510 MS_U64 u64exp_clock = (((MS_U64)ptiming->u16H_TotalCount * (MS_U64)ptiming->u16V_TotalCount * (MS_U64)ptiming->u16ExpFrameRate)/1000);
1511 do_div(u64mpll_clock, u64exp_clock);
1512 MS_U32 u32FreerunClk = (MS_U32)u64mpll_clock;
1513 HAL_MVOP_SetFrequency(HALMVOP_FREERUNMODE);
1514 HAL_WriteByte((REG_DC0_FREERUN_CW_L ), LOWBYTE((MS_U16)u32FreerunClk));
1515 HAL_WriteByte((REG_DC0_FREERUN_CW_L+1), HIGHBYTE((MS_U16)u32FreerunClk));
1516 HAL_WriteByte((REG_DC0_FREERUN_CW_H ), LOWBYTE((MS_U16)(u32FreerunClk >> 16)));
1517 HAL_WriteByte((REG_DC0_FREERUN_CW_H+1), HIGHBYTE((MS_U16)(u32FreerunClk >> 16)));
1518 HAL_WriteRegBit(REG_UPDATE_DC0_CW, 1, UPDATE_DC0_FREERUN_CW);
1519 HAL_WriteRegBit(REG_UPDATE_DC0_CW, 0, UPDATE_DC0_FREERUN_CW);
1520 }
1521 else if (_bEnable60P)
1522 {
1523 //Set DC1 Timing
1524 MS_U32 u32FrameRate = (MS_U32)ptiming->u16ExpFrameRate;
1525 MS_U32 u32VSize = 1024;
1526 MS_U32 u32HSize = ((86400000 / u32FrameRate) * 1000) / u32VSize;
1527
1528 if(u32HSize > 4096)
1529 MVOP_PRINTF("[Warning] xc support u32HSize > 4096 after CL 712830\n");
1530
1531 HAL_MVOP_SetFrequency(HAL_MVOP_GetMaxFreerunClk());
1532
1533 HAL_WriteRegBit(VOP_REG_YC422_EN_H, 0, VOP_FRAME_RST); // reg_frame_rst = 0
1534
1535 HAL_WriteRegBit(VOP_CTRL0, DISABLE, VOP_FSYNC_EN); // frame sync disable
1536 }
1537 else if (_bEnable4k2kClk)
1538 {
1539 HAL_MVOP_SetFrequency(HAL_MVOP_Get4k2kClk());
1540
1541 HAL_WriteRegBit(VOP_REG_YC422_EN_H, 0, VOP_FRAME_RST); // reg_frame_rst = 0
1542
1543 HAL_WriteRegBit(VOP_CTRL0, DISABLE, VOP_FSYNC_EN); // frame sync disable
1544 }
1545 else
1546 {
1547 HAL_MVOP_SetFrequency(HALMVOP_SYNCMODE);
1548 HAL_WriteByte((REG_DC0_NUM ), LOWBYTE( ptiming->u16Num));
1549 HAL_WriteByte((REG_DC0_NUM+1), HIGHBYTE(ptiming->u16Num));
1550 HAL_WriteByte((REG_DC0_DEN ), LOWBYTE( ptiming->u16Den));
1551 HAL_WriteByte((REG_DC0_DEN+1), HIGHBYTE(ptiming->u16Den));
1552 HAL_WriteRegBit(REG_UPDATE_DC0_CW, 1, UPDATE_DC0_SYNC_CW);
1553 HAL_WriteRegBit(REG_UPDATE_DC0_CW, 0, UPDATE_DC0_SYNC_CW);
1554 }
1555 }
1556
1557
HAL_MVOP_SetMonoMode(MS_BOOL bEnable)1558 void HAL_MVOP_SetMonoMode(MS_BOOL bEnable)
1559 {
1560 if(bEnable)
1561 {
1562 HAL_WriteByte(VOP_U_PAT , 0x80);
1563 HAL_WriteByte((VOP_U_PAT+1), 0x80);
1564
1565 HAL_WriteRegBit(VOP_INPUT_SWITCH1, 1, BIT1); // Mono mode enable
1566 }
1567 else
1568 {
1569 HAL_WriteRegBit(VOP_INPUT_SWITCH1, 0, BIT1); //Mono mode disable
1570 }
1571 }
1572
1573 /******************************************************************************/
1574 /// Set MVOP for H264 Hardwire Mode
1575 /******************************************************************************/
HAL_MVOP_SetH264HardwireMode(MS_U16 u16ECOVersion)1576 void HAL_MVOP_SetH264HardwireMode(MS_U16 u16ECOVersion)
1577 {
1578 UNUSED(u16ECOVersion);
1579
1580 // Hardwire mode
1581 HAL_WriteByte(VOP_MPG_JPG_SWITCH, 0x00);
1582
1583 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
1584
1585 //16*32 tile format
1586 HAL_WriteRegBit(VOP_REG_WR, 1, BIT1);
1587
1588 // SVD mode enable
1589 HAL_WriteByteMask(VOP_INPUT_SWITCH1, BIT3, BIT2|BIT3);
1590
1591 // set mvop to 128bit_i128 interface
1592 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
1593
1594 // Only for Monaco: Disable deciding bot by top address + 2
1595 HAL_WriteRegBit(VOP_MIRROR_CFG, 0, VOP_FIELD_FROM_ADDR);
1596
1597 HAL_WriteRegBit(VOP_REG_DUMMY, 1, VOP_32x32_WB); //32x32 from wb
1598
1599 // H264 use WISHBONE(R2) interface
1600 //HAL_WriteRegBit(VOP_INPUT_SWITCH0, 1, VOP_R2_WISHBONE);
1601
1602 // Write trigger
1603 HAL_MVOP_LoadReg();
1604 }
1605
1606 /******************************************************************************/
1607 /// Set MVOP for RM Hardwire Mode
1608 /******************************************************************************/
HAL_MVOP_SetRMHardwireMode(MS_U16 u16ECOVersion)1609 void HAL_MVOP_SetRMHardwireMode(MS_U16 u16ECOVersion)
1610 {
1611 HAL_MVOP_SetH264HardwireMode(u16ECOVersion);
1612 }
1613
1614 /******************************************************************************/
1615 /// Set MVOP for JPEG Hardwire Mode
1616 /******************************************************************************/
HAL_MVOP_SetJpegHardwireMode(void)1617 void HAL_MVOP_SetJpegHardwireMode(void)
1618 {
1619 MS_U8 regval = 0x00;
1620
1621 regval |= 0x80; // packmode
1622 regval |= 0x20; // Dram Rd Contd
1623 HAL_WriteByte(VOP_MPG_JPG_SWITCH, regval);
1624 g_pHalMVOPCtx->bIs422 = 1;
1625 HAL_WriteRegBit(VOP_REG_DUMMY, 0, VOP_420_BW_SAVE);
1626 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
1627
1628 // Write trigger
1629 HAL_MVOP_LoadReg();
1630 }
1631
1632 /******************************************************************************/
1633 /// Set MVOP for EVD Hardwire Mode
1634 /******************************************************************************/
HAL_MVOP_SetEVDHardwireMode(MS_U16 u16ECOVersion)1635 void HAL_MVOP_SetEVDHardwireMode(MS_U16 u16ECOVersion)
1636 {
1637 UNUSED(u16ECOVersion);
1638
1639 // Hardwire mode
1640 HAL_WriteByte(VOP_MPG_JPG_SWITCH, 0x00);
1641
1642 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
1643
1644 //16*32 tile format
1645 HAL_WriteRegBit(VOP_REG_WR, 1, BIT1);
1646
1647 // EVD use HVD interface
1648 //HAL_WriteByteMask(VOP_INPUT_SWITCH1, BIT3, BIT2|BIT3);
1649
1650 // EVD mode enable
1651 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 1, EVD_ENABLE);
1652
1653 // set mvop to 128bit_i128 interface
1654 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
1655
1656 // set evd flag for interlace mode setting
1657 g_pHalMVOPCtx->bIsH265 = 1;
1658
1659 // 10 bits from wb
1660 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_H, 1, VOP_INFO_FROM_CODEC_10BIT);
1661
1662 HAL_WriteByteMask(VOP_REG_MASK, 0, VOP_LSB_REQ_MASK);//10 bits bw control by vdec fw
1663
1664 // Write trigger
1665 HAL_MVOP_LoadReg();
1666 }
1667
1668 /******************************************************************************/
1669 /// Set MVOP for EVD Dolby Vision Hardwire Mode
1670 /******************************************************************************/
HAL_MVOP_SetEVDHardwireMode_DV(void)1671 void HAL_MVOP_SetEVDHardwireMode_DV(void)
1672 {
1673 // Hardwire mode
1674 HAL_WriteByte(VOP_MPG_JPG_SWITCH, 0x00);
1675
1676 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
1677
1678 //16*32 tile format
1679 HAL_WriteRegBit(VOP_REG_WR, 1, BIT1);
1680
1681 // EVD use HVD interface
1682 //HAL_WriteByteMask(VOP_INPUT_SWITCH1, BIT3, BIT2|BIT3);
1683
1684 // EVD mode enable
1685 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 1, EVD_ENABLE);
1686
1687 // set mvop to 128bit_i128 interface
1688 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
1689
1690 // set evd flag for interlace mode setting
1691 g_pHalMVOPCtx->bIsH265 = 1;
1692
1693 // 10 bits from wb
1694 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_H, 1, VOP_INFO_FROM_CODEC_10BIT);
1695
1696 HAL_WriteRegBit(VOP_REG_4K2K_2P, 1, VOP_TRIG_REFER_VB_END);
1697
1698 g_pHalMVOPCtx->bIs265DV = 1;
1699
1700 HAL_WriteByteMask(VOP_REG_MASK, 0, VOP_LSB_REQ_MASK);//10 bits bw control by vdec fw
1701
1702 // Write trigger
1703 HAL_MVOP_LoadReg();
1704 }
1705
1706 /******************************************************************************/
1707 /// Set MVOP for VP9 Hardwire Mode
1708 /// vp9 hw change in Manhathan: tile mode 16x32
1709 /******************************************************************************/
HAL_MVOP_SetVP9HardwireMode(MS_U16 u16ECOVersion)1710 void HAL_MVOP_SetVP9HardwireMode(MS_U16 u16ECOVersion)
1711 {
1712 UNUSED(u16ECOVersion);
1713
1714 // Hardwire mode
1715 HAL_WriteByte(VOP_MPG_JPG_SWITCH, 0x00);
1716
1717 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
1718
1719 //16*32 tile format
1720 HAL_WriteRegBit(VOP_REG_WR, 1, BIT1);
1721
1722 // VP9 use WISHBONE(R2) interface
1723 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 1, VOP_R2_WISHBONE);
1724
1725 // Enable VP9 dram continue mode
1726 //HAL_WriteRegBit(VOP_MPG_JPG_SWITCH, 1, VOP_DRAM_RD_MODE);
1727
1728 // set mvop to 128bit_i128 interface
1729 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
1730
1731 // EVD mode enable
1732 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 1, EVD_ENABLE);
1733 // 10 bits from wb
1734 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_H, 1, VOP_INFO_FROM_CODEC_10BIT);
1735
1736 HAL_WriteByteMask(VOP_REG_MASK, 0, VOP_LSB_REQ_MASK);//10 bits bw control by vdec fw
1737
1738 // Write trigger
1739 HAL_MVOP_LoadReg();
1740 }
1741
1742 /******************************************************************************/
1743 /// Set MVOP for EVD MCU Mode
1744 /******************************************************************************/
HAL_MVOP_SetEVDFeature(MVOP_DevID eID,MVOP_EVDFeature * stEVDInput)1745 void HAL_MVOP_SetEVDFeature(MVOP_DevID eID, MVOP_EVDFeature* stEVDInput)
1746 {
1747 switch(eID)
1748 {
1749 case E_MVOP_DEV_0:
1750
1751 HAL_WriteRegBit(VOP_INPUT_SWITCH0, stEVDInput->bEnableEVD, EVD_ENABLE);// 32x32 enable
1752
1753 switch(stEVDInput->eEVDBit[Y_INFO])
1754 {
1755 case E_MVOP_EVD_8BIT:
1756 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_Y_EN);
1757 break;
1758 case E_MVOP_EVD_10BIT:
1759 HAL_WriteRegBit(VOP_EVD_10B_EN, 1, VOP_EVD_10B_Y_EN);
1760 break;
1761 default:
1762 break;
1763 }
1764
1765 switch(stEVDInput->eEVDBit[UV_INFO])
1766 {
1767 case E_MVOP_EVD_8BIT:
1768 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_UV_EN);
1769 break;
1770 case E_MVOP_EVD_10BIT:
1771 HAL_WriteRegBit(VOP_EVD_10B_EN, 1, VOP_EVD_10B_UV_EN);
1772 break;
1773 default:
1774 break;
1775 }
1776
1777 //LSB BW Discard MASK
1778 if(stEVDInput->eEVDBit[Y_INFO] || stEVDInput->eEVDBit[UV_INFO])
1779 {
1780 HAL_WriteByteMask(VOP_REG_MASK, 0, VOP_LSB_REQ_MASK);
1781 HAL_WriteRegBit(VOP_UV_SHIFT, 0, VOP_GCLK_MIU_ON);
1782 MVOP_DBG(MVOP_PRINTF("[Debug] 10 bits display\n"););
1783 }
1784 else
1785 {
1786 //HAL_WriteByteMask(VOP_REG_MASK, BIT1, VOP_LSB_REQ_MASK);
1787 MVOP_DBG(MVOP_PRINTF("[Debug] 10 bits bw riu control default enable\n"););
1788 }
1789
1790 // Write trigger
1791 HAL_MVOP_LoadReg();
1792 break;
1793 case E_MVOP_DEV_1:
1794 #if MVOP_SUPPORT_SUB
1795
1796 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), stEVDInput->bEnableEVD, EVD_ENABLE);// 32x32 enable
1797
1798 switch(stEVDInput->eEVDBit[Y_INFO])
1799 {
1800 case E_MVOP_EVD_8BIT:
1801 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 0, VOP_EVD_10B_Y_EN);
1802 break;
1803 case E_MVOP_EVD_10BIT:
1804 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 1, VOP_EVD_10B_Y_EN);
1805 break;
1806 default:
1807 break;
1808 }
1809
1810 switch(stEVDInput->eEVDBit[UV_INFO])
1811 {
1812 case E_MVOP_EVD_8BIT:
1813 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 0, VOP_EVD_10B_UV_EN);
1814 break;
1815 case E_MVOP_EVD_10BIT:
1816 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 1, VOP_EVD_10B_UV_EN);
1817 break;
1818 default:
1819 break;
1820 }
1821
1822 //LSB BW Discard MASK
1823 if(stEVDInput->eEVDBit[Y_INFO] || stEVDInput->eEVDBit[UV_INFO])
1824 {
1825 HAL_WriteByteMask(SUB_REG(VOP_REG_MASK), 0, VOP_LSB_REQ_MASK);
1826 HAL_WriteRegBit(SUB_REG(VOP_UV_SHIFT), 0, VOP_GCLK_MIU_ON);
1827 MVOP_DBG(MVOP_PRINTF("[Debug] 10 bits display\n"););
1828 }
1829 else
1830 {
1831 //HAL_WriteByteMask(SUB_REG(VOP_REG_MASK), BIT1, VOP_LSB_REQ_MASK);
1832 MVOP_DBG(MVOP_PRINTF("[Debug] 10 bits bw riu control default enable\n"););
1833 }
1834 // Write trigger
1835 HAL_MVOP_SubLoadReg();
1836 #endif
1837 break;
1838 default:
1839 break;
1840 }
1841
1842 }
1843
1844
1845 ///Enable 3D L/R dual buffer mode
HAL_MVOP_Enable3DLR(MS_BOOL bEnable)1846 MS_BOOL HAL_MVOP_Enable3DLR(MS_BOOL bEnable)
1847 {
1848 if (g_pHalMVOPCtx == NULL)
1849 {
1850 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1851 return FALSE;
1852 }
1853 HAL_WriteRegBit(VOP_MULTI_WIN_CFG0, bEnable, VOP_LR_BUF_MODE);
1854 g_pHalMVOPCtx->b3DLRMode = bEnable;
1855 if(bEnable)
1856 {
1857 //only for monaco: do not wait for data ready.
1858 HAL_WriteByteMask(VOP_NOT_WAIT_READ_DATA, 2, VOP_NOT_WAIT_RDLAT);
1859 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
1860 }
1861 else
1862 {
1863 HAL_WriteByteMask(VOP_NOT_WAIT_READ_DATA, 0, VOP_NOT_WAIT_RDLAT);
1864 }
1865 return TRUE;
1866 }
1867
1868 ///Get if 3D L/R mode is enabled
HAL_MVOP_Get3DLRMode(void)1869 MS_BOOL HAL_MVOP_Get3DLRMode(void)
1870 {
1871 if (g_pHalMVOPCtx == NULL)
1872 {
1873 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1874 return FALSE;
1875 }
1876 return g_pHalMVOPCtx->b3DLRMode;
1877 }
1878
HAL_MVOP_GetTimingInfoFromRegisters(MVOP_TimingInfo_FromRegisters * pMvopTimingInfo)1879 MS_BOOL HAL_MVOP_GetTimingInfoFromRegisters(MVOP_TimingInfo_FromRegisters *pMvopTimingInfo)
1880 {
1881 if(NULL == pMvopTimingInfo)
1882 {
1883 MVOP_PRINTF("HAL_MVOP_GetTimingInfoFromRegisters():pMvopTimingInfo is NULL\n");
1884 return FALSE;
1885 }
1886 if(HAL_MVOP_GetEnableState() == FALSE)
1887 {
1888 MVOP_PRINTF("MVOP is not enabled!\n");
1889 pMvopTimingInfo->bEnabled = FALSE;
1890 return FALSE;
1891 }
1892 pMvopTimingInfo->bEnabled = TRUE;
1893 pMvopTimingInfo->u16H_TotalCount = (HAL_ReadByte((VOP_FRAME_HCOUNT + 1))<< 8) | (HAL_ReadByte((VOP_FRAME_HCOUNT)));
1894 pMvopTimingInfo->u16V_TotalCount = (HAL_ReadByte((VOP_FRAME_VCOUNT + 1))<< 8) | (HAL_ReadByte((VOP_FRAME_VCOUNT)));
1895 pMvopTimingInfo->u16VBlank0_Start = (HAL_ReadByte((VOP_VB0_STR + 1))<< 8) | (HAL_ReadByte((VOP_VB0_STR)));
1896 pMvopTimingInfo->u16VBlank0_End = (HAL_ReadByte((VOP_VB0_END + 1))<< 8) | (HAL_ReadByte((VOP_VB0_END)));
1897 pMvopTimingInfo->u16VBlank1_Start = (HAL_ReadByte((VOP_VB1_STR + 1))<< 8) | (HAL_ReadByte((VOP_VB1_STR)));
1898 pMvopTimingInfo->u16VBlank1_End = (HAL_ReadByte((VOP_VB1_END + 1))<< 8) | (HAL_ReadByte((VOP_VB1_END)));
1899 pMvopTimingInfo->u16TopField_Start = (HAL_ReadByte((VOP_TF_STR + 1))<< 8) | (HAL_ReadByte((VOP_TF_STR)));
1900 pMvopTimingInfo->u16BottomField_Start = (HAL_ReadByte((VOP_BF_STR + 1))<< 8) | (HAL_ReadByte((VOP_BF_STR)));
1901 pMvopTimingInfo->u16HActive_Start = (HAL_ReadByte((VOP_HACT_STR + 1))<< 8) | (HAL_ReadByte((VOP_HACT_STR)));
1902 pMvopTimingInfo->u16TopField_VS = (HAL_ReadByte((VOP_TF_VS + 1))<< 8) | (HAL_ReadByte((VOP_TF_VS)));
1903 pMvopTimingInfo->u16BottomField_VS = (HAL_ReadByte((VOP_BF_VS + 1))<< 8) | (HAL_ReadByte((VOP_BF_VS)));
1904 pMvopTimingInfo->bInterlace = (HAL_ReadRegBit(VOP_CTRL0, BIT7) == BIT7);
1905 return TRUE;
1906 }
1907
HAL_MVOP_SetYUVBaseAdd(MS_PHY u32YOffset,MS_PHY u32UVOffset,MS_BOOL bProgressive,MS_BOOL b422pack)1908 void HAL_MVOP_SetYUVBaseAdd(MS_PHY u32YOffset, MS_PHY u32UVOffset, MS_BOOL bProgressive, MS_BOOL b422pack)
1909 {
1910 MS_PHY u64tmp = 0;
1911
1912 if (g_pHalMVOPCtx == NULL)
1913 {
1914 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1915 return;
1916 }
1917 // Y offset
1918 u64tmp = u32YOffset >> 3;
1919 if ( !bProgressive )
1920 { //Refine Y offset for interlace repeat bottom field
1921 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
1922 {
1923 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
1924 u64tmp += 2;
1925 }
1926 else
1927 {
1928 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
1929 }
1930 }
1931 HAL_WriteByte(VOP_JPG_YSTR0_L, u64tmp & 0xff);
1932 HAL_WriteByte((VOP_JPG_YSTR0_L+1), (u64tmp >> 8) & 0xff);
1933 HAL_WriteByte((VOP_JPG_YSTR0_L+2), (u64tmp >> 16) & 0xff);
1934 HAL_WriteByte((VOP_JPG_YSTR0_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
1935
1936 if (!bProgressive )
1937 { //Y offset of bottom field if interlace
1938 HAL_WriteByte(VOP_JPG_YSTR1_L, u64tmp & 0xff);
1939 HAL_WriteByte((VOP_JPG_YSTR1_L+1), (u64tmp >> 8) & 0xff);
1940 HAL_WriteByte((VOP_JPG_YSTR1_L+2), (u64tmp >> 16) & 0xff);
1941 HAL_WriteByte((VOP_JPG_YSTR1_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
1942 }
1943
1944 if (b422pack)
1945 {
1946 u32UVOffset = u32YOffset + 16; //add 16 for 128bit; add 8 for 64bit
1947 }
1948 // UV offset
1949 u64tmp = u32UVOffset >> 3;
1950 if( !bProgressive )
1951 { //Refine UV offset for interlace repeat bottom field
1952 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
1953 {
1954 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
1955 u64tmp += 2;
1956 }
1957 else
1958 {
1959 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
1960 }
1961 }
1962 HAL_WriteByte(VOP_JPG_UVSTR0_L, u64tmp & 0xff);
1963 HAL_WriteByte((VOP_JPG_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
1964 HAL_WriteByte((VOP_JPG_UVSTR0_L+2), (u64tmp >> 16) & 0xff);
1965 HAL_WriteByte((VOP_JPG_UVSTR0_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
1966
1967 if( !bProgressive )
1968 { //UV offset of bottom field if interlace
1969 HAL_WriteByte(VOP_JPG_UVSTR1_L, u64tmp & 0xff);
1970 HAL_WriteByte((VOP_JPG_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
1971 HAL_WriteByte((VOP_JPG_UVSTR1_L+2), (u64tmp >> 16) & 0xff);
1972 HAL_WriteByte((VOP_JPG_UVSTR1_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
1973 }
1974
1975 return;
1976 }
1977
HAL_MVOP_SetYUVBaseAddMultiView(MVOP_BaseAddInput * stBaseAddInfo)1978 MS_BOOL HAL_MVOP_SetYUVBaseAddMultiView(MVOP_BaseAddInput *stBaseAddInfo)
1979 {
1980 MS_PHY u64tmpY = 0;
1981 MS_PHY u64tmpUV = 0;
1982
1983 if (stBaseAddInfo == NULL)
1984 {
1985 MVOP_DBG(MVOP_PRINTF("%s stBaseAddInfo is NULL pointer\n", __FUNCTION__);)
1986 return FALSE;
1987 }
1988 // Y offset
1989 u64tmpY = (stBaseAddInfo->u32YOffset) >> 3;
1990 // UV offset
1991 u64tmpUV = (stBaseAddInfo->u32UVOffset) >> 3;
1992
1993 switch(stBaseAddInfo->eView)
1994 {
1995 case E_MVOP_MAIN_VIEW:
1996 // Y offset
1997 HAL_WriteByte(VOP_JPG_YSTR0_L, u64tmpY & 0xff);
1998 HAL_WriteByte((VOP_JPG_YSTR0_L+1), (u64tmpY >> 8) & 0xff);
1999 HAL_WriteByte((VOP_JPG_YSTR0_L+2), (u64tmpY >> 16) & 0xff);
2000 HAL_WriteByte((VOP_JPG_YSTR0_L+3), (u64tmpY >> 24) & VOP_YUV_STR_HIBITS);
2001
2002 // UV offset
2003 HAL_WriteByte(VOP_JPG_UVSTR0_L, u64tmpUV & 0xff);
2004 HAL_WriteByte((VOP_JPG_UVSTR0_L+1), (u64tmpUV >> 8) & 0xff);
2005 HAL_WriteByte((VOP_JPG_UVSTR0_L+2), (u64tmpUV >> 16) & 0xff);
2006 HAL_WriteByte((VOP_JPG_UVSTR0_L+3), (u64tmpUV >> 24) & VOP_YUV_STR_HIBITS);
2007 break;
2008 case E_MVOP_2ND_VIEW:
2009 // Y offset
2010 HAL_WriteByte(VOP_JPG_YSTR1_L, u64tmpY & 0xff);
2011 HAL_WriteByte((VOP_JPG_YSTR1_L+1), (u64tmpY >> 8) & 0xff);
2012 HAL_WriteByte((VOP_JPG_YSTR1_L+2), (u64tmpY >> 16) & 0xff);
2013 HAL_WriteByte((VOP_JPG_YSTR1_L+3), (u64tmpY >> 24) & VOP_YUV_STR_HIBITS);
2014
2015 //UV offset
2016 HAL_WriteByte(VOP_JPG_UVSTR1_L, u64tmpUV & 0xff);
2017 HAL_WriteByte((VOP_JPG_UVSTR1_L+1), (u64tmpUV >> 8) & 0xff);
2018 HAL_WriteByte((VOP_JPG_UVSTR1_L+2), (u64tmpUV >> 16) & 0xff);
2019 HAL_WriteByte((VOP_JPG_UVSTR1_L+3), (u64tmpUV >> 24) & VOP_YUV_STR_HIBITS);
2020 break;
2021 default:
2022 break;
2023 }
2024 return TRUE;
2025 }
2026
HAL_MVOP_GetYBaseAdd(void)2027 MS_PHY HAL_MVOP_GetYBaseAdd(void)
2028 {
2029 MS_PHY u64YOffset = 0;
2030 u64YOffset = HAL_ReadByte(VOP_JPG_YSTR0_L)&0xff;
2031 u64YOffset |=((HAL_ReadByte((VOP_JPG_YSTR0_L+1))<<8)&0xff00);
2032 u64YOffset |=((HAL_ReadByte((VOP_JPG_YSTR0_L+2))<<16)&0xff0000);
2033 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
2034 return u64YOffset;
2035 }
2036
HAL_MVOP_GetUVBaseAdd(void)2037 MS_PHY HAL_MVOP_GetUVBaseAdd(void)
2038 {
2039 MS_PHY u64UVOffset = 0;
2040 u64UVOffset = HAL_ReadByte(VOP_JPG_UVSTR0_L)&0xff;
2041 u64UVOffset |=((HAL_ReadByte((VOP_JPG_UVSTR0_L+1))<<8)&0xff00);
2042 u64UVOffset |=((HAL_ReadByte((VOP_JPG_UVSTR0_L+2))<<16)&0xff0000);
2043 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
2044 return u64UVOffset;
2045 }
2046
HAL_MVOP_GetYBaseAddMultiView(MVOP_3DView eView)2047 MS_PHY HAL_MVOP_GetYBaseAddMultiView(MVOP_3DView eView)
2048 {
2049 MS_PHY u64YOffset = 0;
2050 switch(eView)
2051 {
2052 case E_MVOP_MAIN_VIEW:
2053 u64YOffset = HAL_ReadByte(VOP_JPG_YSTR0_L)&0xff;
2054 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR0_L+1))<<8)&0xff00);
2055 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR0_L+2))<<16)&0xff0000);
2056 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
2057 break;
2058 case E_MVOP_2ND_VIEW:
2059 u64YOffset = HAL_ReadByte(VOP_JPG_YSTR1_L)&0xff;
2060 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR1_L+1))<<8)&0xff00);
2061 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR1_L+2))<<16)&0xff0000);
2062 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR1_L+3))<<24)&0x7000000);
2063 break;
2064 default:
2065 u64YOffset = 0;
2066 break;
2067 }
2068 return u64YOffset;
2069 }
2070
HAL_MVOP_GetUVBaseAddMultiView(MVOP_3DView eView)2071 MS_PHY HAL_MVOP_GetUVBaseAddMultiView(MVOP_3DView eView)
2072 {
2073 MS_PHY u64UVOffset = 0;
2074 switch(eView)
2075 {
2076 case E_MVOP_MAIN_VIEW:
2077 u64UVOffset = HAL_ReadByte(VOP_JPG_UVSTR0_L)&0xff;
2078 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR0_L+1))<<8)&0xff00);
2079 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR0_L+2))<<16)&0xff0000);
2080 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
2081 break;
2082 case E_MVOP_2ND_VIEW:
2083 u64UVOffset = HAL_ReadByte(VOP_JPG_UVSTR1_L)&0xff;
2084 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR1_L+1))<<8)&0xff00);
2085 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR1_L+2))<<16)&0xff0000);
2086 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR1_L+3))<<24)&0x7000000);
2087 break;
2088 default:
2089 u64UVOffset = 0;
2090 break;
2091 }
2092 return u64UVOffset;
2093 }
2094
HAL_MVOP_Set3DLRAltOutput_VHalfScaling(MS_BOOL bEnable)2095 MS_BOOL HAL_MVOP_Set3DLRAltOutput_VHalfScaling(MS_BOOL bEnable)
2096 {
2097 MS_BOOL bEnDualBuff = bEnable ? ENABLE : DISABLE; //enable dual buffer
2098 MS_BOOL bEnSWDualBuff = bEnable ? DISABLE : ENABLE; //buffer controlled by HK instead of FW
2099 MS_BOOL bEnMirrMaskBase = bEnable ? DISABLE : ENABLE; //do not mask LSB
2100 MS_BOOL bEnHwFldBase = bEnable ? DISABLE : ENABLE; //hardware calculate field jump base address
2101
2102 if (g_pHalMVOPCtx == NULL)
2103 {
2104 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2105 return FALSE;
2106 }
2107 //Set 0x27[2] = 1 (enable SW dual buffer mode)
2108 HAL_WriteRegBit(VOP_REG_WR, bEnDualBuff, VOP_BUF_DUAL);
2109
2110 //Set 0x38[8] = 0 (use SW dual buffer mode)
2111 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_H, bEnSWDualBuff, VOP_INFO_FROM_CODEC_DUAL_BUFF);
2112
2113 //Set 0x3b[7] = 0 (use MVD/HVD firmware send base)
2114 HAL_WriteRegBit(VOP_MIRROR_CFG, bEnMirrMaskBase, VOP_MASK_BASE_LSB);
2115
2116 //Set 0x3b[5] = 0 (hardware calculate field jump base address)
2117 HAL_WriteRegBit(VOP_MIRROR_CFG, bEnHwFldBase, VOP_HW_FLD_BASE);
2118
2119 g_pHalMVOPCtx->b3DLRAltOutput = bEnable;
2120 return TRUE;
2121 }
2122
HAL_MVOP_Set3DLRAltOutput(MS_BOOL bEnable)2123 MS_BOOL HAL_MVOP_Set3DLRAltOutput(MS_BOOL bEnable)
2124 {
2125 //Set 0x3C[2] = 1 (enable 3D L/R dual buffer line alternative output)
2126 //it works when 0x3C[0] = 1
2127 HAL_WriteRegBit(VOP_MULTI_WIN_CFG0, bEnable, VOP_LR_LA_OUT);
2128 // bw saving not support: LA/SBS
2129 HAL_WriteRegBit(VOP_REG_DUMMY, 0, VOP_420_BW_SAVE);
2130 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
2131 HAL_MVOP_LoadReg();
2132
2133 g_pHalMVOPCtx->b3DLRAltOutput = bEnable;
2134 return TRUE;
2135 }
2136
HAL_MVOP_Set3DLRAltSBSOutput(MS_BOOL bEnable)2137 MS_BOOL HAL_MVOP_Set3DLRAltSBSOutput(MS_BOOL bEnable)
2138 {
2139 //it works when 0x3C[0] = 1 and 0x3C[2] = 1
2140 //Set 0x3C[3] = 1 (3D L/R line alternative read, side-by-side output)
2141 HAL_WriteRegBit(VOP_MULTI_WIN_CFG0, bEnable, VOP_LR_LA2SBS_OUT);
2142 g_pHalMVOPCtx->b3DLRAltSBSOutput = bEnable;
2143 return TRUE;
2144 }
2145
HAL_MVOP_Get3DLRAltOutput(void)2146 MS_BOOL HAL_MVOP_Get3DLRAltOutput(void)
2147 {
2148 if (g_pHalMVOPCtx == NULL)
2149 {
2150 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2151 return FALSE;
2152 }
2153 return g_pHalMVOPCtx->b3DLRAltOutput;
2154 }
2155
HAL_MVOP_Get3DLRAltSBSOutput(void)2156 MS_BOOL HAL_MVOP_Get3DLRAltSBSOutput(void)
2157 {
2158 return g_pHalMVOPCtx->b3DLRAltSBSOutput;
2159 }
2160
HAL_MVOP_GetOutput3DType(void)2161 EN_MVOP_Output_3D_TYPE HAL_MVOP_GetOutput3DType(void)
2162 {
2163 EN_MVOP_Output_3D_TYPE en3DType = E_MVOP_OUTPUT_3D_NONE;
2164 if(g_pHalMVOPCtx->b3DLRMode)
2165 {
2166 if(g_pHalMVOPCtx->b3DLRAltSBSOutput)
2167 {
2168 en3DType = E_MVOP_OUTPUT_3D_SBS;
2169 }
2170 else
2171 {
2172 en3DType = E_MVOP_OUTPUT_3D_TB;
2173 }
2174 }
2175 else if(g_pHalMVOPCtx->b3DLRAltOutput)
2176 {
2177 en3DType = E_MVOP_OUTPUT_3D_LA;
2178 }
2179 return en3DType;
2180 }
2181
HAL_MVOP_Set3DLR2ndCfg(MS_BOOL bEnable)2182 MS_BOOL HAL_MVOP_Set3DLR2ndCfg(MS_BOOL bEnable)
2183 {
2184 //Set 0x3c[7] as 1 to enable
2185 HAL_WriteRegBit(VOP_MULTI_WIN_CFG0, bEnable, VOP_LR_DIFF_SIZE);
2186 return TRUE;
2187 }
2188
HAL_MVOP_Get3DLR2ndCfg(void)2189 MS_BOOL HAL_MVOP_Get3DLR2ndCfg(void)
2190 {
2191 MS_BOOL bEnable = FALSE;
2192 if (VOP_LR_DIFF_SIZE == (VOP_LR_DIFF_SIZE & HAL_ReadRegBit(VOP_MULTI_WIN_CFG0, VOP_LR_DIFF_SIZE)))
2193 {
2194 bEnable = TRUE;
2195 }
2196 return bEnable;
2197 }
2198
HAL_MVOP_GetMirrorMode(MVOP_DevID eID)2199 MVOP_DrvMirror HAL_MVOP_GetMirrorMode(MVOP_DevID eID)
2200 {
2201 MVOP_DrvMirror enMirror = E_VOPMIRROR_NONE;
2202 if (g_pHalMVOPCtx == NULL)
2203 {
2204 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2205 return FALSE;
2206 }
2207 switch(eID)
2208 {
2209 case E_MVOP_DEV_0:
2210 if(g_pHalMVOPCtx->bMirrorModeVer && g_pHalMVOPCtx->bMirrorModeHor)
2211 {
2212 enMirror = E_VOPMIRROR_HVBOTH;
2213 }
2214 else if(g_pHalMVOPCtx->bMirrorModeHor)
2215 {
2216 enMirror = E_VOPMIRROR_HORIZONTALL;
2217 }
2218 else if(g_pHalMVOPCtx->bMirrorModeVer)
2219 {
2220 enMirror = E_VOPMIRROR_VERTICAL;
2221 }
2222 break;
2223 case E_MVOP_DEV_1:
2224 #if MVOP_SUPPORT_SUB
2225 if(g_pHalMVOPCtx->bSubMirrorModeVer &&g_pHalMVOPCtx-> bSubMirrorModeHor)
2226 {
2227 enMirror = E_VOPMIRROR_HVBOTH;
2228 }
2229 else if(g_pHalMVOPCtx->bSubMirrorModeHor)
2230 {
2231 enMirror = E_VOPMIRROR_HORIZONTALL;
2232 }
2233 else if(g_pHalMVOPCtx->bSubMirrorModeVer)
2234 {
2235 enMirror = E_VOPMIRROR_VERTICAL;
2236 }
2237 #endif
2238 break;
2239 default:
2240 break;
2241 }
2242 return enMirror;
2243 }
2244
HAL_MVOP_SetVerDup(MS_BOOL bEnable)2245 MS_BOOL HAL_MVOP_SetVerDup(MS_BOOL bEnable)
2246 {
2247 HAL_WriteRegBit(VOP_CTRL0, bEnable, BIT3);// V line duplicate
2248 return TRUE;
2249 }
2250
HAL_MVOP_GetVerDup(void)2251 MS_BOOL HAL_MVOP_GetVerDup(void)
2252 {
2253 return (HAL_ReadRegBit(VOP_CTRL0, BIT3) == BIT3);
2254 }
2255
HAL_MVOP_SetVerx4Dup(MS_BOOL bEnable)2256 MS_BOOL HAL_MVOP_SetVerx4Dup(MS_BOOL bEnable)
2257 {
2258 HAL_WriteRegBit(VOP_CTRL0, bEnable, BIT3);// x4 duplicate should raise V line duplicate first
2259 HAL_WriteRegBit(VOP_RGB_FMT, bEnable, BIT3);// V line x4 duplicate
2260 return TRUE;
2261 }
2262
HAL_MVOP_SetHorx4Dup(MS_BOOL bEnable)2263 MS_BOOL HAL_MVOP_SetHorx4Dup(MS_BOOL bEnable)
2264 {
2265 HAL_WriteRegBit(VOP_CTRL0, bEnable, BIT2);// x4 duplicate should raise H pixel duplicate first
2266 HAL_WriteRegBit(VOP_RGB_FMT, bEnable, BIT2);// H line x4 duplicate
2267 return TRUE;
2268 }
2269
HAL_MVOP_GetVerx4Dup(void)2270 MS_BOOL HAL_MVOP_GetVerx4Dup(void)
2271 {
2272 return ((HAL_ReadRegBit(VOP_RGB_FMT, BIT3) & HAL_ReadRegBit(VOP_CTRL0, BIT3)) == BIT3);
2273 }
2274
HAL_MVOP_GetHorx4Dup(void)2275 MS_BOOL HAL_MVOP_GetHorx4Dup(void)
2276 {
2277 return ((HAL_ReadRegBit(VOP_RGB_FMT, BIT2) & HAL_ReadRegBit(VOP_CTRL0, BIT2)) == BIT2);
2278 }
2279
HAL_MVOP_GetTopVStart(MVOP_DevID eID)2280 MS_U16 HAL_MVOP_GetTopVStart(MVOP_DevID eID)
2281 {
2282 MS_U16 u16TopVStart = 0;
2283 switch(eID)
2284 {
2285 case E_MVOP_DEV_0:
2286 u16TopVStart = HAL_Read2Byte(VOP_IMG_VSTR0)&0x1fff;
2287 break;
2288 case E_MVOP_DEV_1:
2289 #if MVOP_SUPPORT_SUB
2290 u16TopVStart = HAL_Read2Byte(SUB_REG(VOP_IMG_VSTR0))&0x1fff;
2291 #endif
2292 break;
2293 default:
2294 break;
2295 }
2296 return u16TopVStart;
2297 }
2298
HAL_MVOP_GetBottomVStart(MVOP_DevID eID)2299 MS_U16 HAL_MVOP_GetBottomVStart(MVOP_DevID eID)
2300 {
2301 MS_U16 u16BotVStart = 0;
2302 switch(eID)
2303 {
2304 case E_MVOP_DEV_0:
2305 u16BotVStart = HAL_Read2Byte(VOP_IMG_VSTR1)&0x1fff;
2306 break;
2307 case E_MVOP_DEV_1:
2308 #if MVOP_SUPPORT_SUB
2309 u16BotVStart = HAL_Read2Byte(SUB_REG(VOP_IMG_VSTR1))&0x1fff;
2310 #endif
2311 break;
2312 default:
2313 break;
2314 }
2315 return u16BotVStart;
2316 }
2317
HAL_MVOP_GetVCount(MVOP_DevID eID)2318 MS_U16 HAL_MVOP_GetVCount(MVOP_DevID eID)
2319 {
2320 MS_U16 u16VCount = 0;
2321 switch(eID)
2322 {
2323 case E_MVOP_DEV_0:
2324 u16VCount = HAL_Read2Byte(VOP_DEBUG_2A)&0x1fff;
2325 break;
2326 case E_MVOP_DEV_1:
2327 #if MVOP_SUPPORT_SUB
2328 u16VCount = HAL_Read2Byte(SUB_REG(VOP_DEBUG_2A))&0x1fff;
2329 #endif
2330 break;
2331 default:
2332 break;
2333 }
2334 return u16VCount;
2335 }
2336
HAL_MVOP_SetVC1RangeMap(MVOP_DevID eID,MVOP_VC1RangeMapInfo * stVC1RangeMapInfo)2337 MS_BOOL HAL_MVOP_SetVC1RangeMap(MVOP_DevID eID, MVOP_VC1RangeMapInfo *stVC1RangeMapInfo)
2338 {
2339 MS_U32 u8Luma = 0;
2340 MS_U32 u8Chroma = 0;
2341
2342 if (stVC1RangeMapInfo == NULL)
2343 {
2344 MVOP_DBG(MVOP_PRINTF("%s stBaseAddInfo is NULL pointer\n", __FUNCTION__);)
2345 return FALSE;
2346 }
2347
2348 // Luma value
2349 u8Luma = stVC1RangeMapInfo->u8LumaValue;
2350 // Chroma value
2351 u8Chroma = stVC1RangeMapInfo->u8ChromaValue;
2352
2353 switch(eID)
2354 {
2355 case E_MVOP_DEV_0:
2356 //set VC1 Luma value
2357 if(stVC1RangeMapInfo->bIsEnableLuma)
2358 {
2359 HAL_WriteRegBit(VOP_RAMAP_LUMA, 1, BIT7);
2360 HAL_WriteByteMask(VOP_RAMAP_LUMA, u8Luma, VOP_RAMAP_LUMA_VAL);
2361 }
2362 else //disable
2363 {
2364 HAL_WriteRegBit(VOP_RAMAP_LUMA, 0, BIT7);
2365 }
2366
2367 //set VC1 Chroma value
2368 if(stVC1RangeMapInfo->bIsEnableChroma)
2369 {
2370 HAL_WriteRegBit(VOP_RAMAP_CHROMA, 1, BIT7);
2371 HAL_WriteByteMask(VOP_RAMAP_CHROMA, u8Chroma, VOP_RAMAP_CHROMA_VAL);
2372 }
2373 else
2374 {
2375 HAL_WriteRegBit(VOP_RAMAP_CHROMA, 0, BIT7);
2376 }
2377 break;
2378 case E_MVOP_DEV_1:
2379 #if MVOP_SUPPORT_SUB
2380 //set VC1 Luma value
2381 if(stVC1RangeMapInfo->bIsEnableLuma)
2382 {
2383 HAL_WriteRegBit(SUB_REG(VOP_RAMAP_LUMA), 1, BIT7);
2384 HAL_WriteByteMask(SUB_REG(VOP_RAMAP_LUMA), u8Luma, VOP_RAMAP_LUMA_VAL);
2385 }
2386 else //disable
2387 {
2388 HAL_WriteRegBit(SUB_REG(VOP_RAMAP_LUMA), 0, BIT7);
2389 }
2390
2391 //set VC1 Chroma value
2392 if(stVC1RangeMapInfo->bIsEnableChroma)
2393 {
2394 HAL_WriteRegBit(SUB_REG(VOP_RAMAP_CHROMA), 1, BIT7);
2395 HAL_WriteByteMask(SUB_REG(VOP_RAMAP_CHROMA), u8Chroma, VOP_RAMAP_CHROMA_VAL);
2396 }
2397 else
2398 {
2399 HAL_WriteRegBit(SUB_REG(VOP_RAMAP_CHROMA), 0, BIT7);
2400 }
2401 #endif
2402 break;
2403 default:
2404 break;
2405 }
2406 return TRUE;
2407 }
2408
2409 MS_U16 g_u16SetStartX = 0;
2410 MS_U16 g_u16SetStartY = 0;
2411 MS_BOOL g_bIsY4Align = 0;
2412
HAL_MVOP_SetStartX(MVOP_DevID eID,MS_U16 u16XPos)2413 void HAL_MVOP_SetStartX(MVOP_DevID eID, MS_U16 u16XPos)
2414 {
2415 switch(eID)
2416 {
2417 case E_MVOP_DEV_0:
2418 u16XPos = ALIGN_UPTO_2(u16XPos);
2419 HAL_WriteByte(VOP_REG_CROP_HSTART, u16XPos & 0xff);
2420 HAL_WriteByte((VOP_REG_CROP_HSTART + 1),((u16XPos) >> (8)) & (0x1f));
2421 if(0 == u16XPos)
2422 {
2423 g_pHalMVOPCtx->u16CropXStart = 0;
2424 }
2425 else
2426 {
2427 g_pHalMVOPCtx->u16CropXStart += u16XPos;
2428 }
2429 // Write trigger
2430 HAL_MVOP_LoadReg();
2431 break;
2432 case E_MVOP_DEV_1:
2433 #if MVOP_SUPPORT_SUB
2434 u16XPos = ALIGN_UPTO_2(u16XPos);
2435 HAL_WriteByte(SUB_REG(VOP_REG_CROP_HSTART), u16XPos & 0xff);
2436 HAL_WriteByte(SUB_REG((VOP_REG_CROP_HSTART + 1)),((u16XPos) >> (8)) & (0x1f));
2437 if(0 == u16XPos)
2438 {
2439 g_pHalMVOPCtx->u16SubCropXStart = 0;
2440 }
2441 else
2442 {
2443 g_pHalMVOPCtx->u16SubCropXStart += u16XPos;
2444 }
2445 // Write trigger
2446 HAL_MVOP_SubLoadReg();
2447 #endif
2448 break;
2449 default:
2450 break;
2451 }
2452 }
2453
2454
HAL_MVOP_SetStartY(MVOP_DevID eID,MS_U16 u16YPos,MS_BOOL bIsInterlace)2455 void HAL_MVOP_SetStartY(MVOP_DevID eID, MS_U16 u16YPos, MS_BOOL bIsInterlace)
2456 {
2457 switch(eID)
2458 {
2459 case E_MVOP_DEV_0:
2460 HAL_WriteByteMask(VOP_REG_CROP_VSTART, u16YPos & 0xff, 0xff);
2461 HAL_WriteByteMask((VOP_REG_CROP_VSTART + 1), ((u16YPos) >> (8)) & (0x1f), 0x1f);
2462 if(0 == u16YPos)
2463 {
2464 g_pHalMVOPCtx->u16CropYStart = 0;
2465 }
2466 else
2467 {
2468 g_pHalMVOPCtx->u16CropYStart += u16YPos;
2469 }
2470 // Write trigger
2471 HAL_MVOP_LoadReg();
2472 break;
2473 case E_MVOP_DEV_1:
2474 #if MVOP_SUPPORT_SUB
2475 HAL_WriteByteMask(SUB_REG(VOP_REG_CROP_VSTART), u16YPos & 0xff, 0xff);
2476 HAL_WriteByteMask(SUB_REG((VOP_REG_CROP_VSTART + 1)), ((u16YPos) >> (8)) & (0x1f), 0x1f);
2477 if(0 == u16YPos)
2478 {
2479 g_pHalMVOPCtx->u16SubCropYStart = 0;
2480 }
2481 else
2482 {
2483 g_pHalMVOPCtx->u16SubCropYStart += u16YPos;
2484 }
2485 // Write trigger
2486 HAL_MVOP_SubLoadReg();
2487 #endif
2488 break;
2489 default:
2490 break;
2491 }
2492 }
2493
2494
HAL_MVOP_SetPicWidthMinus(MVOP_DevID eID,MS_U16 u16XSizes,MS_U16 u16Width)2495 void HAL_MVOP_SetPicWidthMinus(MVOP_DevID eID, MS_U16 u16XSizes, MS_U16 u16Width)
2496 {
2497 switch(eID)
2498 {
2499 case E_MVOP_DEV_0:
2500 u16XSizes = ALIGN_UPTO_2(u16XSizes);
2501 if(TRUE == g_pHalMVOPCtx->bMirrorModeHor)
2502 {
2503 MS_U16 u16XstMir = 0;
2504 if((g_pHalMVOPCtx->u16CropXStart + u16XSizes) < u16Width)
2505 {
2506 u16XstMir = u16Width - g_pHalMVOPCtx->u16CropXStart - u16XSizes;
2507 HAL_MVOP_SetStartX(E_MVOP_DEV_0, u16XstMir);
2508 }
2509 else
2510 {
2511 MVOP_PRINTF("[Warning] crop x size or start out of boundary.");
2512 return;
2513 }
2514 }
2515
2516 HAL_WriteByte(VOP_REG_CROP_HSIZE, u16XSizes & 0xff);
2517 HAL_WriteByte((VOP_REG_CROP_HSIZE + 1), ((u16XSizes) >> (8)) & (0x1f));
2518
2519 if(0 == u16XSizes)
2520 {
2521 g_pHalMVOPCtx->u16CropXSize = 0;
2522 }
2523 else
2524 {
2525 g_pHalMVOPCtx->u16CropXSize = u16XSizes;
2526 }
2527 // Write trigger
2528 HAL_MVOP_LoadReg();
2529 break;
2530 case E_MVOP_DEV_1:
2531 #if MVOP_SUPPORT_SUB
2532 u16XSizes = ALIGN_UPTO_2(u16XSizes);
2533
2534 if(TRUE == g_pHalMVOPCtx->bSubMirrorModeHor)
2535 {
2536 MS_U16 u16XstMir = 0;
2537 if((g_pHalMVOPCtx->u16SubCropXStart + u16XSizes) < u16Width)
2538 {
2539 u16XstMir = u16Width - g_pHalMVOPCtx->u16SubCropXStart - u16XSizes;
2540 HAL_MVOP_SetStartX(E_MVOP_DEV_1, u16XstMir);
2541 }
2542 else
2543 {
2544 MVOP_PRINTF("[Warning] sub crop x size or start out of boundary.");
2545 return;
2546 }
2547 }
2548
2549 HAL_WriteByte(SUB_REG(VOP_REG_CROP_HSIZE), u16XSizes & 0xff);
2550 HAL_WriteByte(SUB_REG((VOP_REG_CROP_HSIZE + 1)), ((u16XSizes) >> (8)) & (0x1f));
2551 if(0 == u16XSizes)
2552 {
2553 g_pHalMVOPCtx->u16SubCropXSize = 0;
2554 }
2555 else
2556 {
2557 g_pHalMVOPCtx->u16SubCropXSize = u16XSizes;
2558 }
2559 // Write trigger
2560 HAL_MVOP_SubLoadReg();
2561 #endif
2562 break;
2563 default:
2564 break;
2565 }
2566 }
2567
HAL_MVOP_SetPicHeightMinus(MVOP_DevID eID,MS_U16 u16YSizes,MS_U16 u16Height)2568 void HAL_MVOP_SetPicHeightMinus(MVOP_DevID eID, MS_U16 u16YSizes, MS_U16 u16Height)
2569 {
2570 switch(eID)
2571 {
2572 case E_MVOP_DEV_0:
2573 if(TRUE == g_pHalMVOPCtx->bMirrorModeVer)
2574 {
2575 MS_U16 u16YstMir = 0;
2576 if((g_pHalMVOPCtx->u16CropYStart + u16YSizes) < u16Height)
2577 {
2578 u16YstMir = u16Height - g_pHalMVOPCtx->u16CropYStart - u16YSizes;
2579 HAL_MVOP_SetStartX(E_MVOP_DEV_0, u16YstMir);
2580 }
2581 else
2582 {
2583 MVOP_PRINTF("[Warning] crop y size or start out of boundary.");
2584 return;
2585 }
2586 }
2587 HAL_WriteByte(VOP_REG_CROP_VSIZE, (u16YSizes) & 0xff);
2588 HAL_WriteByte((VOP_REG_CROP_VSIZE + 1), ((u16YSizes) >> (8)) & (0x1f));
2589 if(0 == u16YSizes)
2590 {
2591 g_pHalMVOPCtx->u16CropYSize = 0;
2592 }
2593 else
2594 {
2595 g_pHalMVOPCtx->u16CropYSize += u16YSizes;
2596 }
2597 // Write trigger
2598 HAL_MVOP_LoadReg();
2599 break;
2600 case E_MVOP_DEV_1:
2601 #if MVOP_SUPPORT_SUB
2602 if(TRUE == g_pHalMVOPCtx->bSubMirrorModeVer)
2603 {
2604 MS_U16 u16YstMir = 0;
2605 if((g_pHalMVOPCtx->u16SubCropYStart + u16YSizes) < u16Height)
2606 {
2607 u16YstMir = u16Height - g_pHalMVOPCtx->u16SubCropYStart - u16YSizes;
2608 HAL_MVOP_SetStartX(E_MVOP_DEV_1, u16YstMir);
2609 }
2610 else
2611 {
2612 MVOP_PRINTF("[Warning] crop y size or start out of boundary.");
2613 return;
2614 }
2615 }
2616 HAL_WriteByte(SUB_REG(VOP_REG_CROP_VSIZE), (u16YSizes) & 0xff);
2617 HAL_WriteByte(SUB_REG((VOP_REG_CROP_VSIZE + 1)), ((u16YSizes) >> (8)) & (0x1f));
2618 if(0 == u16YSizes)
2619 {
2620 g_pHalMVOPCtx->u16SubCropYSize = 0;
2621 }
2622 else
2623 {
2624 g_pHalMVOPCtx->u16SubCropYSize += u16YSizes;
2625 }
2626 // Write trigger
2627 HAL_MVOP_SubLoadReg();
2628
2629 #endif
2630 break;
2631 default:
2632 break;
2633 }
2634 }
2635
2636
2637 /******************************************************************************/
2638 /// Set MVOP Saving BW Mode
2639 /// @ Napoli this command should be set after MDrv_MVOP_SetOutputCfg
2640 /******************************************************************************/
HAL_MVOP_Set420BWSaveMode(MS_BOOL bEnable)2641 MS_BOOL HAL_MVOP_Set420BWSaveMode(MS_BOOL bEnable)
2642 {
2643 MS_BOOL bValue = FALSE;
2644
2645 //hw limtation: 3DLA/3DSBS/422/p mode in, i mode out/i mode in, p mode out(only need to check in MCU mode)
2646 bValue = (g_pHalMVOPCtx->b3DLRAltSBSOutput || g_pHalMVOPCtx->b3DLRAltOutput /*|| g_pHalMVOPCtx->b3DLRMode */|| g_pHalMVOPCtx->bIs422 );
2647
2648 if(bValue)
2649 {
2650 MVOP_DBG(MVOP_PRINTF("%s Hit the limitation of saving bw, disable BW Saving mode\n", __FUNCTION__);)
2651 HAL_WriteRegBit(VOP_REG_DUMMY, 0, VOP_420_BW_SAVE);
2652 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
2653 HAL_MVOP_LoadReg();
2654 return FALSE;
2655 }
2656 else
2657 {
2658 HAL_WriteRegBit(VOP_REG_DUMMY, bEnable, VOP_420_BW_SAVE);
2659 if( g_pHalMVOPCtx->b3DLRMode == FALSE)
2660 HAL_WriteRegBit(VOP_REG_BW_SAVE, bEnable, VOP_420_BW_SAVE_EX);
2661 else
2662 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
2663 HAL_MVOP_LoadReg();
2664 return TRUE;
2665 }
2666 }
2667
HAL_MVOP_SetEVDYUVBaseAdd(MVOP_EVDBaseAddInput * stEVDBaseAddInfo)2668 MS_BOOL HAL_MVOP_SetEVDYUVBaseAdd(MVOP_EVDBaseAddInput *stEVDBaseAddInfo)
2669 {
2670 //----------------------------------------------------
2671 // Set MSB YUV Address
2672 //----------------------------------------------------
2673
2674 MS_PHY u64tmp = 0;
2675
2676 if (g_pHalMVOPCtx == NULL)
2677 {
2678 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2679 return FALSE;
2680 }
2681 // Y offset
2682 u64tmp = stEVDBaseAddInfo->u32MSBYOffset >> 3;
2683 if ( !stEVDBaseAddInfo->bProgressive)
2684 { //Refine Y offset for interlace repeat bottom field
2685 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
2686 {
2687 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2688 u64tmp += 2;
2689 }
2690 else
2691 {
2692 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2693 }
2694 }
2695 HAL_WriteByte(VOP_JPG_YSTR0_L, u64tmp & 0xff);
2696 HAL_WriteByte((VOP_JPG_YSTR0_L+1), (u64tmp >> 8) & 0xff);
2697 HAL_WriteByte((VOP_JPG_YSTR0_H), (u64tmp >> 16) & 0xff);
2698 HAL_WriteByte((VOP_JPG_YSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2699
2700 if (!stEVDBaseAddInfo->bProgressive )
2701 { //Y offset of bottom field if interlace
2702 HAL_WriteByte(VOP_JPG_YSTR1_L, u64tmp & 0xff);
2703 HAL_WriteByte((VOP_JPG_YSTR1_L+1), (u64tmp >> 8) & 0xff);
2704 HAL_WriteByte((VOP_JPG_YSTR1_H), (u64tmp >> 16) & 0xff);
2705 HAL_WriteByte((VOP_JPG_YSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2706 }
2707
2708 if (stEVDBaseAddInfo->b422Pack)
2709 {
2710 stEVDBaseAddInfo->u32MSBUVOffset = stEVDBaseAddInfo->u32MSBYOffset + 16; //add 16 for 128bit; add 8 for 64bit
2711 }
2712 // UV offset
2713 u64tmp = stEVDBaseAddInfo->u32MSBUVOffset >> 3;
2714 if( !stEVDBaseAddInfo->bProgressive )
2715 { //Refine UV offset for interlace repeat bottom field
2716 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
2717 {
2718 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2719 u64tmp += 2;
2720 }
2721 else
2722 {
2723 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2724 }
2725 }
2726 HAL_WriteByte(VOP_JPG_UVSTR0_L, u64tmp & 0xff);
2727 HAL_WriteByte((VOP_JPG_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
2728 HAL_WriteByte((VOP_JPG_UVSTR0_H), (u64tmp >> 16) & 0xff);
2729 HAL_WriteByte((VOP_JPG_UVSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2730
2731 if( !stEVDBaseAddInfo->bProgressive )
2732 { //UV offset of bottom field if interlace
2733 HAL_WriteByte(VOP_JPG_UVSTR1_L, u64tmp & 0xff);
2734 HAL_WriteByte((VOP_JPG_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
2735 HAL_WriteByte((VOP_JPG_UVSTR1_H), (u64tmp >> 16) & 0xff);
2736 HAL_WriteByte((VOP_JPG_UVSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2737 }
2738
2739 //----------------------------------------------------
2740 // Set MSB YUV Address
2741 //----------------------------------------------------
2742 if(stEVDBaseAddInfo->bEnLSB)
2743 {
2744 //Enable LSB
2745 HAL_WriteRegBit(VOP_EVD_10B_EN, 1, VOP_EVD_10B_Y_EN);
2746 HAL_WriteRegBit(VOP_EVD_10B_EN, 1, VOP_EVD_10B_UV_EN);
2747 HAL_WriteRegBit(VOP_REG_MASK, 0, VOP_LSB_REQ_MASK);
2748
2749 // Y offset
2750 u64tmp = stEVDBaseAddInfo->u32LSBYOffset >> 3;
2751 if ( !stEVDBaseAddInfo->bProgressive)
2752 { //Refine Y offset for interlace repeat bottom field
2753 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
2754 {
2755 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2756 u64tmp += 2;
2757 }
2758 else
2759 {
2760 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2761 }
2762 }
2763 HAL_WriteByte(VOP_LSB_YSTR0_L, u64tmp & 0xff);
2764 HAL_WriteByte((VOP_LSB_YSTR0_L+1), (u64tmp >> 8) & 0xff);
2765 HAL_WriteByte((VOP_LSB_YSTR0_L), (u64tmp >> 16) & 0xff);
2766 HAL_WriteByte((VOP_LSB_YSTR0_L+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2767
2768 if (!stEVDBaseAddInfo->bProgressive )
2769 { //Y offset of bottom field if interlace
2770 HAL_WriteByte(VOP_LSB_YSTR1_L, u64tmp & 0xff);
2771 HAL_WriteByte((VOP_LSB_YSTR1_L+1), (u64tmp >> 8) & 0xff);
2772 HAL_WriteByte((VOP_LSB_YSTR1_H), (u64tmp >> 16) & 0xff);
2773 HAL_WriteByte((VOP_LSB_YSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2774 }
2775
2776 if (stEVDBaseAddInfo->b422Pack)
2777 {
2778 stEVDBaseAddInfo->u32LSBUVOffset = stEVDBaseAddInfo->u32LSBYOffset + 16; //add 16 for 128bit; add 8 for 64bit
2779 }
2780 // UV offset
2781 u64tmp = stEVDBaseAddInfo->u32LSBUVOffset >> 3;
2782 if( !stEVDBaseAddInfo->bProgressive )
2783 { //Refine UV offset for interlace repeat bottom field
2784 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
2785 {
2786 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2787 u64tmp += 2;
2788 }
2789 else
2790 {
2791 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2792 }
2793 }
2794 HAL_WriteByte(VOP_LSB_UVSTR0_L, u64tmp & 0xff);
2795 HAL_WriteByte((VOP_LSB_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
2796 HAL_WriteByte((VOP_LSB_UVSTR0_H), (u64tmp >> 16) & 0xff);
2797 HAL_WriteByte((VOP_LSB_UVSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2798
2799 if( !stEVDBaseAddInfo->bProgressive )
2800 { //UV offset of bottom field if interlace
2801 HAL_WriteByte(VOP_LSB_UVSTR1_L, u64tmp & 0xff);
2802 HAL_WriteByte((VOP_LSB_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
2803 HAL_WriteByte((VOP_LSB_UVSTR1_H), (u64tmp >> 16) & 0xff);
2804 HAL_WriteByte((VOP_LSB_UVSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2805 }
2806 }
2807
2808 return TRUE;
2809 }
2810
2811 /******************************************************************************/
2812 /// Set MVOP repeat previous frame IF VDEC can not finish vsync.
2813 /// this command should be set disable as call VDEC Exit.
2814 /******************************************************************************/
HAL_MVOP_SetRptPreVsyncFrame(MVOP_DevID eID,MS_BOOL bEnable)2815 void HAL_MVOP_SetRptPreVsyncFrame(MVOP_DevID eID, MS_BOOL bEnable)
2816 {
2817 switch(eID)
2818 {
2819 case E_MVOP_DEV_0:
2820 {
2821 g_pHalMVOPCtx->bRptPreVsync = bEnable;
2822 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, BIT3);
2823 break;
2824 }
2825 case E_MVOP_DEV_1:
2826 {
2827 #if MVOP_SUPPORT_SUB
2828 g_pHalMVOPCtx->bSubRptPreVsync = bEnable;
2829 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, BIT3);
2830 #endif
2831 break;
2832 }
2833 default:
2834 MVOP_PRINTF("[Warning] MVOP_DevID not support!\n");
2835 break;
2836 }
2837 }
2838
HAL_MVOP_PowerStateSuspend(void)2839 void HAL_MVOP_PowerStateSuspend(void)
2840 {
2841 g_pHalMVOPCtx->bIsInit = 0;
2842 g_pHalMVOPCtx->bSubIsInit = 0;
2843 }
2844
HAL_MVOP_GetHandShakeMode(MVOP_DevID eID)2845 MVOP_HSMode HAL_MVOP_GetHandShakeMode(MVOP_DevID eID)
2846 {
2847 MVOP_HSMode eRet = E_MVOP_HS_NOT_SUPPORT;
2848 switch(eID)
2849 {
2850 case E_MVOP_DEV_0:
2851 eRet = E_MVOP_HS_NOT_SUPPORT;
2852 break;
2853 case E_MVOP_DEV_1:
2854 #if MVOP_SUPPORT_SUB
2855 eRet = E_MVOP_HS_NOT_SUPPORT;
2856 #endif
2857 break;
2858 default:
2859 eRet = E_MVOP_HS_INVALID_PARAM;
2860 break;
2861 }
2862 return eRet;
2863 }
2864
HAL_MVOP_CheckSTCCW(void)2865 MS_BOOL HAL_MVOP_CheckSTCCW(void)
2866 {
2867 MS_U16 u16STC_CW_L = 0;
2868 MS_U16 u16STC_CW_H = 0;
2869 MS_BOOL u16STC_CW_SEL = 0;
2870 MS_BOOL u16TSP_CLK_EN = 0;
2871
2872 u16STC_CW_L = HAL_Read2Byte(REG_STC0_CW_L)&0xffff;
2873 u16STC_CW_H = HAL_Read2Byte(REG_STC0_CW_H)&0xffff;
2874
2875 u16STC_CW_SEL = (HAL_ReadRegBit(REG_STC_CW_SLE_L, BIT1) == BIT1);
2876 u16TSP_CLK_EN = !(HAL_ReadRegBit(REG_TSP_CLK, BIT0) == BIT0);
2877
2878 if((((u16STC_CW_L || u16STC_CW_H) == 0) && (u16STC_CW_SEL == 0)) || ((u16STC_CW_SEL == 1) && (u16TSP_CLK_EN == 0)))
2879 return FALSE;
2880 else
2881 return TRUE;
2882
2883 }
2884
2885 #define MIU1_REG_BASE 0x0600
HAL_MVOP_GetIsMiuIPControl(HALMVOPMIUCLIENTINFO stInfo)2886 MS_BOOL HAL_MVOP_GetIsMiuIPControl(HALMVOPMIUCLIENTINFO stInfo)
2887 {
2888 MS_U32 u32RegMiu = 0;
2889 MS_U16 u16Mask = 0;
2890 MS_BOOL bRet = FALSE;
2891
2892 u32RegMiu = MIU1_REG_BASE + (0xF0+(stInfo.u8Gp * 2));
2893 if(stInfo.u8BitPos < 8)
2894 {
2895 u16Mask = 1<<stInfo.u8BitPos;
2896 }
2897 else
2898 {
2899 u16Mask = 1<<(stInfo.u8BitPos-8);
2900 u32RegMiu += 1;
2901 }
2902 MVOP_DBG(MVOP_PRINTF("[%s] u32RegMiu = 0x%lx, u16Mask = 0x%x\n",__FUNCTION__, u32RegMiu,u16Mask);)
2903 if(HAL_ReadRegBit(u32RegMiu, u16Mask))
2904 {
2905 bRet = TRUE;
2906 }
2907
2908 return bRet;
2909 }
2910
HAL_MVOP_SelMIU(MVOP_DevID eDevID,HALMVOPMIUSEL eMiuMSB0,HALMVOPMIUSEL eMiuMSB1,HALMVOPMIUSEL eMiuLSB0,HALMVOPMIUSEL eMiuLSB1)2911 void HAL_MVOP_SelMIU(MVOP_DevID eDevID, HALMVOPMIUSEL eMiuMSB0, HALMVOPMIUSEL eMiuMSB1, HALMVOPMIUSEL eMiuLSB0, HALMVOPMIUSEL eMiuLSB1)
2912 {
2913 MS_U8 u8MSBVlue = 0;
2914 MS_U8 u8LSBVlue = 0;
2915
2916 if(eMiuMSB0 != eMiuMSB1)
2917 HAL_WriteRegBit(VOP_MIU_SEL, TRUE, BIT0);
2918 else
2919 HAL_WriteRegBit(VOP_MIU_SEL, FALSE, BIT0);
2920
2921 if(eMiuLSB0 != eMiuLSB1)
2922 HAL_WriteRegBit(VOP_MIU_SEL, TRUE, BIT1);
2923 else
2924 HAL_WriteRegBit(VOP_MIU_SEL, FALSE, BIT1);
2925
2926 u8MSBVlue |= (eMiuMSB0 << 4);
2927 u8MSBVlue |= (eMiuMSB1 << 6);
2928
2929 u8LSBVlue |= (eMiuLSB0 << 4);
2930 u8LSBVlue |= (eMiuLSB1 << 6);
2931
2932 switch(eDevID)
2933 {
2934 case E_MVOP_DEV_0:
2935 {
2936 // MSB
2937 HAL_WriteByteMask(VOP_MIU_SEL, u8MSBVlue, VOP_MSB_BUF0_MIU_SEL | VOP_MSB_BUF1_MIU_SEL);
2938 // LSB
2939 HAL_WriteByteMask(VOP_MIU_SEL_LSB, u8LSBVlue, VOP_LSB_BUF0_MIU_SEL | VOP_LSB_BUF1_MIU_SEL);
2940 break;
2941 }
2942 #if MVOP_SUPPORT_SUB
2943 case E_MVOP_DEV_1:
2944 {
2945 // MSB
2946 HAL_WriteByteMask(SUB_REG(VOP_MIU_SEL), u8MSBVlue, VOP_MSB_BUF0_MIU_SEL | VOP_MSB_BUF1_MIU_SEL);
2947 // LSB
2948 HAL_WriteByteMask(SUB_REG(VOP_MIU_SEL_LSB), u8LSBVlue, VOP_LSB_BUF0_MIU_SEL | VOP_LSB_BUF1_MIU_SEL);
2949 break;
2950 }
2951 #endif
2952 default:
2953 break;
2954 }
2955 }
2956
HAL_MVOP_GetIsOnlyMiuIPControl(void)2957 MS_BOOL HAL_MVOP_GetIsOnlyMiuIPControl(void)
2958 {
2959 return TRUE;
2960 }
2961
HAL_MVOP_GetMaxFramerate(MVOP_DevID eDevID,MVOP_GetMaxFps * stStreamInfo)2962 void HAL_MVOP_GetMaxFramerate(MVOP_DevID eDevID, MVOP_GetMaxFps* stStreamInfo)
2963 {
2964 MS_U64 u64MaxClk = 0;
2965 MS_U16 u16HsizeTiming = 0;
2966 MS_U16 u16VsizeTiming = 0;
2967
2968 if(NULL == stStreamInfo)
2969 {
2970 MVOP_PRINTF("[%s] Input parameter is NULL!\n",__FUNCTION__);
2971 return;
2972 }
2973
2974 switch(eDevID)
2975 {
2976 case E_MVOP_DEV_0:
2977 #if MVOP_SUPPORT_SUB
2978 case E_MVOP_DEV_1:
2979 #endif
2980 {
2981 if(_HAL_MVOP_IsSupport4k2k2P())
2982 {
2983 u16HsizeTiming = stStreamInfo->u16HSize >> 1;
2984 }
2985 else
2986 {
2987 u16HsizeTiming = stStreamInfo->u16HSize;
2988 u16HsizeTiming = ALIGN_UPTO_2(u16HsizeTiming);
2989 }
2990 if(stStreamInfo->b3DSBS)
2991 {
2992 u16HsizeTiming *= 2;
2993 }
2994 if(stStreamInfo->u16HSize > 720)
2995 {
2996 u16HsizeTiming += MVOP_HBlank_HD;
2997 }
2998 else
2999 {
3000 u16HsizeTiming += MVOP_HBlank_SD;
3001 }
3002
3003 u64MaxClk = HAL_MVOP_GetMaximumClk();
3004 if(stStreamInfo->b3DTB)
3005 {
3006 u16VsizeTiming = stStreamInfo->u16VSize*2 + MVOP_VBlank;
3007 }
3008 else
3009 {
3010 u16VsizeTiming = stStreamInfo->u16VSize + MVOP_VBlank;
3011 }
3012 do_div(u64MaxClk, u16HsizeTiming);
3013 do_div(u64MaxClk, u16VsizeTiming);
3014 stStreamInfo->u32Framerate = (MS_U32)u64MaxClk * 1000;
3015 }
3016 break;
3017 default:
3018 break;
3019 }
3020
3021 }
3022
HAL_MVOP_ResetReg(MVOP_DevID eDevID,MS_U16 u16ECOVersion)3023 void HAL_MVOP_ResetReg(MVOP_DevID eDevID, MS_U16 u16ECOVersion)
3024 {
3025
3026 switch(eDevID)
3027 {
3028 case E_MVOP_DEV_0:
3029 {
3030 #if ENABLE_3D_LR_MODE
3031 HAL_MVOP_Enable3DLR(DISABLE);
3032 #endif
3033 #if SUPPORT_3DLR_ALT_SBS
3034 HAL_MVOP_Set3DLRAltOutput(DISABLE);
3035 HAL_MVOP_Set3DLRAltSBSOutput(DISABLE);
3036 #endif
3037
3038 /*****************************************************/
3039 // Reset MVOP setting
3040 HAL_WriteByte(VOP_TST_IMG, 0x40); //reset test pattern or BG
3041 HAL_MVOP_Set3DLRAltOutput_VHalfScaling(DISABLE); //reset to default: disable 3D L/R alternative output.
3042 HAL_MVOP_Set3DLR2ndCfg(DISABLE); //reset to default: disable 3D L/R 2nd pitch.
3043 HAL_MVOP_SetRgbFormat(E_MVOP_RGB_NONE); //reset rgb format
3044 HAL_WriteRegBit(VOP_CTRL1, 0, VOP_MVD_VS_MD); //default use original vsync
3045 // Only for Monaco: Enable deciding bot by top address + 2
3046 HAL_WriteRegBit(VOP_MIRROR_CFG, 1, VOP_FIELD_FROM_ADDR);
3047 // Reset Mono mode
3048 HAL_MVOP_SetMonoMode(FALSE);
3049
3050 //set MVOP test pattern to black
3051 HAL_MVOP_SetBlackBG();
3052
3053 // clear extend strip len bit by default
3054 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
3055
3056 // set mvop to 128bit_i128 interface
3057 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
3058
3059 // Disable H264 or RM Input
3060 HAL_WriteRegBit(VOP_INPUT_SWITCH1, 0, BIT2|BIT3);
3061 // Clear 422 Flag
3062 g_pHalMVOPCtx->bIs422 = 0;
3063 // Clear evd Flag for interlace mode setting
3064 g_pHalMVOPCtx->bIsH265 = 0;
3065 HAL_WriteRegBit(VOP_INT_TYPE, 0, VOP_EVD_INT_SEP);
3066 //8*32 tile format
3067 HAL_WriteRegBit(VOP_REG_WR, 0, BIT1);
3068 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD);
3069 HAL_MVOP_SetFieldInverse(ENABLE, ENABLE);
3070 // EVD mode disable
3071 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, EVD_ENABLE);
3072 // EVD 10 bits disable
3073 //HAL_WriteByteMask(VOP_REG_MASK, BIT1, VOP_LSB_REQ_MASK);
3074 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_Y_EN);
3075 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_UV_EN);
3076 // Enable 420 BW Saving mode
3077 HAL_MVOP_Set420BWSaveMode(TRUE);
3078 // Disable New Vsync Mode
3079 g_pHalMVOPCtx->bNewVSyncMode = FALSE;
3080 // VP9 MODE disable
3081 //HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, VOP_R2_WISHBONE);
3082 HAL_WriteRegBit(VOP_MPG_JPG_SWITCH, 0, VOP_DRAM_RD_MODE);
3083 // Disable 2p mode
3084 HAL_MVOP_SetEnable4k2k2P(FALSE);
3085 // Setting MF burst len
3086 HAL_WriteByteMask(VOP_REG_MFDEC_0_L, 0x70, VOP_MF1_BURST|VOP_MF0_BURST|VOP_MFDEC_EN);
3087 // Enable mfdec setting from wb
3088 HAL_WriteRegBit(VOP_REG_MFDEC_2_L, 1, VOP_MF_FROM_WB); //str huffman table issue
3089 // MIU select from WB
3090 HAL_WriteByteMask(VOP_INFO_FROM_CODEC_H, 0x30, VOP_INFO_FROM_CODEC_MIU_BUF0_SEL|VOP_INFO_FROM_CODEC_MIU_BUF1_SEL);
3091 HAL_WriteRegBit(VOP_UV_SHIFT, 0, VOP_GCLK_MIU_ON);// yc seperate can not enable(1: saving power)
3092 // All codec use WISHBONE(R2) interface in manhathan
3093 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 1, VOP_R2_WISHBONE);
3094 // MUJI default not support 10 bits display
3095 // Disable 10 bits from codec
3096 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_H, 0, VOP_INFO_FROM_CODEC_10BIT);
3097 HAL_MVOP_SetHandShakeMode(E_MVOP_DEV_0, DISABLE, 25);
3098 HAL_MVOP_SetStartX(E_MVOP_DEV_0, 0);
3099 HAL_MVOP_SetStartY(E_MVOP_DEV_0, 0, 0);
3100 HAL_MVOP_SetPicWidthMinus(E_MVOP_DEV_0, 0, 0);
3101 HAL_MVOP_SetPicHeightMinus(E_MVOP_DEV_0, 0, 0);
3102 HAL_WriteRegBit(VOP_REG_MRQ, 1, VOP_MRQ_EN); //Manhathan only: merge mvop0/1 miu client
3103 HAL_SetSCFEMIUIPSel(NULL);
3104 g_pHalMVOPCtx->eRepeatField = E_MVOP_RPTFLD_NONE;
3105 HAL_WriteRegBit(VOP_REG_DUMMY, 0, VOP_32x32_WB);
3106 #ifdef UFO_MVOP_DOLBY_HDR
3107 HAL_MVOP_Enable2DCTimingSync(DISABLE);
3108 HAL_MVOP_EnableHDRSetting(DISABLE);
3109 #endif
3110 #if 0
3111 if(u16ECOVersion >= 1) //monet u02 support mvop lsb bw control by wb
3112 {
3113 HAL_WriteByteMask(VOP_REG_MASK, 0x0, VOP_LSB_REQ_MASK);
3114 HAL_WriteRegBit(VOP_UV_SHIFT, 0, VOP_GCLK_MIU_ON);
3115 }
3116 #endif
3117 g_pHalMVOPCtx->eInterlaceType = E_MVOP_PRO;
3118 //Disable DV vision
3119 g_pHalMVOPCtx->bIs265DV = 0;
3120 HAL_WriteRegBit(VOP_REG_4K2K_2P, 0, VOP_TRIG_REFER_VB_END);
3121 //set for ddr4: 1014_16 = 0x000a
3122 HAL_WriteByte(VOP_LSB_DMA0, 0x0A);
3123 HAL_WriteByte(VOP_LSB_DMA1, 0x00);
3124 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, VOP_TILE_32x32);
3125 HAL_MVOP_LoadReg();
3126 /*****************************************************/
3127 break;
3128 }
3129 #if MVOP_SUPPORT_SUB
3130 case E_MVOP_DEV_1:
3131 {
3132 #if ENABLE_3D_LR_MODE
3133 HAL_MVOP_SubEnable3DLR(DISABLE);
3134 #endif
3135 #if SUPPORT_3DLR_ALT_SBS
3136 HAL_MVOP_SubSet3DLRAltOutput(DISABLE);
3137 HAL_MVOP_SubSet3DLRAltSBSOutput(DISABLE);
3138 #endif
3139 HAL_MVOP_SubEnableMVDInterface(FALSE);
3140
3141 /*****************************************************/
3142 // Reset MVOP setting
3143 HAL_WriteByte(SUB_REG(VOP_TST_IMG), 0x40);
3144 HAL_MVOP_SubSetRgbFormat(E_MVOP_RGB_NONE);
3145 HAL_WriteRegBit(SUB_REG(VOP_CTRL1), 0, VOP_MVD_VS_MD); //default use original vsync
3146 // Only for Monaco: Enable deciding bot by top address + 2
3147 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), 1, VOP_FIELD_FROM_ADDR);
3148 // Reset Mono mode
3149 HAL_MVOP_SubSetMonoMode(FALSE);
3150
3151 //set MVOP test pattern to black
3152 HAL_MVOP_SubSetBlackBG();
3153
3154 // clear extend strip len bit by default
3155 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
3156
3157 // set mvop to 128bit_i128 interface
3158 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
3159
3160 // Disable H264 or RM Input
3161 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH1), 0, BIT2|BIT3);
3162 // Clear 422 Flag
3163 g_pHalMVOPCtx->bSubIs422 = 0;
3164 // Clear evd Flag for interlace mode setting
3165 g_pHalMVOPCtx->bSubIsH265 = 0;
3166 HAL_WriteRegBit(SUB_REG(VOP_INT_TYPE), 0, VOP_EVD_INT_SEP);
3167 //8*32 tile format
3168 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT1);
3169 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD);
3170 HAL_MVOP_SubSetFieldInverse(ENABLE, ENABLE);
3171 // EVD mode disable
3172 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, EVD_ENABLE);
3173 // EVD 10 bits
3174 //HAL_WriteByteMask(SUB_REG(VOP_REG_MASK), BIT1, VOP_LSB_REQ_MASK);
3175 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 0, VOP_EVD_10B_Y_EN);
3176 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 0, VOP_EVD_10B_UV_EN);
3177 // Enable 420 BW Saving mode
3178 HAL_MVOP_SubSet420BWSaveMode(TRUE, u16ECOVersion);
3179 // VP9 MODE disable
3180 //HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, VOP_R2_WISHBONE);
3181 HAL_WriteRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), 0, VOP_DRAM_RD_MODE);
3182 // Disable 2p mode
3183 HAL_MVOP_SubSetEnable4k2k2P(FALSE);
3184 // Disable New Vsync Mode
3185 g_pHalMVOPCtx->bSubNewVSyncMode = FALSE;
3186 // Sub mvop ds idx from DIU
3187 HAL_WriteRegBit(SUB_REG(VOP_INFO_FROM_CODEC_H), 1, VOP_INFO_FROM_CODEC_DS_IDX);
3188 // Setting MF burst len
3189 HAL_WriteByteMask(SUB_REG(VOP_REG_MFDEC_0_L), 0x70, VOP_MF1_BURST|VOP_MF0_BURST|VOP_MFDEC_EN);
3190 // Enable mfdec setting from wb
3191 HAL_WriteRegBit(SUB_REG(VOP_REG_MFDEC_2_L), 1, VOP_MF_FROM_WB);
3192 // MIU select from WB
3193 HAL_WriteByteMask(SUB_REG(VOP_INFO_FROM_CODEC_H), 0x30, VOP_INFO_FROM_CODEC_MIU_BUF0_SEL|VOP_INFO_FROM_CODEC_MIU_BUF1_SEL);
3194 HAL_WriteRegBit(SUB_REG(VOP_UV_SHIFT), 0, VOP_GCLK_MIU_ON);// yc seperate can not enable(1: saving power)
3195 // All codec use WISHBONE(R2) interface in manhathan
3196 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 1, VOP_R2_WISHBONE);
3197 // MUJI default not support 10 bits display
3198 // Disable 10 bits from codec
3199 HAL_WriteRegBit(SUB_REG(VOP_INFO_FROM_CODEC_H), 0, VOP_INFO_FROM_CODEC_10BIT);
3200 HAL_MVOP_SetHandShakeMode(E_MVOP_DEV_1, DISABLE, 25);
3201 HAL_MVOP_SetStartX(E_MVOP_DEV_1, 0);
3202 HAL_MVOP_SetStartY(E_MVOP_DEV_1, 0, 0);
3203 HAL_MVOP_SetPicWidthMinus(E_MVOP_DEV_1, 0, 0);
3204 HAL_MVOP_SetPicHeightMinus(E_MVOP_DEV_1, 0, 0);
3205 HAL_WriteRegBit(SUB_REG(VOP_REG_MRQ), 1, VOP_MRQ_EN); //Manhathan only: merge mvop0/1 miu client
3206 HAL_SetSCFEMIUIPSel(NULL);
3207 #ifdef UFO_MVOP_DOLBY_HDR
3208 HAL_MVOP_Enable2DCTimingSync(DISABLE);
3209 HAL_MVOP_SubEnableHDRSetting(DISABLE);
3210 #endif
3211 g_pHalMVOPCtx->eSubRepeatField = E_MVOP_RPTFLD_NONE;
3212 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 0, VOP_32x32_WB);
3213 #if 0
3214 if(u16ECOVersion >= 1) //monet u02 support mvop lsb bw control by wb
3215 {
3216 HAL_WriteByteMask(SUB_REG(VOP_REG_MASK), 0x0, VOP_LSB_REQ_MASK);
3217 HAL_WriteRegBit(SUB_REG(VOP_UV_SHIFT), 0, VOP_GCLK_MIU_ON);
3218 }
3219 #endif
3220 g_pHalMVOPCtx->eSubInterlaceType = E_MVOP_PRO;
3221 //set for ddr4: 1014_16 = 0x000a
3222 HAL_WriteByte(SUB_REG(VOP_LSB_DMA0), 0x0A);
3223 HAL_WriteByte(SUB_REG(VOP_LSB_DMA1), 0x00);
3224 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, VOP_TILE_32x32);
3225 HAL_MVOP_SubLoadReg();
3226 /*****************************************************/
3227 break;
3228 }
3229 #endif
3230 default:
3231 MVOP_PRINTF("[%s] Input Device ID is Error!\n",__FUNCTION__);
3232 break;
3233 }
3234 }
3235
3236 /******************************************************************************/
3237 /// Set MVOP Handshake Mode, XC should be synchronous with MVOP.
3238 /// this command should be before mvop enable.(before 1st frame)
3239 /******************************************************************************/
HAL_MVOP_SetHandShakeMode(MVOP_DevID eID,MS_BOOL bEnable,MS_U8 u8Framerate)3240 void HAL_MVOP_SetHandShakeMode(MVOP_DevID eID, MS_BOOL bEnable, MS_U8 u8Framerate)
3241 {
3242 #if 0 //remove patch
3243 MS_U8 u8FrmDur = 40;
3244 MS_BOOL bMCU = FALSE;
3245
3246 if(u8Framerate != 0)
3247 {
3248 u8FrmDur = 1000/u8Framerate; //time of one frame(ms).
3249 }
3250 #endif
3251 switch(eID)
3252 {
3253 case E_MVOP_DEV_0:
3254 {
3255 if(!((bEnable == FALSE) && (g_pHalMVOPCtx->bIsHS == FALSE)) && !(g_pHalMVOPCtx->bIs265DV)) //prevent switch VOP_CTRL0 (mvop enable), for MHEG5 verify
3256 {
3257 #if 0 //remove patch
3258 bMCU = HAL_ReadRegBit(VOP_MPG_JPG_SWITCH, BIT1);
3259 #endif
3260 HAL_WriteRegBit(VOP_CTRL0, 0, BIT0);
3261 g_pHalMVOPCtx->bIsHS = bEnable;
3262 HAL_WriteRegBit(VOP_REG_HS_OUTPUT, bEnable, VOP_HS_MODE);
3263 #if 0 // maserati default mvop timing gen
3264 HAL_WriteRegBit(VOP_REG_HS_OUTPUT, bEnable, BIT2);//reg_vsync_from_sc
3265 HAL_WriteRegBit(VOP_REG_HS_OUTPUT, bEnable, BIT1);//reg_vsync_from_sc
3266 HAL_WriteRegBit(VOP_CTRL0, bEnable, BIT4);
3267 #endif
3268 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background
3269 HAL_WriteRegBit(VOP_REG_4K2K_2P, bEnable, VOP_TRIG_REFER_VB_END);
3270
3271 if(!g_pHalMVOPCtx->bIs2p)
3272 HAL_MVOP_SetEnable4k2k2P(bEnable);
3273 HAL_WriteRegBit(VOP_CTRL0, 1, BIT0);
3274 #if 0 //remove patch
3275 // sw patch: for mvop hsk mode, switching mvop enable/disable may cause video was stuck.
3276 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] HAL_MVOP_Enable patch \n");)
3277 HAL_MVOP_SetBlackBG();
3278 HAL_MVOP_SetPattern(MVOP_PATTERN_FRAMECOLOR);
3279 HAL_WriteRegBit(VOP_REG_WR, 1, BIT4);
3280 HAL_WriteRegBit(VOP_MPG_JPG_SWITCH, 1, BIT1);
3281 MsOS_DelayTask(u8FrmDur);
3282 if(bMCU == FALSE)
3283 {
3284 HAL_WriteRegBit(VOP_MPG_JPG_SWITCH, 0, BIT1);
3285 }
3286 HAL_MVOP_SetPattern(MVOP_PATTERN_NORMAL);
3287 HAL_WriteRegBit(VOP_REG_WR, 0, BIT4);
3288 #endif
3289 HAL_MVOP_LoadReg();
3290 }
3291 break;
3292 }
3293 case E_MVOP_DEV_1:
3294 {
3295 #if MVOP_SUPPORT_SUB
3296 if(!((bEnable == FALSE) && (g_pHalMVOPCtx->bSubIsHS == FALSE)) && !(g_pHalMVOPCtx->bIs265DV)) //prevent switch VOP_CTRL0 (mvop enable), for MHEG5 verify
3297 {
3298 #if 0 //remove patch
3299 bMCU = HAL_ReadRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), BIT1);
3300 #endif
3301 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 0, BIT0);
3302 g_pHalMVOPCtx->bSubIsHS = bEnable;
3303 HAL_WriteRegBit(SUB_REG(VOP_REG_HS_OUTPUT), bEnable, VOP_HS_MODE);
3304 #if 0 // maserati default mvop timing gen
3305 HAL_WriteRegBit(SUB_REG(VOP_REG_HS_OUTPUT), bEnable, BIT2);//reg_vsync_from_sc
3306 HAL_WriteRegBit(SUB_REG(VOP_REG_HS_OUTPUT), bEnable, BIT1);//reg_vsync_from_sc
3307 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), bEnable, BIT4);
3308 #endif
3309 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, VOP_HK_MASK); //bk background
3310 HAL_WriteRegBit(SUB_REG(VOP_REG_4K2K_2P), bEnable, VOP_TRIG_REFER_VB_END);
3311 if(!g_pHalMVOPCtx->bSubIs2p)
3312 HAL_MVOP_SubSetEnable4k2k2P(bEnable);
3313 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 1, BIT0);
3314 #if 0 //remove patch
3315 // sw patch: for mvop hsk mode, switching mvop enable/disable may cause video was stuck.
3316 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] HAL_MVOP_Enable patch \n");)
3317 HAL_MVOP_SubSetBlackBG();
3318 HAL_MVOP_SubSetPattern(MVOP_PATTERN_FRAMECOLOR);
3319 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT4);
3320 HAL_WriteRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), 1, BIT1);
3321 MsOS_DelayTask(u8FrmDur);
3322 if(bMCU == FALSE)
3323 {
3324 HAL_WriteRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), 0, BIT1);
3325 }
3326 HAL_MVOP_SubSetPattern(MVOP_PATTERN_NORMAL);
3327 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT4);
3328 #endif
3329 HAL_MVOP_SubLoadReg();
3330 }
3331 #endif
3332 break;
3333 }
3334 default:
3335 MVOP_PRINTF("[Warning] MVOP_DevID not support!\n");
3336 break;
3337 }
3338 }
3339
HAL_MVOP_SetCropforXC(MVOP_DevID eID,MVOP_XCGetCrop * stXCCrop,MS_U16 u16Width,MS_U16 u16Height)3340 void HAL_MVOP_SetCropforXC(MVOP_DevID eID, MVOP_XCGetCrop* stXCCrop, MS_U16 u16Width, MS_U16 u16Height)
3341 {
3342 MVOP_DBG(MVOP_PRINTF("%s [crop info] xst: 0x%x yst: 0x%x xsize: 0x%x ysize: 0x%x Width: 0x%x Height: 0x%x\n", __FUNCTION__,
3343 stXCCrop->u16XStart, stXCCrop->>u16YStart, stXCCrop->>u16XSize, stXCCrop->u16YSize, u16Width, u16Height);)
3344
3345 switch(eID)
3346 {
3347 case E_MVOP_DEV_0:
3348 {
3349 if(g_pHalMVOPCtx->u16CropXSize == 0)
3350 g_pHalMVOPCtx->u16CropXSize = u16Width;
3351
3352 if((stXCCrop->u16XStart + stXCCrop->u16XSize) > u16Width)
3353 {
3354 MVOP_PRINTF("[Warning] crop x size or start out of boundary.");
3355 return;
3356 }
3357
3358 if(g_pHalMVOPCtx->u16CropYSize == 0)
3359 g_pHalMVOPCtx->u16CropYSize = u16Height;
3360
3361 if((stXCCrop->u16YStart + stXCCrop->u16YSize) > u16Height)
3362 {
3363 MVOP_PRINTF("[Warning] crop y size or start out of boundary.");
3364 return;
3365 }
3366
3367 stXCCrop->u16XStart = ALIGN_UPTO_2(stXCCrop->u16XStart);
3368 stXCCrop->u16XSize = ALIGN_UPTO_2(stXCCrop->u16XSize);
3369 g_pHalMVOPCtx->u16CropXStart = stXCCrop->u16XStart;
3370 g_pHalMVOPCtx->u16CropXSize = stXCCrop->u16XSize;
3371
3372 #if 0 //sw patch, for monet/manhattan: maserati fix
3373 if((stXCCrop->u16YSize <= 512) && (stXCCrop->u16YStart == 0) && (g_pHalMVOPCtx->bMirrorModeVer == TRUE))
3374 {
3375 MVOP_PRINTF("[MVOP][Dbg] crop + mirror patch\n");
3376 stXCCrop->u16YStart = 1;
3377 stXCCrop->u16YStart = stXCCrop->u16YStart | 0x2000;
3378
3379 g_pHalMVOPCtx->u16CropYSize = stXCCrop->u16YSize;
3380 if(g_pHalMVOPCtx->bIsH265 == FALSE)
3381 {
3382 stXCCrop->u16YSize -= 1;
3383 }
3384 }
3385 else
3386 #endif
3387 g_pHalMVOPCtx->u16CropYStart = stXCCrop->u16YStart;
3388 //from maserati
3389 if(g_pHalMVOPCtx->bMirrorModeVer == TRUE)
3390 {
3391 stXCCrop->u16YStart |= 0x2000;
3392 }
3393 if(stXCCrop->u16YStart == 0)
3394 {
3395 stXCCrop->u16YStart |= 0x4000;
3396 }
3397 g_pHalMVOPCtx->u16CropYSize = stXCCrop->u16YSize;
3398
3399 break;
3400 }
3401 case E_MVOP_DEV_1:
3402 {
3403 #if MVOP_SUPPORT_SUB
3404 if(g_pHalMVOPCtx->u16SubCropXSize == 0)
3405 g_pHalMVOPCtx->u16SubCropXSize = u16Width;
3406
3407 if((stXCCrop->u16XStart + stXCCrop->u16XSize) > u16Width)
3408 {
3409 MVOP_PRINTF("[Warning] crop x size or start out of boundary.");
3410 return;
3411 }
3412
3413 if(g_pHalMVOPCtx->u16SubCropYSize == 0)
3414 g_pHalMVOPCtx->u16SubCropYSize = u16Height;
3415
3416 if((stXCCrop->u16YStart + stXCCrop->u16YSize) > u16Height)
3417 {
3418 MVOP_PRINTF("[Warning] crop y size or start out of boundary.");
3419 return;
3420 }
3421
3422 stXCCrop->u16XStart = ALIGN_UPTO_2(stXCCrop->u16XStart);
3423 stXCCrop->u16XSize = ALIGN_UPTO_2(stXCCrop->u16XSize);
3424 g_pHalMVOPCtx->u16SubCropXStart = stXCCrop->u16XStart;
3425 g_pHalMVOPCtx->u16SubCropXSize = stXCCrop->u16XSize;
3426
3427 #if 0 //sw patch, for monet/manhattan: maserati fix
3428 if((stXCCrop->u16YSize <= 512) && (stXCCrop->u16YStart == 0) && (g_pHalMVOPCtx->bSubMirrorModeVer == TRUE))
3429 {
3430 MVOP_PRINTF("[MVOP][Dbg] crop + mirror patch\n");
3431 stXCCrop->u16YStart = 1;
3432 stXCCrop->u16YStart = stXCCrop->u16YStart | 0x2000;
3433
3434 g_pHalMVOPCtx->u16SubCropYSize = stXCCrop->u16YSize;
3435 if(g_pHalMVOPCtx->bSubIsH265 == FALSE)
3436 {
3437 stXCCrop->u16YSize -= 1;
3438 }
3439 }
3440 else
3441 #endif
3442 g_pHalMVOPCtx->u16SubCropYStart = stXCCrop->u16YStart;
3443 //from maserati
3444 if(g_pHalMVOPCtx->bSubMirrorModeVer == TRUE)
3445 {
3446 stXCCrop->u16YStart |= 0x2000;
3447 }
3448 if(stXCCrop->u16YStart == 0)
3449 {
3450 stXCCrop->u16YStart |= 0x4000;
3451 }
3452 g_pHalMVOPCtx->u16SubCropYSize = stXCCrop->u16YSize;
3453
3454 #endif
3455 break;
3456 }
3457 default:
3458 MVOP_PRINTF("[Warning] MVOP_DevID not support!\n");
3459 break;
3460 }
3461 MVOP_DBG(MVOP_PRINTF("[Debug][Crop to XC] xsize = %d, ysize = %d, xstart = %d, ystart=%d\n",stXCCrop->u16XSize,stXCCrop->u16YSize,stXCCrop->u16XStart,stXCCrop->u16YStart);)
3462 return;
3463 }
3464
3465
HAL_MVOP_SupportFRCOutputFPS(MVOP_DevID eID)3466 MS_BOOL HAL_MVOP_SupportFRCOutputFPS(MVOP_DevID eID)
3467 {
3468 MS_BOOL bRet = FALSE;
3469 switch(eID)
3470 {
3471 case E_MVOP_DEV_0:
3472 bRet = TRUE;
3473 break;
3474 #if MVOP_SUPPORT_SUB
3475 case E_MVOP_DEV_1:
3476 bRet = TRUE;
3477 break;
3478 #endif
3479 default:
3480 break;
3481 }
3482 return bRet;
3483 }
3484
HAL_MVOP_GetIsCurrentHSK(MVOP_DevID eID)3485 MS_BOOL HAL_MVOP_GetIsCurrentHSK(MVOP_DevID eID)
3486 {
3487 MS_BOOL bRet = FALSE;
3488 switch(eID)
3489 {
3490 case E_MVOP_DEV_0:
3491 bRet = g_pHalMVOPCtx->bIsHS;
3492 break;
3493 case E_MVOP_DEV_1:
3494 #if MVOP_SUPPORT_SUB
3495 bRet = g_pHalMVOPCtx->bSubIsHS;
3496 #endif
3497 break;
3498 default:
3499 bRet = E_MVOP_HS_INVALID_PARAM;
3500 break;
3501 }
3502 return bRet;
3503 }
3504
HAL_SetSCFEMIUIPSel(MVOP_SCIPSel * stIPSel)3505 void HAL_SetSCFEMIUIPSel(MVOP_SCIPSel *stIPSel)
3506 {
3507 if(NULL == stIPSel)
3508 {
3509 HAL_WriteRegBit(REG_MIU_SEL_FROM_IP, 1, MVOP_MIU_IP_SEL); //mvop
3510 HAL_WriteRegBit(REG_MIU_SEL_FROM_IP, 1, MFDEC0_MIU_IP_SEL); //mfdec0
3511 HAL_WriteRegBit(REG_MIU_SEL_FROM_IP, 1, MFDEC1_MIU_IP_SEL); //mfdec1
3512 }
3513 else
3514 {
3515 HAL_WriteRegBit(REG_MIU_SEL_FROM_IP, stIPSel->bMVOP0, MVOP_MIU_IP_SEL); //mvop
3516 HAL_WriteRegBit(REG_MIU_SEL_FROM_IP, stIPSel->bMFDEC0, MFDEC0_MIU_IP_SEL); //mfdec0
3517 HAL_WriteRegBit(REG_MIU_SEL_FROM_IP, stIPSel->bMFDEC1, MFDEC1_MIU_IP_SEL); //mfdec1
3518 }
3519
3520 }
3521
3522 #ifdef UFO_MVOP_RESET_SETTING
HAL_MVOP_ResetMVOPSetting(MVOP_DevID eDevID)3523 void HAL_MVOP_ResetMVOPSetting(MVOP_DevID eDevID)
3524 {
3525
3526 switch(eDevID)
3527 {
3528 case E_MVOP_DEV_0:
3529 HAL_WriteRegBit(VOP_REG_MFDEC_2_L, 0, VOP_MF_FROM_WB);
3530 break;
3531 #if MVOP_SUPPORT_SUB
3532 case E_MVOP_DEV_1:
3533 HAL_WriteRegBit(SUB_REG(VOP_REG_MFDEC_2_L), 0, VOP_MF_FROM_WB);
3534 break;
3535 #endif
3536 default:
3537 break;
3538 }
3539 return;
3540 }
3541 #endif
3542
HAL_MVOP_ReadBank(MVOP_DevID eID,MS_U16 u16Length)3543 MS_U16 HAL_MVOP_ReadBank(MVOP_DevID eID ,MS_U16 u16Length)
3544 {
3545 MS_U16 u16Reg = 0;
3546 if(eID == E_MVOP_DEV_0)
3547 {
3548 u16Reg = HAL_Read2Byte(MVOP_REG_BASE + (u16Length << 1));
3549 }
3550 #ifdef MVOP_SUPPORT_SUB
3551 else if(eID == E_MVOP_DEV_1)
3552 {
3553 u16Reg = HAL_Read2Byte(SUB_REG(MVOP_REG_BASE + (u16Length << 1)));
3554 }
3555 #endif
3556 return u16Reg;
3557 }
3558
HAL_MVOP_WriteBank(MVOP_DevID eID,MS_U16 u16Length,MS_U16 u16Data)3559 void HAL_MVOP_WriteBank(MVOP_DevID eID ,MS_U16 u16Length,MS_U16 u16Data)
3560 {
3561 if(eID == E_MVOP_DEV_0)
3562 {
3563 HAL_Write2Byte(MVOP_REG_BASE + (u16Length << 1),u16Data);
3564 }
3565 #ifdef MVOP_SUPPORT_SUB
3566 else if(eID == E_MVOP_DEV_1)
3567 {
3568 HAL_Write2Byte(SUB_REG(MVOP_REG_BASE + (u16Length << 1)),u16Data);
3569 }
3570 #endif
3571 }
3572
HAL_MVOP_ReadClkBank(MS_U16 u16Length)3573 MS_U16 HAL_MVOP_ReadClkBank(MS_U16 u16Length)
3574 {
3575 MS_U16 u16Reg = 0;
3576
3577 if(u16Length < 3) // stc cw
3578 {
3579 u16Reg = HAL_Read2Byte(REG_STC_CW_SLE_L + (u16Length << 1));
3580
3581 }
3582 else if(u16Length < 7) // dc clk
3583 {
3584 u16Length -= 3;
3585 u16Reg = HAL_Read2Byte(REG_CKG_DC0 + (u16Length << 1)); // main/sub sram
3586 }
3587 else // freerun/sync clk
3588 {
3589 u16Length -= 7;
3590 u16Reg = HAL_Read2Byte(REG_UPDATE_DC0_CW + (u16Length << 1));
3591 }
3592
3593 //printk("[read][%x] u16Reg = 0x%x\n",u16Length,u16Reg);
3594 return u16Reg;
3595 }
3596
HAL_MVOP_WriteClkBank(MS_U16 u16Length,MS_U16 u16Data)3597 void HAL_MVOP_WriteClkBank(MS_U16 u16Length,MS_U16 u16Data)
3598 {
3599
3600 //printk("[write][%x] u16Reg = 0x%x\n",u16Length,u16Data);
3601
3602 if(u16Length < 3) // stc cw
3603 {
3604 HAL_Write2Byte(REG_STC_CW_SLE_L + (u16Length << 1), u16Data);
3605 }
3606 else if(u16Length < 7) // dc clk
3607 {
3608 u16Length -= 3;
3609 HAL_Write2Byte(REG_CKG_DC0 + (u16Length << 1), u16Data);
3610 }
3611 else // freerun/sync clk
3612 {
3613 u16Length -= 7;
3614 HAL_Write2Byte(REG_UPDATE_DC0_CW + (u16Length << 1), u16Data);
3615 }
3616 HAL_WriteRegBit(REG_UPDATE_DC0_CW, TRUE, UPDATE_DC0_SYNC_CW);
3617 HAL_WriteRegBit(REG_UPDATE_DC0_CW, FALSE, UPDATE_DC0_SYNC_CW);
3618
3619 }
3620
HAL_MVOP_SetInterlaceType(MVOP_DevID eDevID,MS_U16 u16ECONumber,MS_U8 u8Interlace)3621 void HAL_MVOP_SetInterlaceType(MVOP_DevID eDevID, MS_U16 u16ECONumber, MS_U8 u8Interlace)
3622 {
3623 MVOP_DBG(MVOP_PRINTF("%s u8Interlace = %d\n", __FUNCTION__ ,u8Interlace);)
3624
3625 switch(eDevID)
3626 {
3627 case E_MVOP_DEV_0:
3628
3629 switch(u8Interlace)
3630 {
3631 case 0:
3632 g_pHalMVOPCtx->eInterlaceType = E_MVOP_PRO;
3633 break;
3634 case 0x1:
3635 if(g_pHalMVOPCtx->bIsH265)
3636 {
3637 g_pHalMVOPCtx->eInterlaceType = E_MVOP_INT_TB_SEP_FRAME;
3638 }
3639 else
3640 {
3641 g_pHalMVOPCtx->eInterlaceType = E_MVOP_INT_TB_ONE_FRAME;
3642 }
3643 break;
3644 case 0x2:
3645 if(g_pHalMVOPCtx->bIsH265)
3646 {
3647 g_pHalMVOPCtx->eInterlaceType = E_MVOP_INT_TB_ONE_FRAME;
3648 }
3649 else
3650 {
3651 g_pHalMVOPCtx->eInterlaceType = E_MVOP_INT_TB_SEP_FRAME;
3652 }
3653 break;
3654 default:
3655 g_pHalMVOPCtx->eInterlaceType = E_MVOP_PRO;
3656 break;
3657 }
3658
3659 if((g_pHalMVOPCtx->eInterlaceType == E_MVOP_INT_TB_SEP_FRAME) && (g_pHalMVOPCtx->bIsH265))
3660 {
3661 HAL_WriteRegBit(VOP_INT_TYPE, 1, VOP_EVD_INT_SEP);
3662 }
3663 else if((g_pHalMVOPCtx->eInterlaceType == E_MVOP_INT_TB_ONE_FRAME) && (g_pHalMVOPCtx->bIsH265))
3664 {
3665 HAL_WriteRegBit(VOP_INT_TYPE, 0, VOP_EVD_INT_SEP);
3666 HAL_WriteRegBit(VOP_MIRROR_CFG, 0, VOP_FIELD_FROM_ADDR);
3667 }
3668 HAL_MVOP_LoadReg();
3669 break;
3670 #if MVOP_SUPPORT_SUB
3671 case E_MVOP_DEV_1:
3672
3673 switch(u8Interlace)
3674 {
3675 case 0:
3676 g_pHalMVOPCtx->eSubInterlaceType = E_MVOP_PRO;
3677 break;
3678 case 0x1:
3679 if(g_pHalMVOPCtx->bSubIsH265)
3680 {
3681 g_pHalMVOPCtx->eSubInterlaceType = E_MVOP_INT_TB_SEP_FRAME;
3682 }
3683 else
3684 {
3685 g_pHalMVOPCtx->eSubInterlaceType = E_MVOP_INT_TB_ONE_FRAME;
3686 }
3687 break;
3688 case 0x2:
3689 if(g_pHalMVOPCtx->bSubIsH265)
3690 {
3691 g_pHalMVOPCtx->eSubInterlaceType = E_MVOP_INT_TB_ONE_FRAME;
3692 }
3693 else
3694 {
3695 g_pHalMVOPCtx->eSubInterlaceType = E_MVOP_INT_TB_SEP_FRAME;
3696 }
3697 break;
3698 default:
3699 g_pHalMVOPCtx->eSubInterlaceType = E_MVOP_PRO;
3700 break;
3701 }
3702
3703 if((g_pHalMVOPCtx->eSubInterlaceType == E_MVOP_INT_TB_SEP_FRAME) && (g_pHalMVOPCtx->bSubIsH265))
3704 {
3705 HAL_WriteRegBit(SUB_REG(VOP_INT_TYPE), 1, VOP_EVD_INT_SEP);
3706 }
3707 else if((g_pHalMVOPCtx->eSubInterlaceType == E_MVOP_INT_TB_ONE_FRAME) && (g_pHalMVOPCtx->bSubIsH265))
3708 {
3709 HAL_WriteRegBit(SUB_REG(VOP_INT_TYPE), 0, VOP_EVD_INT_SEP);
3710 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), 0, VOP_FIELD_FROM_ADDR);
3711 }
3712 HAL_MVOP_SubLoadReg();
3713 break;
3714 #endif
3715 default:
3716 MVOP_PRINTF("[Warning][%s] MVOP_DevID not support\n",__FUNCTION__);
3717 break;
3718 }
3719 }
3720
3721 #ifdef UFO_MVOP_DOLBY_HDR
HAL_MVOP_Enable2DCTimingSync(MS_BOOL bEnable)3722 void HAL_MVOP_Enable2DCTimingSync(MS_BOOL bEnable)
3723 {
3724 MS_U8 regval;
3725
3726 regval = HAL_ReadRegBit(SUB_REG(VOP_LSB_DMA1), VOP_SYNC_2_DC_TIMING);
3727
3728 if(VOP_SYNC_2_DC_TIMING == regval) //previous enable sync
3729 {
3730 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 0, BIT0); // sub should not work here, turn off
3731 HAL_WriteRegBit(VOP_CTRL0, 0, BIT0);
3732 HAL_WriteRegBit(SUB_REG(VOP_LSB_DMA1), bEnable, VOP_SYNC_2_DC_TIMING);
3733 if(bEnable)
3734 {
3735 HAL_WriteRegBit(VOP_CTRL0, 1, BIT0);
3736 }
3737 else
3738 {
3739 HAL_WriteRegBit(VOP_CTRL0, g_pHalMVOPCtx->bIsEnable, BIT0);
3740 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), g_pHalMVOPCtx->bSubIsEnable, BIT0);
3741 }
3742 }
3743 else //previous disable sync
3744 {
3745 if(bEnable)
3746 {
3747 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 0, BIT0); // sub should not work here, turn off
3748 HAL_WriteRegBit(VOP_CTRL0, 0, BIT0);
3749 HAL_WriteRegBit(SUB_REG(VOP_LSB_DMA1), bEnable, VOP_SYNC_2_DC_TIMING);
3750 HAL_WriteRegBit(VOP_CTRL0, 1, BIT0);
3751 }
3752 }
3753 }
3754
HAL_MVOP_EnableHDRSetting(MS_BOOL bEnable)3755 void HAL_MVOP_EnableHDRSetting(MS_BOOL bEnable)
3756 {
3757 HAL_WriteRegBit(VOP_REG_YC422_EN_H, bEnable, BIT0);
3758 HAL_WriteRegBit(VOP_REG_HS_OUTPUT, bEnable, VOP_HS_MODE);
3759 HAL_WriteRegBit(VOP_CTRL0, bEnable, BIT4);
3760 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background
3761 if(bEnable)
3762 {
3763 HAL_WriteRegBit(VOP_REG_YC422_EN_H, 0, VOP_FRAME_RST); // for Dolby crop
3764 }
3765 g_pHalMVOPCtx->bIsHS = bEnable;
3766 }
3767 #endif
3768
HAL_MVOP_SetSramPower(MVOP_DevID eID,MS_BOOL bEnable)3769 void HAL_MVOP_SetSramPower(MVOP_DevID eID ,MS_BOOL bEnable)
3770 {
3771 switch(eID)
3772 {
3773 case E_MVOP_DEV_0:
3774 #if MVOP_SUPPORT_SUB
3775 if((bEnable== FALSE) && (g_pHalMVOPCtx->bSubIsEnable == FALSE)) //check sub disable -> mfdec sram disable
3776 {
3777 HAL_WriteRegBit(VOP_DC_STRIP_H, 1, MFDEC_SRAM_SD_MASK);
3778 HAL_WriteRegBit(VOP_DC_STRIP_H, 1, VOP_SRAM_SD_MASK);
3779 }
3780 else
3781 {
3782 HAL_WriteRegBit(VOP_DC_STRIP_H, 0, MFDEC_SRAM_SD_MASK);
3783 HAL_WriteRegBit(VOP_DC_STRIP_H, 0, VOP_SRAM_SD_MASK);
3784 }
3785 #else
3786 HAL_WriteRegBit(VOP_DC_STRIP_H, !bEnable, VOP_SRAM_SD_MASK);
3787 #endif
3788 break;
3789 #if MVOP_SUPPORT_SUB
3790 case E_MVOP_DEV_1:
3791 if((bEnable== FALSE) && (g_pHalMVOPCtx->bIsEnable == FALSE))
3792 {
3793 HAL_WriteRegBit(VOP_DC_STRIP_H, 1, MFDEC_SRAM_SD_MASK);
3794 HAL_WriteRegBit(VOP_DC_STRIP_H, 1, VOP_SRAM_SD_MASK);
3795 HAL_WriteRegBit(SUB_REG(VOP_DC_STRIP_H), 1, VOP_SRAM_SD_MASK);
3796 }
3797 else
3798 {
3799 HAL_WriteRegBit(VOP_DC_STRIP_H, 0, MFDEC_SRAM_SD_MASK);
3800 HAL_WriteRegBit(VOP_DC_STRIP_H, 0, VOP_SRAM_SD_MASK); //main need to enable, if sub enable.
3801 HAL_WriteRegBit(SUB_REG(VOP_DC_STRIP_H), 0, VOP_SRAM_SD_MASK);
3802 }
3803 break;
3804 #endif
3805 default:
3806 break;
3807 }
3808 return;
3809 }
3810
HAL_MVOP_Exit(MVOP_DevID eID)3811 void HAL_MVOP_Exit(MVOP_DevID eID)
3812 {
3813 switch(eID)
3814 {
3815 case E_MVOP_DEV_0:
3816 g_pHalMVOPCtx->bIsInit = 0;
3817 break;
3818 #if MVOP_SUPPORT_SUB
3819 case E_MVOP_DEV_1:
3820 g_pHalMVOPCtx->bSubIsInit = 0;
3821 break;
3822 #endif
3823 default:
3824 break;
3825 }
3826 return;
3827 }
3828 /////////////////////// Sub MVOP ////////////////////////
3829 #if MVOP_SUPPORT_SUB
HAL_MVOP_SubRegSetBase(MS_VIRT u32Base)3830 void HAL_MVOP_SubRegSetBase(MS_VIRT u32Base)
3831 {
3832 u32RiuBaseAdd = u32Base;
3833 }
3834
HAL_MVOP_SubInitMirrorMode(MS_BOOL bMir)3835 void HAL_MVOP_SubInitMirrorMode(MS_BOOL bMir)
3836 {
3837 //set bit[3:7] to support mirror mode
3838 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bMir, VOP_MIRROR_CFG_ENABLE);
3839 }
3840
HAL_MVOP_SubInit(void)3841 void HAL_MVOP_SubInit(void)
3842 {
3843 MVOP_HalInitCtxResults eRet;
3844 MS_BOOL pbFirstDrvInstant;
3845
3846 eRet = _HAL_MVOP_InitContext(&pbFirstDrvInstant);
3847 if(eRet == E_MVOP_INIT_FAIL)
3848 {
3849 MVOP_DBG(MVOP_PRINTF("[%s] MVOP Context Init failed!\n",__FUNCTION__);)
3850 return;
3851 }
3852 else if(eRet == E_MVOP_INIT_ALREADY_EXIST)
3853 {
3854 if(g_pHalMVOPCtx->bSubIsInit)
3855 {
3856 MVOP_DBG(MVOP_PRINTF("[%s] Sub MVOP Context has Initialized!\n",__FUNCTION__);)
3857 return;
3858 }
3859 }
3860 HAL_MVOP_SubInitMirrorMode(TRUE);
3861 //Enable dynamic clock gating
3862 //Note: cannot enable VOP_GCLK_VCLK_ON, or hsync cannot be sent out.
3863 HAL_WriteByteMask(SUB_REG(VOP_GCLK), VOP_GCLK_MIU_ON, VOP_GCLK_MIU_ON|VOP_GCLK_VCLK_ON);
3864 g_pHalMVOPCtx->bSubIsInit = 1;
3865 }
3866
HAL_MVOP_SubSetVerticalMirrorMode(MS_BOOL bEnable)3867 void HAL_MVOP_SubSetVerticalMirrorMode(MS_BOOL bEnable)
3868 {
3869 if (g_pHalMVOPCtx == NULL)
3870 {
3871 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
3872 return;
3873 }
3874 if (VOP_MIRROR_CFG_ENABLE != HAL_ReadRegBit(SUB_REG(VOP_MIRROR_CFG), VOP_MIRROR_CFG_ENABLE))
3875 {
3876 //MVOP_PRINTF("Setup mirror mode\n");
3877 HAL_MVOP_SubInitMirrorMode(TRUE);
3878 }
3879
3880 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bEnable, VOP_MIRROR_CFG_VEN);
3881 g_pHalMVOPCtx->bSubMirrorModeVer = bEnable;
3882 }
3883
HAL_MVOP_SubSetHorizontallMirrorMode(MS_BOOL bEnable)3884 void HAL_MVOP_SubSetHorizontallMirrorMode(MS_BOOL bEnable)
3885 {
3886 if (g_pHalMVOPCtx == NULL)
3887 {
3888 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
3889 return;
3890 }
3891 if (VOP_MIRROR_CFG_ENABLE != HAL_ReadRegBit(SUB_REG(VOP_MIRROR_CFG), VOP_MIRROR_CFG_ENABLE))
3892 {
3893 //MVOP_PRINTF("Setup mirror mode\n");
3894 HAL_MVOP_SubInitMirrorMode(TRUE);
3895 }
3896
3897 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bEnable, VOP_MIRROR_CFG_HEN);
3898 g_pHalMVOPCtx->bSubMirrorModeHor = bEnable;
3899 }
3900
HAL_MVOP_SubSetFieldInverse(MS_BOOL b2MVD,MS_BOOL b2IP)3901 void HAL_MVOP_SubSetFieldInverse(MS_BOOL b2MVD, MS_BOOL b2IP)
3902 {
3903 // Set fld inv & ofld_inv
3904 HAL_WriteRegBit(SUB_REG(VOP_CTRL0+1), b2MVD, BIT3); //inverse the field to MVD
3905 HAL_WriteRegBit(SUB_REG(VOP_CTRL0+1), b2IP, BIT4); //inverse the field to IP
3906 }
3907
HAL_MVOP_SubSetChromaWeighting(MS_BOOL bEnable)3908 void HAL_MVOP_SubSetChromaWeighting(MS_BOOL bEnable)
3909 {
3910 HAL_WriteRegBit(SUB_REG(VOP_REG_WEIGHT_CTRL), bEnable, BIT1);
3911 }
3912
3913 //load new value into active registers 0x20-0x26
HAL_MVOP_SubLoadReg(void)3914 void HAL_MVOP_SubLoadReg(void)
3915 {
3916 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT0);
3917 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT0);
3918
3919 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT4);
3920 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT4);
3921 }
3922
HAL_MVOP_SubSetMIUReqMask(MS_BOOL bEnable)3923 void HAL_MVOP_SubSetMIUReqMask(MS_BOOL bEnable)
3924 {
3925 #if 0
3926 if (bEnable)
3927 { // mask MVOP2MI to protect MIU
3928 HAL_MIU_SubSetReqMask(SUBMVOP_R, 1);
3929 MsOS_DelayTask(1);
3930 }
3931 else
3932 { // unmask MVOP2MI
3933 MsOS_DelayTask(1);
3934 HAL_MIU_SubSetReqMask(SUBMVOP_R, 0);
3935 }
3936 #endif
3937 MS_U8 u8Miu;
3938 if(HAL_MVOP_GetIsOnlyMiuIPControl() == TRUE)
3939 {
3940 // mask msb mvop
3941 u8Miu = (HAL_ReadByte(SUB_REG(VOP_MIU_SEL)) & VOP_MSB_BUF0_MIU_SEL) >> 4;
3942 }
3943 else
3944 {
3945 u8Miu = SUBVOP_ON_MIU1;
3946 }
3947 eMIUClientID eClientID = MIU_CLIENT_MVOP1_R;
3948 //MVOP_PRINTF("Enter %s bEnable=%x ReqMask=0x%x, 0x%x, u8Miu=%x\n", __FUNCTION__, bEnable,
3949 // HAL_ReadByte(0x1266), HAL_ReadByte(0x0666), u8Miu);
3950
3951 if (bEnable)
3952 { // mask MVOP2MI to protect MIU
3953 MDrv_MIU_MaskReq(u8Miu, eClientID);
3954 MsOS_DelayTask(1);
3955 }
3956 else
3957 { // unmask MVOP2MI
3958 MsOS_DelayTask(1);
3959 MDrv_MIU_UnMaskReq(u8Miu, eClientID);
3960 }
3961
3962 //MVOP_PRINTF(">Exit %s bEnable=%x ReqMask=0x%x, 0x%x, u8Miu=%x\n", __FUNCTION__, bEnable,
3963 // HAL_ReadByte(0x1266), HAL_ReadByte(0x0666), u8Miu);
3964 }
3965
HAL_MVOP_SubRst(void)3966 void HAL_MVOP_SubRst(void)
3967 {
3968 #if 0
3969 MS_BOOL bMCU = FALSE;
3970
3971 bMCU = HAL_ReadRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), BIT1);
3972 #endif
3973 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 0, BIT0);
3974 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 1, BIT0);
3975
3976 g_pHalMVOPCtx->bSubIsEnable = 1;
3977 #if 0
3978 // sw patch: for mvop hsk mode, switching mvop enable/disable may cause video was stuck.
3979 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] HAL_MVOP_Enable patch \n");)
3980 HAL_MVOP_SubSetBlackBG();
3981 HAL_MVOP_SubSetPattern(MVOP_PATTERN_FRAMECOLOR);
3982 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT4);
3983 HAL_WriteRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), 1, BIT1);
3984 MsOS_DelayTask(40);
3985 if(bMCU == FALSE)
3986 {
3987 HAL_WriteRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), 0, BIT1);
3988 }
3989 HAL_MVOP_SubSetPattern(MVOP_PATTERN_NORMAL);
3990 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT4);
3991 #endif
3992 }
3993
HAL_MVOP_SubEnable(MS_BOOL bEnable,MS_U8 u8Framerate)3994 void HAL_MVOP_SubEnable(MS_BOOL bEnable, MS_U8 u8Framerate)
3995 {
3996 MS_U8 regval;
3997 #if 0
3998 MS_U8 u8FrmDur = 40;
3999 MS_BOOL bMCU = FALSE;
4000
4001 bMCU = HAL_ReadRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), BIT1);
4002
4003 if(u8Framerate != 0)
4004 {
4005 u8FrmDur = 1000/u8Framerate; //time of one frame(ms).
4006 }
4007 #endif
4008 regval = HAL_ReadByte(SUB_REG(VOP_CTRL0));
4009
4010 if ( bEnable )
4011 {
4012 regval |= 0x1;
4013 }
4014 else
4015 {
4016 regval &= ~0x1;
4017 HAL_Write2Byte(SUB_REG(VOP_BF_VS_MVD), 0x200);
4018 HAL_Write2Byte(SUB_REG(VOP_TF_VS_MVD), 0x200);
4019 }
4020 #if 0
4021 // sw patch: for mvop hsk mode, switching mvop enable/disable may cause video was stuck.
4022 if ( bEnable && (g_pHalMVOPCtx->bSubIsEnable == FALSE)) // need patch only from off to on
4023 {
4024 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] HAL_MVOP_Enable patch \n");)
4025 HAL_MVOP_SubSetBlackBG();
4026 HAL_MVOP_SubSetPattern(MVOP_PATTERN_FRAMECOLOR);
4027 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT4);
4028 HAL_WriteRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), 1, BIT1);
4029 MsOS_DelayTask(u8FrmDur);
4030 if(bMCU == FALSE)
4031 {
4032 HAL_WriteRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), 0, BIT1);
4033 }
4034 HAL_MVOP_SubSetPattern(MVOP_PATTERN_NORMAL);
4035 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT4);
4036 }
4037 #endif
4038 g_pHalMVOPCtx->bSubIsEnable = bEnable;
4039
4040 HAL_WriteByte(SUB_REG(VOP_CTRL0), regval);
4041
4042 }
4043
HAL_MVOP_SubGetEnableState(void)4044 MS_BOOL HAL_MVOP_SubGetEnableState(void)
4045 {
4046 return (HAL_ReadRegBit(SUB_REG(VOP_CTRL0), BIT0));
4047 }
4048
HAL_MVOP_SubGetMaxFreerunClk()4049 HALMVOPFREQUENCY HAL_MVOP_SubGetMaxFreerunClk()
4050 {
4051 return HALMVOP_160MHZ;
4052 }
4053
HAL_MVOP_SubGet4k2kClk()4054 HALMVOPFREQUENCY HAL_MVOP_SubGet4k2kClk()
4055 {
4056 return HALMVOP_320MHZ;
4057 }
4058
4059 //FIXME
HAL_MVOP_SubSetFrequency(HALMVOPFREQUENCY enFrequency)4060 void HAL_MVOP_SubSetFrequency(HALMVOPFREQUENCY enFrequency)
4061 {
4062 // clear
4063 HAL_WriteByteMask(REG_CKG_SUB_DC0, 0, CKG_SUB_DC0_MASK);
4064 switch(enFrequency)
4065 {
4066 case HALMVOP_SYNCMODE:
4067 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_SYNCHRONOUS, CKG_SUB_DC0_MASK);
4068 break;
4069 case HALMVOP_FREERUNMODE:
4070 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_FREERUN, CKG_SUB_DC0_MASK);
4071 break;
4072 case HALMVOP_160MHZ:
4073 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_160MHZ, CKG_SUB_DC0_MASK);
4074 break;
4075 case HALMVOP_144MHZ:
4076 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_144MHZ, CKG_SUB_DC0_MASK);
4077 break;
4078 case HALMVOP_320MHZ:
4079 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_320MHZ, CKG_SUB_DC0_MASK);
4080 break;
4081 default:
4082 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_SYNCHRONOUS, CKG_SUB_DC0_MASK);
4083 MVOP_PRINTF("Attention! In HAL_MVOP_SubSetFrequency default path!\n");
4084 break;
4085 }
4086 }
4087
HAL_MVOP_SubSetOutputInterlace(MS_BOOL bEnable,MS_U16 u16ECOVersion)4088 void HAL_MVOP_SubSetOutputInterlace(MS_BOOL bEnable, MS_U16 u16ECOVersion)
4089 {
4090 MS_U8 regval;
4091 UNUSED(u16ECOVersion);
4092
4093 regval = HAL_ReadByte(SUB_REG(VOP_CTRL0));
4094
4095 if ( bEnable )
4096 {
4097 regval |= 0x80;
4098 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
4099 }
4100 else
4101 {
4102 regval &= ~0x80;
4103 }
4104
4105 HAL_WriteByte(SUB_REG(VOP_CTRL0), regval);
4106 }
4107
HAL_MVOP_SubSetPattern(MVOP_Pattern enMVOPPattern)4108 void HAL_MVOP_SubSetPattern(MVOP_Pattern enMVOPPattern)
4109 {
4110 HAL_WriteByteMask(SUB_REG(VOP_TST_IMG), enMVOPPattern, BIT2 | BIT1 | BIT0);
4111 }
4112
HAL_MVOP_SubSetTileFormat(MVOP_TileFormat eTileFmt)4113 MS_BOOL HAL_MVOP_SubSetTileFormat(MVOP_TileFormat eTileFmt)
4114 {
4115 if (eTileFmt == E_MVOP_TILE_8x32)
4116 {
4117 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT1);
4118 return TRUE;
4119 }
4120 else if (eTileFmt == E_MVOP_TILE_16x32)
4121 {
4122 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT1);
4123 return TRUE;
4124 }
4125 else if (eTileFmt == E_MVOP_TILE_32x16)
4126 {
4127 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT1);
4128 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 1, EVD_ENABLE);
4129 return TRUE;
4130 }
4131 else if (eTileFmt == E_MVOP_TILE_32x32)
4132 {
4133 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT1);
4134 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, EVD_ENABLE);
4135 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 1, VOP_TILE_32x32);
4136 return TRUE;
4137 }
4138 else
4139 {
4140 return FALSE;
4141 }
4142 }
4143
HAL_MVOP_SubSetRgbFormat(MVOP_RgbFormat eRgbFmt)4144 MS_BOOL HAL_MVOP_SubSetRgbFormat(MVOP_RgbFormat eRgbFmt)
4145 {
4146 MS_BOOL bRet = FALSE;
4147
4148 if (g_pHalMVOPCtx == NULL)
4149 {
4150 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4151 return FALSE;
4152 }
4153 if (eRgbFmt == E_MVOP_RGB_NONE)
4154 {
4155 HAL_WriteByteMask(SUB_REG(VOP_RGB_FMT), 0, VOP_RGB_FMT_SEL);
4156 bRet = TRUE;
4157 }
4158 else if (eRgbFmt == E_MVOP_RGB_565)
4159 {
4160 HAL_WriteByteMask(SUB_REG(VOP_RGB_FMT), VOP_RGB_FMT_565, VOP_RGB_FMT_SEL);
4161 bRet = TRUE;
4162 }
4163 else if (eRgbFmt == E_MVOP_RGB_888)
4164 {
4165 HAL_WriteByteMask(SUB_REG(VOP_RGB_FMT), VOP_RGB_FMT_888, VOP_RGB_FMT_SEL);
4166 bRet = TRUE;
4167 }
4168
4169 if (bRet == TRUE)
4170 {
4171 g_pHalMVOPCtx->eSubRgbFmt = eRgbFmt;
4172 }
4173 return bRet;
4174 }
4175
HAL_MVOP_SubSetBlackBG(void)4176 void HAL_MVOP_SubSetBlackBG(void)
4177 {
4178 MS_U8 regval;
4179
4180 //set MVOP test pattern to black
4181 HAL_WriteByte(SUB_REG(VOP_TST_IMG + 1), 0x10);
4182 HAL_WriteByte(SUB_REG(VOP_U_PAT ), 0x80);
4183 HAL_WriteByte(SUB_REG(VOP_U_PAT + 1), 0x80);
4184
4185 regval = HAL_ReadByte(SUB_REG(VOP_TST_IMG));
4186 HAL_WriteByte(SUB_REG(VOP_TST_IMG), 0x02);
4187 HAL_WriteByte(SUB_REG(VOP_TST_IMG), 0x00);
4188 HAL_WriteByte(SUB_REG(VOP_TST_IMG), regval);
4189 }
4190
HAL_MVOP_SubSetCropWindow(MVOP_InputCfg * pparam)4191 void HAL_MVOP_SubSetCropWindow(MVOP_InputCfg *pparam)
4192 {
4193 #if 1
4194 UNUSED(pparam);
4195 #else // enable it when test code is ready
4196 MS_U32 x, y;
4197 MS_U32 u32offset;
4198
4199 if(!pparam)
4200 {
4201 return;
4202 }
4203 //set MVOP test pattern to black
4204 HAL_MVOP_SubSetBlackBG();
4205 #if 0
4206 if((pparam->enVideoType == MVOP_H264) && (pparam->u16StripSize == 1920))
4207 {
4208 pparam->u16StripSize = 1952;
4209 }
4210 #endif
4211 if((pparam->enVideoType == MVOP_MPG) || (pparam->enVideoType == MVOP_MPEG4))
4212 {
4213 pparam->u16CropX = (pparam->u16CropX >> 3) << 3; // 8 bytes align
4214 pparam->u16CropY = (pparam->u16CropY >> 6) << 6; // 64 bytes align
4215 }
4216 else if((pparam->enVideoType == MVOP_H264) || (pparam->enVideoType == MVOP_RM))
4217 {
4218 pparam->u16CropX = (pparam->u16CropX >> 4) << 4; // 16 bytes align
4219 pparam->u16CropY = (pparam->u16CropY >> 6) << 6; // 64 bytes align
4220 }
4221 else
4222 {
4223 MS_ASSERT(0);
4224 }
4225
4226 x = (MS_U32)pparam->u16CropX;
4227 y = (MS_U32)pparam->u16CropY;
4228
4229 // y offset
4230 u32offset = ((y * pparam->u16StripSize + (x << 5)) >> 3);
4231 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L ), (MS_U8)(u32offset));
4232 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L + 1), (MS_U8)(u32offset >> 8));
4233 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_H ), (MS_U8)(u32offset >> 16));
4234 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_H + 1), (MS_U8)((u32offset >> 24) & VOP_YUV_STR_HIBITS));
4235
4236 // uv offset
4237 u32offset = ((y >> 1) * pparam->u16StripSize + (x << 5)) >> 3;
4238 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L ), (MS_U8)(u32offset));
4239 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L + 1), (MS_U8)(u32offset >> 8));
4240 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_H ), (MS_U8)(u32offset >> 16));
4241 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_H + 1), (MS_U8)((u32offset >> 24) & VOP_YUV_STR_HIBITS));
4242
4243 pparam->u16CropWidth= (pparam->u16CropWidth >> 3) << 3;
4244 // HSize, VSize
4245 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE ), LOWBYTE(pparam->u16CropWidth ));
4246 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE + 1), HIGHBYTE(pparam->u16CropWidth ));
4247 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE ), LOWBYTE(pparam->u16CropHeight));
4248 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE + 1), HIGHBYTE(pparam->u16CropHeight ));
4249
4250 HAL_WriteByteMask(SUB_REG(VOP_MPG_JPG_SWITCH), BIT0, BIT1|BIT0);
4251
4252 // clear extend strip len bit by default
4253 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
4254 if((pparam->enVideoType == MVOP_MPG) || (pparam->enVideoType == MVOP_MPEG4))
4255 {
4256 // Disable H264 or RM Input
4257 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH), 0, BIT2|BIT3);
4258 //8*32 tile format
4259 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT1);
4260 }
4261 else if((pparam->enVideoType == MVOP_H264) || (pparam->enVideoType == MVOP_RM))
4262 {
4263 //16*32 tile format
4264 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT1);
4265 // SVD mode enable
4266 HAL_WriteByteMask(SUB_REG(VOP_INPUT_SWITCH), BIT3, BIT2|BIT3);
4267 // set mvop to 128bit_i128 interface
4268 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
4269 }
4270 HAL_MVOP_SubLoadReg();
4271 #endif
4272 }
4273
HAL_MVOP_SubSetRepeatField(MVOP_RptFldMode eMode)4274 void HAL_MVOP_SubSetRepeatField(MVOP_RptFldMode eMode)
4275 {
4276 if (g_pHalMVOPCtx == NULL)
4277 {
4278 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4279 return;
4280 }
4281 g_pHalMVOPCtx->eSubRepeatField = eMode;
4282 }
4283
HAL_MVOP_SubSetInputMode(VOPINPUTMODE mode,MVOP_InputCfg * pparam,MS_U16 u16ECOVersion)4284 void HAL_MVOP_SubSetInputMode( VOPINPUTMODE mode, MVOP_InputCfg *pparam, MS_U16 u16ECOVersion )
4285 {
4286 MS_U8 regval;
4287 MS_U16 u16strip, u16strip_lsb;
4288
4289 if (g_pHalMVOPCtx == NULL)
4290 {
4291 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4292 return;
4293 }
4294
4295 #if 0
4296 /*****************************************************/
4297 // Reset MVOP setting
4298 HAL_WriteByte(SUB_REG(VOP_TST_IMG), 0x40);
4299 HAL_MVOP_SubSetRgbFormat(E_MVOP_RGB_NONE);
4300 HAL_WriteRegBit(SUB_REG(VOP_CTRL1), 0, VOP_MVD_VS_MD); //default use original vsync
4301 // Only for Monaco: Enable deciding bot by top address + 2
4302 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), 1, VOP_FIELD_FROM_ADDR);
4303
4304 //set MVOP test pattern to black
4305 HAL_MVOP_SubSetBlackBG();
4306
4307 // clear extend strip len bit by default
4308 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
4309
4310 // set mvop to 128bit_i128 interface
4311 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
4312
4313 // Disable H264 or RM Input
4314 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH1), 0, BIT2|BIT3);
4315 // Clear 422 Flag
4316 g_pHalMVOPCtx->bSubIs422 = 0;
4317 // Clear evd Flag for interlace mode setting
4318 g_pHalMVOPCtx->bSubIsH265 = 0;
4319 HAL_WriteRegBit(SUB_REG(VOP_INFO_FROM_CODEC_L), 1, BIT3);
4320 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), 1, BIT5);
4321 //8*32 tile format
4322 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT1);
4323 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD);
4324 HAL_MVOP_SubSetFieldInverse(ENABLE, ENABLE);
4325 // EVD mode disable
4326 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, EVD_ENABLE);
4327 // EVD 10 bits
4328 HAL_WriteByteMask(SUB_REG(VOP_REG_MASK), BIT1, VOP_LSB_REQ_MASK);
4329 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 0, VOP_EVD_10B_Y_EN);
4330 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 0, VOP_EVD_10B_UV_EN);
4331 HAL_WriteRegBit(SUB_REG(VOP_UV_SHIFT), 1, VOP_GCLK_MIU_ON);
4332 // VP9 MODE disable
4333 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, VOP_R2_WISHBONE);
4334 HAL_WriteRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), 0, VOP_DRAM_RD_MODE);
4335 // Disable 2p mode
4336 HAL_MVOP_SubSetEnable4k2k2P(FALSE);
4337 /*****************************************************/
4338 #endif
4339 regval = 0;
4340 regval |= ( mode & 0x3 );
4341
4342 if ( mode == VOPINPUT_HARDWIRE )
4343 {
4344 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), regval);
4345 }
4346 else if ( mode == VOPINPUT_HARDWIRECLIP )
4347 {
4348 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), regval);
4349
4350 // HSize, VSize
4351 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE ), LOWBYTE( pparam->u16HSize ));
4352 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE + 1), HIGHBYTE( pparam->u16HSize ));
4353 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE ), LOWBYTE( pparam->u16VSize ));
4354 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE + 1), HIGHBYTE( pparam->u16VSize ));
4355 }
4356 else if (mode == VOPINPUT_MCUCTRL)
4357 {
4358 // disable from wb
4359 HAL_WriteRegBit(SUB_REG(VOP_REG_MFDEC_2_L), 0, VOP_MF_FROM_WB);
4360 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, VOP_R2_WISHBONE);
4361 g_pHalMVOPCtx->bSubMirrorMode = (g_pHalMVOPCtx->bSubMirrorModeVer||g_pHalMVOPCtx->bSubMirrorModeHor);
4362 if ( pparam->bProgressive )
4363 regval |= 0x4;
4364 else
4365 {
4366 regval &= ~0x4;
4367 regval |= 0x1; //reg_dc_md=b'11 for interlace input
4368 if (E_MVOP_RPTFLD_NONE == g_pHalMVOPCtx->eSubRepeatField)
4369 {
4370 MVOP_DBG("%s normal NOT repeat field %x\n", __FUNCTION__, g_pHalMVOPCtx->eSubRepeatField);
4371 //To support mcu mode interlace, need to set h'3B[9]=1,
4372 //h'11[12]=0, and Y1/UV1 address equal to Y0/UV0 address.
4373 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 1, VOP_REF_SELF_FLD);
4374 HAL_MVOP_SubSetFieldInverse(ENABLE, DISABLE);
4375 }
4376 }
4377
4378 if ( pparam->bYUV422 )
4379 regval |= 0x10;
4380 else
4381 regval &= ~0x10;
4382
4383 if ( pparam->b422pack )
4384 regval |= 0x80;
4385
4386 if ( pparam->bDramRdContd == 1 )
4387 regval |= 0x20;
4388 else
4389 regval &= ~0x20;
4390
4391 // for backward compatable to saturn
4392 // [3] UV-7bit mode don't care
4393 // [5] dram_rd_md =0
4394 // [6] Fld don't care
4395 // [7] 422pack don'care
4396 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), regval);
4397 g_pHalMVOPCtx->bSubIs422 = pparam->bYUV422;
4398 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), !pparam->bYUV422, VOP_420_BW_SAVE);
4399 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), !pparam->bYUV422, VOP_420_BW_SAVE_EX);
4400
4401 if (pparam->u16StripSize == 0)
4402 {
4403 if (pparam->bSD)
4404 {
4405 u16strip = 720;
4406 u16strip_lsb = 720;
4407 }
4408 else
4409 {
4410 u16strip = 1920;
4411 u16strip_lsb = 1920;
4412 }
4413 }
4414 else
4415 {
4416 u16strip = pparam->u16StripSize;
4417 u16strip_lsb = pparam->u16StripSize;
4418 }
4419
4420 // set dc_strip[7:0]
4421 if (pparam->bDramRdContd == 0)
4422 {
4423 u16strip = (u16strip + 31) / 32 * 32; //need align for monaco
4424 u16strip = u16strip/8;
4425 u16strip_lsb = (u16strip_lsb+127)/128;
4426 u16strip_lsb *= 4;
4427 }
4428 else
4429 {
4430 if ( pparam->b422pack )
4431 {
4432 if (E_MVOP_RGB_888 == g_pHalMVOPCtx->eSubRgbFmt)
4433 {
4434 u16strip *= 2;
4435 }
4436
4437 if ((u16strip < 1024) || g_pHalMVOPCtx->bSubMirrorMode)
4438 {
4439 u16strip = u16strip/4;
4440 // dont extend strip len
4441 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
4442 }
4443 else
4444 {
4445 u16strip = u16strip/8;
4446 // extend strip len to 2048
4447 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 1, BIT0);
4448 }
4449 }
4450 else
4451 {
4452 u16strip = u16strip/8;
4453 }
4454 }
4455
4456 if (u16strip >= 256 )
4457 {
4458 HAL_WriteByte(SUB_REG(VOP_DC_STRIP_H), (u16strip>>8));
4459 //reg_dc_strip_h[2:0] = reg_dc_strip[10:8]
4460 }
4461 else
4462 {
4463 HAL_WriteByteMask(SUB_REG(VOP_DC_STRIP_H), 0, BIT0 | BIT1 | BIT2);
4464 }
4465
4466 regval = u16strip;
4467 HAL_WriteByte(SUB_REG(VOP_DC_STRIP), regval);
4468 //LSB strip
4469 HAL_WriteByte(SUB_REG(VOP_DC_STRIP_LSB), u16strip_lsb & 0x3ff);
4470
4471 HAL_MVOP_SubSetYUVBaseAdd(pparam->u32YOffset, pparam->u32UVOffset,
4472 pparam->bProgressive, pparam->b422pack);
4473
4474 if (E_MVOP_RPTFLD_NONE != g_pHalMVOPCtx->eSubRepeatField)
4475 {
4476 MVOP_DBG("%s reset eRepeatField=%x ==>", __FUNCTION__, g_pHalMVOPCtx->eSubRepeatField);
4477 //To output the same field for single field input,
4478 //do NOT set h'3B[9]=1 and h'11[12]=0
4479 g_pHalMVOPCtx->eSubRepeatField = E_MVOP_RPTFLD_NONE; //reset the flag to repeat field
4480 MVOP_DBG(" %x\n", g_pHalMVOPCtx->eSubRepeatField);
4481 }
4482
4483 // HSize
4484 MS_U16 u16HSize = ALIGN_UPTO_16(pparam->u16HSize);
4485 if (u16HSize != pparam->u16HSize)
4486 {
4487 MVOP_DBG(MVOP_PRINTF("\n\n Change HSize %d to %d\n", pparam->u16HSize, u16HSize);)
4488 }
4489 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE ), LOWBYTE( u16HSize ));
4490 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE + 1), HIGHBYTE( u16HSize ));
4491
4492 // VSize
4493 MS_U16 u16VSize = pparam->u16VSize;
4494 if (g_pHalMVOPCtx->bSubMirrorModeVer)
4495 {
4496 u16VSize = ALIGN_UPTO_4(pparam->u16VSize);
4497 MVOP_DBG(MVOP_PRINTF("\n\n Change VSize %d to %d\n", pparam->u16VSize, u16VSize);)
4498 }
4499 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE ), LOWBYTE( u16VSize ));
4500 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE + 1), HIGHBYTE( u16VSize ));
4501 }
4502
4503 HAL_MVOP_SubLoadReg();
4504 }
4505
4506
HAL_MVOP_SubEnableUVShift(MS_BOOL bEnable)4507 void HAL_MVOP_SubEnableUVShift(MS_BOOL bEnable)
4508 {
4509 MS_U8 regval;
4510
4511 regval = HAL_ReadByte(SUB_REG(VOP_MPG_JPG_SWITCH));
4512
4513 if (((regval & BIT4) == BIT4) && ((regval & 0x3)== 0x2))
4514 { // 422 with MCU control mode
4515 if (bEnable)
4516 {
4517 MS_ASSERT(0);
4518 }
4519 }
4520
4521 // output 420 and interlace
4522 //[IP - Sheet] : Main Page --- 420CUP
4523 //[Project] : Titania2
4524 //[Description]: Chroma artifacts when 420to422 is applied duplicate method.
4525 //[Root cause]: Apply 420to422 average algorithm to all DTV input cases.
4526 //The average algorithm must cooperate with MVOP.
4527 HAL_WriteByteMask(SUB_REG(VOP_UV_SHIFT), (bEnable)?1:0, 0x3);
4528 }
4529
4530 static MS_BOOL _bSubEnable60P = false;
HAL_MVOP_SubSetEnable60P(MS_BOOL bEnable)4531 void HAL_MVOP_SubSetEnable60P(MS_BOOL bEnable)
4532 {
4533 _bSubEnable60P = bEnable;
4534 }
4535
4536 static MS_BOOL _bSubEnable4k2kClk = false;
HAL_MVOP_SubSetEnable4k2kClk(MS_BOOL bEnable)4537 void HAL_MVOP_SubSetEnable4k2kClk(MS_BOOL bEnable)
4538 {
4539 _bSubEnable4k2kClk = bEnable;
4540 }
4541
4542
HAL_MVOP_SubSetEnable4k2k2P(MS_BOOL bEnable)4543 void HAL_MVOP_SubSetEnable4k2k2P(MS_BOOL bEnable)
4544 {
4545 g_pHalMVOPCtx->bSubIs2p = bEnable;
4546 HAL_WriteRegBit(SUB_REG(VOP_REG_4K2K_2P), bEnable, VOP_4K2K_2P);
4547
4548 }
4549
HAL_MVOP_SubEnableFreerunMode(MS_BOOL bEnable)4550 void HAL_MVOP_SubEnableFreerunMode(MS_BOOL bEnable)
4551 {
4552 if (g_pHalMVOPCtx == NULL)
4553 {
4554 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4555 return;
4556 }
4557 g_pHalMVOPCtx->bSubEnableFreerunMode = bEnable;
4558 }
4559
HAL_MVOP_SubSetOutputTiming(MVOP_Timing * ptiming)4560 void HAL_MVOP_SubSetOutputTiming( MVOP_Timing *ptiming )
4561 {
4562 MS_U8 regval;
4563
4564 HAL_WriteByte(SUB_REG(VOP_FRAME_VCOUNT ), LOWBYTE( ptiming->u16V_TotalCount ));
4565 HAL_WriteByte(SUB_REG(VOP_FRAME_VCOUNT + 1), HIGHBYTE( ptiming->u16V_TotalCount ));
4566 HAL_WriteByte(SUB_REG(VOP_FRAME_HCOUNT ), LOWBYTE( ptiming->u16H_TotalCount ));
4567 HAL_WriteByte(SUB_REG(VOP_FRAME_HCOUNT + 1), HIGHBYTE( ptiming->u16H_TotalCount ));
4568
4569 HAL_WriteByte(SUB_REG(VOP_VB0_STR ), LOWBYTE( ptiming->u16VBlank0_Start ));
4570 HAL_WriteByte(SUB_REG(VOP_VB0_STR + 1), HIGHBYTE( ptiming->u16VBlank0_Start ));
4571 HAL_WriteByte(SUB_REG(VOP_VB0_END ), LOWBYTE( ptiming->u16VBlank0_End ));
4572 HAL_WriteByte(SUB_REG(VOP_VB0_END + 1), HIGHBYTE( ptiming->u16VBlank0_End ));
4573 HAL_WriteByte(SUB_REG(VOP_VB1_STR ), LOWBYTE( ptiming->u16VBlank1_Start ));
4574 HAL_WriteByte(SUB_REG(VOP_VB1_STR + 1), HIGHBYTE( ptiming->u16VBlank1_Start ));
4575 HAL_WriteByte(SUB_REG(VOP_VB1_END ), LOWBYTE( ptiming->u16VBlank1_End ));
4576 HAL_WriteByte(SUB_REG(VOP_VB1_END + 1), HIGHBYTE( ptiming->u16VBlank1_End ));
4577 HAL_WriteByte(SUB_REG(VOP_TF_STR ), LOWBYTE( ptiming->u16TopField_Start ));
4578 HAL_WriteByte(SUB_REG(VOP_TF_STR + 1), HIGHBYTE( ptiming->u16TopField_Start ));
4579 HAL_WriteByte(SUB_REG(VOP_BF_STR ), LOWBYTE( ptiming->u16BottomField_Start ));
4580 HAL_WriteByte(SUB_REG(VOP_BF_STR + 1), HIGHBYTE( ptiming->u16BottomField_Start ));
4581 HAL_WriteByte(SUB_REG(VOP_HACT_STR ), LOWBYTE( ptiming->u16HActive_Start ));
4582 HAL_WriteByte(SUB_REG(VOP_HACT_STR + 1), HIGHBYTE( ptiming->u16HActive_Start ));
4583
4584 HAL_WriteByte(SUB_REG(VOP_TF_VS ), LOWBYTE( ptiming->u16TopField_VS ));
4585 HAL_WriteByte(SUB_REG(VOP_TF_VS + 1), HIGHBYTE( ptiming->u16TopField_VS ));
4586 HAL_WriteByte(SUB_REG(VOP_BF_VS ), LOWBYTE( ptiming->u16BottomField_VS ));
4587 HAL_WriteByte(SUB_REG(VOP_BF_VS + 1), HIGHBYTE( ptiming->u16BottomField_VS ));
4588
4589 if(((((ptiming->u16V_TotalCount >= 2160) && (ptiming->u16H_TotalCount >= 3840)) || ((ptiming->u16V_TotalCount >= 2160) && (ptiming->u16H_TotalCount >= 1920) && g_pHalMVOPCtx->bSubIs2p))
4590 && (ptiming->u8Framerate > 15)) || g_pHalMVOPCtx->bIs265DV)
4591 {
4592 g_pHalMVOPCtx->bSubNewVSyncMode = TRUE;
4593 if(g_pHalMVOPCtx->bIs265DV)
4594 {
4595 if(ptiming->u8Framerate > 30) //for 4k60
4596 {
4597 g_pHalMVOPCtx->u16SubVsyncLines = 0x10D;//0x9d->0x10d for 120Hz trick mode.
4598 }
4599 else
4600 {
4601 g_pHalMVOPCtx->u16SubVsyncLines = 0x60;//mantis 1205202
4602 }
4603 HAL_WriteByte(SUB_REG(VOP_DMA0), 0x18);
4604 HAL_WriteByteMask(SUB_REG(VOP_DMA1), 0x01, VOP_BURST_EXT);
4605 }
4606 else
4607 {
4608 if(ptiming->u8Framerate > 30) //for 4k60
4609 {
4610 g_pHalMVOPCtx->u16SubVsyncLines = 0;
4611 HAL_WriteByte(SUB_REG(VOP_DMA0), 0x08);
4612 HAL_WriteByteMask(SUB_REG(VOP_DMA1), 0x02, VOP_BURST_EXT);
4613 }
4614 else
4615 {
4616 g_pHalMVOPCtx->u16SubVsyncLines = 0;
4617 HAL_WriteByte(SUB_REG(VOP_DMA0), 0x08);
4618 HAL_WriteByteMask(SUB_REG(VOP_DMA1), 0x02, VOP_BURST_EXT);
4619 g_pHalMVOPCtx->bSubNewVSyncMode = 0;
4620 HAL_WriteRegBit(SUB_REG(VOP_CTRL1), 1, VOP_MVD_VS_SEL); //4k 30 only 4 lines forwarding: mantis 1185981
4621 }
4622 }
4623 }
4624 else if(((ptiming->u16V_TotalCount >= 1080) && (ptiming->u16H_TotalCount >= 1440)) && (ptiming->u8Framerate >= 24) && (ptiming->bInterlace == 1))
4625 {
4626 if(g_pHalMVOPCtx->bSubMirrorModeVer)
4627 {
4628 g_pHalMVOPCtx->bSubNewVSyncMode = FALSE;
4629 HAL_WriteRegBit(SUB_REG(VOP_CTRL1), 1, VOP_MVD_VS_SEL); // 4 lins forwarding; Mantis ID:1074519
4630 }
4631 else
4632 {
4633 g_pHalMVOPCtx->bSubNewVSyncMode = TRUE;
4634 HAL_MVOP_SubSetFieldInverse(DISABLE, ENABLE);
4635 g_pHalMVOPCtx->u16SubVsyncLines = 0x40;
4636 HAL_WriteByte(SUB_REG(VOP_DMA0), 0x18);
4637 HAL_WriteByteMask(SUB_REG(VOP_DMA1), 0x01, VOP_BURST_EXT);
4638 }
4639 }
4640 else
4641 {
4642 g_pHalMVOPCtx->u16SubVsyncLines = 0;
4643 HAL_WriteByte(SUB_REG(VOP_DMA0), 0x08);
4644 HAL_WriteByteMask(SUB_REG(VOP_DMA1), 0x02, VOP_BURST_EXT);
4645 }
4646
4647 if (g_pHalMVOPCtx->bSubNewVSyncMode)
4648 {
4649 #define SUB_NEW_VSYNC_MODE_ADVANCE_LINECNT 30
4650 MS_U16 u16BottomField_VS2MVD;
4651 MS_U16 u16TopField_VS2MVD;
4652 MVOP_DBG(MVOP_PRINTF("MVOP use new vync mode, forwarding %d lines\n",SUB_NEW_VSYNC_MODE_ADVANCE_LINECNT);)
4653
4654 if(g_pHalMVOPCtx->u16SubVsyncLines == 0)
4655 u16BottomField_VS2MVD = ptiming->u16BottomField_VS - SUB_NEW_VSYNC_MODE_ADVANCE_LINECNT;
4656 else
4657 u16BottomField_VS2MVD = ptiming->u16BottomField_VS - g_pHalMVOPCtx->u16SubVsyncLines;
4658 MVOP_DBG(MVOP_PRINTF("BottomField VS ori=0x%x, new=0x%x\n", ptiming->u16BottomField_VS, u16BottomField_VS2MVD);)
4659 HAL_WriteByte(SUB_REG(VOP_BF_VS_MVD), LOWBYTE( u16BottomField_VS2MVD ));
4660 HAL_WriteByte(SUB_REG((VOP_BF_VS_MVD + 1)), HIGHBYTE( u16BottomField_VS2MVD ));
4661
4662 if(g_pHalMVOPCtx->u16SubVsyncLines == 0)
4663 u16TopField_VS2MVD = ptiming->u16V_TotalCount - SUB_NEW_VSYNC_MODE_ADVANCE_LINECNT;
4664 else
4665 u16TopField_VS2MVD = ptiming->u16V_TotalCount - g_pHalMVOPCtx->u16SubVsyncLines;
4666 MVOP_DBG(MVOP_PRINTF("TopField VS Vtt=0x%x, new=0x%x\n", ptiming->u16V_TotalCount, u16TopField_VS2MVD);)
4667 HAL_WriteByte(SUB_REG(VOP_TF_VS_MVD), LOWBYTE( u16TopField_VS2MVD ));
4668 HAL_WriteByte(SUB_REG((VOP_TF_VS_MVD + 1)), HIGHBYTE( u16TopField_VS2MVD ));
4669
4670 HAL_WriteRegBit(SUB_REG(VOP_GCLK), 0, VOP_GCLK_MIU_ON);
4671
4672 HAL_WriteRegBit(SUB_REG(VOP_CTRL1), 1, VOP_MVD_VS_MD); //Use new vsync
4673
4674 g_pHalMVOPCtx->bSubNewVSyncMode = FALSE; //restore to original mode
4675 }
4676
4677
4678 // + S3, set default IMG_HSTR, IMG_VSTR0, IMG_VSTR1
4679 #ifdef _SUPPORT_IMG_OFFSET_
4680 HAL_WriteByte(SUB_REG(VOP_IMG_HSTR ), LOWBYTE( ptiming->u16HImg_Start));
4681 HAL_WriteByte(SUB_REG(VOP_IMG_HSTR + 1), HIGHBYTE( ptiming->u16HImg_Start ));
4682 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR0 ), LOWBYTE( ptiming->u16VImg_Start0));
4683 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR0+ 1), HIGHBYTE( ptiming->u16VImg_Start0 ));
4684 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR1 ), LOWBYTE( ptiming->u16VImg_Start1 ));
4685 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR1+ 1), HIGHBYTE( ptiming->u16VImg_Start1 ));
4686 #else
4687 HAL_WriteByte(SUB_REG(VOP_IMG_HSTR ), LOWBYTE( ptiming->u16HActive_Start ));
4688 HAL_WriteByte(SUB_REG(VOP_IMG_HSTR + 1), HIGHBYTE( ptiming->u16HActive_Start ));
4689 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR0 ), LOWBYTE( ptiming->u16VBlank0_End ));
4690 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR0+ 1), HIGHBYTE( ptiming->u16VBlank0_End ));
4691 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR1 ), LOWBYTE( ptiming->u16VBlank1_End ));
4692 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR1+ 1), HIGHBYTE( ptiming->u16VBlank1_End ));
4693 #endif
4694 // select mvop output from frame color(black)
4695 HAL_WriteByte(SUB_REG(VOP_TST_IMG + 1), 0x10);
4696 HAL_WriteByte(SUB_REG(VOP_U_PAT ), 0x80);
4697 HAL_WriteByte(SUB_REG(VOP_U_PAT + 1), 0x80);
4698 // set mvop src to test pattern
4699 regval = HAL_ReadByte(SUB_REG(VOP_TST_IMG));
4700 HAL_WriteByte(SUB_REG(VOP_TST_IMG), 0x02);
4701 // make changed registers take effect
4702 HAL_MVOP_SubLoadReg();
4703
4704 HAL_MVOP_SubSetMIUReqMask(TRUE);
4705 // reset mvop to avoid timing change cause mvop hang-up
4706 HAL_MVOP_SubRst();
4707 HAL_MVOP_SubSetMIUReqMask(FALSE);
4708
4709 // select mvop output from mvd
4710 HAL_WriteByte(SUB_REG(VOP_TST_IMG), 0x00);
4711 HAL_WriteByte(SUB_REG(VOP_TST_IMG), regval);
4712 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), ptiming->bHDuplicate, BIT2);// H pixel duplicate
4713
4714 #if 0
4715 MVOP_DBG(MVOP_PRINTF("\nMVOP SetOutputTiming\n");)
4716 MVOP_DBG(MVOP_PRINTF(" VTot=%u,\t",ptiming->u16V_TotalCount);)
4717 MVOP_DBG(MVOP_PRINTF(" HTot=%u,\t",ptiming->u16H_TotalCount);)
4718 MVOP_DBG(MVOP_PRINTF(" I/P=%u\n",ptiming->bInterlace);)
4719 MVOP_DBG(MVOP_PRINTF(" W=%u,\t",ptiming->u16Width);)
4720 MVOP_DBG(MVOP_PRINTF(" H=%u,\t",ptiming->u16Height);)
4721 MVOP_DBG(MVOP_PRINTF(" FRate=%u,\t",ptiming->u8Framerate);)
4722 MVOP_DBG(MVOP_PRINTF(" HFreq=%u\n",ptiming->u16H_Freq);)
4723 MVOP_DBG(MVOP_PRINTF(" Num=0x%x,\t",ptiming->u16Num);)
4724 MVOP_DBG(MVOP_PRINTF(" Den=0x%x,\t",ptiming->u16Den);)
4725 MVOP_DBG(MVOP_PRINTF(" u16ExpFRate=%u #\n\n", ptiming->u16ExpFrameRate);)
4726 #endif
4727 }
4728
HAL_MVOP_SubSetDCClk(MS_U8 clkNum,MS_BOOL bEnable)4729 void HAL_MVOP_SubSetDCClk(MS_U8 clkNum, MS_BOOL bEnable)
4730 {
4731 MS_ASSERT( (clkNum==0) || (clkNum==1) );
4732 if (clkNum==0)
4733 {
4734 HAL_WriteRegBit(REG_CKG_SUB_DC0, !bEnable, CKG_SUB_DC0_GATED);
4735 }
4736 }
4737
HAL_MVOP_SubSetDCSRAMClk(MS_U8 clkNum,MS_BOOL bEnable)4738 void HAL_MVOP_SubSetDCSRAMClk(MS_U8 clkNum, MS_BOOL bEnable)
4739 {
4740 MS_ASSERT( (clkNum==0) || (clkNum==1) );
4741 if (clkNum==0)
4742 {
4743 HAL_WriteRegBit(REG_CKG_DC_SRAM, !bEnable, CKG_DC1_SRAM);
4744 }
4745 }
4746
HAL_MVOP_SubSetSynClk(MVOP_Timing * ptiming)4747 void HAL_MVOP_SubSetSynClk(MVOP_Timing *ptiming)
4748 {
4749 if (g_pHalMVOPCtx == NULL)
4750 {
4751 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4752 return;
4753 }
4754
4755 if ( g_pHalMVOPCtx->bIs265DV == 1)
4756 {
4757 g_pHalMVOPCtx->bSubEnableFreerunMode = g_pHalMVOPCtx->bEnableFreerunMode;
4758 _bSubEnable60P = _bEnable60P;
4759 _bSubEnable4k2kClk = _bEnable4k2kClk;
4760 }
4761
4762 if(g_pHalMVOPCtx->bSubEnableFreerunMode)
4763 {
4764 MS_U64 u64mpll_clock = MPLL_CLOCK_216 << 27 ; //mvop hw bug, tsp default use 216MHz mpll clock @ maserati
4765 if(HAL_ReadRegBit(REG_CLK_SYN_STC, BIT0) == BIT4) //check stc1 clock use 432 or 216
4766 {
4767 u64mpll_clock = MPLL_CLOCK_432 << 27 ;
4768 }
4769 MS_U64 u64exp_clock = (((MS_U64)ptiming->u16H_TotalCount * (MS_U64)ptiming->u16V_TotalCount * (MS_U64)ptiming->u16ExpFrameRate)/1000);
4770 do_div(u64mpll_clock, u64exp_clock);
4771 MS_U32 u32FreerunClk = (MS_U32)u64mpll_clock;
4772 HAL_MVOP_SubSetFrequency(HALMVOP_FREERUNMODE);
4773 HAL_WriteByte((REG_DC1_FREERUN_CW_L ), LOWBYTE((MS_U16)u32FreerunClk));
4774 HAL_WriteByte((REG_DC1_FREERUN_CW_L+1), HIGHBYTE((MS_U16)u32FreerunClk));
4775 HAL_WriteByte((REG_DC1_FREERUN_CW_H ), LOWBYTE((MS_U16)(u32FreerunClk >> 16)));
4776 HAL_WriteByte((REG_DC1_FREERUN_CW_H+1), HIGHBYTE((MS_U16)(u32FreerunClk >> 16)));
4777 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_FREERUN_CW);
4778 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_FREERUN_CW);
4779 }
4780 else if (_bSubEnable60P)
4781 {
4782 //Set DC1 Timing
4783 MS_U32 u32FrameRate = (MS_U32)ptiming->u16ExpFrameRate;
4784 MS_U32 u32VSize = 1024;
4785 MS_U32 u32HSize = ((86400000 / u32FrameRate) * 1000) / u32VSize;
4786
4787 if(u32HSize > 4096)
4788 MVOP_PRINTF("[Warning] xc support u32HSize > 4096 after CL 712830\n");
4789
4790
4791 HAL_MVOP_SubSetFrequency(HAL_MVOP_SubGetMaxFreerunClk());
4792
4793 HAL_WriteRegBit(SUB_REG(VOP_REG_YC422_EN_H), 0, VOP_FRAME_RST); // reg_frame_rst = 0
4794
4795 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), DISABLE, VOP_FSYNC_EN); // frame sync disable
4796 }
4797 else if (_bSubEnable4k2kClk)
4798 {
4799 HAL_MVOP_SubSetFrequency(HAL_MVOP_SubGet4k2kClk());
4800
4801 HAL_WriteRegBit(SUB_REG(VOP_REG_YC422_EN_H), 0, VOP_FRAME_RST); // reg_frame_rst = 0
4802
4803 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), DISABLE, VOP_FSYNC_EN); // frame sync disable
4804 }
4805 else
4806 {
4807 HAL_MVOP_SubSetFrequency(HALMVOP_SYNCMODE);
4808 HAL_WriteByte((REG_DC1_NUM ), LOWBYTE( ptiming->u16Num));
4809 HAL_WriteByte((REG_DC1_NUM+1), HIGHBYTE(ptiming->u16Num));
4810 HAL_WriteByte((REG_DC1_DEN ), LOWBYTE( ptiming->u16Den));
4811 HAL_WriteByte((REG_DC1_DEN+1), HIGHBYTE(ptiming->u16Den));
4812 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_SYNC_CW);
4813 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_SYNC_CW);
4814 }
4815 }
4816
4817
HAL_MVOP_SubSetMonoMode(MS_BOOL bEnable)4818 void HAL_MVOP_SubSetMonoMode(MS_BOOL bEnable)
4819 {
4820 if(bEnable)
4821 {
4822 HAL_WriteByte(SUB_REG(VOP_U_PAT ), 0x80);
4823 HAL_WriteByte(SUB_REG(VOP_U_PAT+1), 0x80);
4824
4825 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH1), 1, BIT1); // Mono mode enable
4826 }
4827 else
4828 {
4829 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH1), 0, BIT1); //Mono mode disable
4830 }
4831 }
4832
4833 /******************************************************************************/
4834 /// Set MVOP for H264 Hardwire Mode
4835 /******************************************************************************/
HAL_MVOP_SubSetH264HardwireMode(MS_U16 u16ECOVersion)4836 void HAL_MVOP_SubSetH264HardwireMode(MS_U16 u16ECOVersion)
4837 {
4838 UNUSED(u16ECOVersion);
4839
4840 // Hardwire mode
4841 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), 0x00);
4842
4843 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
4844
4845 //16*32 tile format
4846 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT1);
4847
4848 // SVD mode enable
4849 HAL_WriteByteMask(SUB_REG(VOP_INPUT_SWITCH1), BIT3, BIT2|BIT3);
4850
4851 // set mvop to 64bit interface
4852 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
4853
4854 // Only for Monaco: Disable deciding bot by top address + 2
4855 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), 0, VOP_FIELD_FROM_ADDR);
4856
4857 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 1, VOP_32x32_WB); //32x32 from wb
4858
4859 // H264 use WISHBONE(R2) interface
4860 //HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 1, VOP_R2_WISHBONE);
4861
4862 // Write trigger
4863 HAL_MVOP_SubLoadReg();
4864 }
4865
HAL_MVOP_SubEnableMVDInterface(MS_BOOL bEnable)4866 void HAL_MVOP_SubEnableMVDInterface(MS_BOOL bEnable)
4867 {
4868 MS_BOOL bMVOPMain2MVD = TRUE;
4869 bMVOPMain2MVD = (bEnable) ? FALSE : TRUE;
4870
4871 //This bit is only valid in main mvop bank.
4872 //Select which mvop interrupt that mvd f/w recieve: 1 for main; 0 for sub.
4873 HAL_WriteByteMask(VOP_INPUT_SWITCH1, bMVOPMain2MVD, VOP_MVD_EN);
4874
4875 //No need to "Write trigger" since HAL_MVOP_SubSetInputMode() will do it later.
4876 //HAL_MVOP_SubLoadReg();
4877 }
4878
4879 /******************************************************************************/
4880 /// Set MVOP for RM Hardwire Mode
4881 /******************************************************************************/
HAL_MVOP_SubSetRMHardwireMode(MS_U16 u16ECOVersion)4882 void HAL_MVOP_SubSetRMHardwireMode(MS_U16 u16ECOVersion)
4883 {
4884 HAL_MVOP_SubSetH264HardwireMode(u16ECOVersion);
4885 }
4886
4887 /******************************************************************************/
4888 /// Set MVOP for JPEG Hardwire Mode
4889 /******************************************************************************/
HAL_MVOP_SubSetJpegHardwireMode(MS_U16 u16ECOVersion)4890 void HAL_MVOP_SubSetJpegHardwireMode(MS_U16 u16ECOVersion)
4891 {
4892 MS_U8 regval = 0x00;
4893 UNUSED(u16ECOVersion);
4894
4895 //16*32 tile format
4896 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT1);
4897
4898 // set mvop to 64bit interface
4899 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
4900
4901 regval |= 0x80; // packmode
4902 regval |= 0x20; // Dram Rd Contd
4903 regval |= 0x10; // reg_img422
4904 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), regval);
4905 /* There is no hardwire:mvd2dc_img422/hvd2dc_img422 0x20[4] in sub mvop*/
4906 HAL_WriteByteMask(SUB_REG(VOP_INFO_FROM_CODEC_L), 0, VOP_INFO_FROM_CODEC_422_FMT);
4907 g_pHalMVOPCtx->bSubIs422 = 1;
4908 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 0, VOP_420_BW_SAVE);
4909 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
4910
4911 // Write trigger
4912 HAL_MVOP_SubLoadReg();
4913 }
4914 /******************************************************************************/
4915 /// Set MVOP for EVD Hardwire Mode
4916 /******************************************************************************/
HAL_MVOP_SubSetEVDHardwireMode(MS_U16 u16ECOVersion)4917 void HAL_MVOP_SubSetEVDHardwireMode(MS_U16 u16ECOVersion)
4918 {
4919 UNUSED(u16ECOVersion);
4920
4921 // Hardwire mode
4922 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), 0x00);
4923
4924 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
4925
4926 //16*32 tile format
4927 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT1);
4928
4929 // EVD use HVD interface
4930 //HAL_WriteByteMask(SUB_REG(VOP_INPUT_SWITCH1), BIT3, BIT2|BIT3);
4931
4932 // EVD mode enable
4933 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 1, EVD_ENABLE);
4934
4935 // set mvop to 128bit_i128 interface
4936 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
4937
4938 // set evd flag for interlace mode setting
4939 g_pHalMVOPCtx->bSubIsH265 = 1;
4940
4941 // 10 bits from wb
4942 HAL_WriteRegBit(SUB_REG(VOP_INFO_FROM_CODEC_H), 1, VOP_INFO_FROM_CODEC_10BIT);
4943
4944 HAL_WriteByteMask(SUB_REG(VOP_REG_MASK), 0, VOP_LSB_REQ_MASK); //10 bits bw control by vdec fw
4945
4946 // Write trigger
4947 HAL_MVOP_SubLoadReg();
4948 }
4949
4950 /******************************************************************************/
4951 /// Set MVOP for VP9 Hardwire Mode
4952 /******************************************************************************/
HAL_MVOP_SubSetVP9HardwireMode(MS_U16 u16ECOVersion)4953 void HAL_MVOP_SubSetVP9HardwireMode(MS_U16 u16ECOVersion)
4954 {
4955 UNUSED(u16ECOVersion);
4956
4957 // Hardwire mode
4958 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), 0x00);
4959
4960 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
4961
4962 //16*32 tile format
4963 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT1);
4964
4965 // Enable VP9 dram continue mode
4966 //HAL_WriteRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), 1, VOP_DRAM_RD_MODE);
4967
4968 // set mvop to 128bit_i128 interface
4969 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
4970
4971 // EVD mode enable
4972 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 1, EVD_ENABLE);
4973
4974 // 10 bits from wb
4975 HAL_WriteRegBit(SUB_REG(VOP_INFO_FROM_CODEC_H), 1, VOP_INFO_FROM_CODEC_10BIT);
4976
4977 HAL_WriteByteMask(SUB_REG(VOP_REG_MASK), 0, VOP_LSB_REQ_MASK); //10 bits bw control by vdec fw
4978
4979 // Write trigger
4980 HAL_MVOP_LoadReg();
4981
4982 }
4983
4984
4985 ///Enable 3D L/R dual buffer mode
HAL_MVOP_SubEnable3DLR(MS_BOOL bEnable)4986 MS_BOOL HAL_MVOP_SubEnable3DLR(MS_BOOL bEnable)
4987 {
4988 if (g_pHalMVOPCtx == NULL)
4989 {
4990 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4991 return FALSE;
4992 }
4993 HAL_WriteRegBit(SUB_REG(VOP_MULTI_WIN_CFG0), bEnable, VOP_LR_BUF_MODE);
4994 g_pHalMVOPCtx->bSub3DLRMode = bEnable;
4995 if(bEnable)
4996 {
4997 //only for monaco: do not wait for data ready.
4998 HAL_WriteByteMask(SUB_REG(VOP_NOT_WAIT_READ_DATA), 2, VOP_NOT_WAIT_RDLAT);
4999 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
5000 }
5001 else
5002 {
5003 HAL_WriteByteMask(SUB_REG(VOP_NOT_WAIT_READ_DATA), 0, VOP_NOT_WAIT_RDLAT);
5004 }
5005 return TRUE;
5006 }
5007
5008 ///Get if 3D L/R mode is enabled
HAL_MVOP_SubGet3DLRMode(void)5009 MS_BOOL HAL_MVOP_SubGet3DLRMode(void)
5010 {
5011 if (g_pHalMVOPCtx == NULL)
5012 {
5013 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5014 return FALSE;
5015 }
5016 return g_pHalMVOPCtx->bSub3DLRMode;
5017 }
5018
HAL_MVOP_SubGetTimingInfoFromRegisters(MVOP_TimingInfo_FromRegisters * pMvopTimingInfo)5019 MS_BOOL HAL_MVOP_SubGetTimingInfoFromRegisters(MVOP_TimingInfo_FromRegisters *pMvopTimingInfo)
5020 {
5021 if(NULL == pMvopTimingInfo)
5022 {
5023 MVOP_PRINTF("HAL_MVOP_SubGetTimingInfoFromRegisters():pMvopTimingInfo is NULL\n");
5024 return FALSE;
5025 }
5026 if(HAL_MVOP_SubGetEnableState() == FALSE)
5027 {
5028 MVOP_PRINTF("MVOP is not enabled!\n");
5029 pMvopTimingInfo->bEnabled = FALSE;
5030 return FALSE;
5031 }
5032 pMvopTimingInfo->bEnabled = TRUE;
5033 pMvopTimingInfo->u16H_TotalCount = (HAL_ReadByte(SUB_REG(VOP_FRAME_HCOUNT + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_FRAME_HCOUNT)));
5034 pMvopTimingInfo->u16V_TotalCount = (HAL_ReadByte(SUB_REG(VOP_FRAME_VCOUNT + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_FRAME_VCOUNT)));
5035 pMvopTimingInfo->u16VBlank0_Start = (HAL_ReadByte(SUB_REG(VOP_VB0_STR + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_VB0_STR)));
5036 pMvopTimingInfo->u16VBlank0_End = (HAL_ReadByte(SUB_REG(VOP_VB0_END + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_VB0_END)));
5037 pMvopTimingInfo->u16VBlank1_Start = (HAL_ReadByte(SUB_REG(VOP_VB1_STR + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_VB1_STR)));
5038 pMvopTimingInfo->u16VBlank1_End = (HAL_ReadByte(SUB_REG(VOP_VB1_END + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_VB1_END)));
5039 pMvopTimingInfo->u16TopField_Start = (HAL_ReadByte(SUB_REG(VOP_TF_STR + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_TF_STR)));
5040 pMvopTimingInfo->u16BottomField_Start = (HAL_ReadByte(SUB_REG(VOP_BF_STR + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_BF_STR)));
5041 pMvopTimingInfo->u16HActive_Start = (HAL_ReadByte(SUB_REG(VOP_HACT_STR + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_HACT_STR)));
5042 pMvopTimingInfo->u16TopField_VS = (HAL_ReadByte(SUB_REG(VOP_TF_VS + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_TF_VS)));
5043 pMvopTimingInfo->u16BottomField_VS = (HAL_ReadByte(SUB_REG(VOP_BF_VS + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_BF_VS)));
5044 pMvopTimingInfo->bInterlace = (HAL_ReadRegBit(SUB_REG(VOP_CTRL0), BIT7) == BIT7);
5045 return TRUE;
5046 }
5047
HAL_MVOP_SubSetYUVBaseAdd(MS_PHY u32YOffset,MS_PHY u32UVOffset,MS_BOOL bProgressive,MS_BOOL b422pack)5048 void HAL_MVOP_SubSetYUVBaseAdd(MS_PHY u32YOffset, MS_PHY u32UVOffset, MS_BOOL bProgressive, MS_BOOL b422pack)
5049 {
5050 MS_PHY u64tmp = 0;
5051
5052 if (g_pHalMVOPCtx == NULL)
5053 {
5054 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5055 return;
5056 }
5057 // Y offset
5058 u64tmp = u32YOffset >> 3;
5059 if ( !bProgressive )
5060 { //Refine Y offset for interlace repeat bottom field
5061 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eSubRepeatField)
5062 {
5063 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eSubRepeatField);
5064 u64tmp += 2;
5065 }
5066 else
5067 {
5068 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eSubRepeatField);
5069 }
5070 }
5071 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L), u64tmp & 0xff);
5072 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L+1), (u64tmp >> 8) & 0xff);
5073 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L+2), (u64tmp >> 16) & 0xff);
5074 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5075
5076 if (!bProgressive )
5077 { //Y offset of bottom field if interlace
5078 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L), u64tmp & 0xff);
5079 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L+1), (u64tmp >> 8) & 0xff);
5080 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L+2), (u64tmp >> 16) & 0xff);
5081 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5082 }
5083
5084 if (b422pack)
5085 {
5086 if (HAL_ReadRegBit(SUB_REG(VOP_MIU_IF), VOP_MIU_128B_I64) != VOP_MIU_128B_I64) //128-bit
5087 {
5088 u32UVOffset = u32YOffset + 16; //add 16 for 128bit; add 8 for 64bit
5089 }
5090 else //64-bit
5091 {
5092 u32UVOffset = u32YOffset + 8; //add 16 for 128bit; add 8 for 64bit
5093 }
5094 }
5095 // UV offset
5096 u64tmp = u32UVOffset >> 3;
5097 if( !bProgressive )
5098 { //Refine UV offset for interlace repeat bottom field
5099 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eSubRepeatField)
5100 {
5101 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eSubRepeatField);
5102 u64tmp += 2;
5103 }
5104 else
5105 {
5106 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eSubRepeatField);
5107 }
5108 }
5109 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L), u64tmp & 0xff);
5110 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
5111 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L+2), (u64tmp >> 16) & 0xff);
5112 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5113
5114 if( !bProgressive )
5115 { //UV offset of bottom field if interlace
5116 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L), u64tmp & 0xff);
5117 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
5118 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L+2), (u64tmp >> 16) & 0xff);
5119 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5120 }
5121
5122 return;
5123 }
5124
HAL_MVOP_SubGetYBaseAdd(void)5125 MS_PHY HAL_MVOP_SubGetYBaseAdd(void)
5126 {
5127 MS_PHY u64YOffset;
5128 u64YOffset = HAL_ReadByte(SUB_REG(VOP_JPG_YSTR0_L))&0xff;
5129 u64YOffset |=((HAL_ReadByte(SUB_REG(VOP_JPG_YSTR0_L+1))<<8)&0xff00);
5130 u64YOffset |=((HAL_ReadByte(SUB_REG(VOP_JPG_YSTR0_L+2))<<16)&0xff0000);
5131 u64YOffset |= ((HAL_ReadByte(SUB_REG(VOP_JPG_YSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
5132 return u64YOffset;
5133 }
5134
HAL_MVOP_SubGetUVBaseAdd(void)5135 MS_PHY HAL_MVOP_SubGetUVBaseAdd(void)
5136 {
5137 MS_PHY u64UVOffset;
5138 u64UVOffset = HAL_ReadByte(SUB_REG(VOP_JPG_UVSTR0_L))&0xff;
5139 u64UVOffset |=((HAL_ReadByte(SUB_REG(VOP_JPG_UVSTR0_L+1))<<8)&0xff00);
5140 u64UVOffset |=((HAL_ReadByte(SUB_REG(VOP_JPG_UVSTR0_L+2))<<16)&0xff0000);
5141 u64UVOffset |= ((HAL_ReadByte(SUB_REG(VOP_JPG_UVSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
5142 return u64UVOffset;
5143 }
5144
5145 /******************************************************************************/
5146 /// Set MVOP Saving BW Mode
5147 /// @ Napoli this command should be set after MDrv_MVOP_SubSetOutputCfg
5148 /******************************************************************************/
HAL_MVOP_SubSet420BWSaveMode(MS_BOOL bEnable,MS_U16 u16ECOVersion)5149 MS_BOOL HAL_MVOP_SubSet420BWSaveMode(MS_BOOL bEnable, MS_U16 u16ECOVersion)
5150 {
5151 MS_BOOL bValue = FALSE;
5152 UNUSED(u16ECOVersion);
5153
5154 //hw limtation: 3DLA/3DSBS/422/p mode in, i mode out/i mode in, p mode out(only need to check in MCU mode)
5155 bValue = (g_pHalMVOPCtx->bSub3DLRAltSBSOutput || g_pHalMVOPCtx->bSub3DLRAltOutput /*|| g_pHalMVOPCtx->bSub3DLRMode*/ || g_pHalMVOPCtx->bSubIs422 );
5156
5157 if(bValue)
5158 {
5159 MVOP_DBG(MVOP_PRINTF("%s Hit the limitation of saving bw, disable BW Saving mode\n", __FUNCTION__);)
5160 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 0, VOP_420_BW_SAVE);
5161 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
5162 HAL_MVOP_SubLoadReg();
5163 return FALSE;
5164 }
5165 else
5166 {
5167 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), bEnable, VOP_420_BW_SAVE);
5168 if( g_pHalMVOPCtx->bSub3DLRMode == FALSE)
5169 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), bEnable, VOP_420_BW_SAVE_EX);
5170 else
5171 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
5172 HAL_MVOP_SubLoadReg();
5173 return TRUE;
5174 }
5175 }
5176
HAL_MVOP_SubSetEVDYUVBaseAdd(MVOP_EVDBaseAddInput * stEVDBaseAddInfo)5177 MS_BOOL HAL_MVOP_SubSetEVDYUVBaseAdd(MVOP_EVDBaseAddInput *stEVDBaseAddInfo)
5178 {
5179 //----------------------------------------------------
5180 // Set MSB YUV Address
5181 //----------------------------------------------------
5182
5183 MS_PHY u64tmp = 0;
5184
5185 if (g_pHalMVOPCtx == NULL)
5186 {
5187 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5188 return FALSE;
5189 }
5190 // Y offset
5191 u64tmp = stEVDBaseAddInfo->u32MSBYOffset >> 3;
5192 if ( !stEVDBaseAddInfo->bProgressive)
5193 { //Refine Y offset for interlace repeat bottom field
5194 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
5195 {
5196 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5197 u64tmp += 2;
5198 }
5199 else
5200 {
5201 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5202 }
5203 }
5204 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L), u64tmp & 0xff);
5205 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L+1), (u64tmp >> 8) & 0xff);
5206 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_H), (u64tmp >> 16) & 0xff);
5207 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5208
5209 if (!stEVDBaseAddInfo->bProgressive )
5210 { //Y offset of bottom field if interlace
5211 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L), u64tmp & 0xff);
5212 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L+1), (u64tmp >> 8) & 0xff);
5213 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_H), (u64tmp >> 16) & 0xff);
5214 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5215 }
5216
5217 if (stEVDBaseAddInfo->b422Pack)
5218 {
5219 stEVDBaseAddInfo->u32MSBUVOffset = stEVDBaseAddInfo->u32MSBYOffset + 16; //add 16 for 128bit; add 8 for 64bit
5220 }
5221 // UV offset
5222 u64tmp = stEVDBaseAddInfo->u32MSBUVOffset >> 3;
5223 if( !stEVDBaseAddInfo->bProgressive )
5224 { //Refine UV offset for interlace repeat bottom field
5225 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
5226 {
5227 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5228 u64tmp += 2;
5229 }
5230 else
5231 {
5232 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5233 }
5234 }
5235 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L), u64tmp & 0xff);
5236 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
5237 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_H), (u64tmp >> 16) & 0xff);
5238 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5239
5240 if( !stEVDBaseAddInfo->bProgressive )
5241 { //UV offset of bottom field if interlace
5242 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L), u64tmp & 0xff);
5243 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
5244 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_H), (u64tmp >> 16) & 0xff);
5245 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5246 }
5247
5248 //----------------------------------------------------
5249 // Set MSB YUV Address
5250 //----------------------------------------------------
5251 if(stEVDBaseAddInfo->bEnLSB)
5252 {
5253 //Enable LSB
5254 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 1, VOP_EVD_10B_Y_EN);
5255 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 1, VOP_EVD_10B_UV_EN);
5256 HAL_WriteRegBit(SUB_REG(VOP_REG_MASK), 0, VOP_LSB_REQ_MASK);
5257
5258 // Y offset
5259 u64tmp = stEVDBaseAddInfo->u32LSBYOffset >> 3;
5260 if ( !stEVDBaseAddInfo->bProgressive)
5261 { //Refine Y offset for interlace repeat bottom field
5262 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
5263 {
5264 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5265 u64tmp += 2;
5266 }
5267 else
5268 {
5269 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5270 }
5271 }
5272 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR0_L), u64tmp & 0xff);
5273 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR0_L+1), (u64tmp >> 8) & 0xff);
5274 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR0_L), (u64tmp >> 16) & 0xff);
5275 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR0_L+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5276
5277 if (!stEVDBaseAddInfo->bProgressive )
5278 { //Y offset of bottom field if interlace
5279 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR1_L), u64tmp & 0xff);
5280 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR1_L+1), (u64tmp >> 8) & 0xff);
5281 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR1_H), (u64tmp >> 16) & 0xff);
5282 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5283 }
5284
5285 if (stEVDBaseAddInfo->b422Pack)
5286 {
5287 stEVDBaseAddInfo->u32LSBUVOffset = stEVDBaseAddInfo->u32LSBYOffset + 16; //add 16 for 128bit; add 8 for 64bit
5288 }
5289 // UV offset
5290 u64tmp = stEVDBaseAddInfo->u32LSBUVOffset >> 3;
5291 if( !stEVDBaseAddInfo->bProgressive )
5292 { //Refine UV offset for interlace repeat bottom field
5293 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
5294 {
5295 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5296 u64tmp += 2;
5297 }
5298 else
5299 {
5300 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5301 }
5302 }
5303 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR0_L), u64tmp & 0xff);
5304 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
5305 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR0_H), (u64tmp >> 16) & 0xff);
5306 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5307
5308 if( !stEVDBaseAddInfo->bProgressive )
5309 { //UV offset of bottom field if interlace
5310 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR1_L), u64tmp & 0xff);
5311 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
5312 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR1_H), (u64tmp >> 16) & 0xff);
5313 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5314 }
5315 }
5316
5317 return TRUE;
5318 }
5319
HAL_MVOP_SubCheckSTCCW(void)5320 MS_BOOL HAL_MVOP_SubCheckSTCCW(void)
5321 {
5322 MS_U16 u16STC_CW_L = 0;
5323 MS_U16 u16STC_CW_H = 0;
5324 MS_BOOL u16STC_CW_SEL = 0;
5325 MS_BOOL u16TSP_CLK_EN = 0;
5326
5327 u16STC_CW_L = HAL_Read2Byte(REG_STC1_CW_L)&0xffff;
5328 u16STC_CW_H = HAL_Read2Byte(REG_STC1_CW_H)&0xffff;
5329
5330 u16STC_CW_SEL = (HAL_ReadRegBit(REG_STC_CW_SLE_H, BIT1) == BIT1);
5331 u16TSP_CLK_EN = !(HAL_ReadRegBit(REG_TSP_CLK, BIT0) == BIT0);
5332
5333 if((((u16STC_CW_L || u16STC_CW_H) == 0) && (u16STC_CW_SEL == 0)) || ((u16STC_CW_SEL == 1) && (u16TSP_CLK_EN == 0)))
5334 return FALSE;
5335 else
5336 return TRUE;
5337 }
5338
HAL_MVOP_SubSetVSyncMode(MS_U8 u8Mode)5339 void HAL_MVOP_SubSetVSyncMode(MS_U8 u8Mode)
5340 {
5341 if (g_pHalMVOPCtx == NULL)
5342 {
5343 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5344 return;
5345 }
5346 if (1==u8Mode)
5347 {
5348 g_pHalMVOPCtx->bSubNewVSyncMode = TRUE;
5349 }
5350 else
5351 {
5352 g_pHalMVOPCtx->bSubNewVSyncMode = FALSE;
5353 }
5354 }
5355
HAL_MVOP_SubSet3DLRAltOutput_VHalfScaling(MS_BOOL bEnable)5356 MS_BOOL HAL_MVOP_SubSet3DLRAltOutput_VHalfScaling(MS_BOOL bEnable)
5357 {
5358 MS_BOOL bEnDualBuff = bEnable ? ENABLE : DISABLE; //enable dual buffer
5359 MS_BOOL bEnSWDualBuff = bEnable ? DISABLE : ENABLE; //buffer controlled by HK instead of FW
5360 MS_BOOL bEnMirrMaskBase = bEnable ? DISABLE : ENABLE; //do not mask LSB
5361 MS_BOOL bEnHwFldBase = bEnable ? DISABLE : ENABLE; //hardware calculate field jump base address
5362 if (g_pHalMVOPCtx == NULL)
5363 {
5364 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5365 return FALSE;
5366 }
5367 //Set 0x27[2] = 1 (enable SW dual buffer mode)
5368 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), bEnDualBuff, VOP_BUF_DUAL);
5369
5370 //Set 0x38[8] = 0 (use SW dual buffer mode)
5371 HAL_WriteRegBit(SUB_REG(VOP_INFO_FROM_CODEC_H), bEnSWDualBuff, VOP_INFO_FROM_CODEC_DUAL_BUFF);
5372
5373 //Set 0x3b[7] = 0 (use MVD/HVD firmware send base)
5374 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bEnMirrMaskBase, VOP_MASK_BASE_LSB);
5375
5376 //Set 0x3b[5] = 0 (hardware calculate field jump base address)
5377 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bEnHwFldBase, VOP_HW_FLD_BASE);
5378 g_pHalMVOPCtx->bSub3DLRAltOutput = bEnable;
5379 return TRUE;
5380 }
5381
HAL_MVOP_SubSet3DLRAltOutput(MS_BOOL bEnable)5382 MS_BOOL HAL_MVOP_SubSet3DLRAltOutput(MS_BOOL bEnable)
5383 {
5384 //Set 0x3C[2] = 1 (enable 3D L/R dual buffer line alternative output)
5385 //it works when 0x3C[0] = 1
5386 HAL_WriteRegBit(SUB_REG(VOP_MULTI_WIN_CFG0), bEnable, VOP_LR_LA_OUT);
5387 // bw saving not support: LA/SBS
5388 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 0, VOP_420_BW_SAVE);
5389 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
5390 HAL_MVOP_LoadReg();
5391
5392 g_pHalMVOPCtx->bSub3DLRAltOutput = bEnable;
5393 return TRUE;
5394 }
5395
HAL_MVOP_SubSet3DLRAltSBSOutput(MS_BOOL bEnable)5396 MS_BOOL HAL_MVOP_SubSet3DLRAltSBSOutput(MS_BOOL bEnable)
5397 {
5398 //it works when 0x3C[0] = 1 and 0x3C[2] = 1
5399 //Set 0x3C[3] = 1 (3D L/R line alternative read, side-by-side output)
5400 HAL_WriteRegBit(SUB_REG(VOP_MULTI_WIN_CFG0), bEnable, VOP_LR_LA2SBS_OUT);
5401 g_pHalMVOPCtx->bSub3DLRAltSBSOutput = bEnable;
5402 return TRUE;
5403 }
5404
HAL_MVOP_SubGet3DLRAltOutput(void)5405 MS_BOOL HAL_MVOP_SubGet3DLRAltOutput(void)
5406 {
5407 if (g_pHalMVOPCtx == NULL)
5408 {
5409 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5410 return FALSE;
5411 }
5412 return g_pHalMVOPCtx->bSub3DLRAltOutput;
5413 }
5414
HAL_MVOP_SubGet3DLRAltSBSOutput(void)5415 MS_BOOL HAL_MVOP_SubGet3DLRAltSBSOutput(void)
5416 {
5417 return g_pHalMVOPCtx->bSub3DLRAltSBSOutput;
5418 }
5419
HAL_MVOP_SubGetOutput3DType(void)5420 EN_MVOP_Output_3D_TYPE HAL_MVOP_SubGetOutput3DType(void)
5421 {
5422 EN_MVOP_Output_3D_TYPE en3DType = E_MVOP_OUTPUT_3D_NONE;
5423 if(g_pHalMVOPCtx->bSub3DLRMode)
5424 {
5425 if(g_pHalMVOPCtx->bSub3DLRAltSBSOutput)
5426 {
5427 en3DType = E_MVOP_OUTPUT_3D_SBS;
5428 }
5429 else
5430 {
5431 en3DType = E_MVOP_OUTPUT_3D_TB;
5432 }
5433 }
5434 else if(g_pHalMVOPCtx->bSub3DLRAltOutput)
5435 {
5436 en3DType = E_MVOP_OUTPUT_3D_LA;
5437 }
5438 return en3DType;
5439 }
5440
5441 #ifdef UFO_MVOP_DOLBY_HDR
HAL_MVOP_SubEnableHDRSetting(MS_BOOL bEnable)5442 void HAL_MVOP_SubEnableHDRSetting(MS_BOOL bEnable)
5443 {
5444 HAL_WriteRegBit(SUB_REG(VOP_REG_YC422_EN_H), bEnable, BIT0);
5445 HAL_WriteRegBit(SUB_REG(VOP_REG_HS_OUTPUT), bEnable, VOP_HS_MODE);
5446 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), bEnable, BIT4);
5447 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, VOP_HK_MASK); //bk background
5448 if(bEnable)
5449 {
5450 HAL_WriteRegBit(SUB_REG(VOP_REG_YC422_EN_H), 0, VOP_FRAME_RST); // for Dolby crop
5451 }
5452 g_pHalMVOPCtx->bSubIsHS = bEnable;
5453 if(g_pHalMVOPCtx->bMirrorModeVer)
5454 {
5455 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bEnable, VOP_MIRROR_CFG_VEN);
5456 g_pHalMVOPCtx->bSubMirrorModeVer = bEnable;
5457 }
5458 if(g_pHalMVOPCtx->bMirrorModeHor)
5459 {
5460 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bEnable, VOP_MIRROR_CFG_HEN);
5461 g_pHalMVOPCtx->bSubMirrorModeHor = bEnable;
5462 }
5463 }
5464 #endif
5465
5466 #endif
5467
5468
5469 #define MVOP_INT_UF BIT0
5470 #define MVOP_INT_OF BIT1
5471 #define MVOP_INT_VSYNC BIT2
5472 #define MVOP_INT_HSYNC BIT3
5473 #define MVOP_INT_RDY BIT4
5474 #define MVOP_INT_FLD BIT5
5475 #define MVOP_INT_ALL (BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
5476
5477 const MS_U16 u16MvopRegBase[2] = { MVOP_REG_BASE, MVOP_SUB_REG_BASE};
5478 #define MAP_REG(_id, _reg) ((_reg) - MVOP_REG_BASE + u16MvopRegBase[(_id)])
5479
HAL_MVOP_IntEnableMask(MVOP_DevID eID,MS_U8 eIntType)5480 MS_BOOL HAL_MVOP_IntEnableMask(MVOP_DevID eID, MS_U8 eIntType)
5481 {
5482 MS_BOOL bRet = TRUE;
5483 MS_U16 u16Reg = MAP_REG( eID, VOP_INT_MASK);
5484 MS_U8 u8Mask = 0;
5485
5486 u8Mask = HAL_ReadByte(u16Reg);
5487
5488 if (E_MVOP_INT_NONE != eIntType)
5489 {
5490 u8Mask = (E_MVOP_INT_VSYNC == (eIntType&E_MVOP_INT_VSYNC)) ?
5491 (u8Mask & ~MVOP_INT_VSYNC) : (u8Mask);
5492 u8Mask = (E_MVOP_INT_HSYNC == (eIntType&E_MVOP_INT_HSYNC)) ?
5493 (u8Mask & ~MVOP_INT_HSYNC) : (u8Mask);
5494 u8Mask = (E_MVOP_INT_FDCHNG == (eIntType&E_MVOP_INT_FDCHNG)) ?
5495 (u8Mask & ~MVOP_INT_FLD) : (u8Mask);
5496 u8Mask = (E_MVOP_INT_RDY == (eIntType&E_MVOP_INT_RDY)) ?
5497 (u8Mask & ~MVOP_INT_RDY) : (u8Mask);
5498 u8Mask = (E_MVOP_INT_BUFF_UF == (eIntType&E_MVOP_INT_BUFF_UF)) ?
5499 (u8Mask & ~MVOP_INT_UF) : (u8Mask);
5500 u8Mask = (E_MVOP_INT_BUFF_OF == (eIntType&E_MVOP_INT_BUFF_OF)) ?
5501 (u8Mask & ~MVOP_INT_OF) : (u8Mask);
5502 }
5503 else //mask all
5504 {
5505 u8Mask |= MVOP_INT_ALL;
5506 }
5507
5508 //MVOP_PRINTF("u8Mask %x ", u8Mask);
5509 HAL_WriteByteMask(u16Reg, u8Mask, MVOP_INT_ALL);
5510 //u8Mask = HAL_ReadByte(u16Reg);
5511 //MVOP_PRINTF("==> %x \n", u8Mask);
5512 return bRet;
5513 }
5514
HAL_MVOP_IntGetStatus(MVOP_DevID eID)5515 MS_U8 HAL_MVOP_IntGetStatus(MVOP_DevID eID)
5516 {
5517 MS_U8 u8IntVal = 0;
5518 MS_U8 u8IntType = E_MVOP_INT_NONE;
5519 MS_U16 u16Reg = MAP_REG(eID, (VOP_INT_MASK+1));
5520
5521 u8IntVal = HAL_ReadByte(u16Reg) & MVOP_INT_ALL;
5522 //MVOP_PRINTF("u8IntVal %x\n", u8IntVal);
5523 if ((u8IntVal & MVOP_INT_VSYNC) == MVOP_INT_VSYNC)
5524 {
5525 u8IntType |= E_MVOP_INT_VSYNC;
5526 }
5527 if ((u8IntVal & MVOP_INT_HSYNC) == MVOP_INT_HSYNC)
5528 {
5529 u8IntType |= E_MVOP_INT_HSYNC;
5530 }
5531 if ((u8IntVal & MVOP_INT_FLD) == MVOP_INT_FLD)
5532 {
5533 u8IntType |= E_MVOP_INT_FDCHNG;
5534 }
5535 if ((u8IntVal & MVOP_INT_RDY) == MVOP_INT_RDY)
5536 {
5537 u8IntType |= E_MVOP_INT_RDY;
5538 }
5539 if ((u8IntVal & MVOP_INT_UF) == MVOP_INT_UF)
5540 {
5541 u8IntType |= E_MVOP_INT_BUFF_UF;
5542 }
5543 if ((u8IntVal & MVOP_INT_OF) == MVOP_INT_OF)
5544 {
5545 u8IntType |= E_MVOP_INT_BUFF_OF;
5546 }
5547 return u8IntType;
5548 }
5549
5550
5551