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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regMSPI.h 98 /// @brief Master SPI Register Definition 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_MSPI_H_ 103 #define _REG_MSPI_H_ 104 105 //------------------------------------------------------------------------------------------------- 106 // Include File 107 //------------------------------------------------------------------------------------------------- 108 109 //------------------------------------------------------------------------------------------------- 110 // Hardware Capability 111 //------------------------------------------------------------------------------------------------- 112 113 //------------------------------------------------------------------------------------------------- 114 // Macro and Define 115 //------------------------------------------------------------------------------------------------- 116 // BASEADDR & BK 117 #define BASEADDR_RIU 0xBF000000 118 119 // BASEADDR & BK 120 #define BK_MSP 0x1300*2 121 #define BK_MSP1 0x0C00*2 122 #define BK_CLK0 0xB00*2 123 124 #define MSPI_REG_BASE 0x200 125 #define MSPI_WRITE_BUF_OFFSET 0x40 126 #define MSPI_READ_BUF_OFFSET 0x44 127 #define MSPI_WBF_SIZE_OFFSET 0x48 128 #define MSPI_RBF_SIZE_OFFSET 0x48 129 // read/ write buffer size 130 #define MSPI_RWSIZE_MASK 0xFF 131 #define MSPI_RSIZE_BIT_OFFSET 0x8 132 #define MAX_READ_BUF_SIZE 0x7 133 #define MAX_WRITE_BUF_SIZE 0x7 134 // CLK config 135 #define MSPI_CTRL_OFFSET 0x49 136 #define MSPI_CLK_CLOCK_OFFSET 0x49 137 #define MSPI_CLK_CLOCK_BIT_OFFSET 0x08 138 #define MSPI_CLK_CLOCK_MASK 0xFF 139 #define MSPI_CLK_PHASE_MASK 0x40 140 #define MSPI_CLK_PHASE_BIT_OFFSET 0x06 141 #define MSPI_CLK_POLARITY_MASK 0x80 142 #define MSPI_CLK_POLARITY_BIT_OFFSET 0x07 143 #define MSPI_CLK_PHASE_MAX 0x1 144 #define MSPI_CLK_POLARITY_MAX 0x1 145 #define MSPI_CLK_CLOCK_MAX 0x7 146 // DC config 147 #define MSPI_DC_MASK 0xFF 148 #define MSPI_DC_BIT_OFFSET 0x08 149 #define MSPI_DC_TR_START_OFFSET 0x4A 150 #define MSPI_DC_TRSTART_MAX 0xFF 151 #define MSPI_DC_TR_END_OFFSET 0x4A 152 #define MSPI_DC_TREND_MAX 0xFF 153 #define MSPI_DC_TB_OFFSET 0x4B 154 #define MSPI_DC_TB_MAX 0xFF 155 #define MSPI_DC_TRW_OFFSET 0x4B 156 #define MSPI_DC_TRW_MAX 0xFF 157 // Frame Config 158 #define MSPI_FRAME_WBIT_OFFSET 0x4C 159 #define MSPI_FRAME_RBIT_OFFSET 0x4E 160 #define MSPI_FRAME_BIT_MAX 0x07 161 #define MSPI_FRAME_BIT_MASK 0x07 162 #define MSPI_FRAME_BIT_FIELD 0x03 163 #define MSPI_LSB_FIRST_OFFSET 0x50 164 #define MSPI_TRIGGER_OFFSET 0x5A 165 #define MSPI_DONE_OFFSET 0x5B 166 #define MSPI_DONE_CLEAR_OFFSET 0x5C 167 #define MSPI_CHIP_SELECT_OFFSET 0x5F 168 //chip select bit map 169 #define MSPI_CHIP_SELECT_MAX 0x07 170 // control bit 171 #define MSPI_DONE_FLAG 0x01 172 #define MSPI_TRIGGER 0x01 173 #define MSPI_CLEAR_DONE 0x01 174 #define MSPI_INT_ENABLE 0x04 175 #define MSPI_RESET 0x02 176 #define MSPI_ENABLE 0x01 177 178 // CLKGEN0 179 #define MSPI_CLK_CFG 0x16 180 #define MSPI_CLK_CFG_OFFSET 0x0A 181 #define MSPI_CLK_MASK 0x1FFF 182 #define MSPI_MAXCLKLEVEL 0x03 183 #endif // _REG_MSPI_H_ 184 185