xref: /utopia/UTPA2-700.0.x/modules/mspi/hal/k6/mspi/halMSPI.c (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
1*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
2*53ee8cc1Swenshuai.xi //
3*53ee8cc1Swenshuai.xi // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
4*53ee8cc1Swenshuai.xi // All rights reserved.
5*53ee8cc1Swenshuai.xi //
6*53ee8cc1Swenshuai.xi // Unless otherwise stipulated in writing, any and all information contained
7*53ee8cc1Swenshuai.xi // herein regardless in any format shall remain the sole proprietary of
8*53ee8cc1Swenshuai.xi // MStar Semiconductor Inc. and be kept in strict confidence
9*53ee8cc1Swenshuai.xi // ("MStar Confidential Information") by the recipient.
10*53ee8cc1Swenshuai.xi // Any unauthorized act including without limitation unauthorized disclosure,
11*53ee8cc1Swenshuai.xi // copying, use, reproduction, sale, distribution, modification, disassembling,
12*53ee8cc1Swenshuai.xi // reverse engineering and compiling of the contents of MStar Confidential
13*53ee8cc1Swenshuai.xi // Information is unlawful and strictly prohibited. MStar hereby reserves the
14*53ee8cc1Swenshuai.xi // rights to any and all damages, losses, costs and expenses resulting therefrom.
15*53ee8cc1Swenshuai.xi //
16*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
17*53ee8cc1Swenshuai.xi 
18*53ee8cc1Swenshuai.xi ///////////////////////////////////////////////////////////////////////////////////////////////////
19*53ee8cc1Swenshuai.xi ///
20*53ee8cc1Swenshuai.xi /// file    halMSPI.c
21*53ee8cc1Swenshuai.xi /// @brief  Master SPI Driver Interface
22*53ee8cc1Swenshuai.xi /// @author MStar Semiconductor Inc.
23*53ee8cc1Swenshuai.xi ///////////////////////////////////////////////////////////////////////////////////////////////////
24*53ee8cc1Swenshuai.xi 
25*53ee8cc1Swenshuai.xi 
26*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
27*53ee8cc1Swenshuai.xi //  Include Files
28*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
29*53ee8cc1Swenshuai.xi #include "MsCommon.h"
30*53ee8cc1Swenshuai.xi #include "MsTypes.h"
31*53ee8cc1Swenshuai.xi #include "halMSPI.h"
32*53ee8cc1Swenshuai.xi #include "regMSPI.h"
33*53ee8cc1Swenshuai.xi 
34*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
35*53ee8cc1Swenshuai.xi //  Local Defines
36*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
37*53ee8cc1Swenshuai.xi #define MSP_READ(addr)                      READ_WORD(_hal_msp.VirtMspBaseAddr + ((addr)<<2))
38*53ee8cc1Swenshuai.xi #define MSP_WRITE(addr, val)                WRITE_WORD(_hal_msp.VirtMspBaseAddr + ((addr)<<2), (val))
39*53ee8cc1Swenshuai.xi #define CLK_READ(addr)                      READ_WORD(_hal_msp.VirtClkBaseAddr + ((addr)<<2))
40*53ee8cc1Swenshuai.xi #define CLK_WRITE(addr, val)                WRITE_WORD(_hal_msp.VirtClkBaseAddr + ((addr)<<2), (val))
41*53ee8cc1Swenshuai.xi #define _HAL_MSPI_Trigger()                 MSP_WRITE(MSPI_TRIGGER_OFFSET,MSPI_TRIGGER)
42*53ee8cc1Swenshuai.xi #define _HAL_MSPI_ClearDone()               MSP_WRITE(MSPI_DONE_CLEAR_OFFSET,MSPI_CLEAR_DONE)
43*53ee8cc1Swenshuai.xi #define MAX_CHECK_CNT                       2000
44*53ee8cc1Swenshuai.xi #define DEBUG_HAL_MSPI(debug_level, x)     do { if (_u8HalMSPIDbgLevel >= (debug_level)) (x); } while(0)
45*53ee8cc1Swenshuai.xi 
46*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
47*53ee8cc1Swenshuai.xi //  Local Structures
48*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
49*53ee8cc1Swenshuai.xi typedef struct
50*53ee8cc1Swenshuai.xi {
51*53ee8cc1Swenshuai.xi     MS_VIRT VirtMspBaseAddr;
52*53ee8cc1Swenshuai.xi     MS_VIRT VirtClkBaseAddr;
53*53ee8cc1Swenshuai.xi } hal_msp_t;
54*53ee8cc1Swenshuai.xi 
55*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
56*53ee8cc1Swenshuai.xi //  Local Variables
57*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
58*53ee8cc1Swenshuai.xi static hal_msp_t _hal_msp =
59*53ee8cc1Swenshuai.xi {
60*53ee8cc1Swenshuai.xi     .VirtMspBaseAddr = BASEADDR_RIU + BK_MSP,
61*53ee8cc1Swenshuai.xi     .VirtClkBaseAddr = BASEADDR_RIU + BK_CLK0
62*53ee8cc1Swenshuai.xi };
63*53ee8cc1Swenshuai.xi 
64*53ee8cc1Swenshuai.xi static MS_U8 guChipSelect = 0;
65*53ee8cc1Swenshuai.xi MS_U8 _u8HalMSPIDbgLevel;
66*53ee8cc1Swenshuai.xi static MS_BOOL _gbMspiIntEnable;
67*53ee8cc1Swenshuai.xi 
68*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
69*53ee8cc1Swenshuai.xi // Local Functions
70*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
71*53ee8cc1Swenshuai.xi 
72*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
73*53ee8cc1Swenshuai.xi /// Description : Set MSPI read /write buf size in current operation
74*53ee8cc1Swenshuai.xi /// @param Direct \b OUT: read /write operation direction
75*53ee8cc1Swenshuai.xi /// @param Size   \b OUT: size of read /write buffer
76*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
77*53ee8cc1Swenshuai.xi 
_HAL_MSPI_RWBUFSize(MS_BOOL Direct,MS_U8 Size)78*53ee8cc1Swenshuai.xi static void _HAL_MSPI_RWBUFSize(MS_BOOL Direct, MS_U8 Size)
79*53ee8cc1Swenshuai.xi {
80*53ee8cc1Swenshuai.xi     MS_U16 u16Data = 0;
81*53ee8cc1Swenshuai.xi     u16Data = MSP_READ(MSPI_RBF_SIZE_OFFSET);
82*53ee8cc1Swenshuai.xi 
83*53ee8cc1Swenshuai.xi     if(Direct == MSPI_READ_INDEX)
84*53ee8cc1Swenshuai.xi     {
85*53ee8cc1Swenshuai.xi         u16Data &= MSPI_RWSIZE_MASK;
86*53ee8cc1Swenshuai.xi 		u16Data |= Size << MSPI_RSIZE_BIT_OFFSET;
87*53ee8cc1Swenshuai.xi     }
88*53ee8cc1Swenshuai.xi     else
89*53ee8cc1Swenshuai.xi     {
90*53ee8cc1Swenshuai.xi         u16Data &= ~MSPI_RWSIZE_MASK;
91*53ee8cc1Swenshuai.xi         u16Data |= Size;
92*53ee8cc1Swenshuai.xi     }
93*53ee8cc1Swenshuai.xi     MSP_WRITE(MSPI_RBF_SIZE_OFFSET, u16Data);
94*53ee8cc1Swenshuai.xi }
95*53ee8cc1Swenshuai.xi 
96*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
97*53ee8cc1Swenshuai.xi /// Description : SPI chip select enable and disable
98*53ee8cc1Swenshuai.xi /// @param Enable \b OUT: enable or disable chip select
99*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
_HAL_MSPI_ChipSelect(MS_BOOL Enable)100*53ee8cc1Swenshuai.xi static void _HAL_MSPI_ChipSelect(MS_BOOL Enable)
101*53ee8cc1Swenshuai.xi {
102*53ee8cc1Swenshuai.xi     MS_U16 regdata = 0;
103*53ee8cc1Swenshuai.xi 	MS_U8 bitmask = 0;
104*53ee8cc1Swenshuai.xi     regdata = MSP_READ(MSPI_CHIP_SELECT_OFFSET);
105*53ee8cc1Swenshuai.xi     if(Enable)
106*53ee8cc1Swenshuai.xi     {
107*53ee8cc1Swenshuai.xi         bitmask = ~(1 << guChipSelect);
108*53ee8cc1Swenshuai.xi 		regdata &= bitmask;
109*53ee8cc1Swenshuai.xi     }
110*53ee8cc1Swenshuai.xi     else
111*53ee8cc1Swenshuai.xi     {
112*53ee8cc1Swenshuai.xi         bitmask = (1 << guChipSelect);
113*53ee8cc1Swenshuai.xi         regdata |= bitmask;
114*53ee8cc1Swenshuai.xi     }
115*53ee8cc1Swenshuai.xi     MSP_WRITE(MSPI_CHIP_SELECT_OFFSET, regdata);
116*53ee8cc1Swenshuai.xi }
117*53ee8cc1Swenshuai.xi 
118*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
119*53ee8cc1Swenshuai.xi /// Description : check MSPI operation complete
120*53ee8cc1Swenshuai.xi /// @return TRUE :  operation complete
121*53ee8cc1Swenshuai.xi /// @return FAIL : failed timeout
122*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
_HAL_MSPI_CheckDone(void)123*53ee8cc1Swenshuai.xi static MS_BOOL _HAL_MSPI_CheckDone(void)
124*53ee8cc1Swenshuai.xi {
125*53ee8cc1Swenshuai.xi     MS_U16 uCheckDoneCnt = 0;
126*53ee8cc1Swenshuai.xi     MS_U16 uDoneFlag = 0;
127*53ee8cc1Swenshuai.xi     while(uCheckDoneCnt < MAX_CHECK_CNT)
128*53ee8cc1Swenshuai.xi     {
129*53ee8cc1Swenshuai.xi         uDoneFlag = MSP_READ(MSPI_DONE_OFFSET);
130*53ee8cc1Swenshuai.xi         if(uDoneFlag & MSPI_DONE_FLAG)
131*53ee8cc1Swenshuai.xi             return TRUE;
132*53ee8cc1Swenshuai.xi         uCheckDoneCnt++;
133*53ee8cc1Swenshuai.xi     }
134*53ee8cc1Swenshuai.xi     DEBUG_MSPI(E_MSPI_DBGLV_ERR,printf("ERROR:MSPI Operation Timeout!!!!!\n"));
135*53ee8cc1Swenshuai.xi     return FALSE;
136*53ee8cc1Swenshuai.xi }
137*53ee8cc1Swenshuai.xi 
_HAL_MSPI_GetCLK(MS_U16 u16CLK)138*53ee8cc1Swenshuai.xi static MS_U32 _HAL_MSPI_GetCLK(MS_U16 u16CLK)
139*53ee8cc1Swenshuai.xi {
140*53ee8cc1Swenshuai.xi     MS_U32 u32MspiClk = 0;
141*53ee8cc1Swenshuai.xi     switch (u16CLK)
142*53ee8cc1Swenshuai.xi     {
143*53ee8cc1Swenshuai.xi     case 0:
144*53ee8cc1Swenshuai.xi 		u32MspiClk = 108000000;
145*53ee8cc1Swenshuai.xi         return u32MspiClk;
146*53ee8cc1Swenshuai.xi     case 1:
147*53ee8cc1Swenshuai.xi         u32MspiClk = 54000000;
148*53ee8cc1Swenshuai.xi         return u32MspiClk;
149*53ee8cc1Swenshuai.xi     case 2:
150*53ee8cc1Swenshuai.xi         u32MspiClk = 24000000;
151*53ee8cc1Swenshuai.xi         return u32MspiClk;
152*53ee8cc1Swenshuai.xi     case 3:
153*53ee8cc1Swenshuai.xi         u32MspiClk = 11000000;
154*53ee8cc1Swenshuai.xi         return u32MspiClk;
155*53ee8cc1Swenshuai.xi     default:
156*53ee8cc1Swenshuai.xi 		printf("ERROR CLOCK SETTING NOT SUPPORT \r\n");
157*53ee8cc1Swenshuai.xi 		return u32MspiClk;
158*53ee8cc1Swenshuai.xi     }
159*53ee8cc1Swenshuai.xi }
160*53ee8cc1Swenshuai.xi 
161*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
162*53ee8cc1Swenshuai.xi //  Global Functions
163*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
164*53ee8cc1Swenshuai.xi 
165*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
166*53ee8cc1Swenshuai.xi /// Description : MSPI initial
167*53ee8cc1Swenshuai.xi /// @return void :
168*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
HAL_MSPI_Init(void)169*53ee8cc1Swenshuai.xi void HAL_MSPI_Init(void)
170*53ee8cc1Swenshuai.xi {
171*53ee8cc1Swenshuai.xi     MS_U16 TempData;
172*53ee8cc1Swenshuai.xi     //init  MSP
173*53ee8cc1Swenshuai.xi     DEBUG_MSPI(E_MSPI_DBGLV_INFO,printf("HAL_MSPI_Init\n"));
174*53ee8cc1Swenshuai.xi 
175*53ee8cc1Swenshuai.xi     // CLK SETTING
176*53ee8cc1Swenshuai.xi     TempData = CLK_READ(MSPI_CLK_CFG);
177*53ee8cc1Swenshuai.xi     TempData &= ~(MSPI_CLK_MASK);                    //use "~" instead of "!" for coverity issue
178*53ee8cc1Swenshuai.xi     CLK_WRITE(MSPI_CLK_CFG, TempData);
179*53ee8cc1Swenshuai.xi 
180*53ee8cc1Swenshuai.xi 
181*53ee8cc1Swenshuai.xi     if(_gbMspiIntEnable)
182*53ee8cc1Swenshuai.xi     {
183*53ee8cc1Swenshuai.xi         MSP_WRITE(MSPI_CTRL_OFFSET,(MSPI_INT_ENABLE|MSPI_RESET|MSPI_ENABLE));
184*53ee8cc1Swenshuai.xi     }
185*53ee8cc1Swenshuai.xi     else
186*53ee8cc1Swenshuai.xi     {
187*53ee8cc1Swenshuai.xi         MSP_WRITE(MSPI_CTRL_OFFSET,(MSPI_RESET|MSPI_ENABLE));
188*53ee8cc1Swenshuai.xi     }
189*53ee8cc1Swenshuai.xi }
190*53ee8cc1Swenshuai.xi 
191*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
192*53ee8cc1Swenshuai.xi /// Description : MSPI    interrupt enable
193*53ee8cc1Swenshuai.xi /// @param bEnable \b OUT: enable or disable mspi interrupt
194*53ee8cc1Swenshuai.xi /// @return void:
195*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
HAL_MSPI_IntEnable(MS_BOOL bEnable)196*53ee8cc1Swenshuai.xi void HAL_MSPI_IntEnable(MS_BOOL bEnable)
197*53ee8cc1Swenshuai.xi {
198*53ee8cc1Swenshuai.xi     if(bEnable)
199*53ee8cc1Swenshuai.xi         _gbMspiIntEnable = TRUE;
200*53ee8cc1Swenshuai.xi     else
201*53ee8cc1Swenshuai.xi         _gbMspiIntEnable = FALSE;
202*53ee8cc1Swenshuai.xi }
203*53ee8cc1Swenshuai.xi 
204*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
205*53ee8cc1Swenshuai.xi /// Description : Get Max of chip select
206*53ee8cc1Swenshuai.xi /// @param void:
207*53ee8cc1Swenshuai.xi /// @return Max of Chip select
208*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
HAL_MSPI_ChipSelectMax(void)209*53ee8cc1Swenshuai.xi MS_U8 HAL_MSPI_ChipSelectMax(void)
210*53ee8cc1Swenshuai.xi {
211*53ee8cc1Swenshuai.xi     return MSPI_CHIP_SELECT_MAX;
212*53ee8cc1Swenshuai.xi }
213*53ee8cc1Swenshuai.xi 
214*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
215*53ee8cc1Swenshuai.xi /// Description : Set MSPI chip select
216*53ee8cc1Swenshuai.xi /// @param u8CS \u8 OUT: MSPI chip select
217*53ee8cc1Swenshuai.xi /// @return void:
218*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
HAL_MSPI_SetChipSelect(MS_U8 u8CS)219*53ee8cc1Swenshuai.xi void HAL_MSPI_SetChipSelect(MS_U8 u8CS)
220*53ee8cc1Swenshuai.xi {
221*53ee8cc1Swenshuai.xi     guChipSelect = u8CS;
222*53ee8cc1Swenshuai.xi }
223*53ee8cc1Swenshuai.xi 
224*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
225*53ee8cc1Swenshuai.xi /// Description : Config MSP MMIO base address
226*53ee8cc1Swenshuai.xi /// @param u32PMBankBaseAddr \b IN :base address of MMIO (PM domain)
227*53ee8cc1Swenshuai.xi /// @param u32NONPMRegBaseAddr \b IN :base address of MMIO
228*53ee8cc1Swenshuai.xi /// @param u8DeviceIndex \b IN: index of HW IP
229*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
HAL_MSPI_MMIOConfig(MS_U32 u32PMBankBaseAddr,MS_U32 u32NONPMRegBaseAddr,MS_U8 u8DeviceIndex)230*53ee8cc1Swenshuai.xi void HAL_MSPI_MMIOConfig(MS_U32 u32PMBankBaseAddr, MS_U32 u32NONPMRegBaseAddr, MS_U8 u8DeviceIndex)
231*53ee8cc1Swenshuai.xi {
232*53ee8cc1Swenshuai.xi     DEBUG_MSPI(E_MSPI_DBGLV_INFO,printf("%s(0x%08X)\n", __FUNCTION__, (int)u32NONPMRegBaseAddr));
233*53ee8cc1Swenshuai.xi     if(u8DeviceIndex)
234*53ee8cc1Swenshuai.xi         _hal_msp.VirtMspBaseAddr = u32NONPMRegBaseAddr + BK_MSP1;
235*53ee8cc1Swenshuai.xi     else
236*53ee8cc1Swenshuai.xi         _hal_msp.VirtMspBaseAddr = u32NONPMRegBaseAddr + BK_MSP;
237*53ee8cc1Swenshuai.xi     _hal_msp.VirtClkBaseAddr = u32NONPMRegBaseAddr + BK_CLK0;
238*53ee8cc1Swenshuai.xi }
239*53ee8cc1Swenshuai.xi 
240*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
241*53ee8cc1Swenshuai.xi /// Description : read data from MSPI
242*53ee8cc1Swenshuai.xi /// @param pData \b IN :pointer to receive data from MSPI read buffer
243*53ee8cc1Swenshuai.xi /// @param u16Size \ b OTU : read data size
244*53ee8cc1Swenshuai.xi /// @return TRUE  : read data success
245*53ee8cc1Swenshuai.xi /// @return FALSE : read data fail
246*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
HAL_MSPI_Read(MS_U8 * pData,MS_U16 u16Size)247*53ee8cc1Swenshuai.xi MS_BOOL HAL_MSPI_Read(MS_U8 *pData, MS_U16 u16Size)
248*53ee8cc1Swenshuai.xi {
249*53ee8cc1Swenshuai.xi     MS_U8  u8Index = 0;
250*53ee8cc1Swenshuai.xi 	MS_U16  u16TempBuf = 0;
251*53ee8cc1Swenshuai.xi     MS_U16 i =0, j = 0;
252*53ee8cc1Swenshuai.xi 
253*53ee8cc1Swenshuai.xi     for(i = 0; i < u16Size; i+= MAX_READ_BUF_SIZE)
254*53ee8cc1Swenshuai.xi     {
255*53ee8cc1Swenshuai.xi         u16TempBuf = u16Size - i;
256*53ee8cc1Swenshuai.xi         if(u16TempBuf > MAX_READ_BUF_SIZE)
257*53ee8cc1Swenshuai.xi         {
258*53ee8cc1Swenshuai.xi             j = MAX_READ_BUF_SIZE;
259*53ee8cc1Swenshuai.xi 		}
260*53ee8cc1Swenshuai.xi 		else
261*53ee8cc1Swenshuai.xi         {
262*53ee8cc1Swenshuai.xi             j = u16TempBuf;
263*53ee8cc1Swenshuai.xi         }
264*53ee8cc1Swenshuai.xi         _HAL_MSPI_RWBUFSize(MSPI_READ_INDEX, j);
265*53ee8cc1Swenshuai.xi 
266*53ee8cc1Swenshuai.xi         HAL_MSPI_Trigger();
267*53ee8cc1Swenshuai.xi         DEBUG_MSPI(E_MSPI_DBGLV_DEBUG,printf("Read Size %x\n",j));
268*53ee8cc1Swenshuai.xi         for(u8Index = 0; u8Index < j; u8Index++)
269*53ee8cc1Swenshuai.xi         {
270*53ee8cc1Swenshuai.xi 
271*53ee8cc1Swenshuai.xi             if(u8Index & 1)
272*53ee8cc1Swenshuai.xi             {
273*53ee8cc1Swenshuai.xi                 u16TempBuf = MSP_READ((MSPI_READ_BUF_OFFSET + (u8Index >> 1)));
274*53ee8cc1Swenshuai.xi                 DEBUG_MSPI(E_MSPI_DBGLV_DEBUG,printf("read Buf data %x index %d\n",u16TempBuf, u8Index));
275*53ee8cc1Swenshuai.xi                 pData[u8Index] = u16TempBuf >> 8;
276*53ee8cc1Swenshuai.xi 			    pData[u8Index-1] = u16TempBuf & 0xFF;
277*53ee8cc1Swenshuai.xi             }
278*53ee8cc1Swenshuai.xi             else if(u8Index == (j -1))
279*53ee8cc1Swenshuai.xi             {
280*53ee8cc1Swenshuai.xi                 u16TempBuf = MSP_READ((MSPI_READ_BUF_OFFSET + (u8Index >> 1)));
281*53ee8cc1Swenshuai.xi                 DEBUG_MSPI(E_MSPI_DBGLV_DEBUG,printf("read Buf data %x index %d\n",u16TempBuf, u8Index));
282*53ee8cc1Swenshuai.xi 			    pData[u8Index] = u16TempBuf & 0xFF;
283*53ee8cc1Swenshuai.xi             }
284*53ee8cc1Swenshuai.xi         }
285*53ee8cc1Swenshuai.xi         pData+= j;
286*53ee8cc1Swenshuai.xi     }
287*53ee8cc1Swenshuai.xi     return TRUE;
288*53ee8cc1Swenshuai.xi }
289*53ee8cc1Swenshuai.xi 
290*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
291*53ee8cc1Swenshuai.xi /// Description : read data from MSPI
292*53ee8cc1Swenshuai.xi /// @param pData \b OUT :pointer to write  data to MSPI write buffer
293*53ee8cc1Swenshuai.xi /// @param u16Size \ b OTU : write data size
294*53ee8cc1Swenshuai.xi /// @return TRUE  : write data success
295*53ee8cc1Swenshuai.xi /// @return FALSE : wirte data fail
296*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
HAL_MSPI_Wirte(MS_U8 * pData,MS_U16 u16Size)297*53ee8cc1Swenshuai.xi MS_BOOL HAL_MSPI_Wirte(MS_U8 *pData, MS_U16 u16Size)
298*53ee8cc1Swenshuai.xi {
299*53ee8cc1Swenshuai.xi     MS_U8  u8Index = 0;
300*53ee8cc1Swenshuai.xi     MS_U16 u16TempBuf = 0;
301*53ee8cc1Swenshuai.xi     MS_U16 i =0, j = 0;
302*53ee8cc1Swenshuai.xi     for(i = 0; i < u16Size; i+= MAX_WRITE_BUF_SIZE)
303*53ee8cc1Swenshuai.xi     {
304*53ee8cc1Swenshuai.xi         u16TempBuf = u16Size - i;
305*53ee8cc1Swenshuai.xi         if(u16TempBuf > MAX_WRITE_BUF_SIZE)
306*53ee8cc1Swenshuai.xi         {
307*53ee8cc1Swenshuai.xi             j = MAX_WRITE_BUF_SIZE;
308*53ee8cc1Swenshuai.xi 		}
309*53ee8cc1Swenshuai.xi 		else
310*53ee8cc1Swenshuai.xi         {
311*53ee8cc1Swenshuai.xi             j = u16TempBuf;
312*53ee8cc1Swenshuai.xi         }
313*53ee8cc1Swenshuai.xi         DEBUG_MSPI(E_MSPI_DBGLV_DEBUG,printf("Write Size %x\n",j));
314*53ee8cc1Swenshuai.xi         for(u8Index = 0; u8Index < j; u8Index++)
315*53ee8cc1Swenshuai.xi         {
316*53ee8cc1Swenshuai.xi             if(u8Index & 1)
317*53ee8cc1Swenshuai.xi             {
318*53ee8cc1Swenshuai.xi                 u16TempBuf = (pData[u8Index] << 8) | pData[u8Index-1];
319*53ee8cc1Swenshuai.xi                 DEBUG_MSPI(E_MSPI_DBGLV_DEBUG,printf("write Buf data %x index %d\n",u16TempBuf, u8Index));
320*53ee8cc1Swenshuai.xi                 MSP_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),u16TempBuf);
321*53ee8cc1Swenshuai.xi             }
322*53ee8cc1Swenshuai.xi             else if(u8Index == (j -1))
323*53ee8cc1Swenshuai.xi             {
324*53ee8cc1Swenshuai.xi                 DEBUG_MSPI(E_MSPI_DBGLV_DEBUG,printf("write Buf data %x index %d\n",pData[u8Index], u8Index));
325*53ee8cc1Swenshuai.xi                 MSP_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),pData[u8Index]);
326*53ee8cc1Swenshuai.xi             }
327*53ee8cc1Swenshuai.xi         }
328*53ee8cc1Swenshuai.xi 		pData += j;
329*53ee8cc1Swenshuai.xi         _HAL_MSPI_RWBUFSize(MSPI_WRITE_INDEX, j);
330*53ee8cc1Swenshuai.xi         HAL_MSPI_Trigger();
331*53ee8cc1Swenshuai.xi     }
332*53ee8cc1Swenshuai.xi         // set write data size
333*53ee8cc1Swenshuai.xi 
334*53ee8cc1Swenshuai.xi     return TRUE;
335*53ee8cc1Swenshuai.xi }
336*53ee8cc1Swenshuai.xi 
337*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
338*53ee8cc1Swenshuai.xi /// Description : Reset  DC register setting of MSPI
339*53ee8cc1Swenshuai.xi /// @param NONE
340*53ee8cc1Swenshuai.xi /// @return TRUE  : reset complete
341*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
HAL_MSPI_Reset_DCConfig(void)342*53ee8cc1Swenshuai.xi MS_BOOL HAL_MSPI_Reset_DCConfig(void)
343*53ee8cc1Swenshuai.xi {
344*53ee8cc1Swenshuai.xi 	//DC reset
345*53ee8cc1Swenshuai.xi     MSP_WRITE(MSPI_DC_TR_START_OFFSET, 0x00);
346*53ee8cc1Swenshuai.xi     MSP_WRITE(MSPI_DC_TB_OFFSET, 0x00);
347*53ee8cc1Swenshuai.xi 	return TRUE;
348*53ee8cc1Swenshuai.xi }
349*53ee8cc1Swenshuai.xi 
350*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
351*53ee8cc1Swenshuai.xi /// Description : Reset  Frame register setting of MSPI
352*53ee8cc1Swenshuai.xi /// @param NONE
353*53ee8cc1Swenshuai.xi /// @return TRUE  : reset complete
354*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
HAL_MSPI_Reset_FrameConfig(void)355*53ee8cc1Swenshuai.xi MS_BOOL HAL_MSPI_Reset_FrameConfig(void)
356*53ee8cc1Swenshuai.xi {
357*53ee8cc1Swenshuai.xi     // Frame reset
358*53ee8cc1Swenshuai.xi     MSP_WRITE(MSPI_FRAME_WBIT_OFFSET, 0xFFF);
359*53ee8cc1Swenshuai.xi 	MSP_WRITE(MSPI_FRAME_WBIT_OFFSET+2, 0xFFF);
360*53ee8cc1Swenshuai.xi 	MSP_WRITE(MSPI_FRAME_RBIT_OFFSET, 0xFFF);
361*53ee8cc1Swenshuai.xi 	MSP_WRITE(MSPI_FRAME_RBIT_OFFSET+2, 0xFFF);
362*53ee8cc1Swenshuai.xi 	return TRUE;
363*53ee8cc1Swenshuai.xi }
364*53ee8cc1Swenshuai.xi 
365*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
366*53ee8cc1Swenshuai.xi /// Description : Reset  CLK register setting of MSPI
367*53ee8cc1Swenshuai.xi /// @param NONE
368*53ee8cc1Swenshuai.xi /// @return TRUE  : reset complete
369*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
HAL_MSPI_Reset_CLKConfig(void)370*53ee8cc1Swenshuai.xi MS_BOOL HAL_MSPI_Reset_CLKConfig(void)
371*53ee8cc1Swenshuai.xi {
372*53ee8cc1Swenshuai.xi     MS_U16 Tempbuf;
373*53ee8cc1Swenshuai.xi 	//reset clock
374*53ee8cc1Swenshuai.xi     Tempbuf = MSP_READ(MSPI_CTRL_OFFSET);
375*53ee8cc1Swenshuai.xi     Tempbuf &= 0x3F;
376*53ee8cc1Swenshuai.xi     MSP_WRITE(MSPI_CTRL_OFFSET, Tempbuf);
377*53ee8cc1Swenshuai.xi 	return TRUE;
378*53ee8cc1Swenshuai.xi }
379*53ee8cc1Swenshuai.xi 
380*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
381*53ee8cc1Swenshuai.xi /// Description : get read/write buffer size
382*53ee8cc1Swenshuai.xi /// @param bDirection    \b OUT   specify to get read/write buffer size
383*53ee8cc1Swenshuai.xi /// @return buffer sizel
384*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
HAL_MSPI_GetBufSize(MS_BOOL bDirection)385*53ee8cc1Swenshuai.xi MS_U8 HAL_MSPI_GetBufSize(MS_BOOL bDirection)
386*53ee8cc1Swenshuai.xi {
387*53ee8cc1Swenshuai.xi     if(bDirection == MSPI_READ_INDEX)
388*53ee8cc1Swenshuai.xi         return MAX_READ_BUF_SIZE;
389*53ee8cc1Swenshuai.xi     else
390*53ee8cc1Swenshuai.xi         return MAX_WRITE_BUF_SIZE;
391*53ee8cc1Swenshuai.xi }
392*53ee8cc1Swenshuai.xi 
393*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
394*53ee8cc1Swenshuai.xi /// Description : Trigger MSPI operation
395*53ee8cc1Swenshuai.xi /// @return TRUE  : operation success
396*53ee8cc1Swenshuai.xi /// @return FALSE : operation timeout
397*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
HAL_MSPI_Trigger(void)398*53ee8cc1Swenshuai.xi MS_BOOL HAL_MSPI_Trigger(void)
399*53ee8cc1Swenshuai.xi {
400*53ee8cc1Swenshuai.xi     // chip select enable
401*53ee8cc1Swenshuai.xi   //  _HAL_MSPI_ChipSelect(TRUE);
402*53ee8cc1Swenshuai.xi 
403*53ee8cc1Swenshuai.xi     // trigger operation
404*53ee8cc1Swenshuai.xi     _HAL_MSPI_Trigger();
405*53ee8cc1Swenshuai.xi     // check operation complete
406*53ee8cc1Swenshuai.xi     if(!_HAL_MSPI_CheckDone())
407*53ee8cc1Swenshuai.xi         return FALSE;
408*53ee8cc1Swenshuai.xi     // clear done flag
409*53ee8cc1Swenshuai.xi     _HAL_MSPI_ClearDone();
410*53ee8cc1Swenshuai.xi     // chip select disable
411*53ee8cc1Swenshuai.xi    // _HAL_MSPI_ChipSelect(FALSE);
412*53ee8cc1Swenshuai.xi     // reset read/write buffer size
413*53ee8cc1Swenshuai.xi     MSP_WRITE(MSPI_RBF_SIZE_OFFSET,0x0);
414*53ee8cc1Swenshuai.xi 	return TRUE;
415*53ee8cc1Swenshuai.xi }
416*53ee8cc1Swenshuai.xi 
HAL_MSPI_SlaveEnable(MS_BOOL Enable)417*53ee8cc1Swenshuai.xi void HAL_MSPI_SlaveEnable(MS_BOOL Enable)
418*53ee8cc1Swenshuai.xi {
419*53ee8cc1Swenshuai.xi      _HAL_MSPI_ChipSelect(Enable);
420*53ee8cc1Swenshuai.xi }
421*53ee8cc1Swenshuai.xi 
422*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
423*53ee8cc1Swenshuai.xi /// Description : get valid range of DC timing
424*53ee8cc1Swenshuai.xi /// @param eDCField    \b OUT enum of DC timing type
425*53ee8cc1Swenshuai.xi /// @return NONE
426*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
HAL_MSPI_DCConfigMax(eDC_config eDCField)427*53ee8cc1Swenshuai.xi MS_U8 HAL_MSPI_DCConfigMax(eDC_config eDCField)
428*53ee8cc1Swenshuai.xi {
429*53ee8cc1Swenshuai.xi     switch(eDCField)
430*53ee8cc1Swenshuai.xi     {
431*53ee8cc1Swenshuai.xi     case E_MSPI_TRSTART:
432*53ee8cc1Swenshuai.xi         return MSPI_DC_TRSTART_MAX;
433*53ee8cc1Swenshuai.xi     case E_MSPI_TREND:
434*53ee8cc1Swenshuai.xi         return MSPI_DC_TREND_MAX;
435*53ee8cc1Swenshuai.xi     case E_MSPI_TB:
436*53ee8cc1Swenshuai.xi         return MSPI_DC_TB_MAX;
437*53ee8cc1Swenshuai.xi     case E_MSPI_TRW:
438*53ee8cc1Swenshuai.xi         return MSPI_DC_TRW_MAX;
439*53ee8cc1Swenshuai.xi     default:
440*53ee8cc1Swenshuai.xi         return 0;
441*53ee8cc1Swenshuai.xi     }
442*53ee8cc1Swenshuai.xi 
443*53ee8cc1Swenshuai.xi }
444*53ee8cc1Swenshuai.xi 
445*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
446*53ee8cc1Swenshuai.xi /// Description : config spi transfer timing
447*53ee8cc1Swenshuai.xi /// @param ptDCConfig    \b OUT  struct pointer of bits of buffer tranferred to slave config
448*53ee8cc1Swenshuai.xi /// @return NONE
449*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
HAL_MSPI_SetDcTiming(eDC_config eDCField,MS_U8 u8DCtiming)450*53ee8cc1Swenshuai.xi void HAL_MSPI_SetDcTiming (eDC_config eDCField, MS_U8 u8DCtiming)
451*53ee8cc1Swenshuai.xi {
452*53ee8cc1Swenshuai.xi    MS_U16 u16TempBuf = 0;
453*53ee8cc1Swenshuai.xi    switch(eDCField)
454*53ee8cc1Swenshuai.xi    {
455*53ee8cc1Swenshuai.xi    case E_MSPI_TRSTART:
456*53ee8cc1Swenshuai.xi        u16TempBuf = MSP_READ(MSPI_DC_TR_START_OFFSET);
457*53ee8cc1Swenshuai.xi        u16TempBuf &= (~MSPI_DC_MASK);
458*53ee8cc1Swenshuai.xi        u16TempBuf |= u8DCtiming;
459*53ee8cc1Swenshuai.xi        MSP_WRITE(MSPI_DC_TR_START_OFFSET, u16TempBuf);
460*53ee8cc1Swenshuai.xi        break;
461*53ee8cc1Swenshuai.xi    case E_MSPI_TREND:
462*53ee8cc1Swenshuai.xi        u16TempBuf = MSP_READ(MSPI_DC_TR_END_OFFSET);
463*53ee8cc1Swenshuai.xi 	   u16TempBuf &= MSPI_DC_MASK;
464*53ee8cc1Swenshuai.xi 	   u16TempBuf |= u8DCtiming << MSPI_DC_BIT_OFFSET;
465*53ee8cc1Swenshuai.xi        MSP_WRITE(MSPI_DC_TR_END_OFFSET, u16TempBuf);
466*53ee8cc1Swenshuai.xi        break;
467*53ee8cc1Swenshuai.xi    case E_MSPI_TB:
468*53ee8cc1Swenshuai.xi        u16TempBuf = MSP_READ(MSPI_DC_TB_OFFSET);
469*53ee8cc1Swenshuai.xi        u16TempBuf &= (~MSPI_DC_MASK);
470*53ee8cc1Swenshuai.xi        u16TempBuf |= u8DCtiming;
471*53ee8cc1Swenshuai.xi        MSP_WRITE(MSPI_DC_TB_OFFSET, u16TempBuf);
472*53ee8cc1Swenshuai.xi        break;
473*53ee8cc1Swenshuai.xi    case E_MSPI_TRW:
474*53ee8cc1Swenshuai.xi        u16TempBuf = MSP_READ(MSPI_DC_TRW_OFFSET);
475*53ee8cc1Swenshuai.xi        u16TempBuf &= MSPI_DC_MASK;
476*53ee8cc1Swenshuai.xi        u16TempBuf |= u8DCtiming << MSPI_DC_BIT_OFFSET;
477*53ee8cc1Swenshuai.xi        MSP_WRITE(MSPI_DC_TRW_OFFSET, u16TempBuf);
478*53ee8cc1Swenshuai.xi        break;
479*53ee8cc1Swenshuai.xi    }
480*53ee8cc1Swenshuai.xi }
481*53ee8cc1Swenshuai.xi 
HAL_MSPI_CLKConfigMax(eCLK_config eCLKField)482*53ee8cc1Swenshuai.xi MS_U8 HAL_MSPI_CLKConfigMax(eCLK_config eCLKField)
483*53ee8cc1Swenshuai.xi {
484*53ee8cc1Swenshuai.xi     switch(eCLKField)
485*53ee8cc1Swenshuai.xi     {
486*53ee8cc1Swenshuai.xi     case E_MSPI_POL:
487*53ee8cc1Swenshuai.xi         return MSPI_CLK_POLARITY_MAX;
488*53ee8cc1Swenshuai.xi     case E_MSPI_PHA:
489*53ee8cc1Swenshuai.xi         return MSPI_CLK_PHASE_MAX;
490*53ee8cc1Swenshuai.xi     case E_MSPI_CLK:
491*53ee8cc1Swenshuai.xi         return MSPI_CLK_CLOCK_MAX;
492*53ee8cc1Swenshuai.xi     default:
493*53ee8cc1Swenshuai.xi         return 0;
494*53ee8cc1Swenshuai.xi     }
495*53ee8cc1Swenshuai.xi }
496*53ee8cc1Swenshuai.xi 
HAL_MSPI_SetCLKTiming(eCLK_config eCLKField,MS_U8 u8CLKVal)497*53ee8cc1Swenshuai.xi void HAL_MSPI_SetCLKTiming(eCLK_config eCLKField, MS_U8 u8CLKVal)
498*53ee8cc1Swenshuai.xi {
499*53ee8cc1Swenshuai.xi    MS_U16 u16TempBuf = 0;
500*53ee8cc1Swenshuai.xi    switch(eCLKField)
501*53ee8cc1Swenshuai.xi    {
502*53ee8cc1Swenshuai.xi    case E_MSPI_POL:
503*53ee8cc1Swenshuai.xi        u16TempBuf = MSP_READ(MSPI_CLK_CLOCK_OFFSET);
504*53ee8cc1Swenshuai.xi 	   u16TempBuf &= ~(MSPI_CLK_POLARITY_MASK);
505*53ee8cc1Swenshuai.xi        u16TempBuf |= u8CLKVal << MSPI_CLK_POLARITY_BIT_OFFSET;
506*53ee8cc1Swenshuai.xi        break;
507*53ee8cc1Swenshuai.xi    case E_MSPI_PHA:
508*53ee8cc1Swenshuai.xi        u16TempBuf = MSP_READ(MSPI_CLK_CLOCK_OFFSET);
509*53ee8cc1Swenshuai.xi 	   u16TempBuf &= ~(MSPI_CLK_PHASE_MASK);
510*53ee8cc1Swenshuai.xi        u16TempBuf |= u8CLKVal << MSPI_CLK_PHASE_BIT_OFFSET;
511*53ee8cc1Swenshuai.xi        break;
512*53ee8cc1Swenshuai.xi    case E_MSPI_CLK:
513*53ee8cc1Swenshuai.xi        u16TempBuf = MSP_READ(MSPI_CLK_CLOCK_OFFSET);
514*53ee8cc1Swenshuai.xi        u16TempBuf &= MSPI_CLK_CLOCK_MASK;
515*53ee8cc1Swenshuai.xi        u16TempBuf |= u8CLKVal << MSPI_CLK_CLOCK_BIT_OFFSET;
516*53ee8cc1Swenshuai.xi        break;
517*53ee8cc1Swenshuai.xi    }
518*53ee8cc1Swenshuai.xi    MSP_WRITE(MSPI_CLK_CLOCK_OFFSET, u16TempBuf);
519*53ee8cc1Swenshuai.xi }
520*53ee8cc1Swenshuai.xi 
HAL_MSPI_FrameConfigMax(void)521*53ee8cc1Swenshuai.xi MS_U8 HAL_MSPI_FrameConfigMax(void)
522*53ee8cc1Swenshuai.xi {
523*53ee8cc1Swenshuai.xi     return MSPI_FRAME_BIT_MAX;
524*53ee8cc1Swenshuai.xi }
525*53ee8cc1Swenshuai.xi 
HAL_MSPI_SetPerFrameSize(MS_BOOL bDirect,MS_U8 u8BufOffset,MS_U8 u8PerFrameSize)526*53ee8cc1Swenshuai.xi void HAL_MSPI_SetPerFrameSize(MS_BOOL bDirect, MS_U8 u8BufOffset, MS_U8 u8PerFrameSize)
527*53ee8cc1Swenshuai.xi {
528*53ee8cc1Swenshuai.xi     MS_U8 u8Index = 0;
529*53ee8cc1Swenshuai.xi     MS_U16 u16TempBuf = 0;
530*53ee8cc1Swenshuai.xi 	MS_U8 u8BitOffset = 0;
531*53ee8cc1Swenshuai.xi 	MS_U16 u16regIndex = 0;
532*53ee8cc1Swenshuai.xi     if(bDirect == MSPI_READ_INDEX)
533*53ee8cc1Swenshuai.xi     {
534*53ee8cc1Swenshuai.xi         u16regIndex = MSPI_FRAME_RBIT_OFFSET;
535*53ee8cc1Swenshuai.xi 	}
536*53ee8cc1Swenshuai.xi 	else
537*53ee8cc1Swenshuai.xi     {
538*53ee8cc1Swenshuai.xi         u16regIndex = MSPI_FRAME_WBIT_OFFSET;
539*53ee8cc1Swenshuai.xi     }
540*53ee8cc1Swenshuai.xi     if(u8BufOffset >=4)
541*53ee8cc1Swenshuai.xi     {
542*53ee8cc1Swenshuai.xi         u8Index++;
543*53ee8cc1Swenshuai.xi         u8BufOffset -= 4;
544*53ee8cc1Swenshuai.xi     }
545*53ee8cc1Swenshuai.xi     u8BitOffset = u8BufOffset * MSPI_FRAME_BIT_FIELD;
546*53ee8cc1Swenshuai.xi     u16TempBuf = MSP_READ(u16regIndex+ u8Index);
547*53ee8cc1Swenshuai.xi     u16TempBuf &= ~(MSPI_FRAME_BIT_MASK << u8BitOffset);
548*53ee8cc1Swenshuai.xi     u16TempBuf |= u8PerFrameSize << u8BitOffset;
549*53ee8cc1Swenshuai.xi     MSP_WRITE((u16regIndex + u8Index), u16TempBuf);
550*53ee8cc1Swenshuai.xi }
551*53ee8cc1Swenshuai.xi 
HAL_MSPI_CLOCK_Config(MS_U32 u32MaxClock)552*53ee8cc1Swenshuai.xi MS_BOOL HAL_MSPI_CLOCK_Config(MS_U32 u32MaxClock)
553*53ee8cc1Swenshuai.xi {
554*53ee8cc1Swenshuai.xi     MS_U16 u16ClkDiv = 0;
555*53ee8cc1Swenshuai.xi 	MS_U16 u16ClkLevel = 0;
556*53ee8cc1Swenshuai.xi 	MS_U16 u16TempDiv = 0;
557*53ee8cc1Swenshuai.xi 	MS_U32 u32Clock = 0;
558*53ee8cc1Swenshuai.xi 	MS_U32 u32TempClock = 0;
559*53ee8cc1Swenshuai.xi 	MS_U32 u32ClockMatch = 0;
560*53ee8cc1Swenshuai.xi 	MS_U8  u8ClkIdx = 0;
561*53ee8cc1Swenshuai.xi 	MS_U8  u8DivIdx = 0;
562*53ee8cc1Swenshuai.xi 	u32MaxClock = u32MaxClock
563*53ee8cc1Swenshuai.xi * 1000000;
564*53ee8cc1Swenshuai.xi     // get current clock
565*53ee8cc1Swenshuai.xi 
566*53ee8cc1Swenshuai.xi     for(u8ClkIdx = 0; u8ClkIdx < MSPI_MAXCLKLEVEL; u8ClkIdx++)
567*53ee8cc1Swenshuai.xi     {
568*53ee8cc1Swenshuai.xi         u32Clock = _HAL_MSPI_GetCLK(u8ClkIdx);
569*53ee8cc1Swenshuai.xi         if(u32Clock < u32MaxClock && u32Clock > u32ClockMatch)
570*53ee8cc1Swenshuai.xi         {
571*53ee8cc1Swenshuai.xi            u32ClockMatch = u32Clock;
572*53ee8cc1Swenshuai.xi 		   u16ClkLevel = u8ClkIdx;
573*53ee8cc1Swenshuai.xi         }
574*53ee8cc1Swenshuai.xi 		else if(u32Clock >= u32MaxClock )
575*53ee8cc1Swenshuai.xi         {
576*53ee8cc1Swenshuai.xi             if(u32Clock == u32MaxClock)
577*53ee8cc1Swenshuai.xi                 break;
578*53ee8cc1Swenshuai.xi 			else
579*53ee8cc1Swenshuai.xi 		    {
580*53ee8cc1Swenshuai.xi                 for(u8DivIdx = 1; u8DivIdx < MSPI_CLK_CLOCK_MAX; u8DivIdx++)
581*53ee8cc1Swenshuai.xi                 {
582*53ee8cc1Swenshuai.xi                     u32TempClock = u32Clock / (1 << (u8DivIdx + 1));
583*53ee8cc1Swenshuai.xi                     if(u32TempClock <= u32MaxClock)
584*53ee8cc1Swenshuai.xi                     {
585*53ee8cc1Swenshuai.xi                         if(u32TempClock > u32ClockMatch)
586*53ee8cc1Swenshuai.xi                         {
587*53ee8cc1Swenshuai.xi                             u32ClockMatch = u32TempClock;
588*53ee8cc1Swenshuai.xi 							u16ClkDiv = u8DivIdx;
589*53ee8cc1Swenshuai.xi 							u16ClkLevel = u8ClkIdx;
590*53ee8cc1Swenshuai.xi                         }
591*53ee8cc1Swenshuai.xi 						break;
592*53ee8cc1Swenshuai.xi                     }
593*53ee8cc1Swenshuai.xi                 }
594*53ee8cc1Swenshuai.xi             }
595*53ee8cc1Swenshuai.xi         }
596*53ee8cc1Swenshuai.xi     }
597*53ee8cc1Swenshuai.xi 	//set clock div of mspi
598*53ee8cc1Swenshuai.xi 	u16TempDiv = MSP_READ(MSPI_CLK_CLOCK_OFFSET);
599*53ee8cc1Swenshuai.xi     u16TempDiv &= MSPI_CLK_CLOCK_MASK;
600*53ee8cc1Swenshuai.xi     u16TempDiv |= u16ClkDiv << MSPI_CLK_CLOCK_BIT_OFFSET;
601*53ee8cc1Swenshuai.xi 	MSP_WRITE(MSPI_CLK_CLOCK_OFFSET, u16TempDiv);
602*53ee8cc1Swenshuai.xi 	u16ClkLevel = u16ClkLevel << MSPI_CLK_CFG_OFFSET;
603*53ee8cc1Swenshuai.xi     CLK_WRITE(MSPI_CLK_CFG, u16ClkLevel);
604*53ee8cc1Swenshuai.xi 	return TRUE;
605*53ee8cc1Swenshuai.xi }
606*53ee8cc1Swenshuai.xi 
607*53ee8cc1Swenshuai.xi 
HAL_MSPI_CLK_Config(MS_U8 u8Chanel,MS_U32 u32MspiClk)608*53ee8cc1Swenshuai.xi MS_BOOL HAL_MSPI_CLK_Config(MS_U8 u8Chanel,MS_U32 u32MspiClk)
609*53ee8cc1Swenshuai.xi {
610*53ee8cc1Swenshuai.xi 
611*53ee8cc1Swenshuai.xi     return TRUE;
612*53ee8cc1Swenshuai.xi }
613*53ee8cc1Swenshuai.xi 
HAL_MSPI_RWBytes(MS_BOOL Direct,MS_U8 u8Bytes)614*53ee8cc1Swenshuai.xi MS_BOOL HAL_MSPI_RWBytes(MS_BOOL Direct, MS_U8 u8Bytes)
615*53ee8cc1Swenshuai.xi {
616*53ee8cc1Swenshuai.xi     //set read write trigger buffer size
617*53ee8cc1Swenshuai.xi     _HAL_MSPI_RWBUFSize(Direct, u8Bytes);
618*53ee8cc1Swenshuai.xi     return TRUE;
619*53ee8cc1Swenshuai.xi }
620