1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 #ifndef _ASM_MIPSREGS_H
79 #define _ASM_MIPSREGS_H
80
81 /*
82 * Coprocessor 0 register names
83 */
84 #define CP0_INDEX $0
85 #define CP0_RANDOM $1
86 #define CP0_ENTRYLO0 $2
87 #define CP0_ENTRYLO1 $3
88 #define CP0_CONF $3
89 #define CP0_CONTEXT $4
90 #define CP0_PAGEMASK $5
91 #define CP0_WIRED $6
92 #define CP0_INFO $7
93 #define CP0_BADVADDR $8
94 #define CP0_COUNT $9
95 #define CP0_ENTRYHI $10
96 #define CP0_COMPARE $11
97 #define CP0_STATUS $12
98 #define CP0_CAUSE $13
99 #define CP0_EPC $14
100 #define CP0_PRID $15
101 #define CP0_CONFIG $16
102 #define CP0_LLADDR $17
103 #define CP0_WATCHLO $18
104 #define CP0_WATCHHI $19
105 #define CP0_XCONTEXT $20
106 #define CP0_FRAMEMASK $21
107 #define CP0_DIAGNOSTIC $22
108 #define CP0_DEBUG $23
109 #define CP0_DEPC $24
110 #define CP0_PERFORMANCE $25
111 #define CP0_ECC $26
112 #define CP0_CACHEERR $27
113 #define CP0_TAGLO $28
114 #define CP0_TAGHI $29
115 #define CP0_ERROREPC $30
116 #define CP0_DESAVE $31
117
118 /*
119 * Functions to access the R10000 performance counters. These are basically
120 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
121 * performance counter number encoded into bits 1 ... 5 of the instruction.
122 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
123 * disassembler these will look like an access to sel 0 or 1.
124 */
125
126 /*
127 * Macros to access the system control coprocessor
128 */
129 #define __read_32bit_c0_register(source, sel) \
130 ({ int __res; \
131 if (sel == 0) \
132 __asm__ __volatile__( \
133 "mfc0\t%0, " #source "\n\t" \
134 : "=r" (__res)); \
135 else \
136 __asm__ __volatile__( \
137 ".set\tmips32\n\t" \
138 "mfc0\t%0, " #source ", " #sel "\n\t" \
139 ".set\tmips0\n\t" \
140 : "=r" (__res)); \
141 __res; \
142 })
143
144 #define __read_64bit_c0_register(source, sel) \
145 ({ unsigned long long __res; \
146 if (sizeof(unsigned long) == 4) \
147 __res = __read_64bit_c0_split(source, sel); \
148 else if (sel == 0) \
149 __asm__ __volatile__( \
150 ".set\tmips3\n\t" \
151 "dmfc0\t%0, " #source "\n\t" \
152 ".set\tmips0" \
153 : "=r" (__res)); \
154 else \
155 __asm__ __volatile__( \
156 ".set\tmips64\n\t" \
157 "dmfc0\t%0, " #source ", " #sel "\n\t" \
158 ".set\tmips0" \
159 : "=r" (__res)); \
160 __res; \
161 })
162
163 #define __write_32bit_c0_register(register, sel, value) \
164 do { \
165 if (sel == 0) \
166 __asm__ __volatile__( \
167 "mtc0\t%z0, " #register "\n\t" \
168 : : "Jr" ((unsigned int)(value))); \
169 else \
170 __asm__ __volatile__( \
171 ".set\tmips32\n\t" \
172 "mtc0\t%z0, " #register ", " #sel "\n\t" \
173 ".set\tmips0" \
174 : : "Jr" ((unsigned int)(value))); \
175 } while (0)
176
177 #define __write_64bit_c0_register(register, sel, value) \
178 do { \
179 if (sizeof(unsigned long) == 4) \
180 __write_64bit_c0_split(register, sel, value); \
181 else if (sel == 0) \
182 __asm__ __volatile__( \
183 ".set\tmips3\n\t" \
184 "dmtc0\t%z0, " #register "\n\t" \
185 ".set\tmips0" \
186 : : "Jr" (value)); \
187 else \
188 __asm__ __volatile__( \
189 ".set\tmips64\n\t" \
190 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
191 ".set\tmips0" \
192 : : "Jr" (value)); \
193 } while (0)
194
195 #define __read_ulong_c0_register(reg, sel) \
196 ((sizeof(unsigned long) == 4) ? \
197 (unsigned long) __read_32bit_c0_register(reg, sel) : \
198 (unsigned long) __read_64bit_c0_register(reg, sel))
199
200 #define __write_ulong_c0_register(reg, sel, val) \
201 do { \
202 if (sizeof(unsigned long) == 4) \
203 __write_32bit_c0_register(reg, sel, val); \
204 else \
205 __write_64bit_c0_register(reg, sel, val); \
206 } while (0)
207
208 /*
209 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
210 */
211 #define __read_32bit_c0_ctrl_register(source) \
212 ({ int __res; \
213 __asm__ __volatile__( \
214 "cfc0\t%0, " #source "\n\t" \
215 : "=r" (__res)); \
216 __res; \
217 })
218
219 #define __write_32bit_c0_ctrl_register(register, value) \
220 do { \
221 __asm__ __volatile__( \
222 "ctc0\t%z0, " #register "\n\t" \
223 : : "Jr" ((unsigned int)(value))); \
224 } while (0)
225
226 /*
227 * These versions are only needed for systems with more than 38 bits of
228 * physical address space running the 32-bit kernel. That's none atm :-)
229 */
230 #define __read_64bit_c0_split(source, sel) \
231 ({ \
232 unsigned long long __val; \
233 \
234 if (sel == 0) \
235 __asm__ __volatile__( \
236 ".set\tmips64\n\t" \
237 "dmfc0\t%M0, " #source "\n\t" \
238 "dsll\t%L0, %M0, 32\n\t" \
239 "dsrl\t%M0, %M0, 32\n\t" \
240 "dsrl\t%L0, %L0, 32\n\t" \
241 ".set\tmips0" \
242 : "=r" (__val)); \
243 else \
244 __asm__ __volatile__( \
245 ".set\tmips64\n\t" \
246 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
247 "dsll\t%L0, %M0, 32\n\t" \
248 "dsrl\t%M0, %M0, 32\n\t" \
249 "dsrl\t%L0, %L0, 32\n\t" \
250 ".set\tmips0" \
251 : "=r" (__val)); \
252 \
253 __val; \
254 })
255
256 #define __write_64bit_c0_split(source, sel, val) \
257 do { \
258 if (sel == 0) \
259 __asm__ __volatile__( \
260 ".set\tmips64\n\t" \
261 "dsll\t%L0, %L0, 32\n\t" \
262 "dsrl\t%L0, %L0, 32\n\t" \
263 "dsll\t%M0, %M0, 32\n\t" \
264 "or\t%L0, %L0, %M0\n\t" \
265 "dmtc0\t%L0, " #source "\n\t" \
266 ".set\tmips0" \
267 : : "r" (val)); \
268 else \
269 __asm__ __volatile__( \
270 ".set\tmips64\n\t" \
271 "dsll\t%L0, %L0, 32\n\t" \
272 "dsrl\t%L0, %L0, 32\n\t" \
273 "dsll\t%M0, %M0, 32\n\t" \
274 "or\t%L0, %L0, %M0\n\t" \
275 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
276 ".set\tmips0" \
277 : : "r" (val)); \
278 } while (0)
279
280 #define read_c0_index() __read_32bit_c0_register($0, 0)
281 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
282
283 #define read_c0_random() __read_32bit_c0_register($1, 0)
284 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
285
286 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
287 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
288
289 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
290 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
291
292 #define read_c0_conf() __read_32bit_c0_register($3, 0)
293 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
294
295 #define read_c0_context() __read_ulong_c0_register($4, 0)
296 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
297
298 #define read_c0_userlocal() __read_ulong_c0_register($4, 2)
299 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
300
301 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
302 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
303
304 #define read_c0_wired() __read_32bit_c0_register($6, 0)
305 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
306
307 #define read_c0_info() __read_32bit_c0_register($7, 0)
308
309 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
310 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
311
312 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
313 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
314
315 #define read_c0_count() __read_32bit_c0_register($9, 0)
316 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
317
318 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
319 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
320
321 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
322 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
323
324 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
325 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
326
327 #define read_c0_compare() __read_32bit_c0_register($11, 0)
328 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
329
330 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
331 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
332
333 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
334 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
335
336 #define read_c0_status() __read_32bit_c0_register($12, 0)
337 #ifdef CONFIG_MIPS_MT_SMTC
338 #define write_c0_status(val) \
339 do { \
340 __write_32bit_c0_register($12, 0, val); \
341 __ehb(); \
342 } while (0)
343 #else
344 /*
345 * Legacy non-SMTC code, which may be hazardous
346 * but which might not support EHB
347 */
348 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
349 #endif /* CONFIG_MIPS_MT_SMTC */
350
351 #define read_c0_cause() __read_32bit_c0_register($13, 0)
352 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
353
354 #define read_c0_epc() __read_ulong_c0_register($14, 0)
355 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
356
357 #define read_c0_prid() __read_32bit_c0_register($15, 0)
358
359 #define read_c0_config() __read_32bit_c0_register($16, 0)
360 #define read_c0_config1() __read_32bit_c0_register($16, 1)
361 #define read_c0_config2() __read_32bit_c0_register($16, 2)
362 #define read_c0_config3() __read_32bit_c0_register($16, 3)
363 #define read_c0_config4() __read_32bit_c0_register($16, 4)
364 #define read_c0_config5() __read_32bit_c0_register($16, 5)
365 #define read_c0_config6() __read_32bit_c0_register($16, 6)
366 #define read_c0_config7() __read_32bit_c0_register($16, 7)
367 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
368 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
369 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
370 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
371 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
372 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
373 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
374 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
375
376 /*
377 * The WatchLo register. There may be upto 8 of them.
378 */
379 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
380 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
381 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
382 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
383 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
384 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
385 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
386 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
387 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
388 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
389 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
390 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
391 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
392 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
393 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
394 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
395
396 /*
397 * The WatchHi register. There may be upto 8 of them.
398 */
399 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
400 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
401 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
402 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
403 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
404 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
405 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
406 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
407
408 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
409 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
410 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
411 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
412 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
413 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
414 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
415 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
416
417 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
418 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
419
420 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
421 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
422
423 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
424 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
425
426 /* RM9000 PerfControl performance counter control register */
427 #define read_c0_perfcontrol() __read_32bit_c0_register($22, 0)
428 #define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
429
430 #define read_c0_diag() __read_32bit_c0_register($22, 0)
431 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
432
433 #define read_c0_diag1() __read_32bit_c0_register($22, 1)
434 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
435
436 #define read_c0_diag2() __read_32bit_c0_register($22, 2)
437 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
438
439 #define read_c0_diag3() __read_32bit_c0_register($22, 3)
440 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
441
442 #define read_c0_diag4() __read_32bit_c0_register($22, 4)
443 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
444
445 #define read_c0_diag5() __read_32bit_c0_register($22, 5)
446 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
447
448 #define read_c0_debug() __read_32bit_c0_register($23, 0)
449 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
450
451 #define read_c0_depc() __read_ulong_c0_register($24, 0)
452 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
453
454 /*
455 * MIPS32 / MIPS64 performance counters
456 */
457 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
458 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
459 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
460 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
461 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
462 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
463 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
464 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
465 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
466 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
467 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
468 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
469 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
470 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
471 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
472 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
473
474 /* RM9000 PerfCount performance counter register */
475 #define read_c0_perfcount() __read_64bit_c0_register($25, 0)
476 #define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
477
478 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
479 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
480
481 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
482 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
483
484 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
485
486 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
487 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
488
489 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
490 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
491
492 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
493 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
494
495 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
496 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
497
498 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
499 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
500
501 /* MIPSR2 */
502 #define read_c0_hwrena() __read_32bit_c0_register($7, 0)
503 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
504
505 #define read_c0_intctl() __read_32bit_c0_register($12, 1)
506 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
507
508 #define read_c0_srsctl() __read_32bit_c0_register($12, 2)
509 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
510
511 #define read_c0_srsmap() __read_32bit_c0_register($12, 3)
512 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
513
514 #define read_c0_ebase() __read_32bit_c0_register($15, 1)
515 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
516
517 /*
518 * TLB operations.
519 *
520 * It is responsibility of the caller to take care of any TLB hazards.
521 */
tlb_write_indexed(void)522 static inline void tlb_write_indexed(void)
523 {
524 __asm__ __volatile__(
525 ".set noreorder\n\t"
526 "tlbwi\n\t"
527 ".set reorder");
528 }
529
530 /*
531 * Manipulate bits in a c0 register.
532 */
533 /*
534 * SMTC Linux requires shutting-down microthread scheduling
535 * during CP0 register read-modify-write sequences.
536 */
537 #define __BUILD_SET_C0(name) \
538 static inline unsigned int \
539 set_c0_##name(unsigned int set) \
540 { \
541 unsigned int res; \
542 \
543 res = read_c0_##name(); \
544 res |= set; \
545 write_c0_##name(res); \
546 \
547 return res; \
548 } \
549 \
550 static inline unsigned int \
551 clear_c0_##name(unsigned int clear) \
552 { \
553 unsigned int res; \
554 \
555 res = read_c0_##name(); \
556 res &= ~clear; \
557 write_c0_##name(res); \
558 \
559 return res; \
560 } \
561 \
562 static inline unsigned int \
563 change_c0_##name(unsigned int change, unsigned int new) \
564 { \
565 unsigned int res; \
566 \
567 res = read_c0_##name(); \
568 res &= ~change; \
569 res |= (new & change); \
570 write_c0_##name(res); \
571 \
572 return res; \
573 }
574
575 #endif /* _ASM_MIPSREGS_H */
576