xref: /utopia/UTPA2-700.0.x/modules/msos/hal/messi/mmio/halMMIO.c (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
1*53ee8cc1Swenshuai.xi //<MStar Software>
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77*53ee8cc1Swenshuai.xi //<MStar Software>
78*53ee8cc1Swenshuai.xi 
79*53ee8cc1Swenshuai.xi ///////////////////////////////////////////////////////////////////////////////////////////////////
80*53ee8cc1Swenshuai.xi ///
81*53ee8cc1Swenshuai.xi /// file    halMMIO.c
82*53ee8cc1Swenshuai.xi /// @brief  memory map io (MMIO) HAL
83*53ee8cc1Swenshuai.xi /// @author MStar Semiconductor Inc.
84*53ee8cc1Swenshuai.xi ///////////////////////////////////////////////////////////////////////////////////////////////////
85*53ee8cc1Swenshuai.xi 
86*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
87*53ee8cc1Swenshuai.xi //  Include Files
88*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
89*53ee8cc1Swenshuai.xi 
90*53ee8cc1Swenshuai.xi #include "MsCommon.h"
91*53ee8cc1Swenshuai.xi #include "halMMIO.h"
92*53ee8cc1Swenshuai.xi #include "drvMMIO.h"
93*53ee8cc1Swenshuai.xi 
94*53ee8cc1Swenshuai.xi // for getting mapped IO base from DRV
95*53ee8cc1Swenshuai.xi extern MS_VIRT  _virtPM_Bank;
96*53ee8cc1Swenshuai.xi extern MS_U32   _u32PM_Bank_SIZE;
97*53ee8cc1Swenshuai.xi extern MS_VIRT  _virtNonPM_Bank;
98*53ee8cc1Swenshuai.xi extern MS_U32   _u32NonPM_Bank_SIZE;
99*53ee8cc1Swenshuai.xi 
100*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
101*53ee8cc1Swenshuai.xi //  Driver Compiler Options
102*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
103*53ee8cc1Swenshuai.xi 
104*53ee8cc1Swenshuai.xi //--------------------------------------------------------------------------------------------------
105*53ee8cc1Swenshuai.xi //  Global Variables
106*53ee8cc1Swenshuai.xi //--------------------------------------------------------------------------------------------------
107*53ee8cc1Swenshuai.xi MS_VIRT         virt_ge0_mmio_base;
108*53ee8cc1Swenshuai.xi 
109*53ee8cc1Swenshuai.xi 
110*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
111*53ee8cc1Swenshuai.xi //  Local Defines
112*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
113*53ee8cc1Swenshuai.xi #ifdef MSOS_TYPE_LINUX
114*53ee8cc1Swenshuai.xi 
115*53ee8cc1Swenshuai.xi #define HAL_MMIO_PM_BASE                0x1f000000UL
116*53ee8cc1Swenshuai.xi #define HAL_MMIO_PM_SIZE                0x00300000UL
117*53ee8cc1Swenshuai.xi #define HAL_MMIO_NONPM_BASE             0x1f200000UL
118*53ee8cc1Swenshuai.xi #define HAL_MMIO_NONPM_SIZE             0x00100000UL
119*53ee8cc1Swenshuai.xi #define HAL_MMIO_FLASH_BASE0            0x14000000UL
120*53ee8cc1Swenshuai.xi #define HAL_MMIO_FLASH_SIZE0            0x01000000UL
121*53ee8cc1Swenshuai.xi 
122*53ee8cc1Swenshuai.xi #else
123*53ee8cc1Swenshuai.xi 
124*53ee8cc1Swenshuai.xi #if defined(MCU_AEON)
125*53ee8cc1Swenshuai.xi #define HAL_MMIO_PM_BASE                0xFA000000UL
126*53ee8cc1Swenshuai.xi #define HAL_MMIO_PM_SIZE                0x00300000UL
127*53ee8cc1Swenshuai.xi #define HAL_MMIO_NONPM_BASE             0xFA200000UL
128*53ee8cc1Swenshuai.xi #define HAL_MMIO_NONPM_SIZE             0x00100000UL
129*53ee8cc1Swenshuai.xi #define HAL_MMIO_FLASH_BASE0            0xA1000000UL // non-cache // 0xA1000000 for cache
130*53ee8cc1Swenshuai.xi #define HAL_MMIO_FLASH_SIZE0            0x01000000UL
131*53ee8cc1Swenshuai.xi 
132*53ee8cc1Swenshuai.xi #elif defined(__mips__)
133*53ee8cc1Swenshuai.xi #define HAL_MMIO_PM_BASE                0xbf000000UL
134*53ee8cc1Swenshuai.xi #define HAL_MMIO_PM_SIZE                0x00300000UL
135*53ee8cc1Swenshuai.xi #define HAL_MMIO_NONPM_BASE             0xbf200000UL
136*53ee8cc1Swenshuai.xi #define HAL_MMIO_NONPM_SIZE             0x00100000UL
137*53ee8cc1Swenshuai.xi #define HAL_MMIO_FLASH_BASE0            0xb4000000UL
138*53ee8cc1Swenshuai.xi #define HAL_MMIO_FLASH_SIZE0            0x01000000UL
139*53ee8cc1Swenshuai.xi 
140*53ee8cc1Swenshuai.xi #elif defined(__aarch64__) || defined(__arm__)
141*53ee8cc1Swenshuai.xi #define HAL_MMIO_PM_BASE                0x1f000000UL
142*53ee8cc1Swenshuai.xi #define HAL_MMIO_PM_SIZE                0x00300000UL
143*53ee8cc1Swenshuai.xi #define HAL_MMIO_NONPM_BASE             0x1f200000UL
144*53ee8cc1Swenshuai.xi #define HAL_MMIO_NONPM_SIZE             0x00100000UL
145*53ee8cc1Swenshuai.xi #define HAL_MMIO_FLASH_BASE0            0x14000000UL
146*53ee8cc1Swenshuai.xi #define HAL_MMIO_FLASH_SIZE0            0x01000000UL
147*53ee8cc1Swenshuai.xi 
148*53ee8cc1Swenshuai.xi #else
149*53ee8cc1Swenshuai.xi #error  "Invalid MCU Type";
150*53ee8cc1Swenshuai.xi #endif
151*53ee8cc1Swenshuai.xi 
152*53ee8cc1Swenshuai.xi #endif  //MSOS_TYPE_LINUX
153*53ee8cc1Swenshuai.xi 
154*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
155*53ee8cc1Swenshuai.xi //  Local Structurs
156*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
157*53ee8cc1Swenshuai.xi 
158*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
159*53ee8cc1Swenshuai.xi //  Global Variables
160*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
161*53ee8cc1Swenshuai.xi 
162*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
163*53ee8cc1Swenshuai.xi //  Local Variables
164*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
165*53ee8cc1Swenshuai.xi 
166*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
167*53ee8cc1Swenshuai.xi //  Debug Functions
168*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
169*53ee8cc1Swenshuai.xi 
170*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
171*53ee8cc1Swenshuai.xi //  Local Functions
172*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
173*53ee8cc1Swenshuai.xi 
174*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
175*53ee8cc1Swenshuai.xi //  Global Functions
176*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
HAL_MMIO_GetType(MS_U32 u32Module)177*53ee8cc1Swenshuai.xi MS_U16  HAL_MMIO_GetType(MS_U32 u32Module)
178*53ee8cc1Swenshuai.xi {
179*53ee8cc1Swenshuai.xi     MS_U16  wMmioBankType = 0xFFFF;
180*53ee8cc1Swenshuai.xi 
181*53ee8cc1Swenshuai.xi     switch (u32Module)
182*53ee8cc1Swenshuai.xi     {
183*53ee8cc1Swenshuai.xi         //HAL_MMIO_PM_BANK
184*53ee8cc1Swenshuai.xi         case MS_MODULE_PM:
185*53ee8cc1Swenshuai.xi         case MS_MODULE_IR:
186*53ee8cc1Swenshuai.xi         case MS_MODULE_ISP:
187*53ee8cc1Swenshuai.xi         case MS_MODULE_PWS:
188*53ee8cc1Swenshuai.xi             wMmioBankType = DRV_MMIO_PM_BANK;
189*53ee8cc1Swenshuai.xi             break;
190*53ee8cc1Swenshuai.xi 
191*53ee8cc1Swenshuai.xi         //HAL_MMIO_NONPM_BANK
192*53ee8cc1Swenshuai.xi         case MS_MODULE_HW:
193*53ee8cc1Swenshuai.xi         case MS_MODULE_CHIPTOP:
194*53ee8cc1Swenshuai.xi         case MS_MODULE_MIU:
195*53ee8cc1Swenshuai.xi         case MS_MODULE_ACE:
196*53ee8cc1Swenshuai.xi         case MS_MODULE_AUDIO:
197*53ee8cc1Swenshuai.xi         case MS_MODULE_AVD:
198*53ee8cc1Swenshuai.xi         case MS_MODULE_BDMA:
199*53ee8cc1Swenshuai.xi         case MS_MODULE_DLC:
200*53ee8cc1Swenshuai.xi         case MS_MODULE_DMD:
201*53ee8cc1Swenshuai.xi         case MS_MODULE_GE:
202*53ee8cc1Swenshuai.xi         case MS_MODULE_GOP:
203*53ee8cc1Swenshuai.xi         case MS_MODULE_GPIO:
204*53ee8cc1Swenshuai.xi         case MS_MODULE_HVD:
205*53ee8cc1Swenshuai.xi         case MS_MODULE_HWI2C:
206*53ee8cc1Swenshuai.xi         case MS_MODULE_IRQ:
207*53ee8cc1Swenshuai.xi         case MS_MODULE_JPD:
208*53ee8cc1Swenshuai.xi         case MS_MODULE_MBX:
209*53ee8cc1Swenshuai.xi         case MS_MODULE_MFE:
210*53ee8cc1Swenshuai.xi         case MS_MODULE_MHEG5:
211*53ee8cc1Swenshuai.xi         case MS_MODULE_MVD:
212*53ee8cc1Swenshuai.xi         case MS_MODULE_MVOP:
213*53ee8cc1Swenshuai.xi         case MS_MODULE_RVD:
214*53ee8cc1Swenshuai.xi         case MS_MODULE_TSP:
215*53ee8cc1Swenshuai.xi         case MS_MODULE_UART:
216*53ee8cc1Swenshuai.xi         case MS_MODULE_VPU:
217*53ee8cc1Swenshuai.xi         case MS_MODULE_XC:
218*53ee8cc1Swenshuai.xi         case MS_MODULE_PCMCIA:
219*53ee8cc1Swenshuai.xi         case MS_MODULE_PFSH:
220*53ee8cc1Swenshuai.xi         case MS_MODULE_PNL:
221*53ee8cc1Swenshuai.xi         case MS_MODULE_PWM:
222*53ee8cc1Swenshuai.xi         case MS_MODULE_SEM:
223*53ee8cc1Swenshuai.xi         case MS_MODULE_VBI:
224*53ee8cc1Swenshuai.xi         case MS_MODULE_VIF:
225*53ee8cc1Swenshuai.xi         case MS_MODULE_DIP:
226*53ee8cc1Swenshuai.xi         case MS_MODULE_MPIF:
227*53ee8cc1Swenshuai.xi         case MS_MODULE_MMFILEIN:
228*53ee8cc1Swenshuai.xi         case MS_MODULE_GPD:
229*53ee8cc1Swenshuai.xi         case MS_MODULE_TSO:
230*53ee8cc1Swenshuai.xi         case MS_MODULE_CMDQ:
231*53ee8cc1Swenshuai.xi             wMmioBankType = DRV_MMIO_NONPM_BANK;
232*53ee8cc1Swenshuai.xi             break;
233*53ee8cc1Swenshuai.xi 
234*53ee8cc1Swenshuai.xi         case MS_MODULE_SC:
235*53ee8cc1Swenshuai.xi             wMmioBankType = DRV_MMIO_SC_BANK;
236*53ee8cc1Swenshuai.xi             break;
237*53ee8cc1Swenshuai.xi 
238*53ee8cc1Swenshuai.xi          //HAL_MMIO_FLASH_BANK0
239*53ee8cc1Swenshuai.xi         case MS_MODULE_FLASH:
240*53ee8cc1Swenshuai.xi             wMmioBankType = DRV_MMIO_FLASH_BANK0;
241*53ee8cc1Swenshuai.xi             break;
242*53ee8cc1Swenshuai.xi 
243*53ee8cc1Swenshuai.xi         default:
244*53ee8cc1Swenshuai.xi             wMmioBankType = 0xFFFF;
245*53ee8cc1Swenshuai.xi             break;
246*53ee8cc1Swenshuai.xi 
247*53ee8cc1Swenshuai.xi     }
248*53ee8cc1Swenshuai.xi 
249*53ee8cc1Swenshuai.xi     return wMmioBankType;
250*53ee8cc1Swenshuai.xi }
251*53ee8cc1Swenshuai.xi 
252*53ee8cc1Swenshuai.xi 
HAL_MMIO_GetBase(MS_PHY * virtBaseAddr,MS_PHY * pu32BaseSize,MS_U32 u32BankType)253*53ee8cc1Swenshuai.xi MS_BOOL HAL_MMIO_GetBase(MS_PHY* virtBaseAddr, MS_PHY* pu32BaseSize, MS_U32 u32BankType)
254*53ee8cc1Swenshuai.xi {
255*53ee8cc1Swenshuai.xi     MS_BOOL bRet = TRUE;
256*53ee8cc1Swenshuai.xi 
257*53ee8cc1Swenshuai.xi     *virtBaseAddr = 0;
258*53ee8cc1Swenshuai.xi     *pu32BaseSize = 0;
259*53ee8cc1Swenshuai.xi     switch (u32BankType)
260*53ee8cc1Swenshuai.xi     {
261*53ee8cc1Swenshuai.xi         case DRV_MMIO_PM_BANK:
262*53ee8cc1Swenshuai.xi             *virtBaseAddr = (MS_PHY) HAL_MMIO_PM_BASE;
263*53ee8cc1Swenshuai.xi             *pu32BaseSize = (MS_PHY) HAL_MMIO_PM_SIZE;
264*53ee8cc1Swenshuai.xi             break;
265*53ee8cc1Swenshuai.xi 
266*53ee8cc1Swenshuai.xi         case DRV_MMIO_NONPM_BANK:
267*53ee8cc1Swenshuai.xi             *virtBaseAddr = (MS_PHY) HAL_MMIO_NONPM_BASE;
268*53ee8cc1Swenshuai.xi             *pu32BaseSize = (MS_PHY) HAL_MMIO_NONPM_SIZE;
269*53ee8cc1Swenshuai.xi             break;
270*53ee8cc1Swenshuai.xi 
271*53ee8cc1Swenshuai.xi         case DRV_MMIO_FLASH_BANK0:
272*53ee8cc1Swenshuai.xi             *virtBaseAddr = (MS_PHY) HAL_MMIO_FLASH_BASE0;
273*53ee8cc1Swenshuai.xi             *pu32BaseSize = (MS_PHY) HAL_MMIO_FLASH_SIZE0;
274*53ee8cc1Swenshuai.xi             break;
275*53ee8cc1Swenshuai.xi 
276*53ee8cc1Swenshuai.xi         case DRV_MMIO_FRC_BANK:
277*53ee8cc1Swenshuai.xi             break;
278*53ee8cc1Swenshuai.xi 
279*53ee8cc1Swenshuai.xi         default:
280*53ee8cc1Swenshuai.xi //          MS_ASSERT(0);
281*53ee8cc1Swenshuai.xi             bRet = FALSE;
282*53ee8cc1Swenshuai.xi             break;
283*53ee8cc1Swenshuai.xi     }
284*53ee8cc1Swenshuai.xi 
285*53ee8cc1Swenshuai.xi     return bRet;
286*53ee8cc1Swenshuai.xi }
287*53ee8cc1Swenshuai.xi 
288*53ee8cc1Swenshuai.xi 
289*53ee8cc1Swenshuai.xi // @NOTE: Only run after MMIO_Init
HAL_MMIO_GetIPBase(MS_VIRT * virtBaseAddr,MS_U16 u16BankType)290*53ee8cc1Swenshuai.xi MS_BOOL HAL_MMIO_GetIPBase(MS_VIRT *virtBaseAddr, MS_U16 u16BankType)
291*53ee8cc1Swenshuai.xi {
292*53ee8cc1Swenshuai.xi     *virtBaseAddr = 0;
293*53ee8cc1Swenshuai.xi 
294*53ee8cc1Swenshuai.xi     // if MMIO_Init is not yet initialized.
295*53ee8cc1Swenshuai.xi     if((_u32PM_Bank_SIZE == 0x0) || (_u32NonPM_Bank_SIZE == 0x0))
296*53ee8cc1Swenshuai.xi     {
297*53ee8cc1Swenshuai.xi         return FALSE;
298*53ee8cc1Swenshuai.xi     }
299*53ee8cc1Swenshuai.xi 
300*53ee8cc1Swenshuai.xi     switch (u16BankType)
301*53ee8cc1Swenshuai.xi     {
302*53ee8cc1Swenshuai.xi         case DRV_MMIO_SC_BANK:
303*53ee8cc1Swenshuai.xi             *virtBaseAddr =_virtNonPM_Bank  + 0x00005200; // 0xBF220C00, 0xBF220C80
304*53ee8cc1Swenshuai.xi             break;
305*53ee8cc1Swenshuai.xi 
306*53ee8cc1Swenshuai.xi         default:
307*53ee8cc1Swenshuai.xi             return FALSE;
308*53ee8cc1Swenshuai.xi     }
309*53ee8cc1Swenshuai.xi 
310*53ee8cc1Swenshuai.xi     return TRUE;
311*53ee8cc1Swenshuai.xi }
312*53ee8cc1Swenshuai.xi 
313*53ee8cc1Swenshuai.xi #if defined(__aarch64__) || defined(__arm__)
314*53ee8cc1Swenshuai.xi #ifndef MSOS_TYPE_LINUX
_chip_flush_miu_pipe(void)315*53ee8cc1Swenshuai.xi static void _chip_flush_miu_pipe(void)
316*53ee8cc1Swenshuai.xi {
317*53ee8cc1Swenshuai.xi     unsigned int    dwReadData = 0;
318*53ee8cc1Swenshuai.xi 
319*53ee8cc1Swenshuai.xi      //toggle the flush miu pipe fire bit
320*53ee8cc1Swenshuai.xi     *(volatile unsigned int *)(HAL_MMIO_PM_BASE + (0x10188A << 1)) &= ~(0x0001);
321*53ee8cc1Swenshuai.xi     *(volatile unsigned int *)(HAL_MMIO_PM_BASE + (0x10188A << 1)) |= 0x0001;
322*53ee8cc1Swenshuai.xi 
323*53ee8cc1Swenshuai.xi     do
324*53ee8cc1Swenshuai.xi     {
325*53ee8cc1Swenshuai.xi         dwReadData = *(volatile unsigned int *)(HAL_MMIO_PM_BASE+ (0x1018A0 << 1));
326*53ee8cc1Swenshuai.xi         dwReadData &= BIT(12);  //Check Status of Flush Pipe Finish
327*53ee8cc1Swenshuai.xi 
328*53ee8cc1Swenshuai.xi     } while(dwReadData == 0);
329*53ee8cc1Swenshuai.xi }
330*53ee8cc1Swenshuai.xi #endif
331*53ee8cc1Swenshuai.xi #endif
332*53ee8cc1Swenshuai.xi 
HAL_MMIO_FlushMemory(void)333*53ee8cc1Swenshuai.xi void HAL_MMIO_FlushMemory(void)
334*53ee8cc1Swenshuai.xi {
335*53ee8cc1Swenshuai.xi #if defined(__aarch64__) || defined(__arm__)
336*53ee8cc1Swenshuai.xi #ifndef MSOS_TYPE_LINUX
337*53ee8cc1Swenshuai.xi     _chip_flush_miu_pipe();
338*53ee8cc1Swenshuai.xi #endif
339*53ee8cc1Swenshuai.xi #endif
340*53ee8cc1Swenshuai.xi }
341*53ee8cc1Swenshuai.xi 
HAL_MMIO_ReadMemory(void)342*53ee8cc1Swenshuai.xi void HAL_MMIO_ReadMemory(void)
343*53ee8cc1Swenshuai.xi {
344*53ee8cc1Swenshuai.xi #if defined(__aarch64__) || defined(__arm__)
345*53ee8cc1Swenshuai.xi #ifndef MSOS_TYPE_LINUX
346*53ee8cc1Swenshuai.xi     _chip_flush_miu_pipe();
347*53ee8cc1Swenshuai.xi #endif
348*53ee8cc1Swenshuai.xi #endif
349*53ee8cc1Swenshuai.xi }
350*53ee8cc1Swenshuai.xi 
351*53ee8cc1Swenshuai.xi 
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