1*53ee8cc1Swenshuai.xi //<MStar Software>
2*53ee8cc1Swenshuai.xi //******************************************************************************
3*53ee8cc1Swenshuai.xi // MStar Software
4*53ee8cc1Swenshuai.xi // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5*53ee8cc1Swenshuai.xi // All software, firmware and related documentation herein ("MStar Software") are
6*53ee8cc1Swenshuai.xi // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7*53ee8cc1Swenshuai.xi // law, including, but not limited to, copyright law and international treaties.
8*53ee8cc1Swenshuai.xi // Any use, modification, reproduction, retransmission, or republication of all
9*53ee8cc1Swenshuai.xi // or part of MStar Software is expressly prohibited, unless prior written
10*53ee8cc1Swenshuai.xi // permission has been granted by MStar.
11*53ee8cc1Swenshuai.xi //
12*53ee8cc1Swenshuai.xi // By accessing, browsing and/or using MStar Software, you acknowledge that you
13*53ee8cc1Swenshuai.xi // have read, understood, and agree, to be bound by below terms ("Terms") and to
14*53ee8cc1Swenshuai.xi // comply with all applicable laws and regulations:
15*53ee8cc1Swenshuai.xi //
16*53ee8cc1Swenshuai.xi // 1. MStar shall retain any and all right, ownership and interest to MStar
17*53ee8cc1Swenshuai.xi // Software and any modification/derivatives thereof.
18*53ee8cc1Swenshuai.xi // No right, ownership, or interest to MStar Software and any
19*53ee8cc1Swenshuai.xi // modification/derivatives thereof is transferred to you under Terms.
20*53ee8cc1Swenshuai.xi //
21*53ee8cc1Swenshuai.xi // 2. You understand that MStar Software might include, incorporate or be
22*53ee8cc1Swenshuai.xi // supplied together with third party`s software and the use of MStar
23*53ee8cc1Swenshuai.xi // Software may require additional licenses from third parties.
24*53ee8cc1Swenshuai.xi // Therefore, you hereby agree it is your sole responsibility to separately
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26*53ee8cc1Swenshuai.xi // such third party`s software.
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29*53ee8cc1Swenshuai.xi // MStar`s confidential information and you agree to keep MStar`s
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31*53ee8cc1Swenshuai.xi // third party.
32*53ee8cc1Swenshuai.xi //
33*53ee8cc1Swenshuai.xi // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34*53ee8cc1Swenshuai.xi // kind. Any warranties are hereby expressly disclaimed by MStar, including
35*53ee8cc1Swenshuai.xi // without limitation, any warranties of merchantability, non-infringement of
36*53ee8cc1Swenshuai.xi // intellectual property rights, fitness for a particular purpose, error free
37*53ee8cc1Swenshuai.xi // and in conformity with any international standard. You agree to waive any
38*53ee8cc1Swenshuai.xi // claim against MStar for any loss, damage, cost or expense that you may
39*53ee8cc1Swenshuai.xi // incur related to your use of MStar Software.
40*53ee8cc1Swenshuai.xi // In no event shall MStar be liable for any direct, indirect, incidental or
41*53ee8cc1Swenshuai.xi // consequential damages, including without limitation, lost of profit or
42*53ee8cc1Swenshuai.xi // revenues, lost or damage of data, and unauthorized system use.
43*53ee8cc1Swenshuai.xi // You agree that this Section 4 shall still apply without being affected
44*53ee8cc1Swenshuai.xi // even if MStar Software has been modified by MStar in accordance with your
45*53ee8cc1Swenshuai.xi // request or instruction for your use, except otherwise agreed by both
46*53ee8cc1Swenshuai.xi // parties in writing.
47*53ee8cc1Swenshuai.xi //
48*53ee8cc1Swenshuai.xi // 5. If requested, MStar may from time to time provide technical supports or
49*53ee8cc1Swenshuai.xi // services in relation with MStar Software to you for your use of
50*53ee8cc1Swenshuai.xi // MStar Software in conjunction with your or your customer`s product
51*53ee8cc1Swenshuai.xi // ("Services").
52*53ee8cc1Swenshuai.xi // You understand and agree that, except otherwise agreed by both parties in
53*53ee8cc1Swenshuai.xi // writing, Services are provided on an "AS IS" basis and the warranty
54*53ee8cc1Swenshuai.xi // disclaimer set forth in Section 4 above shall apply.
55*53ee8cc1Swenshuai.xi //
56*53ee8cc1Swenshuai.xi // 6. Nothing contained herein shall be construed as by implication, estoppels
57*53ee8cc1Swenshuai.xi // or otherwise:
58*53ee8cc1Swenshuai.xi // (a) conferring any license or right to use MStar name, trademark, service
59*53ee8cc1Swenshuai.xi // mark, symbol or any other identification;
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61*53ee8cc1Swenshuai.xi // including without limitation, you and your customers, any assistance
62*53ee8cc1Swenshuai.xi // of any kind whatsoever, or any information; or
63*53ee8cc1Swenshuai.xi // (c) conferring any license or right under any intellectual property right.
64*53ee8cc1Swenshuai.xi //
65*53ee8cc1Swenshuai.xi // 7. These terms shall be governed by and construed in accordance with the laws
66*53ee8cc1Swenshuai.xi // of Taiwan, R.O.C., excluding its conflict of law rules.
67*53ee8cc1Swenshuai.xi // Any and all dispute arising out hereof or related hereto shall be finally
68*53ee8cc1Swenshuai.xi // settled by arbitration referred to the Chinese Arbitration Association,
69*53ee8cc1Swenshuai.xi // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70*53ee8cc1Swenshuai.xi // Rules of the Association by three (3) arbitrators appointed in accordance
71*53ee8cc1Swenshuai.xi // with the said Rules.
72*53ee8cc1Swenshuai.xi // The place of arbitration shall be in Taipei, Taiwan and the language shall
73*53ee8cc1Swenshuai.xi // be English.
74*53ee8cc1Swenshuai.xi // The arbitration award shall be final and binding to both parties.
75*53ee8cc1Swenshuai.xi //
76*53ee8cc1Swenshuai.xi //******************************************************************************
77*53ee8cc1Swenshuai.xi //<MStar Software>
78*53ee8cc1Swenshuai.xi
79*53ee8cc1Swenshuai.xi ///////////////////////////////////////////////////////////////////////////////////////////////////
80*53ee8cc1Swenshuai.xi ///
81*53ee8cc1Swenshuai.xi /// file halMMIO.c
82*53ee8cc1Swenshuai.xi /// @brief memory map io (MMIO) HAL
83*53ee8cc1Swenshuai.xi /// @author MStar Semiconductor Inc.
84*53ee8cc1Swenshuai.xi ///////////////////////////////////////////////////////////////////////////////////////////////////
85*53ee8cc1Swenshuai.xi
86*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
87*53ee8cc1Swenshuai.xi // Include Files
88*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
89*53ee8cc1Swenshuai.xi
90*53ee8cc1Swenshuai.xi #include "MsCommon.h"
91*53ee8cc1Swenshuai.xi #include "halMMIO.h"
92*53ee8cc1Swenshuai.xi #include "drvMMIO.h"
93*53ee8cc1Swenshuai.xi
94*53ee8cc1Swenshuai.xi // for getting mapped IO base from DRV
95*53ee8cc1Swenshuai.xi extern MS_U32 _u32PM_Bank;
96*53ee8cc1Swenshuai.xi extern MS_U32 _u32PM_Bank_SIZE;
97*53ee8cc1Swenshuai.xi extern MS_U32 _u32NonPM_Bank;
98*53ee8cc1Swenshuai.xi extern MS_U32 _u32NonPM_Bank_SIZE;
99*53ee8cc1Swenshuai.xi
100*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
101*53ee8cc1Swenshuai.xi // Driver Compiler Options
102*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
103*53ee8cc1Swenshuai.xi
104*53ee8cc1Swenshuai.xi //--------------------------------------------------------------------------------------------------
105*53ee8cc1Swenshuai.xi // Global Variables
106*53ee8cc1Swenshuai.xi //--------------------------------------------------------------------------------------------------
107*53ee8cc1Swenshuai.xi MS_U32 u32_ge0_mmio_base;
108*53ee8cc1Swenshuai.xi
109*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
110*53ee8cc1Swenshuai.xi // Local Defines
111*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
112*53ee8cc1Swenshuai.xi #ifdef MSOS_TYPE_LINUX
113*53ee8cc1Swenshuai.xi
114*53ee8cc1Swenshuai.xi #define HAL_MMIO_PM_BASE 0x1f000000UL
115*53ee8cc1Swenshuai.xi #define HAL_MMIO_PM_SIZE 0x002E0000UL
116*53ee8cc1Swenshuai.xi #define HAL_MMIO_NONPM_BASE 0x1f200000UL
117*53ee8cc1Swenshuai.xi #define HAL_MMIO_NONPM_SIZE 0x000e0000UL
118*53ee8cc1Swenshuai.xi #define HAL_MMIO_FLASH_BASE0 0x14000000UL
119*53ee8cc1Swenshuai.xi #define HAL_MMIO_FLASH_SIZE0 0x01000000UL
120*53ee8cc1Swenshuai.xi #define HAL_MMIO_OTP_BASE 0x10000000UL
121*53ee8cc1Swenshuai.xi #define HAL_MMIO_OTP_SIZE 0x00002000UL
122*53ee8cc1Swenshuai.xi
123*53ee8cc1Swenshuai.xi #else
124*53ee8cc1Swenshuai.xi
125*53ee8cc1Swenshuai.xi #if defined(MCU_AEON)
126*53ee8cc1Swenshuai.xi #define HAL_MMIO_PM_BASE 0xFA000000UL
127*53ee8cc1Swenshuai.xi #define HAL_MMIO_PM_SIZE 0x00007B80UL
128*53ee8cc1Swenshuai.xi #define HAL_MMIO_NONPM_BASE 0xFA200000UL
129*53ee8cc1Swenshuai.xi #define HAL_MMIO_NONPM_SIZE 0x00025600UL
130*53ee8cc1Swenshuai.xi #define HAL_MMIO_FLASH_BASE0 0xF9000000UL // non-cache // 0xA1000000 for cache
131*53ee8cc1Swenshuai.xi #define HAL_MMIO_FLASH_SIZE0 0x01000000UL
132*53ee8cc1Swenshuai.xi
133*53ee8cc1Swenshuai.xi #elif defined(__mips__)
134*53ee8cc1Swenshuai.xi #define HAL_MMIO_PM_BASE 0xbf000000UL
135*53ee8cc1Swenshuai.xi #define HAL_MMIO_PM_SIZE 0x00007B80UL
136*53ee8cc1Swenshuai.xi #define HAL_MMIO_NONPM_BASE 0xbf200000UL
137*53ee8cc1Swenshuai.xi #define HAL_MMIO_NONPM_SIZE 0x00025600UL
138*53ee8cc1Swenshuai.xi #define HAL_MMIO_FLASH_BASE0 0xB4000000UL // 0x94000000 for cache
139*53ee8cc1Swenshuai.xi #define HAL_MMIO_FLASH_SIZE0 0x01000000UL
140*53ee8cc1Swenshuai.xi #define HAL_MMIO_OTP_BASE 0xB0000000UL
141*53ee8cc1Swenshuai.xi #define HAL_MMIO_OTP_SIZE 0x00002000UL
142*53ee8cc1Swenshuai.xi
143*53ee8cc1Swenshuai.xi #elif defined(__arm__)
144*53ee8cc1Swenshuai.xi #if defined (MBOOT) || defined (MSOS_TYPE_NUTTX)
145*53ee8cc1Swenshuai.xi #define HAL_MMIO_PM_BASE 0x1f000000UL
146*53ee8cc1Swenshuai.xi #define HAL_MMIO_PM_SIZE 0x00007B80UL
147*53ee8cc1Swenshuai.xi #define HAL_MMIO_NONPM_BASE 0x1f200000UL
148*53ee8cc1Swenshuai.xi #define HAL_MMIO_NONPM_SIZE 0x00025600UL
149*53ee8cc1Swenshuai.xi #define HAL_MMIO_FLASH_BASE0 0x14000000UL
150*53ee8cc1Swenshuai.xi #define HAL_MMIO_FLASH_SIZE0 0x01000000UL
151*53ee8cc1Swenshuai.xi #define HAL_MMIO_OTP_BASE 0xfd800000UL
152*53ee8cc1Swenshuai.xi #define HAL_MMIO_OTP_SIZE 0x00002000UL
153*53ee8cc1Swenshuai.xi #else
154*53ee8cc1Swenshuai.xi #define HAL_MMIO_PM_BASE 0xfd000000UL
155*53ee8cc1Swenshuai.xi #define HAL_MMIO_PM_SIZE 0x00007B80UL
156*53ee8cc1Swenshuai.xi #define HAL_MMIO_NONPM_BASE 0xfd200000UL
157*53ee8cc1Swenshuai.xi #define HAL_MMIO_NONPM_SIZE 0x00025600UL
158*53ee8cc1Swenshuai.xi #define HAL_MMIO_FLASH_BASE0 0xfe000000UL
159*53ee8cc1Swenshuai.xi #define HAL_MMIO_FLASH_SIZE0 0x01000000UL
160*53ee8cc1Swenshuai.xi #define HAL_MMIO_OTP_BASE 0xfd800000UL
161*53ee8cc1Swenshuai.xi #define HAL_MMIO_OTP_SIZE 0x00002000UL
162*53ee8cc1Swenshuai.xi #endif
163*53ee8cc1Swenshuai.xi
164*53ee8cc1Swenshuai.xi #else
165*53ee8cc1Swenshuai.xi #error "Invalid MCU Type";
166*53ee8cc1Swenshuai.xi #endif
167*53ee8cc1Swenshuai.xi
168*53ee8cc1Swenshuai.xi #endif //MSOS_TYPE_LINUX
169*53ee8cc1Swenshuai.xi
170*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
171*53ee8cc1Swenshuai.xi // Local Structurs
172*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
173*53ee8cc1Swenshuai.xi
174*53ee8cc1Swenshuai.xi
175*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
176*53ee8cc1Swenshuai.xi // Global Variables
177*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
178*53ee8cc1Swenshuai.xi
179*53ee8cc1Swenshuai.xi
180*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
181*53ee8cc1Swenshuai.xi // Local Variables
182*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
183*53ee8cc1Swenshuai.xi
184*53ee8cc1Swenshuai.xi
185*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
186*53ee8cc1Swenshuai.xi // Debug Functions
187*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
188*53ee8cc1Swenshuai.xi
189*53ee8cc1Swenshuai.xi
190*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
191*53ee8cc1Swenshuai.xi // Local Functions
192*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
193*53ee8cc1Swenshuai.xi
194*53ee8cc1Swenshuai.xi
195*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
196*53ee8cc1Swenshuai.xi // Global Functions
197*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
HAL_MMIO_GetType(MS_U32 u32Module)198*53ee8cc1Swenshuai.xi MS_U16 HAL_MMIO_GetType(MS_U32 u32Module)
199*53ee8cc1Swenshuai.xi {
200*53ee8cc1Swenshuai.xi MS_U16 wMmioBankType = 0xFFFF;
201*53ee8cc1Swenshuai.xi
202*53ee8cc1Swenshuai.xi switch (u32Module)
203*53ee8cc1Swenshuai.xi {
204*53ee8cc1Swenshuai.xi //HAL_MMIO_PM_BANK
205*53ee8cc1Swenshuai.xi case MS_MODULE_PM:
206*53ee8cc1Swenshuai.xi case MS_MODULE_IR:
207*53ee8cc1Swenshuai.xi case MS_MODULE_ISP:
208*53ee8cc1Swenshuai.xi case MS_MODULE_PWS:
209*53ee8cc1Swenshuai.xi wMmioBankType = DRV_MMIO_PM_BANK;
210*53ee8cc1Swenshuai.xi break;
211*53ee8cc1Swenshuai.xi
212*53ee8cc1Swenshuai.xi //HAL_MMIO_NONPM_BANK
213*53ee8cc1Swenshuai.xi case MS_MODULE_HW:
214*53ee8cc1Swenshuai.xi case MS_MODULE_CHIPTOP:
215*53ee8cc1Swenshuai.xi case MS_MODULE_MIU:
216*53ee8cc1Swenshuai.xi case MS_MODULE_ACE:
217*53ee8cc1Swenshuai.xi case MS_MODULE_AUDIO:
218*53ee8cc1Swenshuai.xi case MS_MODULE_AVD:
219*53ee8cc1Swenshuai.xi case MS_MODULE_BDMA:
220*53ee8cc1Swenshuai.xi case MS_MODULE_DLC:
221*53ee8cc1Swenshuai.xi case MS_MODULE_DMD:
222*53ee8cc1Swenshuai.xi case MS_MODULE_GE:
223*53ee8cc1Swenshuai.xi case MS_MODULE_GOP:
224*53ee8cc1Swenshuai.xi case MS_MODULE_GPIO:
225*53ee8cc1Swenshuai.xi case MS_MODULE_HVD:
226*53ee8cc1Swenshuai.xi case MS_MODULE_HWI2C:
227*53ee8cc1Swenshuai.xi case MS_MODULE_IRQ:
228*53ee8cc1Swenshuai.xi case MS_MODULE_JPD:
229*53ee8cc1Swenshuai.xi case MS_MODULE_MBX:
230*53ee8cc1Swenshuai.xi case MS_MODULE_MFE:
231*53ee8cc1Swenshuai.xi case MS_MODULE_MHEG5:
232*53ee8cc1Swenshuai.xi case MS_MODULE_MVD:
233*53ee8cc1Swenshuai.xi case MS_MODULE_MVOP:
234*53ee8cc1Swenshuai.xi case MS_MODULE_RVD:
235*53ee8cc1Swenshuai.xi case MS_MODULE_TSP:
236*53ee8cc1Swenshuai.xi case MS_MODULE_UART:
237*53ee8cc1Swenshuai.xi case MS_MODULE_VPU:
238*53ee8cc1Swenshuai.xi case MS_MODULE_XC:
239*53ee8cc1Swenshuai.xi case MS_MODULE_PCMCIA:
240*53ee8cc1Swenshuai.xi case MS_MODULE_PFSH:
241*53ee8cc1Swenshuai.xi case MS_MODULE_PNL:
242*53ee8cc1Swenshuai.xi case MS_MODULE_PWM:
243*53ee8cc1Swenshuai.xi case MS_MODULE_SEM:
244*53ee8cc1Swenshuai.xi case MS_MODULE_VBI:
245*53ee8cc1Swenshuai.xi case MS_MODULE_VIF:
246*53ee8cc1Swenshuai.xi case MS_MODULE_DIP:
247*53ee8cc1Swenshuai.xi case MS_MODULE_MPIF:
248*53ee8cc1Swenshuai.xi case MS_MODULE_MMFILEIN:
249*53ee8cc1Swenshuai.xi case MS_MODULE_GPD:
250*53ee8cc1Swenshuai.xi case MS_MODULE_TSO:
251*53ee8cc1Swenshuai.xi case MS_MODULE_CMDQ:
252*53ee8cc1Swenshuai.xi wMmioBankType = DRV_MMIO_NONPM_BANK;
253*53ee8cc1Swenshuai.xi break;
254*53ee8cc1Swenshuai.xi
255*53ee8cc1Swenshuai.xi case MS_MODULE_SC:
256*53ee8cc1Swenshuai.xi wMmioBankType = DRV_MMIO_SC_BANK;
257*53ee8cc1Swenshuai.xi break;
258*53ee8cc1Swenshuai.xi
259*53ee8cc1Swenshuai.xi //HAL_MMIO_FLASH_BANK0
260*53ee8cc1Swenshuai.xi case MS_MODULE_FLASH:
261*53ee8cc1Swenshuai.xi wMmioBankType = DRV_MMIO_FLASH_BANK0;
262*53ee8cc1Swenshuai.xi break;
263*53ee8cc1Swenshuai.xi
264*53ee8cc1Swenshuai.xi default:
265*53ee8cc1Swenshuai.xi wMmioBankType = 0xFFFF;
266*53ee8cc1Swenshuai.xi break;
267*53ee8cc1Swenshuai.xi
268*53ee8cc1Swenshuai.xi }
269*53ee8cc1Swenshuai.xi
270*53ee8cc1Swenshuai.xi return wMmioBankType;
271*53ee8cc1Swenshuai.xi }
272*53ee8cc1Swenshuai.xi
273*53ee8cc1Swenshuai.xi
HAL_MMIO_GetBase(MS_U32 * pu32BaseAddr,MS_U32 * pu32BaseSize,MS_U32 u32BankType)274*53ee8cc1Swenshuai.xi MS_BOOL HAL_MMIO_GetBase(MS_U32* pu32BaseAddr, MS_U32* pu32BaseSize, MS_U32 u32BankType)
275*53ee8cc1Swenshuai.xi {
276*53ee8cc1Swenshuai.xi MS_BOOL bRet = TRUE;
277*53ee8cc1Swenshuai.xi
278*53ee8cc1Swenshuai.xi *pu32BaseAddr = 0;
279*53ee8cc1Swenshuai.xi *pu32BaseSize = 0;
280*53ee8cc1Swenshuai.xi switch (u32BankType)
281*53ee8cc1Swenshuai.xi {
282*53ee8cc1Swenshuai.xi case DRV_MMIO_PM_BANK:
283*53ee8cc1Swenshuai.xi *pu32BaseAddr = HAL_MMIO_PM_BASE;
284*53ee8cc1Swenshuai.xi *pu32BaseSize = HAL_MMIO_PM_SIZE;
285*53ee8cc1Swenshuai.xi break;
286*53ee8cc1Swenshuai.xi
287*53ee8cc1Swenshuai.xi case DRV_MMIO_NONPM_BANK:
288*53ee8cc1Swenshuai.xi *pu32BaseAddr = HAL_MMIO_NONPM_BASE;
289*53ee8cc1Swenshuai.xi *pu32BaseSize = HAL_MMIO_NONPM_SIZE;
290*53ee8cc1Swenshuai.xi break;
291*53ee8cc1Swenshuai.xi
292*53ee8cc1Swenshuai.xi case DRV_MMIO_FLASH_BANK0:
293*53ee8cc1Swenshuai.xi *pu32BaseAddr = HAL_MMIO_FLASH_BASE0;
294*53ee8cc1Swenshuai.xi *pu32BaseSize = HAL_MMIO_FLASH_SIZE0;
295*53ee8cc1Swenshuai.xi break;
296*53ee8cc1Swenshuai.xi
297*53ee8cc1Swenshuai.xi case DRV_MMIO_OTP_BANK:
298*53ee8cc1Swenshuai.xi #if defined (MCU_AEON)
299*53ee8cc1Swenshuai.xi bRet = FALSE;
300*53ee8cc1Swenshuai.xi #else
301*53ee8cc1Swenshuai.xi *pu32BaseAddr = HAL_MMIO_OTP_BASE;
302*53ee8cc1Swenshuai.xi *pu32BaseSize = HAL_MMIO_OTP_SIZE;
303*53ee8cc1Swenshuai.xi #endif
304*53ee8cc1Swenshuai.xi break;
305*53ee8cc1Swenshuai.xi case DRV_MMIO_FRC_BANK:
306*53ee8cc1Swenshuai.xi break;
307*53ee8cc1Swenshuai.xi default:
308*53ee8cc1Swenshuai.xi // MS_ASSERT(0);
309*53ee8cc1Swenshuai.xi bRet = FALSE;
310*53ee8cc1Swenshuai.xi break;
311*53ee8cc1Swenshuai.xi }
312*53ee8cc1Swenshuai.xi
313*53ee8cc1Swenshuai.xi return bRet;
314*53ee8cc1Swenshuai.xi }
315*53ee8cc1Swenshuai.xi
316*53ee8cc1Swenshuai.xi
317*53ee8cc1Swenshuai.xi // @NOTE: Only run after MMIO_Init
HAL_MMIO_GetIPBase(MS_U32 * pu32BaseAddr,MS_U16 u16BankType)318*53ee8cc1Swenshuai.xi MS_BOOL HAL_MMIO_GetIPBase(MS_U32 *pu32BaseAddr, MS_U16 u16BankType)
319*53ee8cc1Swenshuai.xi {
320*53ee8cc1Swenshuai.xi *pu32BaseAddr = 0;
321*53ee8cc1Swenshuai.xi
322*53ee8cc1Swenshuai.xi // if MMIO_Init is not yet initialized.
323*53ee8cc1Swenshuai.xi if((_u32PM_Bank_SIZE == 0x0) || (_u32NonPM_Bank_SIZE == 0x0))
324*53ee8cc1Swenshuai.xi {
325*53ee8cc1Swenshuai.xi return FALSE;
326*53ee8cc1Swenshuai.xi }
327*53ee8cc1Swenshuai.xi
328*53ee8cc1Swenshuai.xi switch (u16BankType)
329*53ee8cc1Swenshuai.xi {
330*53ee8cc1Swenshuai.xi case DRV_MMIO_SC_BANK:
331*53ee8cc1Swenshuai.xi *pu32BaseAddr =_u32NonPM_Bank + 0x00005200; // 0xBF220C00, 0xBF220C80
332*53ee8cc1Swenshuai.xi break;
333*53ee8cc1Swenshuai.xi
334*53ee8cc1Swenshuai.xi default:
335*53ee8cc1Swenshuai.xi return FALSE;
336*53ee8cc1Swenshuai.xi }
337*53ee8cc1Swenshuai.xi
338*53ee8cc1Swenshuai.xi return TRUE;
339*53ee8cc1Swenshuai.xi }
340*53ee8cc1Swenshuai.xi
341*53ee8cc1Swenshuai.xi #if defined(__arm__)
342*53ee8cc1Swenshuai.xi #ifndef MSOS_TYPE_LINUX
_chip_flush_miu_pipe(void)343*53ee8cc1Swenshuai.xi static void _chip_flush_miu_pipe(void)
344*53ee8cc1Swenshuai.xi {
345*53ee8cc1Swenshuai.xi unsigned int dwReadData = 0;
346*53ee8cc1Swenshuai.xi
347*53ee8cc1Swenshuai.xi
348*53ee8cc1Swenshuai.xi //toggle the flush miu pipe fire bit
349*53ee8cc1Swenshuai.xi *(volatile unsigned int *)(HAL_MMIO_PM_BASE + (0x10188A << 1)) &= ~(0x0001);
350*53ee8cc1Swenshuai.xi *(volatile unsigned int *)(HAL_MMIO_PM_BASE + (0x10188A << 1)) |= 0x0001;
351*53ee8cc1Swenshuai.xi
352*53ee8cc1Swenshuai.xi do
353*53ee8cc1Swenshuai.xi {
354*53ee8cc1Swenshuai.xi dwReadData = *(volatile unsigned int *)(HAL_MMIO_PM_BASE+ (0x1018A0 << 1));
355*53ee8cc1Swenshuai.xi dwReadData &= BIT(12); //Check Status of Flush Pipe Finish
356*53ee8cc1Swenshuai.xi
357*53ee8cc1Swenshuai.xi } while(dwReadData == 0);
358*53ee8cc1Swenshuai.xi }
359*53ee8cc1Swenshuai.xi #endif
360*53ee8cc1Swenshuai.xi #endif
361*53ee8cc1Swenshuai.xi
HAL_MMIO_FlushMemory(void)362*53ee8cc1Swenshuai.xi void HAL_MMIO_FlushMemory(void)
363*53ee8cc1Swenshuai.xi {
364*53ee8cc1Swenshuai.xi #if defined(__arm__)
365*53ee8cc1Swenshuai.xi #ifndef MSOS_TYPE_LINUX
366*53ee8cc1Swenshuai.xi _chip_flush_miu_pipe();
367*53ee8cc1Swenshuai.xi #endif
368*53ee8cc1Swenshuai.xi #endif
369*53ee8cc1Swenshuai.xi }
370*53ee8cc1Swenshuai.xi
HAL_MMIO_ReadMemory(void)371*53ee8cc1Swenshuai.xi void HAL_MMIO_ReadMemory(void)
372*53ee8cc1Swenshuai.xi {
373*53ee8cc1Swenshuai.xi #if defined(__arm__)
374*53ee8cc1Swenshuai.xi #ifndef MSOS_TYPE_LINUX
375*53ee8cc1Swenshuai.xi _chip_flush_miu_pipe();
376*53ee8cc1Swenshuai.xi #endif
377*53ee8cc1Swenshuai.xi #endif
378*53ee8cc1Swenshuai.xi }
379*53ee8cc1Swenshuai.xi
380*53ee8cc1Swenshuai.xi
381