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93 ///////////////////////////////////////////////////////////////////////////////
94
95 ///////////////////////////////////////////////////////////////////////////////////////////////////
96 ///
97 /// file halMMIO.c
98 /// @brief memory map io (MMIO) HAL
99 /// @author MStar Semiconductor Inc.
100 ///////////////////////////////////////////////////////////////////////////////////////////////////
101
102
103 //-------------------------------------------------------------------------------------------------
104 // Include Files
105 //-------------------------------------------------------------------------------------------------
106
107 #include "MsCommon.h"
108 #include "halMMIO.h"
109 #include "drvMMIO.h"
110
111 // for getting mapped IO base from DRV
112 extern MS_VIRT _virtPM_Bank ;
113 extern MS_U32 _u32PM_Bank_SIZE ;
114 extern MS_VIRT _virtNonPM_Bank ;
115 extern MS_U32 _u32NonPM_Bank_SIZE ;
116 extern MS_VIRT _virtFRC_Bank ; //frcr2_integration###
117 extern MS_U32 _u32FRC_Bank_SIZE ; //frcr2_integration###
118
119 //-------------------------------------------------------------------------------------------------
120 // Driver Compiler Options
121 //-------------------------------------------------------------------------------------------------
122
123
124 //--------------------------------------------------------------------------------------------------
125 // Global Variables
126 //--------------------------------------------------------------------------------------------------
127 MS_VIRT virt_ge0_mmio_base;
128
129
130 //-------------------------------------------------------------------------------------------------
131 // Local Defines
132 //-------------------------------------------------------------------------------------------------
133 #ifdef MSOS_TYPE_LINUX
134 // assume linux always running on mips
135 #define HAL_MMIO_PM_BASE 0x1f000000UL
136 #define HAL_MMIO_PM_SIZE 0x00A00000UL
137 #define HAL_MMIO_NONPM_BASE 0x1f200000UL
138 #define HAL_MMIO_NONPM_SIZE 0x000e0000UL
139 #define HAL_MMIO_FLASH_BASE0 0x14000000UL
140 #define HAL_MMIO_FLASH_SIZE0 0x1000000UL
141 #define HAL_MMIO_FRC_BASE 0x1f800000UL //frcr2_integration###
142 #define HAL_MMIO_FRC_SIZE 0x00013600UL //frcr2_integration###
143 #else
144 #if defined (MCU_AEON)
145 #define HAL_MMIO_PM_BASE 0xFA000000UL
146 #define HAL_MMIO_PM_SIZE 0x00007B80UL
147 #define HAL_MMIO_NONPM_BASE 0xFA200000UL
148 #define HAL_MMIO_NONPM_SIZE 0x00025600UL
149 #define HAL_MMIO_FLASH_BASE0 0xA1000000UL // non-cache // 0xA1000000 for cache
150 #define HAL_MMIO_FLASH_SIZE0 0x1000000UL
151 #define HAL_MMIO_FRC_BASE 0xFA800000UL //frcr2_integration###
152 #define HAL_MMIO_FRC_SIZE 0x00013600UL //frcr2_integration###
153 #elif defined (MCU_ARM_CA7)
154 #define HAL_MMIO_PM_BASE 0x1f000000UL
155 #define HAL_MMIO_PM_SIZE 0x00007B80UL
156 #define HAL_MMIO_NONPM_BASE 0x1f200000UL
157 #define HAL_MMIO_NONPM_SIZE 0x00025600UL
158 #define HAL_MMIO_FLASH_BASE0 0x14000000UL
159 #define HAL_MMIO_FLASH_SIZE0 0x1000000UL
160 #define HAL_MMIO_FRC_BASE 0x1f800000UL //frcr2_integration###
161 #define HAL_MMIO_FRC_SIZE 0x00013600UL //frcr2_integration###
162 #elif defined (MCU_ARM_CA53)
163 #define HAL_MMIO_PM_BASE 0x1f000000UL
164 #define HAL_MMIO_PM_SIZE 0x00007B80UL
165 #define HAL_MMIO_NONPM_BASE 0x1f200000UL
166 #define HAL_MMIO_NONPM_SIZE 0x00025600UL
167 #define HAL_MMIO_FLASH_BASE0 0x14000000UL
168 #define HAL_MMIO_FLASH_SIZE0 0x1000000UL
169 #define HAL_MMIO_FRC_BASE 0x1f800000UL //frcr2_integration###
170 #define HAL_MMIO_FRC_SIZE 0x00013600UL //frcr2_integration###
171 #elif defined (MCU_ARM_9)
172 #if defined (MBOOT) || defined (MSOS_TYPE_NUTTX) || defined (MSOS_TYPE_OPTEE)
173 #define HAL_MMIO_PM_BASE 0x1f000000
174 #define HAL_MMIO_PM_SIZE 0x00007B80
175 #define HAL_MMIO_NONPM_BASE 0x1f200000
176 #define HAL_MMIO_NONPM_SIZE 0x00025600
177 #define HAL_MMIO_FLASH_BASE0 0x14000000
178 #define HAL_MMIO_FLASH_SIZE0 0x1000000
179 #else
180 #define HAL_MMIO_PM_BASE 0xfd000000
181 #define HAL_MMIO_PM_SIZE 0x00007B80
182 #define HAL_MMIO_NONPM_BASE 0xfd200000
183 #define HAL_MMIO_NONPM_SIZE 0x00025600
184 #define HAL_MMIO_FLASH_BASE0 0xfe000000
185 #define HAL_MMIO_FLASH_SIZE0 0x1000000
186 #endif
187 #define HAL_MMIO_FRC_BASE 0x1f800000UL //frcr2_integration###
188 #define HAL_MMIO_FRC_SIZE 0x00013600UL //frcr2_integration###
189 #else
190 #error "Please choose MCU";
191 #endif
192 #endif
193
194
195 //-------------------------------------------------------------------------------------------------
196 // Local Structurs
197 //-------------------------------------------------------------------------------------------------
198
199
200 //-------------------------------------------------------------------------------------------------
201 // Global Variables
202 //-------------------------------------------------------------------------------------------------
203
204
205 //-------------------------------------------------------------------------------------------------
206 // Local Variables
207 //-------------------------------------------------------------------------------------------------
208
209
210 //-------------------------------------------------------------------------------------------------
211 // Debug Functions
212 //-------------------------------------------------------------------------------------------------
213
214
215 //-------------------------------------------------------------------------------------------------
216 // Local Functions
217 //-------------------------------------------------------------------------------------------------
218
219
220 //-------------------------------------------------------------------------------------------------
221 // Global Functions
222 //-------------------------------------------------------------------------------------------------
HAL_MMIO_GetType(MS_U32 u32Module)223 MS_U16 HAL_MMIO_GetType(MS_U32 u32Module)
224 {
225 switch (u32Module)
226 {
227 //HAL_MMIO_PM_BANK
228 case MS_MODULE_PM :
229 case MS_MODULE_IR :
230 case MS_MODULE_ISP :
231 case MS_MODULE_PWS :
232 return DRV_MMIO_PM_BANK;
233
234 //HAL_MMIO_NONPM_BANK
235 case MS_MODULE_HW :
236 case MS_MODULE_CHIPTOP :
237 case MS_MODULE_MIU :
238 case MS_MODULE_ACE :
239 case MS_MODULE_AUDIO :
240 case MS_MODULE_AVD :
241 case MS_MODULE_BDMA :
242 case MS_MODULE_DLC :
243 case MS_MODULE_DMD :
244 case MS_MODULE_GE :
245 case MS_MODULE_GOP :
246 case MS_MODULE_GPIO :
247 case MS_MODULE_HVD :
248 case MS_MODULE_HWI2C :
249 case MS_MODULE_IRQ :
250 case MS_MODULE_JPD :
251 case MS_MODULE_MBX :
252 case MS_MODULE_MFE :
253 case MS_MODULE_MHEG5 :
254 case MS_MODULE_MVD :
255 case MS_MODULE_MVOP :
256 case MS_MODULE_RVD :
257 case MS_MODULE_TSP :
258 case MS_MODULE_UART :
259 case MS_MODULE_VPU :
260 case MS_MODULE_XC :
261 case MS_MODULE_PCMCIA :
262 case MS_MODULE_PFSH :
263 case MS_MODULE_PNL :
264 case MS_MODULE_PWM :
265 case MS_MODULE_SEM :
266 case MS_MODULE_VBI :
267 case MS_MODULE_VIF :
268 case MS_MODULE_DIP :
269 case MS_MODULE_MPIF :
270 case MS_MODULE_MMFILEIN :
271 case MS_MODULE_GPD :
272 case MS_MODULE_TSO :
273 case MS_MODULE_CMDQ :
274 return DRV_MMIO_NONPM_BANK;
275
276 case MS_MODULE_SC :
277 return DRV_MMIO_SC_BANK;
278
279 //HAL_MMIO_FLASH_BANK0
280 case MS_MODULE_FLASH :
281 return DRV_MMIO_FLASH_BANK0;
282 case MS_MODULE_FRC : //frcr2_integration###
283 return DRV_MMIO_FRC_BANK; //frcr2_integration###
284
285 default:
286 return 0xFFFF; //undefine type
287 }
288
289 return 0xFFFF; //undefine type
290 }
291
292
HAL_MMIO_GetBase(MS_PHY * virtBaseAddr,MS_PHY * pu32BaseSize,MS_U32 u32BankType)293 MS_BOOL HAL_MMIO_GetBase(MS_PHY* virtBaseAddr, MS_PHY* pu32BaseSize, MS_U32 u32BankType)
294 {
295 MS_BOOL bRet = TRUE;
296
297 *virtBaseAddr = 0;
298 *pu32BaseSize = 0;
299 switch (u32BankType)
300 {
301 case DRV_MMIO_PM_BANK:
302 *virtBaseAddr = (MS_PHY)HAL_MMIO_PM_BASE;
303 *pu32BaseSize = (MS_PHY)HAL_MMIO_PM_SIZE;
304 break;
305 case DRV_MMIO_NONPM_BANK:
306 *virtBaseAddr = (MS_PHY)HAL_MMIO_NONPM_BASE;
307 *pu32BaseSize = (MS_PHY)HAL_MMIO_NONPM_SIZE;
308 break;
309 case DRV_MMIO_FLASH_BANK0:
310 *virtBaseAddr = (MS_PHY)HAL_MMIO_FLASH_BASE0;
311 *pu32BaseSize = (MS_PHY)HAL_MMIO_FLASH_SIZE0;
312 break;
313 case DRV_MMIO_FRC_BANK:
314 *virtBaseAddr = (MS_PHY)HAL_MMIO_FRC_BASE;
315 *pu32BaseSize = (MS_PHY)HAL_MMIO_FRC_SIZE;
316 break;
317 default:
318 // MS_ASSERT(0);
319 bRet = FALSE;
320 break;
321 }
322
323 return bRet;
324 }
325
326
327 // @NOTE: Only run after MMIO_Init
HAL_MMIO_GetIPBase(MS_VIRT * virtBaseAddr,MS_U16 u16BankType)328 MS_BOOL HAL_MMIO_GetIPBase(MS_VIRT *virtBaseAddr, MS_U16 u16BankType)
329 {
330 *virtBaseAddr = 0;
331
332 // if MMIO_Init is not yet initialized.
333 if ( (_u32PM_Bank_SIZE == 0x0) || (_u32NonPM_Bank_SIZE == 0x0) || (_u32FRC_Bank_SIZE == 0x0) ) //frcr2_integration###
334 {
335 return FALSE;
336 }
337
338 switch (u16BankType)
339 {
340 case DRV_MMIO_SC_BANK:
341 *virtBaseAddr =_virtNonPM_Bank + 0x00005200; // 0xBF220C00, 0xBF220C80
342 break;
343 default:
344 return FALSE;
345 }
346
347 return TRUE;
348 }
349
350 #if defined(__aarch64__) || defined(__arm__)
351 #ifndef MSOS_TYPE_LINUX
_chip_flush_miu_pipe(void)352 static void _chip_flush_miu_pipe(void)
353 {
354 unsigned int dwReadData = 0;
355
356
357 //toggle the flush miu pipe fire bit
358 *(volatile unsigned int *)(HAL_MMIO_PM_BASE + (0x10188A << 1)) &= ~(0x0001);
359 *(volatile unsigned int *)(HAL_MMIO_PM_BASE + (0x10188A << 1)) |= 0x0001;
360
361 do
362 {
363 dwReadData = *(volatile unsigned int *)(HAL_MMIO_PM_BASE+ (0x1018A0 << 1));
364 dwReadData &= BIT(12); //Check Status of Flush Pipe Finish
365
366 } while(dwReadData == 0);
367 }
368 #endif
369 #endif
370
HAL_MMIO_FlushMemory(void)371 void HAL_MMIO_FlushMemory(void)
372 {
373 #if defined(__aarch64__) || defined(__arm__)
374 #ifndef MSOS_TYPE_LINUX
375 _chip_flush_miu_pipe();
376 #endif
377 #endif
378 }
379
HAL_MMIO_ReadMemory(void)380 void HAL_MMIO_ReadMemory(void)
381 {
382 #if defined(__aarch64__) || defined(__arm__)
383 #ifndef MSOS_TYPE_LINUX
384 _chip_flush_miu_pipe();
385 #endif
386 #endif
387 }
388
389
390