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93 ///////////////////////////////////////////////////////////////////////////////
94
95 ///////////////////////////////////////////////////////////////////////////////////////////////////
96 ///
97 /// file halMMIO.c
98 /// @brief memory map io (MMIO) HAL
99 /// @author MStar Semiconductor Inc.
100 ///////////////////////////////////////////////////////////////////////////////////////////////////
101
102 //-------------------------------------------------------------------------------------------------
103 // Include Files
104 //-------------------------------------------------------------------------------------------------
105
106 #include "MsCommon.h"
107 #include "halMMIO.h"
108 #include "drvMMIO.h"
109
110 // for getting mapped IO base from DRV
111 extern MS_VIRT _virtPM_Bank ;
112 extern MS_U32 _u32PM_Bank_SIZE ;
113 extern MS_VIRT _virtNonPM_Bank ;
114 extern MS_U32 _u32NonPM_Bank_SIZE ;
115
116 //-------------------------------------------------------------------------------------------------
117 // Driver Compiler Options
118 //-------------------------------------------------------------------------------------------------
119
120 //--------------------------------------------------------------------------------------------------
121 // Global Variables
122 //--------------------------------------------------------------------------------------------------
123 MS_VIRT virt_ge0_mmio_base;
124
125 //-------------------------------------------------------------------------------------------------
126 // Local Defines
127 //-------------------------------------------------------------------------------------------------
128 #ifdef MSOS_TYPE_LINUX
129
130 #define HAL_MMIO_PM_BASE 0x1f000000
131 #define HAL_MMIO_PM_SIZE 0x00400000
132 #define HAL_MMIO_NONPM_BASE 0x1f200000
133 #define HAL_MMIO_NONPM_SIZE 0x00200000
134 #define HAL_MMIO_FLASH_BASE0 0x14000000
135 #define HAL_MMIO_FLASH_SIZE0 0x01000000
136 #define HAL_MMIO_OTP_BASE 0x10000000
137 #define HAL_MMIO_OTP_SIZE 0x00024000
138 #define HAL_MMIO_OTP_RAW_BASE 0x1f320000
139 #elif defined(MSOS_TYPE_LINUX_KERNEL)
140
141 #if defined(CONFIG_UTOPIA_FRAMEWORK_KERNEL_DRIVER_64BIT)
142 extern ptrdiff_t mstar_pm_base;
143 #define RIU_BASE mstar_pm_base
144 #else
145 #define RIU_BASE 0xfd000000UL
146 #endif
147 #define HAL_MMIO_PM_BASE RIU_BASE
148 #define HAL_MMIO_PM_SIZE 0x00400000UL
149 #define HAL_MMIO_NONPM_BASE RIU_BASE+0x200000UL
150 #define HAL_MMIO_NONPM_SIZE 0x00200000UL
151 #define HAL_MMIO_FLASH_BASE0 0x14000000UL
152 #define HAL_MMIO_FLASH_SIZE0 0x0100000UL
153 #define HAL_MMIO_OTP_BASE 0x10000000
154 #define HAL_MMIO_OTP_SIZE 0x00024000
155 #define HAL_MMIO_OTP_RAW_BASE RIU_BASE+0x320000UL
156 #else
157
158 #if defined(MCU_AEON)
159 #define HAL_MMIO_PM_BASE 0xFA000000
160 #define HAL_MMIO_PM_SIZE 0x00007B80
161 #define HAL_MMIO_NONPM_BASE 0xFA200000
162 #define HAL_MMIO_NONPM_SIZE 0x00025600
163 #define HAL_MMIO_FLASH_BASE0 0xF9000000 // non-cache // 0xA1000000 for cache
164 #define HAL_MMIO_FLASH_SIZE0 0x01000000
165
166 #elif defined(__mips__)
167 #define HAL_MMIO_PM_BASE 0xbf000000
168 #define HAL_MMIO_PM_SIZE 0x00007B80
169 #define HAL_MMIO_NONPM_BASE 0xbf200000
170 #define HAL_MMIO_NONPM_SIZE 0x00025600
171 #define HAL_MMIO_FLASH_BASE0 0xB4000000 // 0x94000000 for cache
172 #define HAL_MMIO_FLASH_SIZE0 0x01000000
173 #define HAL_MMIO_OTP_BASE 0xB0000000
174 #define HAL_MMIO_OTP_SIZE 0x00002000
175
176 #elif defined(__arm__) || defined(__aarch64__)
177 #if defined (CONFIG_MBOOT) || defined (MSOS_TYPE_NUTTX) || defined (MSOS_TYPE_OPTEE)
178 #define HAL_MMIO_PM_BASE 0x1f000000
179 #define HAL_MMIO_PM_SIZE 0x00400000
180 #define HAL_MMIO_NONPM_BASE 0x1f200000
181 #define HAL_MMIO_NONPM_SIZE 0x00200000
182 #define HAL_MMIO_FLASH_BASE0 0x14000000
183 #define HAL_MMIO_FLASH_SIZE0 0x01000000
184 #define HAL_MMIO_OTP_BASE 0xfd800000
185 #define HAL_MMIO_OTP_SIZE 0x00004000
186 #define HAL_MMIO_OTP_RAW_BASE 0x1f190000
187
188 #else
189 #define HAL_MMIO_PM_BASE 0xfd000000
190 #define HAL_MMIO_PM_SIZE 0x00400000
191 #define HAL_MMIO_NONPM_BASE 0xfd200000
192 #define HAL_MMIO_NONPM_SIZE 0x00200000
193 #define HAL_MMIO_FLASH_BASE0 0xfe000000
194 #define HAL_MMIO_FLASH_SIZE0 0x01000000
195 #define HAL_MMIO_OTP_BASE 0xfd800000
196 #define HAL_MMIO_OTP_SIZE 0x00024000
197 #define HAL_MMIO_OTP_RAW_BASE 0xfd320000
198
199 #endif
200
201 #else
202 #error "Invalid MCU Type";
203 #endif
204
205 #endif //MSOS_TYPE_LINUX
206
207 //-------------------------------------------------------------------------------------------------
208 // Local Structurs
209 //-------------------------------------------------------------------------------------------------
210
211
212 //-------------------------------------------------------------------------------------------------
213 // Global Variables
214 //-------------------------------------------------------------------------------------------------
215
216
217 //-------------------------------------------------------------------------------------------------
218 // Local Variables
219 //-------------------------------------------------------------------------------------------------
220
221
222 //-------------------------------------------------------------------------------------------------
223 // Debug Functions
224 //-------------------------------------------------------------------------------------------------
225
226
227 //-------------------------------------------------------------------------------------------------
228 // Local Functions
229 //-------------------------------------------------------------------------------------------------
230
231
232 //-------------------------------------------------------------------------------------------------
233 // Global Functions
234 //-------------------------------------------------------------------------------------------------
HAL_MMIO_GetType(MS_U32 u32Module)235 MS_U16 HAL_MMIO_GetType(MS_U32 u32Module)
236 {
237 switch (u32Module)
238 {
239 //HAL_MMIO_PM_BANK
240 case MS_MODULE_PM :
241 case MS_MODULE_IR :
242 case MS_MODULE_ISP :
243 case MS_MODULE_PWS :
244 case MS_MODULE_IR_TX :
245 return DRV_MMIO_PM_BANK;
246
247 //HAL_MMIO_NONPM_BANK
248 case MS_MODULE_HW :
249 case MS_MODULE_CHIPTOP :
250 case MS_MODULE_MIU :
251 case MS_MODULE_ACE :
252 case MS_MODULE_AUDIO :
253 case MS_MODULE_AVD :
254 case MS_MODULE_BDMA :
255 case MS_MODULE_DLC :
256 case MS_MODULE_DMD :
257 case MS_MODULE_GE :
258 case MS_MODULE_GOP :
259 case MS_MODULE_GPIO :
260 case MS_MODULE_HVD :
261 case MS_MODULE_HWI2C :
262 case MS_MODULE_IRQ :
263 case MS_MODULE_JPD :
264 case MS_MODULE_MBX :
265 case MS_MODULE_MFE :
266 case MS_MODULE_MHEG5 :
267 case MS_MODULE_MVD :
268 case MS_MODULE_MVOP :
269 case MS_MODULE_RVD :
270 case MS_MODULE_TSP :
271 case MS_MODULE_UART :
272 case MS_MODULE_VPU :
273 case MS_MODULE_XC :
274 case MS_MODULE_PCMCIA :
275 case MS_MODULE_PFSH :
276 case MS_MODULE_PNL :
277 case MS_MODULE_PWM :
278 case MS_MODULE_SEM :
279 case MS_MODULE_VBI :
280 case MS_MODULE_VIF :
281 case MS_MODULE_DIP :
282 case MS_MODULE_MPIF :
283 case MS_MODULE_MMFILEIN :
284 case MS_MODULE_GPD :
285 case MS_MODULE_TSO :
286 case MS_MODULE_CMDQ :
287 return DRV_MMIO_NONPM_BANK;
288
289 case MS_MODULE_SC :
290 return DRV_MMIO_SC_BANK;
291 case MS_MODULE_SC1 :
292 return DRV_MMIO_SC1_BANK;
293
294 //HAL_MMIO_FLASH_BANK0
295 case MS_MODULE_FLASH :
296 return DRV_MMIO_FLASH_BANK0;
297
298 case MS_MODULE_OTP2 :
299 return DRV_MMIO_OTP_BANK2;
300
301 default:
302 return 0xFFFF; //undefine type
303 }
304
305 return 0xFFFF; //undefine type
306 }
307
308
HAL_MMIO_GetBase(MS_PHY * virtBaseAddr,MS_PHY * pu32BaseSize,MS_U32 u32BankType)309 MS_BOOL HAL_MMIO_GetBase(MS_PHY* virtBaseAddr, MS_PHY* pu32BaseSize, MS_U32 u32BankType)
310 {
311 MS_BOOL bRet = TRUE;
312
313 *virtBaseAddr = 0;
314 *pu32BaseSize = 0;
315 switch (u32BankType)
316 {
317 case DRV_MMIO_FRC_BANK:
318 break;
319 case DRV_MMIO_PM_BANK:
320 *virtBaseAddr = (MS_PHY)HAL_MMIO_PM_BASE;
321 *pu32BaseSize = (MS_PHY)HAL_MMIO_PM_SIZE;
322 break;
323
324 case DRV_MMIO_NONPM_BANK:
325 *virtBaseAddr = (MS_PHY)HAL_MMIO_NONPM_BASE;
326 *pu32BaseSize = (MS_PHY)HAL_MMIO_NONPM_SIZE;
327 break;
328
329 case DRV_MMIO_FLASH_BANK0:
330 *virtBaseAddr = (MS_PHY)HAL_MMIO_FLASH_BASE0;
331 *pu32BaseSize = (MS_PHY)HAL_MMIO_FLASH_SIZE0;
332 break;
333
334 case DRV_MMIO_OTP_BANK:
335 #if defined (MCU_AEON)
336 bRet = FALSE;
337 #else
338 *virtBaseAddr = (MS_PHY)HAL_MMIO_OTP_BASE;
339 *pu32BaseSize = (MS_PHY)HAL_MMIO_OTP_SIZE;
340 #endif
341 break;
342 case DRV_MMIO_OTP_BANK2:
343 #if defined (MCU_AEON)
344 bRet = FALSE;
345 #else
346 *virtBaseAddr = (MS_PHY)HAL_MMIO_OTP_RAW_BASE;
347 *pu32BaseSize = (MS_PHY)HAL_MMIO_OTP_SIZE;
348 #endif
349 break;
350
351 default:
352 // MS_ASSERT(0);
353 bRet = FALSE;
354 break;
355 }
356
357 return bRet;
358 }
359
360
361 // @NOTE: Only run after MMIO_Init
HAL_MMIO_GetIPBase(MS_VIRT * virtBaseAddr,MS_U16 u16BankType)362 MS_BOOL HAL_MMIO_GetIPBase(MS_VIRT *virtBaseAddr, MS_U16 u16BankType)
363 {
364 *virtBaseAddr = 0;
365
366 // if MMIO_Init is not yet initialized.
367 if ( (_u32PM_Bank_SIZE == 0x0) || (_u32NonPM_Bank_SIZE == 0x0) )
368 {
369 return FALSE;
370 }
371
372 switch (u16BankType)
373 {
374 case DRV_MMIO_SC_BANK:
375 *virtBaseAddr =_virtNonPM_Bank + 0x00005200;
376 break;
377 case DRV_MMIO_SC1_BANK:
378 *virtBaseAddr =_virtNonPM_Bank + 0x00005400;
379 break;
380 default:
381 return FALSE;
382 }
383
384 return TRUE;
385 }
386
387 #if defined(__aarch64__) || defined(__arm__)
388 #if !defined (MSOS_TYPE_LINUX) && !defined (MSOS_TYPE_LINUX_KERNEL)
_chip_flush_miu_pipe(void)389 static void _chip_flush_miu_pipe(void)
390 {
391 unsigned int dwReadData = 0;
392
393
394 //toggle the flush miu pipe fire bit
395 *(volatile unsigned int *)(HAL_MMIO_PM_BASE + (0x10188A << 1)) &= ~(0x0001);
396 *(volatile unsigned int *)(HAL_MMIO_PM_BASE + (0x10188A << 1)) |= 0x0001;
397
398 do
399 {
400 dwReadData = *(volatile unsigned int *)(HAL_MMIO_PM_BASE+ (0x1018A0 << 1));
401 dwReadData &= BIT(12); //Check Status of Flush Pipe Finish
402
403 } while(dwReadData == 0);
404 }
405 #endif
406 #endif
407
HAL_MMIO_FlushMemory(void)408 void HAL_MMIO_FlushMemory(void)
409 {
410 #if defined(__aarch64__) || defined(__arm__)
411
412 #if !defined (MSOS_TYPE_LINUX) && !defined (MSOS_TYPE_LINUX_KERNEL)
413 _chip_flush_miu_pipe();
414 #endif
415 #endif
416 }
417
HAL_MMIO_ReadMemory(void)418 void HAL_MMIO_ReadMemory(void)
419 {
420 #if defined(__aarch64__) || defined(__arm__)
421 #if !defined (MSOS_TYPE_LINUX) && !defined (MSOS_TYPE_LINUX_KERNEL)
422 _chip_flush_miu_pipe();
423 #endif
424 #endif
425 }
426