1 #ifndef __RISC32_SPR_H__ 2 #define __RISC32_SPR_H__ 3 4 #if defined (__arm__) 5 #define set_cpsr(value) asm volatile ("msr cpsr, %0": :"r"(value)) 6 #define get_cpsr() \ 7 ({ \ 8 unsigned long value; \ 9 asm volatile ("mrs\t\t%0,cpsr": "=r"(value) : ); \ 10 value; \ 11 }) 12 #define mem_barrier(value) asm volatile ("mcr p15, 0, %0, c7, c10, 4": :"r"(value)) 13 14 #elif defined (__mips__) 15 16 #define mtsr(value) asm volatile (" mtc0 %0, $12" : : "r" (value)) 17 #define mfsr() \ 18 ({ \ 19 unsigned long value; \ 20 asm volatile ("mfc0\t\t%0,$12" : "=r" (value) : ); \ 21 value; \ 22 }) 23 24 #define mtcause(value) asm volatile (" mtc0 %0, $13" : : "r" (value)) 25 #define mfcause() \ 26 ({ \ 27 unsigned long value; \ 28 asm volatile ("mfc0\t\t%0,$13" : "=r" (value) : ); \ 29 value; \ 30 }) 31 32 #define mtepc(value) asm volatile (" mtc0 %0, $14" : : "r" (value)) 33 #define mfepc() \ 34 ({ \ 35 unsigned long value; \ 36 asm volatile ("mfc0\t\t%0,$14" : "=r" (value) : ); \ 37 value; \ 38 }) 39 40 41 #else 42 /* 43 * macros for SPR access 44 * 45 */ 46 #define mtspr(spr, value) \ 47 __asm__ __volatile__ ("l.mtspr\t\t%0,%1,0" : : "r" (spr), "r" (value)) 48 49 #define mfspr(spr) \ 50 ({ \ 51 unsigned long value; \ 52 __asm__ __volatile__ ("l.mfspr\t\t%0,%1,0" : "=r" (value) : "r" (spr) : "memory"); \ 53 value; \ 54 }) 55 #endif 56 57 #define MAX_GRPS (32) 58 #define MAX_SPRS_PER_GRP_BITS (11) 59 #define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS) 60 #define MAX_SPRS (0x10000) 61 62 /* Base addresses for the groups */ 63 #define SPRGROUP_SYS (0 << MAX_SPRS_PER_GRP_BITS) 64 #define SPRGROUP_DMMU (1 << MAX_SPRS_PER_GRP_BITS) 65 #define SPRGROUP_IMMU (2 << MAX_SPRS_PER_GRP_BITS) 66 #define SPRGROUP_DC (3 << MAX_SPRS_PER_GRP_BITS) 67 #define SPRGROUP_IC (4 << MAX_SPRS_PER_GRP_BITS) 68 #define SPRGROUP_MAC (5 << MAX_SPRS_PER_GRP_BITS) 69 #define SPRGROUP_D (6 << MAX_SPRS_PER_GRP_BITS) 70 #define SPRGROUP_PC (7 << MAX_SPRS_PER_GRP_BITS) 71 #define SPRGROUP_PM (8 << MAX_SPRS_PER_GRP_BITS) 72 #define SPRGROUP_PIC (9 << MAX_SPRS_PER_GRP_BITS) 73 #define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS) 74 75 /* System control and status group */ 76 #define SPR_VR (SPRGROUP_SYS + 0) 77 #define SPR_UPR (SPRGROUP_SYS + 1) 78 #define SPR_CPUCFGR (SPRGROUP_SYS + 2) 79 #define SPR_DMMUCFGR (SPRGROUP_SYS + 3) 80 #define SPR_IMMUCFGR (SPRGROUP_SYS + 4) 81 #define SPR_DCCFGR (SPRGROUP_SYS + 5) 82 #define SPR_ICCFGR (SPRGROUP_SYS + 6) 83 #define SPR_DCFGR (SPRGROUP_SYS + 7) 84 #define SPR_PCCFGR (SPRGROUP_SYS + 8) 85 #define SPR_NPC (SPRGROUP_SYS + 16) 86 #define SPR_SR (SPRGROUP_SYS + 17) 87 #define SPR_PPC (SPRGROUP_SYS + 18) 88 #define SPR_EPCR_BASE (SPRGROUP_SYS + 32) 89 #define SPR_EPCR_LAST (SPRGROUP_SYS + 47) 90 #define SPR_EEAR_BASE (SPRGROUP_SYS + 48) 91 #define SPR_EEAR_LAST (SPRGROUP_SYS + 63) 92 #define SPR_ESR_BASE (SPRGROUP_SYS + 64) 93 #define SPR_ESR_LAST (SPRGROUP_SYS + 79) 94 95 /* Data cache group */ 96 #define SPR_DCCR (SPRGROUP_DC + 0) 97 #define SPR_DCBPR (SPRGROUP_DC + 1) 98 #define SPR_DCBFR (SPRGROUP_DC + 2) 99 #define SPR_DCBIR (SPRGROUP_DC + 3) 100 #define SPR_DCBWR (SPRGROUP_DC + 4) 101 #define SPR_DCBLR (SPRGROUP_DC + 5) 102 #define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200) 103 #define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200) 104 105 /* Instruction cache group */ 106 #define SPR_ICCR (SPRGROUP_IC + 0) 107 #define SPR_ICBPR (SPRGROUP_IC + 1) 108 #define SPR_ICBIR (SPRGROUP_IC + 2) 109 #define SPR_ICBLR (SPRGROUP_IC + 3) 110 #define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200) 111 #define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200) 112 113 /* MAC group */ 114 #define SPR_MACLO (SPRGROUP_MAC + 1) 115 #define SPR_MACHI (SPRGROUP_MAC + 2) 116 #define SPR_MACHI2 (SPRGROUP_MAC + 3) 117 118 /* PIC group */ 119 #define SPR_PICMR (SPRGROUP_PIC + 0) 120 #define SPR_PICPR (SPRGROUP_PIC + 1) 121 #define SPR_PICSR (SPRGROUP_PIC + 2) 122 123 /* Tick Timer group */ 124 #define SPR_TTMR (SPRGROUP_TT + 0) 125 #define SPR_TTCR (SPRGROUP_TT + 1) 126 127 /* 128 * Bit definitions for the Supervision Register 129 * 130 */ 131 #define SPR_SR_CID 0xf0000000 /* Context ID */ 132 #define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */ 133 #define SPR_SR_FO 0x00008000 /* Fixed one */ 134 #define SPR_SR_EPH 0x00004000 /* Exception Prefix High */ 135 #define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */ 136 #if 1//M10/M12 R2 137 #define SPR_SR_TDE 0x00001000 /* Trap Disable Exception */ 138 #else 139 #define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */ 140 #endif 141 #define SPR_SR_OV 0x00000800 /* Overflow flag */ 142 #define SPR_SR_CY 0x00000400 /* Carry flag */ 143 #define SPR_SR_F 0x00000200 /* Condition Flag */ 144 #define SPR_SR_CE 0x00000100 /* CID Enable */ 145 #define SPR_SR_LEE 0x00000080 /* Little Endian Enable */ 146 #define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */ 147 #define SPR_SR_DME 0x00000020 /* Data MMU Enable */ 148 #define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */ 149 #define SPR_SR_DCE 0x00000008 /* Data Cache Enable */ 150 #define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */ 151 #define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */ 152 #define SPR_SR_SM 0x00000001 /* Supervisor Mode */ 153 154 /* 155 * Bit definitions for Data Cache Control register 156 * 157 */ 158 #define SPR_DCCR_EW 0x000000ff /* Enable ways */ 159 160 /* 161 * Bit definitions for Insn Cache Control register 162 * 163 */ 164 #define SPR_ICCR_EW 0x000000ff /* Enable ways */ 165 166 /* 167 * Bit definitions for PICMR 168 * 169 */ 170 #define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */ 171 172 /* 173 * Bit definitions for PICPR 174 * 175 */ 176 #define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */ 177 178 /* 179 * Bit definitions for PICSR 180 * 181 */ 182 #define SPR_PICSR_IS 0xffffffff /* Interrupt status */ 183 184 /* 185 * Bit definitions for Tick Timer Control Register 186 * 187 */ 188 #define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */ 189 #define SPR_TTMR_PERIOD SPR_TTCR_PERIOD 190 #define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */ 191 #define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */ 192 #define SPR_TTMR_RT 0x40000000 /* Restart tick */ 193 #define SPR_TTMR_SR 0x80000000 /* Single run */ 194 #define SPR_TTMR_CR 0xc0000000 /* Continuous run */ 195 #define SPR_TTMR_M 0xc0000000 /* Tick mode */ 196 197 #endif /* __RISC32_SPR_H__ */ 198