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93 ///////////////////////////////////////////////////////////////////////////////
94
95 ///////////////////////////////////////////////////////////////////////////////////////////////////
96 ///
97 /// file halMMIO.c
98 /// @brief memory map io (MMIO) HAL
99 /// @author MStar Semiconductor Inc.
100 ///////////////////////////////////////////////////////////////////////////////////////////////////
101
102
103 //-------------------------------------------------------------------------------------------------
104 // Include Files
105 //-------------------------------------------------------------------------------------------------
106
107 #include "MsCommon.h"
108 #include "halMMIO.h"
109 #include "drvMMIO.h"
110
111 // for getting mapped IO base from DRV
112 extern MS_VIRT _virtPM_Bank ;
113 extern MS_U32 _u32PM_Bank_SIZE ;
114 extern MS_VIRT _virtNonPM_Bank ;
115 extern MS_U32 _u32NonPM_Bank_SIZE ;
116 extern MS_VIRT _virtFRC_Bank ; //frcr2_integration###
117 extern MS_U32 _u32FRC_Bank_SIZE ; //frcr2_integration###
118
119 //-------------------------------------------------------------------------------------------------
120 // Driver Compiler Options
121 //-------------------------------------------------------------------------------------------------
122
123
124 //--------------------------------------------------------------------------------------------------
125 // Global Variables
126 //--------------------------------------------------------------------------------------------------
127 MS_VIRT virt_ge0_mmio_base;
128
129
130 //-------------------------------------------------------------------------------------------------
131 // Local Defines
132 //-------------------------------------------------------------------------------------------------
133 #ifdef MSOS_TYPE_LINUX
134 // assume linux always running on mips
135 #define HAL_MMIO_PM_BASE 0x1f000000UL //[MMIO][HAL][001] Base address of PM domain registers
136 #define HAL_MMIO_PM_SIZE 0x00A00000UL //[MMIO][HAL][002] Size of PM domain registers
137 #define HAL_MMIO_NONPM_BASE 0x1f200000UL //[MMIO][HAL][003] Base address of Non-PM domain registers
138 #define HAL_MMIO_NONPM_SIZE 0x01000000UL //[MMIO][HAL][004] Size of Non-PM domain registers
139 #define HAL_MMIO_FLASH_BASE0 0x14000000UL //[MMIO][HAL][005] Base address of SPI flash
140 #define HAL_MMIO_FLASH_SIZE0 0x01000000UL //[MMIO][HAL][006] Size of SPI flash
141 #define HAL_MMIO_FRC_BASE 0x1f800000UL //frcr2_integration### //[MMIO][HAL][026] Base address of FRC R2
142 #define HAL_MMIO_FRC_SIZE 0x00013600UL //frcr2_integration### //[MMIO][HAL][027] Size of FRC R2
143 #elif defined(MSOS_TYPE_LINUX_KERNEL)
144 #ifdef CONFIG_UTOPIA_FRAMEWORK_KERNEL_DRIVER_64BIT
145 extern ptrdiff_t mstar_pm_base;
146 #define RIU_BASE mstar_pm_base
147 #else
148 #define RIU_BASE 0xfd000000UL
149 #endif
150 #define HAL_MMIO_PM_BASE RIU_BASE //[MMIO][HAL][007] Base address of PM domain registers (Kernel Mode)
151 #define HAL_MMIO_PM_SIZE 0x00A00000UL //[MMIO][HAL][008] Size of PM domain registers (Kernel Mode)
152 #define HAL_MMIO_NONPM_BASE RIU_BASE+0x200000UL //[MMIO][HAL][009] Base address of Non-PM domain registers (Kernel Mode)
153 #define HAL_MMIO_NONPM_SIZE 0x01000000UL //[MMIO][HAL][010] Size of Non-PM domain registers (Kernel Mode)
154 #define HAL_MMIO_FLASH_BASE0 0x14000000UL //[MMIO][HAL][011] Base address of SPI flash (Kernel Mode)
155 #define HAL_MMIO_FLASH_SIZE0 0x01000000UL //[MMIO][HAL][012] Size of SPI flash (Kernel Mode)
156 #define HAL_MMIO_FRC_BASE RIU_BASE+0x800000UL //0x1f800000UL //frcr2_integration### //[MMIO][HAL][028] Base address of FRC R2 (Kernel Mode)
157 #define HAL_MMIO_FRC_SIZE 0x00013600UL //frcr2_integration### //[MMIO][HAL][029] Size of FRC R2 (Kernel Mode)
158 #else
159 #if defined (MCU_AEON)
160 #define HAL_MMIO_PM_BASE 0xFA000000UL
161 #define HAL_MMIO_PM_SIZE 0x00007B80UL
162 #define HAL_MMIO_NONPM_BASE 0xFA200000UL
163 #define HAL_MMIO_NONPM_SIZE 0x00025600UL
164 #define HAL_MMIO_FLASH_BASE0 0xA1000000UL // non-cache // 0xA1000000 for cache
165 #define HAL_MMIO_FLASH_SIZE0 0x1000000UL
166 #define HAL_MMIO_FRC_BASE 0xFA800000UL //frcr2_integration###
167 #define HAL_MMIO_FRC_SIZE 0x00013600UL //frcr2_integration###
168 #elif defined (MCU_ARM_CA7)
169 #define HAL_MMIO_PM_BASE 0x1f000000UL
170 #define HAL_MMIO_PM_SIZE 0x00007B80UL
171 #define HAL_MMIO_NONPM_BASE 0x1f200000UL
172 #define HAL_MMIO_NONPM_SIZE 0x00025600UL
173 #define HAL_MMIO_FLASH_BASE0 0x14000000UL
174 #define HAL_MMIO_FLASH_SIZE0 0x1000000UL
175 #define HAL_MMIO_FRC_BASE 0x1f800000UL //frcr2_integration###
176 #define HAL_MMIO_FRC_SIZE 0x00013600UL //frcr2_integration###
177 #elif defined (MCU_ARM_CA53)
178 #define HAL_MMIO_PM_BASE 0x1f000000UL //[MMIO][HAL][013] Base address of PM domain registers (Non-OS)
179 #define HAL_MMIO_PM_SIZE 0x00007B80UL //[MMIO][HAL][014] Size of PM domain registers (Non-OS)
180 #define HAL_MMIO_NONPM_BASE 0x1f200000UL //[MMIO][HAL][015] Base address of Non-PM domain registers (Non-OS)
181 #define HAL_MMIO_NONPM_SIZE 0x00025600UL //[MMIO][HAL][016] Size of Non-PM domain registers (Non-OS)
182 #define HAL_MMIO_FLASH_BASE0 0x14000000UL //[MMIO][HAL][017] Base address of SPI flash (Non-OS)
183 #define HAL_MMIO_FLASH_SIZE0 0x1000000UL //[MMIO][HAL][018] Size of SPI flash (Non-OS)
184 #define HAL_MMIO_FRC_BASE 0x1f800000UL //frcr2_integration### //[MMIO][HAL][030] Base address of FRC R2 (Non-OS)
185 #define HAL_MMIO_FRC_SIZE 0x00013600UL //frcr2_integration### //[MMIO][HAL][031] Size of FRC R2 (Non-OS)
186 #elif defined (CONFIG_FPGA)
187 #define HAL_MMIO_PM_BASE 0xfd000000
188 #define HAL_MMIO_PM_SIZE 0x00007B80
189 #define HAL_MMIO_NONPM_BASE 0xfd200000
190 #define HAL_MMIO_NONPM_SIZE 0x00025600
191 #define HAL_MMIO_FLASH_BASE0 0xfe000000
192 #define HAL_MMIO_FLASH_SIZE0 0x01000000
193 #define HAL_MMIO_FRC_BASE 0xfd800000UL //frcr2_integration###
194 #define HAL_MMIO_FRC_SIZE 0x00013600UL //frcr2_integration###
195 #else
196 #error "Please choose MCU";
197 #endif
198 #endif
199
200
201 //-------------------------------------------------------------------------------------------------
202 // Local Structurs
203 //-------------------------------------------------------------------------------------------------
204
205
206 //-------------------------------------------------------------------------------------------------
207 // Global Variables
208 //-------------------------------------------------------------------------------------------------
209
210
211 //-------------------------------------------------------------------------------------------------
212 // Local Variables
213 //-------------------------------------------------------------------------------------------------
214
215
216 //-------------------------------------------------------------------------------------------------
217 // Debug Functions
218 //-------------------------------------------------------------------------------------------------
219
220
221 //-------------------------------------------------------------------------------------------------
222 // Local Functions
223 //-------------------------------------------------------------------------------------------------
224
225
226 //-------------------------------------------------------------------------------------------------
227 // Global Functions
228 //-------------------------------------------------------------------------------------------------
HAL_MMIO_GetType(MS_U32 u32Module)229 MS_U16 HAL_MMIO_GetType(MS_U32 u32Module)
230 {
231 switch (u32Module)
232 {
233 //HAL_MMIO_PM_BANK
234 case MS_MODULE_PM :
235 case MS_MODULE_IR :
236 case MS_MODULE_ISP :
237 case MS_MODULE_PWS :
238 return DRV_MMIO_PM_BANK;
239
240 //HAL_MMIO_NONPM_BANK
241 case MS_MODULE_HW :
242 case MS_MODULE_CHIPTOP :
243 case MS_MODULE_MIU :
244 case MS_MODULE_ACE :
245 case MS_MODULE_AUDIO :
246 case MS_MODULE_AVD :
247 case MS_MODULE_BDMA :
248 case MS_MODULE_DLC :
249 case MS_MODULE_DMD :
250 case MS_MODULE_GE :
251 case MS_MODULE_GOP :
252 case MS_MODULE_GPIO :
253 case MS_MODULE_HVD :
254 case MS_MODULE_HWI2C :
255 case MS_MODULE_IRQ :
256 case MS_MODULE_JPD :
257 case MS_MODULE_MBX :
258 case MS_MODULE_MFE :
259 case MS_MODULE_MHEG5 :
260 case MS_MODULE_MVD :
261 case MS_MODULE_MVOP :
262 case MS_MODULE_RVD :
263 case MS_MODULE_TSP :
264 case MS_MODULE_UART :
265 case MS_MODULE_VPU :
266 case MS_MODULE_XC :
267 case MS_MODULE_PCMCIA :
268 case MS_MODULE_PFSH :
269 case MS_MODULE_PNL :
270 case MS_MODULE_PWM :
271 case MS_MODULE_SEM :
272 case MS_MODULE_VBI :
273 case MS_MODULE_VIF :
274 case MS_MODULE_DIP :
275 case MS_MODULE_MPIF :
276 case MS_MODULE_MMFILEIN :
277 case MS_MODULE_GPD :
278 case MS_MODULE_TSO :
279 case MS_MODULE_CMDQ :
280 return DRV_MMIO_NONPM_BANK;
281
282 case MS_MODULE_SC :
283 return DRV_MMIO_SC_BANK;
284
285 //HAL_MMIO_FLASH_BANK0
286 case MS_MODULE_FLASH :
287 return DRV_MMIO_FLASH_BANK0;
288 case MS_MODULE_FRC : //frcr2_integration###
289 return DRV_MMIO_FRC_BANK; //frcr2_integration###
290
291 default:
292 return 0xFFFF; //undefine type
293 }
294
295 return 0xFFFF; //undefine type
296 }
297
298
HAL_MMIO_GetBase(MS_PHY * virtBaseAddr,MS_PHY * pu32BaseSize,MS_U32 u32BankType)299 MS_BOOL HAL_MMIO_GetBase(MS_PHY* virtBaseAddr, MS_PHY* pu32BaseSize, MS_U32 u32BankType)
300 {
301 MS_BOOL bRet = TRUE;
302
303 *virtBaseAddr = 0;
304 *pu32BaseSize = 0;
305 switch (u32BankType)
306 {
307 case DRV_MMIO_PM_BANK:
308 *virtBaseAddr = (MS_PHY)HAL_MMIO_PM_BASE;
309 *pu32BaseSize = (MS_PHY)HAL_MMIO_PM_SIZE;
310 break;
311 case DRV_MMIO_NONPM_BANK:
312 *virtBaseAddr = (MS_PHY)HAL_MMIO_NONPM_BASE;
313 *pu32BaseSize = (MS_PHY)HAL_MMIO_NONPM_SIZE;
314 break;
315 case DRV_MMIO_FLASH_BANK0:
316 *virtBaseAddr = (MS_PHY)HAL_MMIO_FLASH_BASE0;
317 *pu32BaseSize = (MS_PHY)HAL_MMIO_FLASH_SIZE0;
318 break;
319 case DRV_MMIO_FRC_BANK:
320 *virtBaseAddr = (MS_PHY)HAL_MMIO_FRC_BASE;
321 *pu32BaseSize = (MS_PHY)HAL_MMIO_FRC_SIZE;
322 break;
323 default:
324 // MS_ASSERT(0);
325 bRet = FALSE;
326 break;
327 }
328
329 return bRet;
330 }
331
332
333 // @NOTE: Only run after MMIO_Init
HAL_MMIO_GetIPBase(MS_VIRT * virtBaseAddr,MS_U16 u16BankType)334 MS_BOOL HAL_MMIO_GetIPBase(MS_VIRT *virtBaseAddr, MS_U16 u16BankType)
335 {
336 *virtBaseAddr = 0;
337
338 // if MMIO_Init is not yet initialized.
339 if ( (_u32PM_Bank_SIZE == 0x0) || (_u32NonPM_Bank_SIZE == 0x0) || (_u32FRC_Bank_SIZE == 0x0) ) //frcr2_integration###
340 {
341 return FALSE;
342 }
343
344 switch (u16BankType)
345 {
346 case DRV_MMIO_SC_BANK:
347 *virtBaseAddr =_virtNonPM_Bank + 0x00005200; // 0xBF220C00, 0xBF220C80
348 break;
349 default:
350 return FALSE;
351 }
352
353 return TRUE;
354 }
355
356 #if defined(__aarch64__) || defined(__arm__)
357 #ifndef MSOS_TYPE_LINUX
_chip_flush_miu_pipe(void)358 static void _chip_flush_miu_pipe(void)
359 {
360 unsigned int dwReadData = 0;
361
362 //[MMIO][HAL][019] Flush MIU pipe [START]
363 //toggle the flush miu pipe fire bit
364 *(volatile unsigned int *)(HAL_MMIO_PM_BASE + (0x10188A << 1)) &= ~(0x0001);
365 *(volatile unsigned int *)(HAL_MMIO_PM_BASE + (0x10188A << 1)) |= 0x0001;
366
367 do
368 {
369 dwReadData = *(volatile unsigned int *)(HAL_MMIO_PM_BASE+ (0x1018A0 << 1));
370 dwReadData &= BIT(11); //Check Status of Flush Pipe Finish
371
372 } while(dwReadData == 0);
373 //[MMIO][HAL][019] Flush MIU pipe [END]
374 }
375 #endif
376 #endif
377
HAL_MMIO_FlushMemory(void)378 void HAL_MMIO_FlushMemory(void)
379 {
380 #if defined(__aarch64__) || defined(__arm__)
381 #ifndef MSOS_TYPE_LINUX
382 _chip_flush_miu_pipe();
383 #endif
384 #endif
385 }
386
HAL_MMIO_ReadMemory(void)387 void HAL_MMIO_ReadMemory(void)
388 {
389 #if defined(__aarch64__) || defined(__arm__)
390 #ifndef MSOS_TYPE_LINUX
391 _chip_flush_miu_pipe();
392 #endif
393 #endif
394 }
395
396
397