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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _MHAL_MFE_H_ 96 #define _MHAL_MFE_H_ 97 98 #if defined(_MFE_UTOPIA_) 99 #include <stdio.h> 100 #endif 101 102 #include "MFE_chip.h" 103 #include "drv_mfe_st.h" 104 #if defined(_MIPS_PLATFORM_) 105 #if defined(_MFE_BIG2_) 106 #include <sys/bsdtypes.h> 107 #include "shellcfg.h" //for diag_printf 108 #elif defined(_KERNEL_MODE_)&&defined(_MFE_T8_) 109 #include "mdrv_types.h" 110 #elif defined(__MOBILE_CASE__) 111 #include "msutil/MsTypes.h" 112 #else 113 #include "MsTypes.h" 114 #endif 115 #endif 116 117 #include "mfe_type.h" 118 #include "mfe_common.h" 119 120 #ifdef _MFE_BIG2_ 121 #define MIU_SHIFT 2//3 122 #define MIU_SIZE 4//8 123 #else 124 #define MIU_SHIFT 3 125 #define MIU_SIZE 8 126 #endif 127 128 #if defined(_AEON_PLATFORM_) && defined(_MFE_T8_) 129 extern U32 RIU_BASE;// = 0xA0000000; 130 #define REG_BANK_MFE 0x111000 131 #define __MFE_REG(reg) (*(volatile U16 *) ( RIU_BASE + (REG_BANK_MFE + reg*2)*2) ) 132 #elif defined(__MFE_G2__) 133 #define T8_RIU_BASE u32MFERegOSBase // = 0x25000000; G2 RIU base. 134 #define REG_BANK_MFE 0x400 135 #define __MFE_REG(reg) (*(volatile MFE_U32 *) (void*)( T8_RIU_BASE + (reg)*4 ) ) 136 #elif defined(_AEON_PLATFORM_) 137 extern U32 RIU_BASE;// = 0xA0000000; 138 #define REG_BANK_MFE 0x1200 139 #define __MFE_REG(reg) (*(volatile U16 *) ( RIU_BASE + (REG_BANK_MFE + reg)*4) ) 140 //extern U8 FSwrite_ready; 141 #elif defined(_MFE_BIG2_) && defined(_MIPS_PLATFORM_) 142 extern U32 RIU_BASE;// = 0xBF834000; 143 #define REG_BANK_MFE 0 144 #define __MFE_REG(reg) (*(volatile U16 *) ( RIU_BASE + REG_BANK_MFE + (reg)*4) ) 145 #elif defined(_MFE_T8_) && defined(_MIPS_PLATFORM_)&&defined(_KERNEL_MODE_) 146 extern MFE_U32 RIU_BASE;// = 0xBF200000; //CH4 147 #define REG_BANK_MFE 0x8800 148 #define __MFE_REG(reg) (*(volatile MFE_U16 *) ( RIU_BASE + (REG_BANK_MFE + reg) * 4 ) ) 149 #elif defined(_MFE_T8_) && defined(_MIPS_PLATFORM_)&& defined(_MFE_UTOPIA_) 150 #define T8_RIU_BASE u32MFERegOSBase // = 0xBF200000; //CH4 151 #ifdef _MFE_KAISER_ 152 #define REG_BANK_MFE 0x11380 153 #else 154 #define REG_BANK_MFE 0x8800 155 #endif 156 #define __MFE_REG(reg) (*(volatile MFE_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE + reg) * 4 ) ) 157 #define REG_BANK_MFE1 0x8880 158 #define __MFE_REG1(reg) (*(volatile MFE_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE1 + reg) * 4 ) ) 159 #else //if defined(_WIN32)//defined(_BCB_PLATFORM_) 160 #define T8_RIU_BASE 0x0a80 // = 0xBF200000; //CH4 161 #define REG_BANK_MFE 0x0a80 //Local FPGA 162 #define REG_BANK_MFE1 0x0b80 //Local FPGA 163 //#define T8_RIU_BASE 0x0b80 // = 0xBF200000; //CH4 164 //#define REG_BANK_MFE 0x0b80 //Local FPGA 165 //#define REG_BANK_MFE1 0x01080 //Local FPGA 166 #endif 167 168 MS_BOOL MHal_MFE_GetHWCap(MS_U16 *width, MS_U16 *height); 169 170 #if (defined(_MFE_T8_)||defined(_MFE_M1_)) && defined(_MIPS_PLATFORM_)&& !defined(_KERNEL_MODE_) 171 void MHAL_MFE_InitRegBase(MFE_U32 u32RegBase); 172 void MHAL_MFE_CreateRegMap(MFE_REG* mfe_reg, MFE_REG1* mfe_reg1); 173 void MHAL_MFE_DelRegMap(MFE_REG* mfe_reg, MFE_REG1* mfe_reg1); 174 #endif 175 void MHal_MFE_PowerOff(MFE_U32 is_off,MFE_CLK_LEVEL clock_level); 176 MFE_U32 MHal_MFE_GetBitstreamEncodedLen(void); 177 void MHal_MFE_set_outbitsbuf(MFE_REG* mfe_reg, OutBitSBUF *bitsbuf,int outbufsize); 178 void MHal_MFE_SetIrqMask(MFE_U16 mask); 179 180 #ifdef MFE_MIU_PROTECT 181 void MHal_MFE_Enable_MIU_Protection(int MIU_TEST_MODE,MFE_CONFIG* pConfig); 182 void MHal_MFE_Enable_MIU_Protection_Check(int MIU_TEST_MODE,int TYPE); 183 #endif 184 MFE_U32 MHal_MFE_CycleReport(void); 185 void MHal_MFE_ClearIRQ(MFE_U16 irq_bits); 186 void MHal_MFE_GetIRQ(MFE_U16 *irq_bits); 187 void MHal_MFE_SWReset(MFE_REG* mfe_reg); 188 void MHal_MFE_start(void); 189 void MHal_MFE_SetCLKCTL(MFE_REG* mfe_reg); 190 void MHal_MFE_ResetReg(MFE_REG* mfe_reg); 191 void MHal_MFE_GetCRC(MFE_U8 checksum_HW[8]); 192 #endif//_MHAL_MFE_H_ 193 194