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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 /// @file drvMFE.h 94 /// @brief MFE driver 95 /// @author MStar Semiconductor Inc. 96 /// 97 /// MFE is the Mpeg4 ASP encoder, used for PVR function. 98 /// 99 /// Features: 100 /// - Mpeg 4 ASP ( part 2 ) encoder. 101 /// 102 //////////////////////////////////////////////////////////////////////////////// 103 104 #ifndef _MHAL_MFE_H_ 105 #define _MHAL_MFE_H_ 106 107 #ifndef _KERNEL_MODE_ 108 #include <stdio.h> 109 #endif 110 111 #include "MFE_chip.h" 112 113 #ifdef _AEON_PLATFORM_ 114 #if defined(_MFE_T8_) 115 #include "DataType.h" 116 #else 117 #include "MsTypes.h" 118 #endif 119 #endif 120 121 #if defined(_MIPS_PLATFORM_) 122 #if defined(_MFE_BIG2_) 123 #include <sys/bsdtypes.h> 124 #include "shellcfg.h" //for diag_printf 125 #elif defined(_KERNEL_MODE_)&&defined(_MFE_T8_) 126 #include "mdrv_types.h" 127 #else 128 //#include "mdrv_types.h" 129 #include "MsTypes.h" 130 #endif 131 #endif 132 133 #include "mfe_type.h" 134 #include "mfe_common.h" 135 136 #ifdef _MFE_BIG2_ 137 #define MIU_SHIFT 2//3 138 #define MIU_SIZE 4//8 139 #else 140 #define MIU_SHIFT 3 141 #define MIU_SIZE 8 142 #endif 143 144 145 typedef struct { 146 unsigned long start_addr; 147 unsigned long end_addr; 148 long used_size; // 0 means not used 149 } OutBitSBUF; 150 151 #if !(defined(_KERNEL_MODE_)&&defined(_MIPS_PLATFORM_)&&defined(_MFE_T8_)) 152 #ifdef _NO_FILESYSTEM_ //defined(_AEON_PLATFORM_) 153 extern int fp_script; 154 #else 155 extern FILE *fp_script; 156 #endif 157 #endif 158 #ifdef _WIN32//_BCB_PLATFORM_ 159 #define MFE_SCRIPT_OUT 1 160 //#define _IPB_FRAMEQP_ 161 #elif defined(_TRACE32_CMM_) 162 #define MFE_SCRIPT_OUT 0 163 #else 164 #define MFE_SCRIPT_OUT 0 165 #endif 166 #if (MFE_SCRIPT_OUT == 1) 167 #define MFE_SCRIPT(x) (x) 168 #else 169 #define MFE_SCRIPT(x) {} 170 #endif 171 172 #if defined(_AEON_PLATFORM_) && defined(_MFE_T8_) 173 extern U32 RIU_BASE;// = 0xA0000000; 174 #define REG_BANK_MFE 0x111000 175 #define __MFE_REG(reg) (*(volatile U16 *) ( RIU_BASE + (REG_BANK_MFE + reg*2)*2) ) 176 #elif defined(_AEON_PLATFORM_) 177 extern U32 RIU_BASE;// = 0xA0000000; 178 #define REG_BANK_MFE 0x1200 179 #define __MFE_REG(reg) (*(volatile U16 *) ( RIU_BASE + (REG_BANK_MFE + reg)*4) ) 180 //extern U8 FSwrite_ready; 181 #elif defined(_MFE_BIG2_) && defined(_MIPS_PLATFORM_) 182 extern U32 RIU_BASE;// = 0xBF834000; 183 #define REG_BANK_MFE 0 184 #define __MFE_REG(reg) (*(volatile U16 *) ( RIU_BASE + REG_BANK_MFE + (reg)*4) ) 185 #elif defined(_MFE_T8_) && defined(_MIPS_PLATFORM_)&&defined(_KERNEL_MODE_) 186 extern MFE_U32 RIU_BASE;// = 0xBF200000; //CH4 187 #define REG_BANK_MFE 0x8800 188 #define __MFE_REG(reg) (*(volatile MFE_U16 *) ( RIU_BASE + (REG_BANK_MFE + reg) * 4 ) ) 189 #elif defined(_MFE_T8_) && defined(_MIPS_PLATFORM_) 190 #define T8_RIU_BASE u32MFERegOSBase // = 0xBF200000; //CH4 191 #define REG_BANK_MFE 0x8800 192 #define __MFE_REG(reg) (*(volatile MFE_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE + reg) * 4 ) ) 193 #elif defined(_HIF_) && defined(_MFE_BIG2_) 194 extern U32 RIU_BASE;// = 0xA0000000; 195 #define REG_BANK_MFE 0xd000 196 #define __MFE_REG(reg) FPGA_RIURead16(REG_BANK_MFE+reg, &val_64) 197 #elif defined(_FPGA_) 198 extern U32 RIU_BASE;// = 0xA0000000; 199 #define REG_BANK_MFE 0xa80 200 #define __MFE_REG(reg) FPGA_RIURead16(REG_BANK_MFE+reg, &val_64) 201 #else //if defined(_WIN32)//defined(_BCB_PLATFORM_) 202 extern unsigned short REG_BANK_MFE[0x100]; 203 #define __MFE_REG(reg) REG_BANK_MFE[reg] 204 #endif 205 206 #if defined(_MFE_T8_) && defined(_MIPS_PLATFORM_)&& !defined(_KERNEL_MODE_) 207 void MHAL_MFE_InitRegBase(MFE_U32 u32RegBase); 208 #endif 209 void MHal_MFE_PowerOff(MFE_U32 is_off,MFE_U32 clock_level); 210 MFE_U32 MHal_MFE_GetBitstreamEncodedLen(void); 211 void MHal_MFE_set_outbitsbuf(OutBitSBUF *bitsbuf); 212 void MHal_MFE_SetIrqMask(MFE_U16 mask); 213 #ifdef _MFE_T8_ 214 void MHal_MFE_Enable_MIU_Protection(int MIU_TEST_MODE,MFE_CONFIG* pConfig); 215 void MHal_MFE_Enable_MIU_Protection_Check(int MIU_TEST_MODE,int TYPE); 216 #endif 217 218 void MHal_MFE_ClearIRQ(MFE_U16 irq_bits); 219 void MHal_MFE_GetIRQ(MFE_U16 *irq_bits); 220 void MHal_MFE_SWReset(void); 221 void MHal_MFE_start(void); 222 void MHal_MFE_SetCLKCTL(void); 223 void MHal_MFE_ResetReg(void); 224 void MHal_MFE_GetCRC(MFE_U8 checksum_HW[8]); 225 #endif//_MHAL_MFE_H_ 226