1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2006-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
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91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #include "MFE_chip.h"
96 #include "mfe_type.h"
97 #include "mfe_common.h"
98 #include "ms_dprintf.h"
99
100 #if defined(__MOBILE_CASE__)
101 #include "drv_clkgen_cmu.h"
102 #endif
103 #if defined(_MIPS_PLATFORM_)&&defined(_MFE_T8_)&&defined(_KERNEL_MODE_)
104 #elif defined(__UBOOT__)
105 #include <linux/string.h>
106 #else
107 #include <string.h>
108 #endif
109
110 #include "mhal_mfe.h"
111 #include "mfe_reg.h"
112
113 #ifdef CONFIG_MSTAR_CLKM
114 #include "drvCLKM.h"
115 #endif
116
MHal_MFE_GetHWCap(MS_U16 * width,MS_U16 * height)117 MS_BOOL MHal_MFE_GetHWCap(MS_U16 *width, MS_U16 *height)
118 {
119 #ifdef MFE_SUPPORT_1080P
120 *width = 1920;
121 *height = 1088;
122 #else
123 *width = 1280;
124 *height = 720;
125 #endif
126 return TRUE;
127 }
128
129 #if (defined(_MFE_T8_)||defined(_MFE_M1_))&& !defined(_KERNEL_MODE_)
130 MS_U32 u32MFERegOSBase;
131
MHAL_MFE_InitRegBase(MS_U32 U32RegBase)132 void MHAL_MFE_InitRegBase(MS_U32 U32RegBase)
133 {
134 ms_dprintk(HAL_L1,"HAL_MFE_InitRegBase 0x%x\n", (unsigned int)U32RegBase);
135 u32MFERegOSBase = U32RegBase;
136 }
137
MHAL_MFE_CreateRegMap(MFE_REG * mfe_reg,MFE_REG1 * mfe_reg1)138 void MHAL_MFE_CreateRegMap(MFE_REG* mfe_reg, MFE_REG1* mfe_reg1)
139 {
140 //mfe_reg = malloc(sizeof(MFE_REG));
141 memset(mfe_reg, 0, sizeof(MFE_REG));
142 //mfe_reg1 = malloc(sizeof(MFE_REG1));
143 memset(mfe_reg1, 0, sizeof(MFE_REG1));
144
145 }
146
MHAL_MFE_DelRegMap(MFE_REG * mfe_reg,MFE_REG1 * mfe_reg1)147 void MHAL_MFE_DelRegMap(MFE_REG* mfe_reg, MFE_REG1* mfe_reg1)
148 {
149 //free(mfe_reg);
150 //free(mfe_reg1);
151 }
152
153 #endif
154
155
MHal_MFE_PowerOff(MS_U32 is_off,MFE_CLK_LEVEL clock_level)156 void MHal_MFE_PowerOff(MS_U32 is_off,MFE_CLK_LEVEL clock_level)
157 {
158 #ifndef WIN32
159
160 #if defined(__MOBILE_CASE__)
161 //#define CMU_MMP_ASIC_CLK_MFE 170UL //clk_occmux_sel CMU_CLK_OFF, CMU_CLK_32K, CMU_CLK_12M, CMU_CLK_24M, CMU_CLK_64M, CMU_CLK_85P3M, CMU_CLK_109P6M, CMU_CLK_128M, CMU_CLK_153P6M, CMU_CLK_170P6M
162 #ifndef CMU_CLK_24M
163 #define CMU_CLK_24M CMU_MMP_ASIC_CLK_24M
164 #define CMU_CLK_64M CMU_MMP_ASIC_CLK_64M
165 #define CMU_CLK_128M CMU_MMP_ASIC_CLK_128M
166 #define CMU_CLK_170P6M CMU_MMP_ASIC_CLK_170P6M
167 #define CMU_CLK_170P6M CMU_MMP_ASIC_CLK_170P6M
168 #endif
169
170 MS_S32 ret;
171 if (is_off) {
172 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MFE, CMU_CLK_OFF);
173 if(ret < 0)
174 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_OFF fail\n");
175 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MIU_MFE, CMU_CLK_OFF);
176 if(ret < 0)
177 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_OFF fail\n");
178 } else {
179 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MIU_MFE, CMU_CLK_ON);
180 if(ret < 0)
181 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_ON fail\n");
182 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MFE, CMU_CLK_ON);
183 if(ret < 0)
184 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_ON fail\n");
185
186 ms_dprintk(HAL_L1,"clk level = %d\n",clock_level);
187 switch (clock_level)
188 {
189 case MFE_CLK_VERY_SLOW:
190 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MFE, CMU_CLK_24M); break;
191 case MFE_CLK_SLOW:
192 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MFE, CMU_CLK_64M); break;
193 case MFE_CLK_MEDIUM:
194 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MFE, CMU_CLK_128M); break;
195 case MFE_CLK_FAST:
196 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MFE, CMU_CLK_170P6M); break;
197 default:
198 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MFE, CMU_CLK_170P6M); break;
199 }
200 if(ret < 0)
201 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE Switch fail\n");
202 }
203
204 #elif defined(_MFE_T8_) &&defined(_MIPS_PLATFORM_)&&defined(_KERNEL_MODE_)
205 if (is_off) {
206 *(MS_U16*)(0xbf206600+(0x18)*4) = 1;//disable MFE clock
207 } else {
208 //*(MS_U16*)(0xbf206600+(0x18)*4) = 0; // 4'b0000 123
209 //*(MS_U16*)(0xbf206600+(0x18)*4) = 4; // 4'b0100 144
210 //*(MS_U16*)(0xbf206600+(0x18)*4) = 8; // 4'b1000 172
211 //*(MS_U16*)(0xbf206600+(0x18)*4) = 12; // 4'b1100 192
212
213 if((clock_level >>2) == 0 )
214 *(MS_U16*)(0xbf206600+(0x18)*4) = clock_level*4;
215 else
216 *(MS_U16*)(0xbf206600+(0x18)*4) = 8;
217 }
218 //MFE clock;
219 //*(MS_U16*)(0xbf200000+(0x1980+0x18)*4) = 2<<2; //2<<2
220 #elif defined(_MFE_T8_) &&defined(_MIPS_PLATFORM_)&&defined(_MFE_UTOPIA_)
221
222 #ifdef CONFIG_MSTAR_CLKM
223 MS_S32 handle = Drv_Clkm_Get_Handle("g_clk_mfe");
224 if (is_off) {
225 Drv_Clkm_Clk_Gate_Disable(handle);
226 ms_dprintk(HAL_L1, "CLKM disable clock.\n");
227 } else {
228 switch (clock_level)
229 {
230 case MFE_CLK_VERY_SLOW:
231 Drv_Clkm_Set_Clk_Source(handle, "Debug_mode"); break; // 4'b0000
232 case MFE_CLK_SLOW:
233 Drv_Clkm_Set_Clk_Source(handle, "SDp30_mode"); break; // 4'b0100
234 case MFE_CLK_MEDIUM:
235 Drv_Clkm_Set_Clk_Source(handle, "720p30_mode"); break; // 4'b1000
236 case MFE_CLK_FAST:
237 Drv_Clkm_Set_Clk_Source(handle, "720p60_1080p30_mode"); break; // 4'b1100
238 default:
239 Drv_Clkm_Set_Clk_Source(handle, "720p60_1080p30_mode"); break; // 4'b1100
240 }
241 ms_dprintk(HAL_L1, "CLKM enable clock level %d.\n", clock_level);
242 }
243 #else
244 if (is_off) {
245 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0x1; // 4'b0001, disable MFE clock
246 ms_dprintk(HAL_L1, "Disable clock.\n");
247 } else {
248 switch (clock_level)
249 {
250 case MFE_CLK_VERY_SLOW:
251 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0x0; break; // 4'b0000
252 case MFE_CLK_SLOW:
253 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0x4; break; // 4'b0100
254 case MFE_CLK_MEDIUM:
255 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0x8; break; // 4'b1000
256 case MFE_CLK_FAST:
257 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0xC; break; // 4'b1100
258 default:
259 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0xC; break; // 4'b1100
260 }
261 ms_dprintk(HAL_L1, "Enable clock level %d.\n", clock_level);
262 }
263 #endif // #ifdef CONFIG_MSTAR_CLKM
264
265 #ifdef CONFIG_MSTAR_SRAMPD
266 // SRAM power: reg_codec_sram_sd_en[20] (32-bit register)
267 // Base 0x1712, offset 0x10, bit 20
268 // 1: power down
269 // 0: power on
270 if (is_off) {
271 *((volatile MS_U32 *)(MS_VIRT)(T8_RIU_BASE + 0x71200*2 + 0x10*2*2)) |= (1UL << 20);
272 ms_dprintk(HAL_L1, "[MFE] SRAM power down.\n");
273 } else {
274 *((volatile MS_U32 *)(MS_VIRT)(T8_RIU_BASE + 0x71200*2 + 0x10*2*2)) &= ~(1UL << 20);
275 ms_dprintk(HAL_L1, "[MFE] SRAM power on.\n");
276 }
277 MsOS_DelayTaskUs(1);
278 #endif
279
280 #endif
281
282 #endif // _FPGA_
283 }
284
MHal_MFE_SWReset(MFE_REG * mfe_reg)285 void MHal_MFE_SWReset(MFE_REG* mfe_reg)
286 {
287 MS_U16 temp;
288 mfe_reg->reg_mfe_g_soft_rstz = 1;
289 WriteRegMFE(0x0, mfe_reg->reg00, (MS_S8*)(""), 0, (MS_S8*)(""));
290 ReadRegMFE(0x0, &temp);
291 ms_dprintk(HAL_L1, "[HAL] SWReset reg00: 0x%04x\n", (unsigned int)temp);
292 }
293
MHal_MFE_GetBitstreamEncodedLen(void)294 MS_U32 MHal_MFE_GetBitstreamEncodedLen(void)
295 {
296 MS_U16 reg_mfe_s_bsp_bit_cnt_high=0;
297 MS_U16 reg_mfe_s_bsp_bit_cnt_low=0;
298 MS_U32 nHwBytes;
299
300 // Read bit count
301 ReadRegMFE(0x42, ®_mfe_s_bsp_bit_cnt_low);
302 ReadRegMFE(0x43, ®_mfe_s_bsp_bit_cnt_high);
303 // Convert into byte count
304 nHwBytes = (((MS_U32)reg_mfe_s_bsp_bit_cnt_high<<16) + reg_mfe_s_bsp_bit_cnt_low ) >> 3;
305 return nHwBytes;
306 }
307
308
MHal_MFE_ClearIRQ(MS_U16 irq_bits)309 void MHal_MFE_ClearIRQ(MS_U16 irq_bits)
310 {
311 irq_bits = irq_bits&0x7f;
312 WriteRegMFE(0x1d, irq_bits, (MS_S8*)(""), 0, (MS_S8*)(""));
313 ms_dprintk(HAL_L2, "[HAL] ClearIRQ: %u\n", irq_bits);
314 }
315
MHal_MFE_GetIRQ(MS_U16 * irq_bits)316 void MHal_MFE_GetIRQ(MS_U16 *irq_bits)
317 {
318 ReadRegMFE(0x1e, irq_bits);
319 ms_dprintk(HAL_L2, "[HAL] GetIRQ reg1e: 0x%x\n", (unsigned int)(*irq_bits));
320 }
321
MHal_MFE_CycleReport(void)322 MS_U32 MHal_MFE_CycleReport(void)
323 {
324 MS_U16 tmp_reg,tmp_reg1;
325 MS_U32 tCycles = 0;
326 ReadRegMFE(0x73, &tmp_reg);
327 tmp_reg = tmp_reg | 0x200; //enable total time;
328 WriteRegMFE(0x73, tmp_reg, (MS_S8*)(""), 0, (MS_S8*)(""));
329
330 ReadRegMFE(0x76, &tmp_reg);
331 ReadRegMFE(0x77, &tmp_reg1);
332
333 tCycles = ((tmp_reg1 & 0xff)<<16) | tmp_reg;
334 return tCycles;
335 }
336
MHal_MFE_set_outbitsbuf(MFE_REG * mfe_reg,OutBitSBUF * bitsbuf,MS_S32 outbufsize)337 void MHal_MFE_set_outbitsbuf(MFE_REG* mfe_reg, OutBitSBUF *bitsbuf, MS_S32 outbufsize)
338 {
339 #if defined(_MFE_M1_)||defined(_MFE_AGATE_)
340 SetObufAddr(mfe_reg, bitsbuf->start_addr, outbufsize, 0, 1);
341 #else
342 MS_U16 sadr_low, sadr_high, eadr_low, eadr_high;
343
344 sadr_low = LOWORD(bitsbuf->start_addr>>MIU_SHIFT);
345 sadr_high = HIWORD(bitsbuf->start_addr>>MIU_SHIFT);
346 eadr_low = LOWORD(((bitsbuf->end_addr)>>MIU_SHIFT)-1);
347 eadr_high = HIWORD(((bitsbuf->end_addr)>>MIU_SHIFT)-1);
348 SetObufAddr(mfe_reg, sadr_low, sadr_high, eadr_low, eadr_high);
349 #endif
350 }
351
MHal_MFE_SetCLKCTL(MFE_REG * mfe_reg)352 void MHal_MFE_SetCLKCTL(MFE_REG* mfe_reg)
353 {
354 WriteRegMFE(0x0a, (MS_U16)mfe_reg->reg0a, (MS_S8*)(""), 0, (MS_S8*)(""));
355 }
356
MHal_MFE_ResetReg(MFE_REG * mfe_reg)357 void MHal_MFE_ResetReg(MFE_REG* mfe_reg)
358 {
359 memset(mfe_reg, 0, sizeof(MFE_REG));
360 }
361
MHal_MFE_GetCRC(MS_U8 checksum_HW[8])362 void MHal_MFE_GetCRC(MS_U8 checksum_HW[8])
363 {
364 MS_S32 i;
365 MS_U16 u16Reg1;
366
367 ReadRegMFE(0x73, &u16Reg1);
368 u16Reg1 = u16Reg1 & 0xFDFF;
369 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)(""));
370
371 //call HW CRC64
372 for(i=0;i<4;i++){
373 ReadRegMFE(0x76+i, &u16Reg1);
374 checksum_HW[2*i] = (MS_U8)(u16Reg1&0xFF);
375 checksum_HW[2*i+1] = u16Reg1>>8;
376 }
377
378 ReadRegMFE(0x73, &u16Reg1);
379 u16Reg1 = u16Reg1 | 0x0100;
380 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)(""));
381 }
382