1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2006-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // (�uMStar Confidential Information�v) by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #include "MFE_chip.h"
96 #include "mfe_type.h"
97 #include "mfe_common.h"
98 #include "ms_dprintf.h"
99
100 #if defined(__MOBILE_CASE__)
101 #include "drv_clkgen_cmu.h"
102 #endif
103 #if defined(_MIPS_PLATFORM_)&&defined(_MFE_T8_)&&defined(_KERNEL_MODE_)
104 #elif defined(__UBOOT__)
105 #include <linux/string.h>
106 #else
107 #include <string.h>
108 #endif
109
110 #include "mhal_mfe.h"
111 #include "mfe_reg.h"
112
113 #ifdef CONFIG_MSTAR_CLKM
114 #include "drvCLKM.h"
115 #endif
116
MHal_MFE_GetHWCap(MS_U16 * width,MS_U16 * height)117 MS_BOOL MHal_MFE_GetHWCap(MS_U16 *width, MS_U16 *height)
118 {
119 #ifdef MFE_SUPPORT_1080P
120 *width = 1920;
121 *height = 1088;
122 #else
123 *width = 1280;
124 *height = 720;
125 #endif
126 return TRUE;
127 }
128
129 #if (defined(_MFE_T8_)||defined(_MFE_M1_))&& !defined(_KERNEL_MODE_)
130 MS_U32 u32MFERegOSBase;
131
MHAL_MFE_InitRegBase(MS_U32 U32RegBase)132 void MHAL_MFE_InitRegBase(MS_U32 U32RegBase)
133 {
134 ms_dprintk(HAL_L1, "HAL_MFE_InitRegBase 0x%x\n", (unsigned int)U32RegBase);
135 u32MFERegOSBase = U32RegBase;
136 }
137
MHAL_MFE_CreateRegMap(MFE_REG * mfe_reg,MFE_REG1 * mfe_reg1)138 void MHAL_MFE_CreateRegMap(MFE_REG* mfe_reg, MFE_REG1* mfe_reg1)
139 {
140 //mfe_reg = malloc(sizeof(MFE_REG));
141 memset(mfe_reg, 0, sizeof(MFE_REG));
142 //mfe_reg1 = malloc(sizeof(MFE_REG1));
143 memset(mfe_reg1, 0, sizeof(MFE_REG1));
144
145 }
146
MHAL_MFE_DelRegMap(MFE_REG * mfe_reg,MFE_REG1 * mfe_reg1)147 void MHAL_MFE_DelRegMap(MFE_REG* mfe_reg, MFE_REG1* mfe_reg1)
148 {
149 //free(mfe_reg);
150 //free(mfe_reg1);
151 }
152
153 #endif
154
155
MHal_MFE_PowerOff(MS_U32 is_off,MFE_CLK_LEVEL clock_level)156 void MHal_MFE_PowerOff(MS_U32 is_off,MFE_CLK_LEVEL clock_level)
157 {
158 #ifndef WIN32
159
160 #if defined(__MOBILE_CASE__)
161 //#define CMU_MMP_ASIC_CLK_MFE 170UL //clk_occmux_sel CMU_CLK_OFF, CMU_CLK_32K, CMU_CLK_12M, CMU_CLK_24M, CMU_CLK_64M, CMU_CLK_85P3M, CMU_CLK_109P6M, CMU_CLK_128M, CMU_CLK_153P6M, CMU_CLK_170P6M
162 #ifndef CMU_CLK_24M
163 #define CMU_CLK_24M CMU_MMP_ASIC_CLK_24M
164 #define CMU_CLK_64M CMU_MMP_ASIC_CLK_64M
165 #define CMU_CLK_128M CMU_MMP_ASIC_CLK_128M
166 #define CMU_CLK_170P6M CMU_MMP_ASIC_CLK_170P6M
167 #define CMU_CLK_170P6M CMU_MMP_ASIC_CLK_170P6M
168 #endif
169
170 MS_S32 ret;
171 if (is_off) {
172 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MFE, CMU_CLK_OFF);
173 if(ret < 0)
174 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_OFF fail\n");
175 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MIU_MFE, CMU_CLK_OFF);
176 if(ret < 0)
177 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_OFF fail\n");
178 } else {
179 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MIU_MFE, CMU_CLK_ON);
180 if(ret < 0)
181 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_ON fail\n");
182 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MFE, CMU_CLK_ON);
183 if(ret < 0)
184 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_ON fail\n");
185
186 ms_dprintk(HAL_L1,"clk level = %d\n",clock_level);
187 switch (clock_level)
188 {
189 case MFE_CLK_VERY_SLOW:
190 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MFE, CMU_CLK_24M); break;
191 case MFE_CLK_SLOW:
192 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MFE, CMU_CLK_64M); break;
193 case MFE_CLK_MEDIUM:
194 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MFE, CMU_CLK_128M); break;
195 case MFE_CLK_FAST:
196 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MFE, CMU_CLK_170P6M); break;
197 default:
198 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MFE, CMU_CLK_170P6M); break;
199 }
200 if(ret < 0)
201 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE Switch fail\n");
202 }
203
204 #elif defined(_MFE_T8_) &&defined(_MIPS_PLATFORM_)&&defined(_KERNEL_MODE_)
205 if (is_off) {
206 *(MS_U16*)(0xbf206600+(0x18)*4) = 1;//disable MFE clock
207 } else {
208 //*(MS_U16*)(0xbf206600+(0x18)*4) = 0; // 4'b0000 123
209 //*(MS_U16*)(0xbf206600+(0x18)*4) = 4; // 4'b0100 144
210 //*(MS_U16*)(0xbf206600+(0x18)*4) = 8; // 4'b1000 172
211 //*(MS_U16*)(0xbf206600+(0x18)*4) = 12; // 4'b1100 192
212
213 if((clock_level >>2) == 0 )
214 *(MS_U16*)(0xbf206600+(0x18)*4) = clock_level*4;
215 else
216 *(MS_U16*)(0xbf206600+(0x18)*4) = 8;
217 }
218 //MFE clock;
219 //*(MS_U16*)(0xbf200000+(0x1980+0x18)*4) = 2<<2; //2<<2
220 #elif defined(_MFE_T8_) &&defined(_MIPS_PLATFORM_)&&defined(_MFE_UTOPIA_)
221
222 #ifdef CONFIG_MSTAR_CLKM
223 MS_S32 handle = Drv_Clkm_Get_Handle("g_clk_mfe");
224 if (is_off) {
225 Drv_Clkm_Clk_Gate_Disable(handle);
226 ms_dprintk(HAL_L1, "CLKM disable clock.\n");
227 } else {
228 switch (clock_level)
229 {
230 case MFE_CLK_VERY_SLOW:
231 Drv_Clkm_Set_Clk_Source(handle, "Debug_mode"); break; // 4'b0000
232 case MFE_CLK_SLOW:
233 Drv_Clkm_Set_Clk_Source(handle, "SDp30_mode"); break; // 4'b0100
234 case MFE_CLK_MEDIUM:
235 Drv_Clkm_Set_Clk_Source(handle, "720p30_mode"); break; // 4'b1000
236 case MFE_CLK_FAST:
237 Drv_Clkm_Set_Clk_Source(handle, "720p60_1080p30_mode"); break; // 4'b1100
238 default:
239 Drv_Clkm_Set_Clk_Source(handle, "720p60_1080p30_mode"); break; // 4'b1100
240 }
241 ms_dprintk(HAL_L1, "CLKM enable clock level %d.\n", clock_level);
242 }
243 #else
244 if (is_off) {
245 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 1;//disable MFE clock
246 ms_dprintk(HAL_L1, "Disable clock.\n");
247 } else {
248 //*(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 0; // 4'b0000 123
249 //*(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 4; // 4'b0100 144
250 //*(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 8; // 4'b1000 172
251 //*(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; // 4'b1100 192
252 switch (clock_level)
253 {
254 case MFE_CLK_VERY_SLOW:
255 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 0; break;
256 case MFE_CLK_SLOW:
257 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 4; break;
258 case MFE_CLK_MEDIUM:
259 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 8; break;
260 case MFE_CLK_FAST:
261 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; break;
262 default:
263 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; break;
264 }
265 ms_dprintk(HAL_L1, "Enable clock level %d.\n", clock_level);
266 }
267 #endif // #ifdef CONFIG_MSTAR_CLKM
268
269 #ifdef CONFIG_MSTAR_SRAMPD
270 // ip10_PWR_CTRL:mfe
271 // Base 0x1111, offset 0x50, bit 0
272 // 1: power down
273 // 0: power on
274 if (is_off) {
275 *((volatile MS_U16 *)(MS_VIRT)(T8_RIU_BASE + 0x11100*2 + 0x50*2*2)) |= ((MS_U16)1);
276 ms_dprintk(HAL_L1, "[MFE] SRAM power down.\n");
277 } else {
278 *((volatile MS_U16 *)(MS_VIRT)(T8_RIU_BASE + 0x11100*2 + 0x50*2*2)) &= ~((MS_U16)1);
279 ms_dprintk(HAL_L1, "[MFE] SRAM power on.\n");
280 }
281 MsOS_DelayTaskUs(1);
282 #endif
283
284 #endif
285
286 #endif // _FPGA_
287 }
288
MHal_MFE_SWReset(MFE_REG * mfe_reg)289 void MHal_MFE_SWReset(MFE_REG* mfe_reg)
290 {
291 MS_U16 temp;
292 mfe_reg->reg_mfe_g_soft_rstz = 1;
293 WriteRegMFE(0x0, mfe_reg->reg00, (MS_S8*)(""), 0, (MS_S8*)(""));
294 ReadRegMFE(0x0, &temp);
295 ms_dprintk(HAL_L1, "[HAL] SWReset reg00: 0x%04x\n", (unsigned int)temp);
296 }
297
MHal_MFE_GetBitstreamEncodedLen(void)298 MS_U32 MHal_MFE_GetBitstreamEncodedLen(void)
299 {
300 MS_U16 reg_mfe_s_bsp_bit_cnt_high=0;
301 MS_U16 reg_mfe_s_bsp_bit_cnt_low=0;
302 MS_U32 nHwBytes;
303
304 // Read bit count
305 ReadRegMFE(0x42, ®_mfe_s_bsp_bit_cnt_low);
306 ReadRegMFE(0x43, ®_mfe_s_bsp_bit_cnt_high);
307 // Convert into byte count
308 nHwBytes = (((MS_U32)reg_mfe_s_bsp_bit_cnt_high<<16) + reg_mfe_s_bsp_bit_cnt_low ) >> 3;
309 return nHwBytes;
310 }
311
312
MHal_MFE_ClearIRQ(MS_U16 irq_bits)313 void MHal_MFE_ClearIRQ(MS_U16 irq_bits)
314 {
315 irq_bits = irq_bits&0x7f;
316 WriteRegMFE(0x1d, irq_bits, (MS_S8*)(""), 0, (MS_S8*)(""));
317 ms_dprintk(HAL_L2, "[HAL] ClearIRQ: %u\n", irq_bits);
318 }
319
MHal_MFE_GetIRQ(MS_U16 * irq_bits)320 void MHal_MFE_GetIRQ(MS_U16 *irq_bits)
321 {
322 ReadRegMFE(0x1e, irq_bits);
323 ms_dprintk(HAL_L2, "[HAL] GetIRQ reg1e: 0x%x\n", (unsigned int)(*irq_bits));
324 }
325
MHal_MFE_CycleReport(void)326 MS_U32 MHal_MFE_CycleReport(void)
327 {
328 MS_U16 tmp_reg,tmp_reg1;
329 MS_U32 tCycles = 0;
330 ReadRegMFE(0x73, &tmp_reg);
331 tmp_reg = tmp_reg | 0x200; //enable total time;
332 WriteRegMFE(0x73, tmp_reg, (MS_S8*)(""), 0, (MS_S8*)(""));
333
334 ReadRegMFE(0x76, &tmp_reg);
335 ReadRegMFE(0x77, &tmp_reg1);
336
337 tCycles = ((tmp_reg1 & 0xff)<<16) | tmp_reg;
338 return tCycles;
339 }
340
MHal_MFE_set_outbitsbuf(MFE_REG * mfe_reg,OutBitSBUF * bitsbuf,MS_S32 outbufsize)341 void MHal_MFE_set_outbitsbuf(MFE_REG* mfe_reg, OutBitSBUF *bitsbuf, MS_S32 outbufsize)
342 {
343 #if defined(_MFE_M1_)||defined(_MFE_AGATE_)
344 SetObufAddr(mfe_reg, bitsbuf->start_addr, outbufsize, 0, 1);
345 #else
346 MS_U16 sadr_low, sadr_high, eadr_low, eadr_high;
347
348 sadr_low = LOWORD(bitsbuf->start_addr>>MIU_SHIFT);
349 sadr_high = HIWORD(bitsbuf->start_addr>>MIU_SHIFT);
350 eadr_low = LOWORD(((bitsbuf->end_addr)>>MIU_SHIFT)-1);
351 eadr_high = HIWORD(((bitsbuf->end_addr)>>MIU_SHIFT)-1);
352 SetObufAddr(mfe_reg, sadr_low, sadr_high, eadr_low, eadr_high);
353 #endif
354 }
355
MHal_MFE_SetCLKCTL(MFE_REG * mfe_reg)356 void MHal_MFE_SetCLKCTL(MFE_REG* mfe_reg)
357 {
358 WriteRegMFE(0x0a, (MS_U16)mfe_reg->reg0a, (MS_S8*)(""), 0, (MS_S8*)(""));
359 }
360
MHal_MFE_ResetReg(MFE_REG * mfe_reg)361 void MHal_MFE_ResetReg(MFE_REG* mfe_reg)
362 {
363 memset(mfe_reg, 0, sizeof(MFE_REG));
364 }
365
MHal_MFE_GetCRC(MS_U8 checksum_HW[8])366 void MHal_MFE_GetCRC(MS_U8 checksum_HW[8])
367 {
368 MS_S32 i;
369 MS_U16 u16Reg1;
370
371 ReadRegMFE(0x73, &u16Reg1);
372 u16Reg1 = u16Reg1 & 0xFDFF;
373 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)(""));
374
375 //call HW CRC64
376 for(i=0;i<4;i++){
377 ReadRegMFE(0x76+i, &u16Reg1);
378 checksum_HW[2*i] = (MS_U8)(u16Reg1&0xFF);
379 checksum_HW[2*i+1] = u16Reg1>>8;
380 }
381
382 ReadRegMFE(0x73, &u16Reg1);
383 u16Reg1 = u16Reg1 | 0x0100;
384 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)(""));
385 }
386
387
388