xref: /utopia/UTPA2-700.0.x/modules/mfe/drv/mfe_ex/mdrv_mfe.c (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
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94 
95 #include "MFE_chip.h"
96 #include "mfe_type.h"
97 #include "mfe_common.h"
98 #include "ms_dprintf.h"
99 
100 #include "mdrv_mfe_io.h"
101 #include "drv_mfe_st.h"
102 #include "parset.h"
103 
104 #if (defined(_MFE_T8_)||defined(_MFE_M1_)) \
105    &&defined(_MIPS_PLATFORM_)&&(!defined(_KERNEL_MODE_))&&(!defined(WIN32))
106     #include "MsCommon.h"
107     #include "MsOS.h"
108     #include "drvMMIO.h"
109 #endif
110 
111 #if defined(__UBOOT__)
112     #include <linux/string.h>
113 #else
114     //#include "drvMFE.h"
115     #include <string.h>
116 #endif
117 
118 #include "mhal_mfe.h"
119 #include "mdrv_mfe.h"
120 #include "stdarg.h"
121 #include "BufMng.h"
122 #ifdef __MFE_G2__
123 #include "Exif.h"
124 #include "jcmarker.h"
125 #endif
126 
127 //MFE_CONFIG *gpMfeConfig;
128 //GOPINFO *gpGopInfo;
129 
130 //out buffer
131 //OutBitSBUF outbitsbuf[MAX_OUTBUFFER];
132 //MS_S32 rbits_index=0;
133 
134 //static MS_U32 _MFE_U32MFEEvent = 0;
135 //BITSFRAME_INFO bitsframe[MAX_OUTBUFFER];
136 //volatile MFE_STAT encode_state;
137 //MS_BOOL g_bForceIframe = FALSE;
138 //MS_U32 MFE_U32MFEMIUOffset=0;
139 
140 #if (DEBUG_LEVEL & DRV_L6)
141 #include "api_mfe_performance.h"
142 mfe_performance_t mfe_enc;
143 mfe_performance_t mfe_hw_enc;
144 mfe_performance_t mfe_duration_enc;
145 MS_S32 mfecount = 0;
146 #endif
147 
148 #define DROP_TEST 0UL
149 
150 #if defined(MFE_SUPPORT_TLB)
151 #define MFE_ENABLE_TLB_FLAG 0x1UL
152 #endif
153 
154 #if DROP_TEST
155 MS_S32 mfe_count;
156 #endif
157 
158 static MS_BOOL MDrv_MFE_CheckEncodeDone(MFE_CONFIG *pConfig);
159 
160 // user mode function
161 #if (defined(_MFE_T8_)||defined(_MFE_M1_)) && defined(_MIPS_PLATFORM_)&& !defined(_KERNEL_MODE_)
MDrv_MFE_SetOSRegBase(MFE_CONFIG * pConfig,MS_U32 MFE_U32RegBaseAddr)162 void MDrv_MFE_SetOSRegBase(MFE_CONFIG *pConfig, MS_U32 MFE_U32RegBaseAddr )
163 {
164     MHAL_MFE_InitRegBase((MS_U32)MFE_U32RegBaseAddr );
165 }
166 #endif
167 
168 
169 //////////////////////////////////////////////////////////////////////////
170 // ioctl API's
171 //////////////////////////////////////////////////////////////////////////
172 
MDrv_MFE_ENC_Continue(MFE_CONFIG * pConfig)173 static void MDrv_MFE_ENC_Continue(MFE_CONFIG *pConfig)
174 {
175     MS_ASSERT(pConfig->outbitsbuf[pConfig->nOBufIndex].used_size==0);
176     ms_dprintk(DRV_L3, "Continue with buf[%u]\n", (unsigned int)pConfig->nOBufIndex);
177        MHal_MFE_set_outbitsbuf(&pConfig->mfe_reg, &pConfig->outbitsbuf[pConfig->nOBufIndex],pConfig->ctxBufInfo.m_OutBufferSize);
178     pConfig->encode_state = WAIT_FRAME_DONE;
179 }
180 
181 
MDrv_MFE_clear_bitsbuf(MFE_CONFIG * pConfig,MS_U32 clear_num)182 static void MDrv_MFE_clear_bitsbuf(MFE_CONFIG *pConfig, MS_U32 clear_num)
183 {
184 
185     ms_dprintk(DRV_L3, "clear rbits_index = %d, state = %d, clear_num = %u\n", (int)pConfig->rbits_index, pConfig->encode_state, (unsigned int)clear_num);
186 #ifndef _NON_THREAD_
187     spin_lock(&_spinlock);
188 #endif
189     MS_ASSERT(clear_num==1);
190 
191     pConfig->outbitsbuf[pConfig->rbits_index].used_size = 0;
192     pConfig->rbits_index = MFE_MUX((pConfig->rbits_index+1)==pConfig->ctxBufInfo.m_nOutBuffer, 0, pConfig->rbits_index+1);
193 #ifndef _NON_THREAD_
194     spin_unlock(&_spinlock);
195 #endif
196     if (pConfig->encode_state==WAIT_AVAIL_BITSBUF)
197         MDrv_MFE_ENC_Continue(pConfig);
198 
199 }
200 
MDrv_MFE_GetDispOrder(MFE_CONFIG * pConfig,GOPINFO * pGopInfo,MS_U32 * pDispOrder)201 static MS_S32 MDrv_MFE_GetDispOrder(MFE_CONFIG *pConfig, GOPINFO *pGopInfo, MS_U32 *pDispOrder)
202 {
203 
204 
205     if (!pDispOrder) {
206         ms_dprintk(DRV_L4, "MDrv_MFE_GetDispOrder: pDispOrder is NULL pointer.\n");
207         return 0;
208     }
209 
210     // If H264 PAFF, always assume Top-field first, assume top -> bottom -> top -> bottom input fields.
211     if (pConfig->nCodecType==REG_ENC_MODE_H264 && (pConfig->bInterlace!=PROGRESSIVE)) {
212         if (pConfig->ctxH264Info.structure==FRAME) // Initial value
213             pConfig->ctxH264Info.structure = TOP_FIELD;
214         else if (pConfig->ctxH264Info.structure==TOP_FIELD)
215             pConfig->ctxH264Info.structure = BOTTOM_FIELD;
216         else if (pConfig->ctxH264Info.structure==BOTTOM_FIELD)
217             pConfig->ctxH264Info.structure = TOP_FIELD;
218     }
219 
220     mfeSetVopType(pConfig, pGopInfo);
221     *pDispOrder = pGopInfo->nDispOrder;
222 
223     ms_dprintk(DRV_L3, "MDrv_MFE_GetDispOrder: Enc=%u Disp=%u\n", (unsigned int)pGopInfo->nCodingOrder, (unsigned int)(*pDispOrder));
224     return 1;
225 }
226 
227 
228 // Consumer of copybits2file()
MDrv_MFE_GetBits(MFE_CONFIG * gpMfeConfig,BITSFRAME_INFO * bits_info)229 static MS_S32 MDrv_MFE_GetBits(MFE_CONFIG* gpMfeConfig, BITSFRAME_INFO *bits_info)
230 {
231     MS_S32 i=0;
232     MS_S32 index;
233     MS_S32 num_of_buffers = gpMfeConfig->ctxBufInfo.m_nOutBuffer;
234     ms_dprintk(DRV_L3, "MDrv_MFE_GetBits...\n");
235 
236     if(gpMfeConfig->PollingMode) {
237         MS_U16 val_1e = 0;
238 
239         do{
240             MHal_MFE_GetIRQ(&val_1e);
241             if(val_1e == 0) {
242                 ms_dprintf(DRV_L3, "Wait frame done");
243 #ifdef _MFE_UTOPIA_
244                 MsOS_DelayTask(5);
245 #else
246                 Sleep(5);
247 #endif
248             }
249         }
250         while(val_1e == 0);
251     }
252 #if (DEBUG_LEVEL & DRV_L6)
253     if(gpMfeConfig->GopInfo.nCodingOrder > 2){
254         mfe_enc.mfe_endtime = MsOS_GetSystemTime();
255         mfe_enc.mfe_total_time += (mfe_enc.mfe_endtime-mfe_enc.mfe_starttime);
256         mfe_enc.mfe_total_count ++;
257 
258         mfe_enc.mfe_maxtime = mfe_get_max(mfe_enc.mfe_maxtime,mfe_enc.mfe_endtime-mfe_enc.mfe_starttime);
259         mfe_enc.mfe_mintime = mfe_get_min(mfe_enc.mfe_mintime,mfe_enc.mfe_endtime-mfe_enc.mfe_starttime);
260         ms_dprintk(DRV_L6,"mfe count = %d\n",mfecount);
261         ms_dprintk(DRV_L6,"[TIME] total [%d] frms cur: %d, avg: %d us [MAX] %d [MIN] %d\n",
262             mfe_enc.mfe_total_count,mfe_enc.mfe_endtime-mfe_enc.mfe_starttime,
263             mfe_enc.mfe_total_time/mfe_enc.mfe_total_count,
264             mfe_enc.mfe_maxtime,mfe_enc.mfe_mintime);
265         {
266             MS_U32 clk;
267             MS_S32 cur_time;
268 #ifdef _MFE_EDISON_
269              switch (gpMfeConfig->MFEClk)
270             {
271                 case MFE_CLK_VERY_SLOW:
272                     clk = 144; break;
273                 case MFE_CLK_SLOW:
274                     clk = 192; break;
275                 case MFE_CLK_MEDIUM:
276                     clk = 216; break;
277                 case MFE_CLK_FAST:
278                     clk = 240; break;
279     			default:
280     				clk = 240;
281             }
282 #else
283              switch (gpMfeConfig->MFEClk)
284             {
285                 case MFE_CLK_VERY_SLOW:
286                     clk = 24; break;
287                 case MFE_CLK_SLOW:
288                     clk = 64; break;
289                 case MFE_CLK_MEDIUM:
290                     clk = 128; break;
291                 case MFE_CLK_FAST:
292                     clk = 192; break;
293     			default:
294     				clk = 192;
295             }
296 #endif
297              cur_time = MHal_MFE_CycleReport()/clk;
298              mfe_hw_enc.mfe_total_time += cur_time;
299             mfe_hw_enc.mfe_maxtime = mfe_get_max(mfe_hw_enc.mfe_maxtime,cur_time);
300             mfe_hw_enc.mfe_mintime = mfe_get_min(mfe_hw_enc.mfe_mintime,cur_time);
301             ms_dprintk(DRV_L6,"[TIME] HW report: %d us, avg: %d us [MAX] %d [MIN] %d\n",cur_time,
302                 mfe_hw_enc.mfe_total_time/mfe_enc.mfe_total_count,mfe_hw_enc.mfe_maxtime,mfe_hw_enc.mfe_mintime);
303         }
304     }
305 #endif
306 #ifdef _GenSkipHeader_
307 
308 #endif
309     if(MDrv_MFE_CheckEncodeDone(gpMfeConfig) == FALSE) {
310         bits_info[0].status = gpMfeConfig->bitsframe[gpMfeConfig->rbits_index].status = BITS_INFO_ZERO;
311         //ms_dprintk(DRV_L3, "MDrv_MFE_GetBits...fail!!\n");
312         return 1;
313     }
314         ms_dprintk(DRV_L3, "MDrv_MFE_GetBits...done\n");
315 
316 
317 #ifndef _NON_THREAD_
318     spin_lock(&_spinlock);
319 #endif
320     index = gpMfeConfig->rbits_index;
321     // Now we only copy one buffer
322     if (gpMfeConfig->_MFE_U32MFEEvent!=0) {
323         bits_info[i].miuAddress = gpMfeConfig->bitsframe[index].miuAddress;
324         bits_info[i].miuPointer = gpMfeConfig->bitsframe[index].miuPointer;
325         bits_info[i].size = gpMfeConfig->bitsframe[index].size;
326         bits_info[i].status = gpMfeConfig->bitsframe[index].status;
327         bits_info[i].voptype = gpMfeConfig->bitsframe[index].voptype;
328         bits_info[i].is_more_bits = 1;
329         bits_info[i].IVOP_address= gpMfeConfig->bitsframe[index].IVOP_address;
330         gpMfeConfig->_MFE_U32MFEEvent ^= (1<<index);
331         index = MFE_MUX((index+1)==num_of_buffers, 0, index+1);
332         i++;
333         if (i>num_of_buffers) {
334             ms_dprintk(DRV_L0, "MDrv_MFE_GetBits error!! use too many bits buffer\n");
335         }
336     }
337 
338     bits_info[i-1].is_more_bits = 0;
339 #ifndef _NON_THREAD_
340     spin_unlock(&_spinlock);
341 #endif
342     ms_dprintk(DRV_L3, "Leave MDrv_MFE_GetBits.\n");
343     return 0;
344 }
345 
346 
MDrv_MFE_EncodeVOP_End(MFE_CONFIG * pConfig)347 static MS_S32 MDrv_MFE_EncodeVOP_End(MFE_CONFIG *pConfig)
348 {
349 /*
350     //mark the last frame is Drop.
351     if(gpMfeConfig->VTMode && rc_CheckSkippedFrame(&gpMfeConfig->VTRateCtrl)) {
352         pConfig->nDropFlag = 1;
353         pConfig->m_cvbrFrameSkip = 1;
354         MfeDrvRateControlUpdate(gpMfeConfig, 0);
355 		return 0;
356     }
357     else {
358         pConfig->nDropFlag = 0;
359     }
360 */
361 #if DROP_TEST
362     mfe_count++;
363     if(mfe_count == 6) {
364         pConfig->nDropFlag = 1;
365         return 0;
366     }
367     else
368         pConfig->nDropFlag = 0;
369 #endif
370     switch (pConfig->nCodecType) {
371     case REG_ENC_MODE_MPG4:
372     case REG_ENC_MODE_H263:
373         mfeM4VE_UpdateFrame(pConfig);
374         break;
375     case REG_ENC_MODE_H264:
376         mfeH264_UpdateFrame(pConfig);
377         break;
378     case REG_ENC_MODE_JPEG:
379         //MS_ASSERT(0);
380         break;
381     }
382 #ifdef _GenSkipHeader_
383         if(pConfig->VTMode && (pConfig->vopPredType==I_VOP))
384 #endif
385             pConfig->bForceIframe = FALSE;
386 
387     //ms_dprintk(DRV_L3, "pConfig->vopPredType = %d\n",pConfig->vopPredType);
388     ms_dprintk(DRV_L3, "encode one frame end\n");
389     return 0;
390 }
391 
get_hw_encode_done_size(MS_U32 start)392 static MS_U32 get_hw_encode_done_size(MS_U32 start)
393 {
394     MS_U16 u16Reg1, u16Reg2;
395     MS_U32 hwlen;
396     MS_U32 wptr;
397     MS_S32 size;
398     // Final frame bit count -> byte count
399     ReadRegMFE(0x42, &u16Reg1);
400     ReadRegMFE(0x43, &u16Reg2);
401     //ms_dprintk(DRV_L3, "u16Reg2 = 0x%x, u16Reg1 = 0x%x\n", u16Reg2, u16Reg1);
402     hwlen = (((u16Reg2)<<16) | u16Reg1)>>3;
403     ms_dprintk(DRV_L3, "start = 0x%x, hwlen = 0x%x\n", (unsigned int)start, (unsigned int)hwlen);
404 
405     // The last outbuf filled-size
406     ReadRegMFE(0x44, &u16Reg1);
407     ReadRegMFE(0x45, &u16Reg2);
408     wptr = ((u16Reg2<<16) | u16Reg1)<<3;
409     ms_dprintk(DRV_L3, "bspobuf write pointer wptr = 0x%x\n", (unsigned int)wptr);
410     size = wptr - start + ((hwlen&7)?(hwlen&7):8);
411     if (size<=0)
412         ms_dprintk(DRV_L0, "[Error] copybits2file(): size %d < 0. start = 0x%x, wptr = 0x%x, hwlen = 0x%x\n",
413             (int)size, (unsigned int)start, (unsigned int)wptr, (unsigned int)hwlen);
414 
415     return size;
416 }
417 
418 // Supplier of MDrv_MFE_GetBits()
copybits2file(MFE_CONFIG * pConfig,MS_U16 val_1e)419 static MS_BOOL copybits2file(MFE_CONFIG *pConfig, MS_U16 val_1e)
420 {
421     MS_S32 wbits_index;
422     MS_U8   voptype = pConfig->vopPredType;
423     MS_U32 Y_start = pConfig->ctxBufInfo.m_nRecYAddr.miuAddress;
424     MS_U32 start = 0;
425     MS_S32 size = 0;
426     MS_S32 bFrameDone = CHECK_IRQ_STATUS(val_1e, IRQ_FRAME_DONE);
427     MS_S32 bBufFull = CHECK_IRQ_STATUS(val_1e, IRQ_BSPOBUF_FULL);    // Output buffer full.
428     MS_S32 bImgFull = CHECK_IRQ_STATUS(val_1e, IRQ_IMG_BUF_FULL);    // Input buffer full. Only when JPEG row-mode.
429 
430     start = pConfig->outbitsbuf[pConfig->nOBufIndex].start_addr;
431 
432     if (bBufFull) {
433         ms_dprintk(DRV_L3, "copybits2file(): Buffer full.\n");
434         size = pConfig->ctxBufInfo.m_OutBufferSize;
435         //MS_ASSERT(size == pConfig->ctxBufInfo.m_OutBufferSize);
436     }
437     else if (bFrameDone) {
438         ms_dprintk(DRV_L3, "copybits2file(): Frame done.\n");
439 #ifdef _GenSkipHeader_
440               if(pConfig->VTMode && rc_CheckSkippedFrame(&pConfig->VTRateCtrl)){
441                 OutStream* pStream = &pConfig->m_OutStream;
442                 size = pStream->m_nByteCount;
443                 memcpy(addr_phy2log(start + pConfig->MFE_U32MFEMIUOffset),
444                     pStream->m_pbFrameBuffer, pStream->m_nByteCount);
445               }
446               else
447 #endif
448             if(pConfig->SecurityMode) {
449                 MS_U16 u16Reg1, u16Reg2;
450                 ReadRegMFE(0x42, &u16Reg1);
451                 ReadRegMFE(0x43, &u16Reg2);
452                 ms_dprintk(DRV_L3, "size = 0x%x\n", (unsigned int)size);
453                 size = (((u16Reg2)<<16) | u16Reg1)>>3;
454             } else {
455                  size = get_hw_encode_done_size(start);
456             }
457 
458     }
459     else if (bImgFull) {
460         start = 0;
461         size = 0;
462              ms_dprintk(DRV_L3, "image buff full!0x%x\n", val_1e);
463     }
464     else {
465         ms_dprintk(DRV_L0, "copybits2file(): Error IRQ=0x%x not handled!\n", val_1e);
466         return FALSE;
467     }
468 
469     //clear all set irq, need to set before change bitstream buffer
470     wbits_index = pConfig->nOBufIndex;
471     pConfig->nOBufIndex = (pConfig->nOBufIndex+1)%pConfig->ctxBufInfo.m_nOutBuffer; //next outbuf
472     //ms_dprintk(DRV_L3, "OBufIndex=%d, state=%d\n", pConfig->nOBufIndex, pConfig->encode_state);
473 
474 
475     if (bBufFull) {
476         ms_dprintk(DRV_L3, "MFE encoding bitsbuf full! buf %u, size %d\n", (unsigned int)pConfig->nOBufIndex, (int)size);
477         pConfig->encode_state = WAIT_AVAIL_BITSBUF;
478     }
479 
480     MHal_MFE_ClearIRQ(val_1e);    // Conrad: Should this be here or above??
481 
482     // Output info filling
483     pConfig->bitsframe[wbits_index].miuAddress = start;
484     pConfig->bitsframe[wbits_index].miuPointer = (MS_U32)addr_phy2log(start + pConfig->MFE_U32MFEMIUOffset);
485     pConfig->bitsframe[wbits_index].size = size;
486 
487     //CABAC stuffing byte
488     if(pConfig->UseCABAC && bFrameDone) {
489         pConfig->bitsframe[wbits_index].stuffing_bytes = MfeDrvCabacStuffingReport(pConfig);
490     }
491 #ifdef WIN32
492     if(!pConfig->SecurityMode)
493         UDMAOP_DMAGet((MS_S8*)pConfig->bitsframe[wbits_index].miuPointer, size, start, 0);
494 #endif
495     if (bFrameDone)
496         pConfig->bitsframe[wbits_index].status = BITS_INFO_FRAMEDONE;
497     else if(bBufFull)
498         pConfig->bitsframe[wbits_index].status = BITS_INFO_BUFFULL;
499     else if (bImgFull)
500         pConfig->bitsframe[wbits_index].status = BITS_INFO_IMG_BUFFULL;
501 
502     pConfig->bitsframe[wbits_index].voptype = voptype;
503     // For I-VOP Thumbnail
504     if (voptype==I_VOP) {
505         pConfig->bitsframe[wbits_index].IVOP_address = Y_start;
506     } else {
507         pConfig->bitsframe[wbits_index].IVOP_address = 0;
508     }
509 
510     pConfig->_MFE_U32MFEEvent |= 1<<wbits_index;
511 
512     // NOTE: When acts as kernel mode, wait up for poll()
513     //       When acts as user mode, release semaphore (paired with MDrv_MFE_GetBits())
514     //printk("next: 0x%x  prev: 0x%x\n", _MFE_wait_queue.task_list.next, _MFE_wait_queue.task_list.prev);
515     if (bFrameDone) {
516     MDrv_MFE_EncodeVOP_End(pConfig);
517 #ifdef MFE_MIU_PROTECT
518     //MIU MODE, check type(0:BPS,1:MC.2:MV,3:GN)
519     MHal_MFE_Enable_MIU_Protection_Check(TEST_MIU_PROTECTION_MODE,0);
520 #endif
521     pConfig->encode_state = WAIT_INPUT_FRAME;
522     }
523 
524 #if defined(_MFE_T8_) && defined(_MIPS_PLATFORM_)
525     if (bFrameDone || bBufFull)
526         return TRUE;
527     else {
528         ms_dprintk(DRV_L0, "[ERROR] CHECK_IRQ_STATUS not bFrameDone or bBufFull.\n");
529         return FALSE;
530     }
531 #endif
532     return TRUE;
533 }
534 
MDrv_MFE_CheckEncodeDone(MFE_CONFIG * pConfig)535 static MS_BOOL MDrv_MFE_CheckEncodeDone(MFE_CONFIG *pConfig)
536 {
537     MS_U16 val_1e;
538     //MS_U8  voptype = pConfig->vopPredType;
539     //MS_S32 sgc_frame_done;
540 #ifdef _GenSkipHeader_
541     if(pConfig->VTMode && rc_CheckSkippedFrame(&pConfig->VTRateCtrl)){
542         val_1e = 0x1; //fake frame done
543     }
544     else
545 #endif
546         MHal_MFE_GetIRQ(&val_1e);
547 
548     ms_dprintk(DRV_L3, "CheckEncodeDone() reg1e=0x%x\n",val_1e);
549     if (val_1e==0) {
550         //ms_dprintk(DRV_L4, "[WARN] CheckEncodeDone() reg1e=0\n");
551         return FALSE;
552     }
553 #ifdef MFE_MIU_PROFILE
554     {
555         MS_U16 tmp_r = 0, tmp_w = 0;
556         ReadRegMFE_BANK1(0x49,&tmp_r);
557         ReadRegMFE_BANK1(0x44,&tmp_w);
558         pConfig->total_r_count += tmp_r;
559         pConfig->total_w_count += tmp_w;
560         if(pConfig->miu_count == 0) {
561             pConfig->max_r_count = tmp_r;
562             pConfig->max_w_count = tmp_w;
563             pConfig->min_r_count = tmp_r;
564             pConfig->min_w_count = tmp_w;
565         } else {
566             if(tmp_r > pConfig->max_r_count)
567                 pConfig->max_r_count = tmp_r;
568             if(tmp_w > pConfig->max_w_count)
569                 pConfig->max_w_count = tmp_w;
570             if(tmp_r < pConfig->min_r_count)
571                 pConfig->min_r_count = tmp_r;
572             if(tmp_w < pConfig->min_w_count)
573                 pConfig->min_w_count = tmp_w;
574         }
575         pConfig->miu_count++;
576         ms_dprintk(DRV_L1, "[MIU]cur r/w=(0x%04x,0x%04x), avg (0x%04x,0x%04x), max (0x%04x,0x%04x), min (0x%04x,0x%04x)\n"
577             ,tmp_r,tmp_w,pConfig->total_r_count/pConfig->miu_count,pConfig->total_w_count/pConfig->miu_count
578             ,pConfig->max_r_count,pConfig->max_w_count,pConfig->min_r_count,pConfig->min_w_count );
579     }
580 #endif
581     DumpAllReg(&pConfig->mfe_reg);
582     //h1e: [7:0]  status of interrupt on CPU side
583     //    {2'b0, net_trigger, fs_fail_irq, txip_time_out, bspobuf_full_irq, img_buf_full_irq, marb_bspobuf_ful, frame_done_irq}
584     //sgc_frame_done = CHECK_IRQ_STATUS(val_1e, IRQ_FRAME_DONE);
585     copybits2file(pConfig, val_1e);
586 
587     return TRUE;
588 }
589 
MDrv_MFE_EncodeVOP(MFE_CONFIG * pConfig,GOPINFO * pGopInfo)590 static void MDrv_MFE_EncodeVOP(MFE_CONFIG *pConfig, GOPINFO* pGopInfo)
591 {
592 
593     ms_dprintk(DRV_L2, "MDrv_MFE_EncodeVOP : %d(I/P/B)\n", pConfig->vopPredType);
594 
595     //mark the last frame is Drop.
596     if(pConfig->VTMode && rc_CheckSkippedFrame(&pConfig->VTRateCtrl)) {
597 #ifndef _GenSkipHeader_
598         MfeDrvRateControlUpdate(pConfig, 0);
599         pConfig->nDropFlag = 1;
600         return ;
601 #else
602         pConfig->nDropFlag = 0;
603 #endif
604     }
605     else {
606         pConfig->nDropFlag = 0;
607     }
608 
609     switch (pConfig->nCodecType) {
610         case REG_ENC_MODE_MPG4:
611         case REG_ENC_MODE_H263:
612             mfeM4VE_EncodeFrame(pConfig, pGopInfo);
613             break;
614         case REG_ENC_MODE_H264:
615             if (pConfig->encodeDummyFrame)
616             {
617                 mfeH264_EncodeDummyFrame(pConfig, pGopInfo);
618             }
619             else
620             {
621                 mfeH264_EncodeFrame(pConfig, pGopInfo);
622             }
623             break;
624 #ifdef _MFE_M1_
625         case REG_ENC_MODE_JPEG:
626             mfeJPE_EncodeFrame(pConfig, pGopInfo);
627             break;
628 #endif
629         default:
630             MS_ASSERT(0);
631             break;
632     }
633     pConfig->encode_state = WAIT_FRAME_DONE;
634 
635     ms_dprintk(DRV_L3, "In MDrv_MFE_EncodeVOP() After encode_state = WAIT_FRAME_DONE\n");
636 }
637 
mdrvLoadTestCasePre(MFE_CONFIG * pConfig)638 static void mdrvLoadTestCasePre(MFE_CONFIG *pConfig)
639 {
640 
641     if (pConfig->nCodecType==REG_ENC_MODE_H263) {
642         pConfig->bQuantType = 0;
643     }
644     else if(pConfig->nCodecType==REG_ENC_MODE_MPG4) {
645         pConfig->bQuantType = 1;
646     }
647 
648 }
mdrvLoadTestCasePost(MFE_CONFIG * pConfig)649 static void mdrvLoadTestCasePost(MFE_CONFIG *pConfig)
650 {
651 
652 }
653 
MDrv_MFE_Init(MFE_CONFIG * pConfig)654 static void MDrv_MFE_Init(MFE_CONFIG *pConfig)
655 {
656     MS_S32 i;
657 #if DROP_TEST
658     mfe_count=0;
659 #endif
660     ms_dprintk(DRV_L1, "CodecType = %d\n", (int)pConfig->nCodecType);
661     ms_dprintk(DRV_L1, "ColorFormat = %d\n", (int)pConfig->bColorFormat);
662     ms_dprintk(DRV_L1, "FrameRatex100 = %d\n", (int)pConfig->FrameRatex100);
663     ms_dprintk(DRV_L1, "bitrate = %d\n", (int)pConfig->nBitrate);
664     mdrvLoadTestCasePre(pConfig);
665     if (pConfig->MfeAdvInfo.low_bandwidth_en){
666         MS_U32 imi_addr = (MS_U32)pConfig->MfeAdvInfo.imi_buf_addr.miuAddress;
667         MS_U32 imi_size;
668         imi_addr = (((imi_addr) + 0x3) & ~0x3);
669         imi_size = (((pConfig->nBufWidth + 15)>>4)*2 + 6)*256; //Y MB rows, plus 5MB's
670 
671         if(imi_size <= 0x2000)
672             imi_size = 0x2000;
673         else if(imi_size <= 0x4000)
674             imi_size = 0x4000;
675         else if(imi_size <= 0x8000)
676             imi_size = 0x8000;
677         else if(imi_size <= 0x10000)
678             imi_size = 0x10000;
679         else imi_size = 0;
680 
681         pConfig->imi_addr = imi_addr;
682         pConfig->imi_size = imi_size;
683     }
684     switch (pConfig->nCodecType) {
685         case REG_ENC_MODE_MPG4:
686         case REG_ENC_MODE_H263:
687             mfeM4VE_Init(pConfig);
688             break;
689         case REG_ENC_MODE_H264:
690             mfeH264_Init(pConfig);
691             break;
692 #ifdef _MFE_M1_
693         case REG_ENC_MODE_JPEG:
694             mfeJPE_Init(pConfig);
695             break;
696 #endif
697         default:
698             MS_ASSERT(0);
699     }
700 
701     mdrvLoadTestCasePost(pConfig);
702 
703 
704     ms_dprintk(DRV_L3, "In MDrv_MFE_Init.. set clock level %d\n", pConfig->MFEClk);
705     MHal_MFE_PowerOff(0,pConfig->MFEClk);
706 
707     MMAPInit(pConfig->dram_base, pConfig->dram_size, &pConfig->dram_ptr);
708 
709     pConfig->encode_state = WAIT_INPUT_FRAME; //init encode_state
710     MHal_MFE_ResetReg(&pConfig->mfe_reg);
711     //DumpAllReg(pConfig->mfe_reg);
712 
713     switch (pConfig->nCodecType) {
714         case REG_ENC_MODE_MPG4:
715         case REG_ENC_MODE_H263:
716             m4veAllocDRAM(pConfig);
717             break;
718         case REG_ENC_MODE_H264:
719             h264AllocDRAM(pConfig);
720             break;
721 #ifdef _MFE_M1_
722         case REG_ENC_MODE_JPEG:
723             jpeAllocDRAM(pConfig);
724             break;
725 #endif
726         default:
727             MS_ASSERT(0);
728             break;
729     }
730 
731     for (i=0; i<pConfig->ctxBufInfo.m_nOutBuffer; i++) {
732         pConfig->outbitsbuf[i].start_addr  = pConfig->ctxBufInfo.m_nOutBufAddr[i].miuAddress;
733         pConfig->outbitsbuf[i].end_addr   = pConfig->ctxBufInfo.m_nOutBufAddr[i].miuAddress+pConfig->ctxBufInfo.m_OutBufferSize;
734         pConfig->outbitsbuf[i].used_size  = 0;
735      ms_dprintk(DRV_L2, "Obuf index %d: PhyAddr=0x%08x\n", (int)i, (unsigned int)pConfig->outbitsbuf[i].start_addr);
736     }
737     pConfig->nOBufIndex = 0;
738 
739 #if (DEBUG_LEVEL & DRV_L6)
740     mfe_performance_init(& mfe_enc);
741     mfe_performance_init(& mfe_hw_enc);
742     mfe_performance_init(& mfe_duration_enc);
743     mfecount=0;
744 #endif
745 
746 #ifdef MFE_MIU_PROFILE
747     pConfig->miu_count = 0;
748     pConfig->total_r_count = 0;
749     pConfig->total_w_count = 0;
750 #endif
751     MHal_MFE_ClearIRQ(0x3f);
752 }
753 
754 
MDrv_MFE_ENC_OneFrame(MFE_CONFIG * gpMfeConfig,MEMMAP_CUR_t * YUV_addr)755 static MS_S32 MDrv_MFE_ENC_OneFrame(MFE_CONFIG* gpMfeConfig, MEMMAP_CUR_t *YUV_addr)
756 {
757     MS_S32 i;
758 
759     gpMfeConfig->encode_state = WRITE_MFE_REG;
760 #if (DEBUG_LEVEL & DRV_L6)
761     {
762         MS_U32 cur_time = MsOS_GetSystemTime();
763         if(gpMfeConfig->GopInfo.nCodingOrder > 2){
764             mfe_duration_enc.mfe_durationtime = cur_time - mfe_duration_enc.mfe_lasttime;
765             mfe_duration_enc.mfe_maxtime = mfe_get_max(mfe_duration_enc.mfe_maxtime,cur_time);
766             mfe_duration_enc.mfe_mintime = mfe_get_min(mfe_duration_enc.mfe_mintime,cur_time);
767             mfe_duration_enc.mfe_total_time += mfe_duration_enc.mfe_durationtime;
768             mfe_duration_enc.mfe_total_count++;
769             ms_dprintk(DRV_L6, "cur_time = %u,duration = %d,[AVG]:%d, [MAX]:%d,[MIN]:%d\n",cur_time,mfe_duration_enc.mfe_durationtime,
770                 mfe_duration_enc.mfe_total_time/mfe_duration_enc.mfe_total_count,
771                 mfe_duration_enc.mfe_maxtime,mfe_duration_enc.mfe_mintime );
772         }
773         else {
774             mfe_duration_enc.mfe_total_time = 0;
775             mfe_duration_enc.mfe_total_count = 0;
776             mfe_duration_enc.mfe_maxtime = cur_time;
777             mfe_duration_enc.mfe_mintime = cur_time;
778         }
779         mfe_duration_enc.mfe_lasttime = cur_time;
780     }
781 #endif
782     for (i=0; i<gpMfeConfig->ctxBufInfo.m_nOutBuffer; i++) {
783         MS_ASSERT(gpMfeConfig->outbitsbuf[i].used_size==0);
784         gpMfeConfig->outbitsbuf[i].used_size = 0;
785     }
786 
787     ms_dprintk(DRV_L2, "start to encode frame #%u(Enc) #%u(Disp)\n", (unsigned int)gpMfeConfig->GopInfo.nCodingOrder, (unsigned int)gpMfeConfig->GopInfo.nDispOrder);
788 
789     gpMfeConfig->ctxBufInfo.m_nCurYAddr = YUV_addr->Cur_Y0;
790     gpMfeConfig->ctxBufInfo.m_nCurCAddr = YUV_addr->Cur_C0;
791 
792     if(gpMfeConfig->m_bFrameMode == 0) {
793         gpMfeConfig->ctxBufInfo.m_nRefYAddr[1] = YUV_addr->Cur_Y1;
794         gpMfeConfig->ctxBufInfo.m_nRefCAddr[1] = YUV_addr->Cur_C1;
795     }
796 
797     MDrv_MFE_EncodeVOP(gpMfeConfig, &gpMfeConfig->GopInfo);
798 
799     // If H264 PAFF, always assume Top-field first
800     if (!(gpMfeConfig->nCodecType==REG_ENC_MODE_H264 && gpMfeConfig->ctxH264Info.structure==TOP_FIELD))
801         gpMfeConfig->GopInfo.nCodingOrder++;
802     return 0;
803 }
804 
805 
MDrv_MFE_Finish(MFE_CONFIG * pConfig)806 static MS_S32 MDrv_MFE_Finish(MFE_CONFIG* pConfig)
807 {
808 
809     switch (pConfig->nCodecType) {
810         case REG_ENC_MODE_MPG4:
811         case REG_ENC_MODE_H263:
812             break;
813         case REG_ENC_MODE_H264:
814             mfeH264_DeInit(pConfig);
815             break;
816         case REG_ENC_MODE_JPEG:
817             break;
818         default:
819             MS_ASSERT(0);
820             break;
821     }
822 
823     MfeDrvRateControlDeInit(pConfig);
824 #if !(defined(_MFE_T8_)&&defined(_KERNEL_MODE_))
825 #ifndef _NON_THREAD_
826     MDrv_MFE_Sem_Destroy();
827     pthread_mutex_destroy(&_spinlock);
828 #endif
829 #endif
830 
831     //MHal_MFE_PowerOff(1,pConfig->MFEClk);
832 
833     return 0;
834 }
835 
MDrv_MFE_SetMIUOffset(MFE_CONFIG * pConfig,MS_U32 MFE_U32MIUOffset)836 static void MDrv_MFE_SetMIUOffset(MFE_CONFIG *pConfig, MS_U32 MFE_U32MIUOffset )
837 {
838     ms_dprintk(DRV_L1, "MFE_U32MFEMIUOffset = 0x%x\n", (unsigned int)MFE_U32MIUOffset);
839     pConfig->MFE_U32MFEMIUOffset = MFE_U32MIUOffset;
840 }
841 
842 // Output: Fill 16bit byte-length into pOutBuf[0] (LSB) and pOutBuf[1] (MSB)
843 //         Then following pOutBuf+2 is the byte stream of video headers.
MDrv_MFE_GetConfigBytes(MFE_CONFIG * pConfig,void * pHeader_info)844 static void MDrv_MFE_GetConfigBytes(MFE_CONFIG *pConfig, void* pHeader_info)
845 {
846     OutStream* pStream = NULL;
847     MS_U8* pBuf = NULL;
848 
849     if (pHeader_info ==NULL || pConfig==NULL)
850         return;
851 
852     pStream = &pConfig->m_OutStream;
853 
854     if(rc_CheckSkippedFrame(&pConfig->VTRateCtrl)){
855         VOL_INFO_t *vol_info = (VOL_INFO_t *)pHeader_info;
856         vol_info->Len = codeM4vConfigHeaders(pConfig,TRUE);
857         pBuf = vol_info->pHeader;
858         goto EXIT;
859     }
860 
861     switch (pConfig->nCodecType) {
862     case REG_ENC_MODE_MPG4:
863         {
864             VOL_INFO_t *vol_info = (VOL_INFO_t *)pHeader_info;
865             vol_info->Len = codeM4vConfigHeaders(pConfig,FALSE);
866             pBuf = vol_info->pHeader;
867             break;
868         }
869     case REG_ENC_MODE_H264:
870         {
871             SPSPPS_INFO_t *spspps_info = (SPSPPS_INFO_t*)pHeader_info;
872             codeH264ConfigHeaders(pConfig,&spspps_info->SPSLen,&spspps_info->PPSLen);
873             spspps_info->pHeaderPPS = spspps_info->pHeaderSPS + spspps_info->SPSLen;
874             pBuf = spspps_info->pHeaderSPS;
875             break;
876         }
877     case REG_ENC_MODE_H263:
878     case REG_ENC_MODE_JPEG:
879         // pBuf is NULL
880         return;
881     }
882 
883 EXIT:
884     if (pBuf)
885         memcpy(pBuf, pStream->m_pbFrameBuffer, pStream->m_nByteCount);
886 
887 }
888 
MDrv_MFE_Ioctl(MS_VIRT MFE_fd,MS_U32 cmd,MS_VIRT arg)889 MS_S32 MDrv_MFE_Ioctl(MS_VIRT MFE_fd, MS_U32 cmd, MS_VIRT  arg)
890 {
891     PVR_Info *pappPVR_Info;
892     BITSFRAME_INFO *bits_info;
893     MFE_CONFIG* gpMfeConfig = (MFE_CONFIG *)MFE_fd;
894     switch(cmd)
895     {
896     case MFE_IOC_INIT:
897         if (gpMfeConfig != NULL && arg != 0) {
898             //MFE_CONFIG *gpMfeConfig = (MFE_CONFIG *)MFE_fd;
899             ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_INIT\n");
900             //gpMfeConfig = malloc(sizeof(MFE_CONFIG));
901             memset(gpMfeConfig, 0, sizeof(MFE_CONFIG));
902             memset(&gpMfeConfig->GopInfo, 0, sizeof(GOPINFO));
903             pappPVR_Info = (PVR_Info *)arg;
904             gpMfeConfig->rbits_index = 0;
905             gpMfeConfig->GopInfo.nCodingOrder = 0;
906             gpMfeConfig->_MFE_U32MFEEvent = 0;
907             gpMfeConfig->bForceIframe = FALSE;
908             gpMfeConfig->nDropFlag =0;
909             ms_dprintk(DRV_L1, "W = %d, H = %d, nCodecType = %d\n", (int)pappPVR_Info->width, (int)pappPVR_Info->height, (int)pappPVR_Info->nCodecType);
910             gpMfeConfig->nCodecType = pappPVR_Info->nCodecType;
911             gpMfeConfig->nDispWidth = pappPVR_Info->nDispWidth;
912             gpMfeConfig->nDispHeight = pappPVR_Info->nDispHeight;
913             gpMfeConfig->nBufWidth = pappPVR_Info->nBufWidth;
914             gpMfeConfig->nBufHeight = pappPVR_Info->nBufHeight;
915             gpMfeConfig->dram_base = pappPVR_Info->BitsBuffStart;
916             gpMfeConfig->dram_size = pappPVR_Info->BitsBuffSize;
917             gpMfeConfig->bInterlace = pappPVR_Info->bInterlace;
918             gpMfeConfig->nPbetweenI = pappPVR_Info->nPbetweenI;
919             gpMfeConfig->nBbetweenP = pappPVR_Info->nBbetweenP;
920             gpMfeConfig->FrameRatex100 = pappPVR_Info->FrameRatex100;
921             gpMfeConfig->nBitrate = pappPVR_Info->nBitrate;
922             gpMfeConfig->nP_is_infinite = pappPVR_Info->nP_is_infinite;
923             gpMfeConfig->ctxBufInfo.m_nOutBuffer = pappPVR_Info->nOutBuffer;
924             gpMfeConfig->ctxBufInfo.m_OutBufferSize = pappPVR_Info->OutBufferSize;
925             gpMfeConfig->enableReduceBW = pappPVR_Info->enableReduceBW;
926             gpMfeConfig->enableFastMode = pappPVR_Info->enableFastMode;
927             memcpy(&gpMfeConfig->MfeCropInfo, &pappPVR_Info->MfeCropInfo,sizeof(MFE_CROP_INFO_t));
928 #ifdef _MFE_M1_
929             gpMfeConfig->m_bFrameMode = pappPVR_Info->m_bFrameMode;
930             gpMfeConfig->m_bFDC_mode = pappPVR_Info->fdc_mode;
931             gpMfeConfig->m_quality = pappPVR_Info->quality;
932             memcpy(&gpMfeConfig->MfeAdvInfo,&pappPVR_Info->MfeAdvInfo,sizeof(MFE_ADV_INFO_t));
933 #else
934             gpMfeConfig->m_bFrameMode = 1;
935 #endif
936             if(pappPVR_Info->enableISR == 0)
937                 gpMfeConfig->PollingMode = 1;
938             gpMfeConfig->ctxRateControl.m_nVPMbRow = MFE_ER_MBY;
939             gpMfeConfig->ctxRateControl.m_nVPSize = MFE_ER_BS_TH;
940             gpMfeConfig->MFEClk= pappPVR_Info->MFEClk;
941             gpMfeConfig->TimeIncreamentRes = pappPVR_Info->TimeIncreamentRes;
942             gpMfeConfig->VopTimeIncreament = pappPVR_Info->VopTimeIncreament;
943 
944             if(gpMfeConfig->nPbetweenI == -1){
945                 gpMfeConfig->nP_is_infinite = 1;
946             }
947 #ifdef _MFE_M1_
948             if(pappPVR_Info->enableVTRateControl)
949             {
950                 gpMfeConfig->VTMode = 1;
951                 gpMfeConfig->VTRateCtrl.m_bDropFrameEnabled= 1;
952             }
953 #endif
954             gpMfeConfig->bColorFormat = pappPVR_Info->bColorFormat;
955             if(pappPVR_Info->enableSecurityMode) {
956                 gpMfeConfig->SecurityMode = 1;
957             }
958             if(gpMfeConfig->bColorFormat==MFE_YUYV) {
959                 gpMfeConfig->g_nUseYUV422 = 1;
960             } else if(gpMfeConfig->bColorFormat==MFE_YVYU) {
961                 gpMfeConfig->g_nUseYUV422 = 2;
962             } else if(gpMfeConfig->bColorFormat==MFE_UYVY) {
963                 gpMfeConfig->g_nUseYUV422 = 3;
964             } else if(gpMfeConfig->bColorFormat==MFE_VYUY) {
965                 gpMfeConfig->g_nUseYUV422 = 4;
966             } else {
967                 gpMfeConfig->g_nUseYUV422 = 0;
968             }
969 
970             if(pappPVR_Info->enableCABAC)
971                 gpMfeConfig->UseCABAC = 1;
972 
973 #if defined(MFE_SUPPORT_TLB)
974             gpMfeConfig->bEnableTLB = (pappPVR_Info->reserved1 & (MS_U32)MFE_ENABLE_TLB_FLAG) ? 1 : 0;
975 #endif
976             MHAL_MFE_CreateRegMap(&gpMfeConfig->mfe_reg,&gpMfeConfig->mfe_reg1);
977             MDrv_MFE_Init(gpMfeConfig);
978         }
979         break;
980     case MFE_IOC_GET_QTABLE:
981         if (gpMfeConfig != NULL && arg != 0) {
982             memcpy((MS_S32*)arg,&gpMfeConfig->ctxJpgInfo.QTable[0][0],sizeof(MS_S32)*64);
983             memcpy(((MS_S32*)arg)+64,&gpMfeConfig->ctxJpgInfo.QTable[1][0],sizeof(MS_S32)*64);
984         }
985         break;
986     case MFE_IOC_SET_QUALITY:
987         if (gpMfeConfig != NULL) {
988             gpMfeConfig->m_quality = (MS_U32)arg;
989 #ifdef _MFE_M1_
990             mfeJPE_Set_QTABLE(gpMfeConfig);
991 #endif
992         }
993         break;
994     case MFE_IOC_ENC_ONEFRAME:
995         if (gpMfeConfig != NULL && arg != 0) {
996             ms_dprintk(DRV_L2, "[IOCTL] MFE_IOC_ENC_ONEFRAME\n");
997             MDrv_MFE_ENC_OneFrame(gpMfeConfig, (MEMMAP_CUR_t*)arg);
998         }
999         break;
1000     case MFE_IOC_GET_DISPORDER:
1001         if (gpMfeConfig != NULL && arg != 0) {
1002             ms_dprintk(DRV_L3, "[IOCTL] MFE_IOC_GET_DISPORDER\n");
1003             MDrv_MFE_GetDispOrder(gpMfeConfig, &gpMfeConfig->GopInfo, (MS_U32*)arg);
1004         }
1005         break;
1006     case MFE_IOC_GETBITS:
1007         if (gpMfeConfig != NULL && arg != 0) {
1008             ms_dprintk(DRV_L3, "[IOCTL] MFE_IOC_GETBITS\n");
1009             bits_info = (BITSFRAME_INFO *)arg;
1010             return MDrv_MFE_GetBits(gpMfeConfig,bits_info);
1011         }
1012         break;
1013     case MFE_IOC_SETBITRATE:
1014         if (gpMfeConfig != NULL && arg != 0) {
1015             pappPVR_Info = (PVR_Info *)arg;
1016             gpMfeConfig->nBitrate = pappPVR_Info->nBitrate;
1017             ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_SETBITRATE = %d\n", (int)gpMfeConfig->nBitrate);
1018         }
1019         break;
1020     case MFE_IOC_SET_COLOR_FORMAT:
1021         if (gpMfeConfig != NULL && arg != 0) {
1022             pappPVR_Info = (PVR_Info *)arg;
1023             gpMfeConfig->bColorFormat = pappPVR_Info->bColorFormat;
1024             if(gpMfeConfig->bColorFormat==MFE_YUYV) {
1025                 gpMfeConfig->g_nUseYUV422 = 1;
1026             } else if(gpMfeConfig->bColorFormat==MFE_YVYU) {
1027                 gpMfeConfig->g_nUseYUV422 = 2;
1028             } else if(gpMfeConfig->bColorFormat==MFE_UYVY) {
1029                 gpMfeConfig->g_nUseYUV422 = 3;
1030             } else if(gpMfeConfig->bColorFormat==MFE_VYUY) {
1031                 gpMfeConfig->g_nUseYUV422 = 4;
1032             } else {
1033                 gpMfeConfig->g_nUseYUV422 = 0;
1034             }
1035             ms_dprintk(DRV_L2, "[IOCTL] MFE_IOC_SET_COLOR_FORMAT = %d\n", gpMfeConfig->bColorFormat);
1036         }
1037         break;
1038     case MFE_IOC_RESET_BITRATE:
1039         if (gpMfeConfig != NULL && arg != 0) {
1040             pappPVR_Info = (PVR_Info *)arg;
1041             gpMfeConfig->nBitrate = pappPVR_Info->nBitrate;
1042             ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_RESET_BITRATE = %d\n", (int)gpMfeConfig->nBitrate);
1043             MfeDrvRateControlInit(gpMfeConfig);
1044         }
1045         break;
1046    case MFE_IOC_SET_ISR:
1047         if (gpMfeConfig != NULL && arg != 0) {
1048             pappPVR_Info = (PVR_Info *)arg;
1049             gpMfeConfig->PollingMode = pappPVR_Info->enableISR==1?0:1;
1050             ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_SET_ISR = %u\n", (unsigned int)gpMfeConfig->PollingMode);
1051         }
1052         break;
1053     case MFE_IOC_RESET_FRAMERATE:
1054         if (gpMfeConfig != NULL && arg != 0) {
1055             pappPVR_Info = (PVR_Info *)arg;
1056             gpMfeConfig->FrameRatex100 = pappPVR_Info->FrameRatex100;
1057             ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_RESET_FRAMERATE = %d\n", (int)gpMfeConfig->FrameRatex100);
1058             MfeDrvRateControlInit(gpMfeConfig);
1059         }
1060         break;
1061     case MFE_IOC_RESET_BITRATE_AND_FRAMERATE:
1062         if (gpMfeConfig != NULL && arg != 0) {
1063             pappPVR_Info = (PVR_Info *)arg;
1064             gpMfeConfig->FrameRatex100 = pappPVR_Info->FrameRatex100;
1065             gpMfeConfig->nBitrate = pappPVR_Info->nBitrate;
1066             MfeDrvRateControlInit(gpMfeConfig);
1067             ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_RESET_BITRATE = %d, FRAMERATE = %d\n",
1068                 (int)gpMfeConfig->nBitrate, (int)gpMfeConfig->FrameRatex100);
1069         }
1070         break;
1071     case MFE_IOC_CLEAR_BITSBUF:
1072         if (gpMfeConfig != NULL) {
1073             ms_dprintk(DRV_L3, "[IOCTL] MFE_IOC_CLEAR_BITSBUF\n");
1074             MDrv_MFE_clear_bitsbuf(gpMfeConfig, arg);
1075         }
1076         break;
1077     case MFE_IOC_FINISH:
1078         if (gpMfeConfig != NULL) {
1079             ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_FINISH\n");
1080             MDrv_MFE_Finish(gpMfeConfig);
1081             MHAL_MFE_DelRegMap(&gpMfeConfig->mfe_reg,&gpMfeConfig->mfe_reg1);
1082         }
1083         break;
1084     case MFE_IOC_SET_FORCEDI:   // no implement
1085         if (gpMfeConfig != NULL) {
1086             ms_dprintk(DRV_L1, "[IOCTL] MDRV: MFE_IOC_SET_FORCEDI\n");
1087             gpMfeConfig->bForceIframe = TRUE;
1088         }
1089         break;
1090     case MFE_IOC_GET_DROPFLAG:
1091         if (gpMfeConfig != NULL && arg != 0) {
1092             ms_dprintk(DRV_L3, "[IOCTL] MFE_IOC_GET_DROPFLAG = %u\n", (unsigned int)gpMfeConfig->nDropFlag);
1093             *((MS_U32 *)arg) = gpMfeConfig->nDropFlag;
1094         }
1095         break;
1096     case MFE_IOC_GET_SKIPFLAG:
1097         if (gpMfeConfig != NULL && arg != 0) {
1098             ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_GET_SKIPFLAG = %d\n", (int)rc_CheckSkippedFrame(&gpMfeConfig->VTRateCtrl));
1099             *((MS_U32 *)arg) = rc_CheckSkippedFrame(&gpMfeConfig->VTRateCtrl);
1100         }
1101         break;
1102     case MFE_IOC_SET_MIU_OFFSET:
1103         if (gpMfeConfig != NULL) {
1104             ms_dprintk(DRV_L3, "[IOCTL] MFE_IOC_SET_MIU_OFFSET\n");
1105             MDrv_MFE_SetMIUOffset(gpMfeConfig, arg);
1106         }
1107         break;
1108     case MFE_IOC_POWEROFF:
1109         if (arg != 0) {
1110             POWERON_t* tmp_Info;
1111             tmp_Info = (POWERON_t*)arg;
1112             //gpMfeConfig->MFEClk = tmp_Info->clock_level ;
1113             ms_dprintk(DRV_L3, "[IOCTL] MFE_IOC_POWEROFF, clock level= %d\n",tmp_Info->clock_level);
1114             MHal_MFE_PowerOff((MS_U32)tmp_Info->is_off,tmp_Info->clock_level);
1115         }
1116         break;
1117     case MFE_IOC_GET_VOL:
1118         if (gpMfeConfig != NULL && arg != 0) {
1119             ms_dprintk(DRV_L3, "[IOCTL] MFE_IOC_GET_VOL\n");
1120             MDrv_MFE_GetConfigBytes(gpMfeConfig, (void*)arg);
1121         }
1122        break;
1123     case MFE_IOC_GET_SKIPSHORTHEADER:
1124         if (gpMfeConfig != NULL && arg != 0) {
1125             ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_GET_SKIPSHORTHEADER = %d\n", (int)rc_CheckSkippedFrame(&gpMfeConfig->VTRateCtrl));
1126             *((MS_U32 *)arg) = rc_CheckSkippedFrame(&gpMfeConfig->VTRateCtrl);
1127         }
1128         break;
1129     case MFE_IOC_GET_FRAME_TYPE:
1130         if (gpMfeConfig != NULL && arg != 0) {
1131             ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_GET_FRAME_TYPE = %u\n", (unsigned int)gpMfeConfig->vopPredType);
1132             *((MS_U32 *)arg) = gpMfeConfig->vopPredType;
1133         }
1134         break;
1135     case MFE_IOC_SET_RIU_BASE:
1136         if (arg != 0) {
1137             ms_dprintk(DRV_L3, "[IOCTL] MFE_IOC_SET_RIU_BASE 0x%tx\n", (ptrdiff_t)arg);
1138             MDrv_MFE_SetOSRegBase(gpMfeConfig,arg);
1139         }
1140         break;
1141     case MFE_IOC_RESET_SPSPPS:
1142         if (gpMfeConfig != NULL) {
1143             ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_RESET_SPSPPS\n");
1144             if(gpMfeConfig->nCodecType == REG_ENC_MODE_H264)
1145                 GenerateSPSPPS(gpMfeConfig);
1146             else
1147                 ms_dprintk(DRV_L4, "[IOCTL]MFE_IOC_RESET_SPSPPS only support H264.\n");
1148         }
1149         break;
1150     case MFE_IOC_GET_HWCAP:
1151         if (arg != 0) {
1152             MFE_HwCapV0 *mfe_hwcap;
1153             mfe_hwcap = (MFE_HwCapV0 *)arg;
1154             MHal_MFE_GetHWCap( &mfe_hwcap->u16MaxEncodeWidth, &mfe_hwcap->u16MaxEncodeHeight);
1155             ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_GET_HWCAP\n");
1156         }
1157         break;
1158     case MFE_IOC_SET_VUI:
1159         if (gpMfeConfig != NULL && arg != 0) {
1160             ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_SET_VUI\n");
1161 
1162             VUI_Info* vui_info = (VUI_Info *)arg;
1163             gpMfeConfig->setLevel = vui_info->level;
1164             gpMfeConfig->setVUI_aspect_ratio_info_present_flag = vui_info->aspect_ratio_info_present_flag;
1165             gpMfeConfig->setVUI_aspect_ratio_idc = vui_info->aspect_ratio_idc;
1166             gpMfeConfig->setVUI_sar_width = vui_info->sar_width;
1167             gpMfeConfig->setVUI_sar_height = vui_info->sar_height;
1168             gpMfeConfig->ctxH264Info.LevelIDC = gpMfeConfig->setLevel;
1169             GenerateSPSPPS(gpMfeConfig);
1170         }
1171         break;
1172     default:
1173         ms_dprintk(DRV_L4, "[IOCTL] MFE receive non-defined Ioctl\n");
1174         break;
1175     }
1176 
1177     return 0;
1178 }
1179 
1180 
1181