1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
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76 //******************************************************************************
77 //<MStar Software>
78
79
80
81 #include "MFE_chip.h"
82 #include "mfe_type.h"
83 #include "mfe_common.h"
84 #include "ms_dprintf.h"
85 #include "mhal_mfe.h"
86 #ifdef __MOBILE_CASE__
87 #include <stdio.h>
88 #include <string.h>
89 #endif
90
91 #include "parset.h"
92 #include "msRateCtrl.h"
93 #include "BufMng.h"
94
95 #include "mfe_reg.h"
96 // Sync with cModel QExp.h
97 #define CLOCK_GATING // Enable clock gating
98 #define FME_PIPELINE_OPEN // Enable David's FME speedup version
99 #define CHECK_P8x8_BOUND_RECT
100
101 // Memory bound addr units is 8-byte.
102 #define EIGHT_BYTE_ADDR(addr) ((addr) >> 3)
103 #define LO_WORD(val) ((val) & 0xFFFF)
104 #define HI_WORD(val) (((val) >> 16) & 0xFFFF)
105 #define MEM_BOUND_LO(addr) (LO_WORD(EIGHT_BYTE_ADDR(addr)))
106 #define MEM_BOUND_HI(addr) (HI_WORD(EIGHT_BYTE_ADDR(addr)))
107
108 #if defined(_MFE_T8_)
109 #define MAX_REF_FRAME 2UL
110 #define SEARCH_RANGE_X 32UL
111 #define BLOCK_TYPE_4x4 1UL
112 #define BLOCK_TYPE_4x8 1UL
113 #define BLOCK_TYPE_8x4 1UL
114 #elif defined(_MFE_M1_)
115 #define MAX_REF_FRAME 1UL
116 #define SEARCH_RANGE_X 16UL
117 #define BLOCK_TYPE_4x4 0UL
118 #define BLOCK_TYPE_4x8 0UL
119 #define BLOCK_TYPE_8x4 0UL
120 #endif
121
122 #if (DEBUG_LEVEL & DRV_L6)
123 #include "api_mfe_performance.h"
124 extern mfe_performance_t mfe_enc;
125 extern mfe_performance_t mfe_hw_enc;
126 extern mfe_performance_t mfe_duration_enc;
127 #endif
128
129 #ifdef MFE_MIU_PROTECT
130 extern void MHal_MFE_Enable_MIU_Protection(MS_S32 MIU_TEST_MODE,MFE_CONFIG* pConfig);
131 #endif
132 void OutputSwCfg1_H264(MS_S32 nFrmNum, MFE_CONFIG* pConfig);
133
mfeH264_DeInit(MFE_CONFIG * pConfig)134 void mfeH264_DeInit(MFE_CONFIG* pConfig)
135 {
136 MS_S32 i;
137 H264INFO* pInfo = &pConfig->ctxH264Info;
138 FreeSPSPPSBuf(pConfig);
139 if(pInfo->dpb)
140 MfeDrvMemFree((void**)&pInfo->dpb, (const MS_S8*)("pInfo->dpb"));
141
142
143 for(i=0;i<pInfo->BufPool.FrameBufPoolSize;i++) {
144 if(pInfo->BufPool.addr[i])
145 MfeDrvMemFree((void**)&(pInfo->BufPool.addr[i]), (const MS_S8*)("BufPool.addr[i]"));
146 }
147 if(pInfo->BufPool.addr)
148 MfeDrvMemFree((void**)&pInfo->BufPool.addr, (const MS_S8*)("BufPool.addr"));
149 if(pInfo->BufPool.available)
150 MfeDrvMemFree((void**)&pInfo->BufPool.available, (const MS_S8*)("BufPool.available"));
151 IntraUpdateClose(pConfig);
152
153 }
mfeH264_Init(MFE_CONFIG * pConfig)154 void mfeH264_Init(MFE_CONFIG *pConfig)
155 {
156 MS_S32 i;
157 H264INFO* pInfo = &pConfig->ctxH264Info;
158 MS_S32 FrameSizeInMbs = (pConfig->nBufWidth>>4) * (pConfig->nBufHeight>>4);
159
160 memset(pInfo, 0, sizeof(H264INFO));
161
162 if(pConfig->UseCABAC) {
163 pInfo->ProfileIDC = 77; // Baseline
164 pInfo->LevelIDC = 40; // Up to 720x576x25 or 720x480x30
165 } else {
166 pInfo->ProfileIDC = 66; // Baseline
167 pInfo->LevelIDC = 30; // Up to 720x576x25 or 720x480x30
168 if(pConfig->nDispHeight> 576)
169 pInfo->LevelIDC = 31;
170 }
171 pInfo->PicInterlace = (pConfig->bInterlace == PROGRESSIVE)? FRAME_CODING : FIELD_CODING;
172 if (pInfo->PicInterlace==FIELD_CODING) {
173 pInfo->ProfileIDC = 77; // Forced to be main profile
174 MS_ASSERT((pConfig->nBufHeight&0x1F)==0);
175 }
176
177 if (pConfig->setLevel != 0) {
178 pInfo->LevelIDC = pConfig->setLevel;
179 }
180
181 if (pConfig->enableReduceBW) {
182 pInfo->nMaxP8x8Count = FrameSizeInMbs / 2;
183 } else {
184 pInfo->nMaxP8x8Count = FrameSizeInMbs;
185 }
186 pInfo->log2_max_frame_num_minus4 = 1;
187
188 // ME
189 pInfo->num_ref_frames = MAX_REF_FRAME; // sequence-level
190
191 if (pInfo->PicInterlace==FIELD_CODING)
192 pInfo->num_ref_frames = MAX_REF_FRAME -1; // means: 2 field pictures
193 else
194 pInfo->num_ref_frames = MAX_REF_FRAME; // means: 2 frame
195
196 if((pConfig->nBufHeight*pConfig->nBufWidth) >= (1280*720))
197 pInfo->num_ref_frames = 1;
198 #ifdef MFE_MIU_PROFILE
199 pInfo->num_ref_frames = 1;
200 #endif
201 pInfo->iSearchRangeForward = SEARCH_RANGE_X;
202 pInfo->SEARCH_RANGE_Y = 16;
203 pInfo->IME_ADAPTIVE_WINDOW = 1;
204 pInfo->fme_precision = 2; // 0--fullpel, 1--halfpel, 2--quarterpel
205 pInfo->nMaxFmeMode = (FrameSizeInMbs>396) ? 1 : 2;
206 pInfo->no_umv = 0;
207 pInfo->InterSearch[0][0] = 1; // PSKIP
208 pInfo->InterSearch[0][BLOCK16x16] = 1;
209 pInfo->InterSearch[0][BLOCK16x8] = 1;
210 pInfo->InterSearch[0][BLOCK8x16] = 1;
211 pInfo->InterSearch[0][BLOCK8x8] = 1;
212 if (pConfig->enableReduceBW) {
213 pInfo->InterSearch[0][BLOCK8x4] = 0;
214 pInfo->InterSearch[0][BLOCK4x8] = 0;
215 pInfo->InterSearch[0][BLOCK4x4] = 0;
216 } else {
217 pInfo->InterSearch[0][BLOCK8x4] = BLOCK_TYPE_8x4;
218 pInfo->InterSearch[0][BLOCK4x8] = BLOCK_TYPE_4x8;
219 pInfo->InterSearch[0][BLOCK4x4] = BLOCK_TYPE_4x4;
220 }
221 for (i=0; i<=BLOCK4x4; i++)
222 pInfo->InterSearch[1][i] = 0;
223
224 if (pInfo->PicInterlace==FIELD_CODING)
225 pInfo->num_ref_idx_l0_active_minus1 = 2*pInfo->num_ref_frames-1; // PPS info
226 else
227 pInfo->num_ref_idx_l0_active_minus1 = pInfo->num_ref_frames-1; // PPS info
228
229 // DBF
230 pInfo->bDeblockCtrlPresent = 0;
231 pInfo->nDeblockIDC = 2; // 0--all edges; 1--no edges; 2--edges inside slice boundary
232 // NOTE: MFE does not support er_en enabled with DeblockIDC=0
233 pInfo->nDeblockAlpha = 0;
234 pInfo->nDeblockBeta = 0;
235
236 // Frame type
237 pInfo->pic_order_cnt_type = 2; // HW only support 2
238 pInfo->structure = FRAME; // If H264 PAFF, override for each input field in MDrv_MFE_GetDispOrder()
239 pInfo->idr_flag = 1;
240 pInfo->nal_ref_idc = 1;
241 pInfo->frame_num = 0;
242 pInfo->number = 0;
243 pInfo->num_ref_idx_l0_active = 0;
244 pInfo->RefCount = 0; // frame-level 0: 1ref, 1: 2ref
245 pInfo->h264_mcc_offset[0] = pInfo->h264_mcc_offset[1] = 0;
246 pInfo->intQP = 0;
247
248 // Slice header
249 if ((pInfo->PicInterlace==FRAME_CODING) /*&& (pInfo->MbInterlace==FRAME_CODING)*/)
250 {
251 pInfo->pic_order_present_flag = 0;
252 pInfo->delta_pic_order_cnt_bottom = 0;
253 }
254 else
255 {
256 pInfo->pic_order_present_flag = 1;
257 pInfo->delta_pic_order_cnt_bottom = 1;
258 }
259
260 // IEAP
261 pInfo->ieap_last_mode = 8;
262 pInfo->ieap_constraint_intra = 0;
263 pInfo->ieap_ccest_en = !(pInfo->PicInterlace==FIELD_CODING) ? 1 : 0;
264 pInfo->ieap_ccest_thr = pInfo->ieap_ccest_en ? (4-1) : 0;
265 pInfo->ieap_drop_i16 = 0;
266
267 if (pConfig->enableFastMode) {
268 pInfo->ieap_last_mode = 2;
269 pInfo->ieap_drop_i16 = 1;
270 pInfo->fme_precision = 0;
271 }
272
273 // Rate control
274 MfeDrvRateControlInit(pConfig);
275 // FDC header initialization
276 osCreate(&pConfig->m_OutStream);
277
278 osSetWriteBuffer(&pConfig->m_OutStream, pConfig->m_FdcBuffer);
279
280 // Intra-update initialization
281 IntraUpdateInit(pConfig);
282
283 // Prepare SPS, PPS
284 MallocSPSPPSBuf(pConfig);
285 GenerateSPSPPS(pConfig);
286
287 // DPB initialization
288 if (pInfo->PicInterlace==FIELD_CODING)
289 pInfo->dpb_size = pInfo->num_ref_frames + 1;
290 else
291 pInfo->dpb_size = pInfo->num_ref_frames;
292 pInfo->dpb = MfeDrvMemMalloc(sizeof(DPB_ITEM)*pInfo->dpb_size, (const MS_S8*)("dpb"));
293 for (i=0; i<pInfo->dpb_size; i++)
294 pInfo->dpb[i].is_used = 0;
295
296
297 //FrameBufPool initialization
298 pInfo->BufPool.FrameBufPoolSize = pInfo->dpb_size+1;
299 pInfo->BufPool.addr = (MEMMAP_t**)MfeDrvMemMalloc(sizeof(MEMMAP_t*)*(pInfo->BufPool.FrameBufPoolSize), (const MS_S8*)("BufPool.addr"));
300 pInfo->BufPool.available = MfeDrvMemMalloc(sizeof(MS_S32)*pInfo->BufPool.FrameBufPoolSize, (const MS_S8*)("BufPool.available"));
301
302 if (pInfo->BufPool.addr) {
303 for (i = 0; i < pInfo->BufPool.FrameBufPoolSize; i++) {
304 pInfo->BufPool.addr[i] = (MEMMAP_t*)MfeDrvMemMalloc(sizeof(MEMMAP_t) * 2, (const MS_S8*)("BufPool.addr[i]"));
305 }
306 }
307 }
308
309
310 #ifdef DRV_MFE_TIME_MEASURE
311 extern void MFE_MsOS_START_TIMER (void);
312 #endif
313
mfeH264_EncodeFrame(MFE_CONFIG * pConfig,GOPINFO * pGopInfo)314 void mfeH264_EncodeFrame(MFE_CONFIG *pConfig, GOPINFO* pGopInfo)
315 {
316 H264INFO* pInfo = &pConfig->ctxH264Info;
317 BitsInfo* pBitsInfo = &pConfig->ctxBitsInfo;
318 OutStream* pStream = &pConfig->m_OutStream;
319 const MS_U8 gBITMASK[8] = { 0x0, 0x80, 0xc0, 0xe0, 0xf0, 0xf8, 0xfc, 0xfe };
320 // This is done in msAPI_MFE_EnOneFrm()
321 //mfeSetVopType(pConfig, pGopInfo); // Will set pConfig->vopPredType
322 #ifdef SPS_PPS_IN_EACH_I
323 pInfo->idr_flag = pConfig->vopPredType==I_VOP ? 1 : 0;
324 //#elif defined(NO_SPS_PPS)
325 // pInfo->idr_flag = 0;
326 #else
327 /*
328 // Frame type
329 if (pGopInfo->nCodingOrder==0)
330 pInfo->idr_flag = pConfig->vopPredType==I_VOP ? 1 : 0;
331 else
332 pInfo->idr_flag = 0;
333 */
334 pInfo->idr_flag = pConfig->vopPredType==I_VOP ? 1 : 0;
335 #endif
336 pInfo->nal_ref_idc = (get_NALU_1stbyte(pInfo, pConfig->vopPredType)>>5)&0x3;
337 if (pInfo->idr_flag) {
338 //pInfo->number = 0;
339 pInfo->frame_num = 0;
340 }
341 //pInfo->frame_num, pInfo->number
342 if (pInfo->idr_flag)//(pConfig->vopPredType==I_VOP)
343 pInfo->num_ref_idx_l0_active = 0;
344 else {
345 if (pInfo->num_ref_idx_l0_active<pInfo->num_ref_idx_l0_active_minus1+1)
346 pInfo->num_ref_idx_l0_active++;
347 }
348
349 if(pInfo->PicInterlace==FIELD_CODING){
350 if(pInfo->structure==BOTTOM_FIELD){
351 //always set bottom field to override.
352 if (pInfo->num_ref_idx_l0_active==(pInfo->num_ref_idx_l0_active_minus1+1))
353 pInfo->num_ref_idx_l0_active -= 1;
354 }
355 }
356
357 pInfo->RefCount = pConfig->vopPredType==I_VOP ? 0 : pInfo->num_ref_idx_l0_active;
358 pInfo->h264_mcc_offset[0] = pInfo->h264_mcc_offset[1] = 0; // If PAFF, will possibly override in h264GetBufferAddr()
359
360 if(pConfig->VTMode) {
361 MS_S8 chFrameType;
362 if(pConfig->vopPredType==I_VOP)
363 chFrameType = 'I';
364 else
365 chFrameType = 'P';
366 pInfo->intQP = rc_InitFrame(&pConfig->VTRateCtrl, chFrameType);
367 }
368 else
369 pInfo->intQP = cvbr_InitFrame(&pConfig->ctxRateControl, pConfig->vopPredType, pInfo->structure);
370
371 // Buffer management
372 h264GetBufferAddr(pConfig);
373
374 // Prepare header
375 osReset(pStream);
376 #if 0//ndef _MFE_M1_
377 // SPS, PPS
378 if (pGopInfo->nCodingOrder==0||pInfo->idr_flag) {
379 codeSPSPPS(pConfig,pStream);
380 }
381 #endif
382 // First slice header
383 codeSliceHeader(pConfig, pStream);
384 // Finalize
385 osFlushAll(pStream);
386 pBitsInfo->ptr = pStream->m_pbFrameBuffer;
387 pBitsInfo->len = pStream->m_nByteCount;
388 if ((pStream->BC_nCumulativeBits&7)==0) {
389 pBitsInfo->bit_len = 0;
390 pBitsInfo->bits = 0;
391 }
392 else {
393 pBitsInfo->len--;
394 pBitsInfo->bit_len = pStream->BC_nCumulativeBits&7;
395 pBitsInfo->bits = pStream->m_pbFrameBuffer[pStream->BC_nCumulativeBits>>3] & gBITMASK[pBitsInfo->bit_len];
396 }
397
398
399
400
401 //MODE 0: (Checking range > real range ) reg_mfe_s_marb_miu_bound_err = 0
402 //MODE 1: (Checking range < real range ) reg_mfe_s_marb_miu_bound_err = 1
403 //#define TEST_MIU_PROTECTION_MODE 0UL
404 #ifdef MFE_MIU_PROTECT
405 MHal_MFE_Enable_MIU_Protection(TEST_MIU_PROTECTION_MODE,pConfig);
406 #endif
407 /*
408 { // DEBUG codes
409 MS_S32 i;
410 ms_dprintk(DRV_L3,"FDC bitcount %d ==> "), pBitsInfo->len*8+pBitsInfo->bit_len);
411 for (i=0; i<pBitsInfo->len; i++) {
412 ms_dprintk(DRV_L3,"%02x "), pBitsInfo->ptr[i]);
413 }
414 ms_dprintk(DRV_L3,"%02x(msb %d bits)\n"), pBitsInfo->bits, pBitsInfo->bit_len);
415 }
416 */
417 #if (DEBUG_LEVEL & DRV_L6)
418 mfe_enc.mfe_starttime = MsOS_GetSystemTime();
419 #endif
420 // Set reg and start encoding
421 // DumpAllReg(mfe_reg);
422 OutputSwCfg1_H264(pGopInfo->nCodingOrder, pConfig);
423
424 // printf("DumpAllReg After delay OutputSwCfg1_H264\n"));
425 // DumpAllReg(mfe_reg);
426
427
428 }
429
mfeH264_EncodeDummyFrame(MFE_CONFIG * pConfig,GOPINFO * pGopInfo)430 void mfeH264_EncodeDummyFrame(MFE_CONFIG *pConfig, GOPINFO* pGopInfo)
431 {
432 H264INFO* pInfo = &pConfig->ctxH264Info;
433 BitsInfo* pBitsInfo = &pConfig->ctxBitsInfo;
434 OutStream* pStream = &pConfig->m_OutStream;
435 const MS_U8 gBITMASK[8] = { 0x0, 0x80, 0xc0, 0xe0, 0xf0, 0xf8, 0xfc, 0xfe };
436
437 pInfo->RefCount = pInfo->num_ref_idx_l0_active; // frame-level 0: 1ref, 1: 2ref
438 pInfo->h264_mcc_offset[0] = pInfo->h264_mcc_offset[1] = 0;
439
440 // Prepare header
441 osReset(pStream);
442 // First slice header
443 codeDummySliceHeader(pConfig, pStream);
444 // Finalize
445 osFlushAll(pStream);
446 pBitsInfo->ptr = pStream->m_pbFrameBuffer;
447 pBitsInfo->len = pStream->m_nByteCount;
448 if ((pStream->BC_nCumulativeBits&7)==0) {
449 pBitsInfo->bit_len = 0;
450 pBitsInfo->bits = 0;
451 }
452 else {
453 pBitsInfo->len--;
454 pBitsInfo->bit_len = pStream->BC_nCumulativeBits&7;
455 pBitsInfo->bits = pStream->m_pbFrameBuffer[pStream->BC_nCumulativeBits>>3] & gBITMASK[pBitsInfo->bit_len];
456 }
457 }
458
mfeH264_UpdateFrame(MFE_CONFIG * pConfig)459 void mfeH264_UpdateFrame(MFE_CONFIG *pConfig)
460 {
461 H264INFO* pInfo = &pConfig->ctxH264Info;
462 MS_S32 max_frame_num = 1 << (pInfo->log2_max_frame_num_minus4 + 4);
463 //if (pConfig->vopPredType==I_VOP)
464 // IntraUpdateInit(pConfig);
465 IntraUpdateFrame(pConfig);
466
467 // Rate control
468 MfeDrvRateControlUpdate(pConfig, pInfo->structure);
469
470 h264DpbHandling(pConfig);
471
472 if (pInfo->structure!=TOP_FIELD)
473 {
474 pInfo->frame_num++;
475 pInfo->frame_num %= max_frame_num;
476 }
477 pInfo->number++;
478 //pInfo->number++;
479
480 // If PAFF, always assume top-field first.
481 // A trick here: restore to top type for correct mfeSetVopType()
482 if (pInfo->structure==BOTTOM_FIELD)
483 pConfig->vopPredType = pInfo->vopPredType_FirstField;
484
485 }
486
OutputSwCfg1_H264(MS_S32 nFrmNum,MFE_CONFIG * pConfig)487 void OutputSwCfg1_H264(MS_S32 nFrmNum, MFE_CONFIG* pConfig)
488 {
489 MS_S32 nTarWriteCount;
490 MS_S32 nRegWriteCount;
491 MS_S32 nTarFDCCount;
492 MS_S32 nRegFDCCount;
493
494 H264INFO* pInfo = &pConfig->ctxH264Info;
495 BufInfo* pBufInfo = &pConfig->ctxBufInfo;
496 BitsInfo *pBitsInfo = &pConfig->ctxBitsInfo;
497 CVBRRateControl* rcCtx = &pConfig->ctxRateControl;
498 MFE_REG* mfe_reg = &pConfig->mfe_reg;
499 #if defined(_MFE_MUJI_) || defined(_MFE_MONET_) || defined(_MFE_MESSI_) || defined(_MFE_MANHATTAN_) || defined(_MFE_MASERATI_) || defined(_MFE_MAXIM_) || defined(_MFE_KANO_) || defined(_MFE_K6_)
500 MFE_REG1* mfe_reg1 = &pConfig->mfe_reg1;
501 #endif
502 void* pContext = (void*)pBitsInfo;
503
504 //////////////////////////////////////////////////////////////////////////
505 // Sequence-wide settings
506
507 if (nFrmNum==0) {
508 memset(mfe_reg, 0, sizeof(MFE_REG)); // Initial
509 mfe_reg->reg_mfe_g_enc_mode = REG_ENC_MODE_H264;
510 mfe_reg->reg_mfe_g_pic_width = pConfig->nBufWidth;
511 mfe_reg->reg_mfe_g_pic_height = (pInfo->PicInterlace==FIELD_CODING) ? (pConfig->nBufHeight>>1) : pConfig->nBufHeight;
512
513 // Qtable
514 mfe_reg->reg_mfe_g_qmode = 0;
515 #if defined(_MFE_M1_)||defined(_MFE_AGATE_)
516 if(0) {
517 mfe_reg->reg_mfe_g_mb_pitch_en = 1;
518 //pirch for x-axle
519 mfe_reg->reg_mfe_g_mb_pitch = 0;//g_nMBPitch;//mfe_reg.reg_mfe_g_pic_width;
520 }
521 else {
522 mfe_reg->reg_mfe_g_mb_pitch_en = 0;
523 //pirch for x-axle
524 mfe_reg->reg_mfe_g_mb_pitch = mfe_reg->reg_mfe_g_pic_width/16;
525 }
526 #endif
527 //Field Coding
528 if (pInfo->PicInterlace==FIELD_CODING) {
529 mfe_reg->reg_mfe_g_fldpic_en = 1;
530 #if defined(_MFE_AGATE_)
531 mfe_reg->reg_mfe_g_mstar_tile_field_split = (pConfig->bInterlace ==INTERLACE_SPLITED)? 1:0 ;
532 mfe_reg->reg_mfe_g_fldpic_idx = 0; //top
533 #endif
534 }
535 #if defined(_MFE_MUJI_) || defined(_MFE_MONET_) || defined(_MFE_MESSI_) || defined(_MFE_MANHATTAN_) || defined(_MFE_MASERATI_) || defined(_MFE_MAXIM_) || defined(_MFE_KANO_) || defined(_MFE_K6_)
536 //Entropy coding mode
537 if(pConfig->UseCABAC==1)
538 mfe_reg->reg_mfe_g_cabac_en = 1;
539 else
540 mfe_reg->reg_mfe_g_cabac_en = 0;
541 #endif
542 #if defined(_MFE_AGATE_)
543 if(pConfig->bColorFormat != YUVTILE)
544 mfe_reg->reg_mfe_g_mstar_tile = 1;
545 else
546 mfe_reg->reg_mfe_g_mstar_tile = 0;
547 #endif
548
549 // ME partition type
550 mfe_reg->reg_mfe_s_me_16x16_disable = !pInfo->InterSearch[0][BLOCK16x16];
551 mfe_reg->reg_mfe_s_me_8x8_disable = !pInfo->InterSearch[0][BLOCK8x8];
552 mfe_reg->reg_mfe_s_me_16x8_disable = !pInfo->InterSearch[0][BLOCK16x8];
553 mfe_reg->reg_mfe_s_me_8x16_disable = !pInfo->InterSearch[0][BLOCK8x16];
554 mfe_reg->reg_mfe_s_me_8x4_disable = !pInfo->InterSearch[0][BLOCK8x4];
555 mfe_reg->reg_mfe_s_me_4x8_disable = !pInfo->InterSearch[0][BLOCK4x8];
556 mfe_reg->reg_mfe_s_me_4x4_disable = !pInfo->InterSearch[0][BLOCK4x4];
557
558 // MDC
559 mfe_reg->reg_mfe_s_mbr_qp_cidx_offset = 0;//active_pps->chroma_qp_index_offset;
560 #if defined(_MFE_M1_)||defined(_MFE_AGATE_)
561 // pre-fetch
562 mfe_reg->reg_mfe_s_prfh_cryc_en = 1;
563 mfe_reg->reg_mfe_s_prfh_refy_en = 1;
564 mfe_reg->reg_mfe_s_prfh_cryc_idle_cnt = 0;
565 mfe_reg->reg_mfe_s_prfh_refy_idle_cnt = 0;
566 #ifdef SW_BUF_MODE
567 mfe_reg->reg_mfe_g_sw_buffer_mode = 1;
568 #else
569 mfe_reg->reg_mfe_g_sw_buffer_mode = 0;
570 #endif
571
572 mfe_reg->reg_mfe_g_jpe_buffer_mode = 1; // frame-mode
573 mfe_reg->reg_mfe_g_jpe_fsvs_mode = 0;
574 #endif
575 }
576 else {
577 mfe_reg->reg_mfe_g_frame_start_sw = 0;
578 #if defined(_MFE_AGATE_)
579 mfe_reg->reg_mfe_g_fldpic_idx = ~mfe_reg->reg_mfe_g_fldpic_idx; //change top and bottom.
580 #endif
581 }
582
583 #if defined(_MFE_MUJI_) || defined(_MFE_MONET_) || defined(_MFE_MESSI_) || defined(_MFE_MANHATTAN_) || defined(_MFE_MASERATI_) || defined(_MFE_MAXIM_) || defined(_MFE_KANO_) || defined(_MFE_K6_)
584 mfe_reg1->reg_mfe_g_jpd_hsk_en = 0;
585 if(pConfig->g_nUseYUV422 != 0) {
586 mfe_reg1->reg_mfe_s_packed422_en = 1;
587 }
588 else {
589 mfe_reg1->reg_mfe_s_packed422_en = 0;
590 }
591
592 if(pConfig->g_nUseYUV422 == 1){
593 mfe_reg1->reg_mfe_s_packed422_uv_swap = 0;
594 mfe_reg1->reg_mfe_s_packed422_yc_swap = 0;
595 }
596 else if(pConfig->g_nUseYUV422 == 2) {
597 mfe_reg1->reg_mfe_s_packed422_uv_swap = 1;
598 mfe_reg1->reg_mfe_s_packed422_yc_swap = 0;
599 }
600 else if(pConfig->g_nUseYUV422 == 3) {
601 mfe_reg1->reg_mfe_s_packed422_uv_swap = 0;
602 mfe_reg1->reg_mfe_s_packed422_yc_swap = 1;
603 }
604 else if(pConfig->g_nUseYUV422 == 4) {
605 mfe_reg1->reg_mfe_s_packed422_uv_swap = 1;
606 mfe_reg1->reg_mfe_s_packed422_yc_swap = 1;
607 }
608 #endif
609
610 #if defined(MFE_YUV_LOADER)
611 mfe_reg1->reg0b = 0;
612 mfe_reg1->reg56 = 0;
613
614 if (YUVTILE != pConfig->bColorFormat) {
615 mfe_reg1->reg_mfe_g_yuvldr_en = 1;
616 if (MFE_EVDTILE == pConfig->bColorFormat) {
617 mfe_reg1->reg_mfe_g_hevd_tile = 1;
618 }
619 else if (MFE_32x32TILE == pConfig->bColorFormat) {
620 mfe_reg1->reg_mfe_g_hevd_tile32 = 1;
621 }
622 else if (MFE_NV12 == pConfig->bColorFormat) {
623 mfe_reg1->reg_mfe_g_yuv420_semi = 1;
624 }
625 else if (MFE_NV21 == pConfig->bColorFormat) {
626 mfe_reg1->reg_mfe_g_yuv420_semi = 1;
627 mfe_reg1->reg_mfe_g_yuv420_semi_uv_swap = 1;
628 }
629 else if (pConfig->g_nUseYUV422 != 0) {
630 mfe_reg1->reg_mfe_g_mb_pitch = pConfig->nBufWidth / 16;
631 }
632 }
633 #endif
634
635 //////////////////////////////////////////////////////////////////////////
636 // Frame-wide settings
637 #ifdef CLOCK_GATING
638 mfe_reg->reg16 = 0xffff; // clock gating
639 #endif
640 ms_dprintk(DRV_L3," RecY:0x%x, RecC:0x%x\n", (unsigned int)pBufInfo->m_nRecYAddr.miuAddress, (unsigned int)pBufInfo->m_nRecCAddr.miuAddress);
641 ms_dprintk(DRV_L3,"[0]RefY:0x%x, RefC:0x%x\n", (unsigned int)pBufInfo->m_nRefYAddr[0].miuAddress, (unsigned int)pBufInfo->m_nRefCAddr[0].miuAddress);
642 if(pInfo->num_ref_frames==2)
643 ms_dprintk(DRV_L3,"[1]RefY:0x%x, RefC:0x%x\n", (unsigned int)pBufInfo->m_nRefYAddr[1].miuAddress, (unsigned int)pBufInfo->m_nRefCAddr[1].miuAddress);
644
645 if(pConfig->g_nUseYUV422 != 0) {
646 #if defined(_MFE_MUJI_) || defined(_MFE_MONET_) || defined(_MFE_MESSI_) || defined(_MFE_MANHATTAN_) || defined(_MFE_MASERATI_) || defined(_MFE_MAXIM_) || defined(_MFE_KANO_) || defined(_MFE_K6_)
647 MS_ASSERT((pBufInfo->m_nCurYAddr.miuAddress&0xF)==0);
648 mfe_reg1->reg_mfe_g_enc_cury_offset = 0;
649 mfe_reg1->reg_mfe_g_enc_cury_adr_low = (MS_U16)((pBufInfo->m_nCurYAddr.miuAddress>>3)& 0x1FFF); //13bit
650 mfe_reg1->reg_mfe_g_enc_cury_adr_high = (MS_U16)(pBufInfo->m_nCurYAddr.miuAddress >> (13+3));
651 #else
652 MS_ASSERT(0); // 422 mode didnot supported at old chip.
653 #endif
654 } else {
655 // Input buffer address: Must be 256-byte aligned.
656 MS_ASSERT((pBufInfo->m_nCurYAddr.miuAddress&0xFF)==0);
657 MS_ASSERT((pBufInfo->m_nCurCAddr.miuAddress&0xFF)==0);
658 mfe_reg->reg_mfe_g_cur_y_adr_low = (MS_U16)((pBufInfo->m_nCurYAddr.miuAddress>>8)&0xFFFF);
659 mfe_reg->reg_mfe_g_cur_y_adr_high = (MS_U16)(pBufInfo->m_nCurYAddr.miuAddress>>(8+16));
660 mfe_reg->reg_mfe_g_cur_c_adr_low = (MS_U16)((pBufInfo->m_nCurCAddr.miuAddress>>8)&0xFFFF);
661 mfe_reg->reg_mfe_g_cur_c_adr_high = (MS_U16)(pBufInfo->m_nCurCAddr.miuAddress>>(8+16));
662 }
663 MS_ASSERT((pBufInfo->m_nRefYAddr[0].miuAddress&0xFF)==0);
664 MS_ASSERT((pBufInfo->m_nRefCAddr[0].miuAddress&0xFF)==0);
665 #ifndef _MFE_M1_
666 MS_ASSERT((pBufInfo->m_nRefYAddr[1].miuAddress&0xFF)==0);
667 MS_ASSERT((pBufInfo->m_nRefCAddr[1].miuAddress&0xFF)==0);
668 #endif
669 if(!pConfig->SecurityMode) {
670 MS_ASSERT((pBufInfo->m_nOutBufAddr[pConfig->nOBufIndex].miuAddress&0x7)==0);
671 }
672
673 mfe_reg->reg_mfe_g_ref_y_adr0_low = (MS_U16)((pBufInfo->m_nRefYAddr[0].miuAddress>>8)&0xFFFF);
674 mfe_reg->reg_mfe_g_ref_y_adr0_high = (MS_U16)(pBufInfo->m_nRefYAddr[0].miuAddress>>(8+16));
675 #ifndef _MFE_M1_
676 mfe_reg->reg_mfe_g_ref_y_adr1_low = (MS_U16)((pBufInfo->m_nRefYAddr[1].miuAddress>>8)&0xFFFF);
677 mfe_reg->reg_mfe_g_ref_y_adr1_high = (MS_U16)(pBufInfo->m_nRefYAddr[1].miuAddress>>(8+16));
678 #endif
679 mfe_reg->reg_mfe_g_ref_c_adr0_low = (MS_U16)((pBufInfo->m_nRefCAddr[0].miuAddress>>8)&0xFFFF);
680 mfe_reg->reg_mfe_g_ref_c_adr0_high = (MS_U16)(pBufInfo->m_nRefCAddr[0].miuAddress>>(8+16));
681 #ifndef _MFE_M1_
682 mfe_reg->reg_mfe_g_ref_c_adr1_low = (MS_U16)((pBufInfo->m_nRefCAddr[1].miuAddress>>8)&0xFFFF);
683 mfe_reg->reg_mfe_g_ref_c_adr1_high = (MS_U16)(pBufInfo->m_nRefCAddr[1].miuAddress>>(8+16));
684 #endif
685
686 mfe_reg->reg_mfe_g_rec_y_adr_low = (MS_U16)((pBufInfo->m_nRecYAddr.miuAddress>>8)&0xFFFF);
687 mfe_reg->reg_mfe_g_rec_y_adr_high = (MS_U16)(pBufInfo->m_nRecYAddr.miuAddress>>(8+16));
688 mfe_reg->reg_mfe_g_rec_c_adr_low = (MS_U16)((pBufInfo->m_nRecCAddr.miuAddress>>8)&0xFFFF);
689 mfe_reg->reg_mfe_g_rec_c_adr_high = (MS_U16)(pBufInfo->m_nRecCAddr.miuAddress>>(8+16));
690
691 ms_dprintk(DRV_L3, "field = %d, Rec = 0x%x, Ref0 = 0x%x, Ref1 = 0x%x\n",
692 pInfo->structure, (unsigned int)pBufInfo->m_nRecYAddr.miuAddress,
693 (unsigned int)pBufInfo->m_nRefCAddr[0].miuAddress, (unsigned int)pBufInfo->m_nRefCAddr[1].miuAddress);
694
695 // Output buffers: Must be 8-byte aligned.
696 #if defined(_MFE_M1_)||defined(_MFE_AGATE_)
697 mfe_reg->reg_mfe_s_bspobuf_hw_en = 0;
698 #if defined(USE_HW_DBL_OBUF)
699 mfe_reg->reg_mfe_s_bspobuf_hw_en = 1;
700 #endif
701 #else
702 mfe_reg->reg_mfe_s_bspobuf_sadr_low = (MS_U16)((pBufInfo->m_nOutBufAddr[pConfig->nOBufIndex].miuAddress>>3)&0xFFFF);
703 mfe_reg->reg_mfe_s_bspobuf_sadr_high = (MS_U16)(pBufInfo->m_nOutBufAddr[pConfig->nOBufIndex].miuAddress>>(3+16));
704 mfe_reg->reg_mfe_s_bspobuf_eadr_low = (MS_U16)(((pBufInfo->m_nOutBufAddr[pConfig->nOBufIndex].miuAddress+pBufInfo->m_OutBufferSize-8)>>3)&0xFFFF);
705 mfe_reg->reg_mfe_s_bspobuf_eadr_high = (MS_U16)((pBufInfo->m_nOutBufAddr[pConfig->nOBufIndex].miuAddress+pBufInfo->m_OutBufferSize-8)>>(3+16));
706 #endif
707
708 // GN
709 mfe_reg->reg_mfe_s_gn_sadr_low = (MS_U16)((pBufInfo->m_nGNAddr.miuAddress>>3)&0xFFFF);
710 mfe_reg->reg_mfe_s_gn_sadr_high = (MS_U16)(pBufInfo->m_nGNAddr.miuAddress>>(3+16));
711 #ifdef _MFE_M1_
712 mfe_reg->reg_mfe_s_gn_sadr_mode =
713 #if defined(GN_WHOLE_FRAME)
714 1;
715 #else
716 0;
717 #endif
718
719 // IMI buffer
720 mfe_reg->reg_mfe_s_marb_eimi_block = 0;
721 mfe_reg->reg_mfe_s_marb_lbwd_mode = 0;
722 mfe_reg->reg_mfe_s_marb_imi_sadr_low = 0;
723 mfe_reg->reg_mfe_s_marb_imi_sadr_high = 0;
724
725 if (pConfig->vopPredType!=I_VOP && pConfig->MfeAdvInfo.low_bandwidth_en && pConfig->imi_size>0) {
726 mfe_reg->reg_mfe_s_marb_eimi_block = 1;
727 mfe_reg->reg_mfe_s_marb_lbwd_mode = 1;
728 mfe_reg->reg_mfe_s_marb_imi_sadr_low = (pConfig->imi_addr>>3)&0xFFFF;
729 mfe_reg->reg_mfe_s_marb_imi_sadr_high = pConfig->imi_addr>>(3+16);
730 switch (pConfig->imi_size) {
731 // 0: 64kB, 1:32kB, 2:16kB, 3:8kB
732 case 0x10000:
733 mfe_reg->reg_mfe_s_marb_imi_cache_size = 0;
734 break;
735 case 0x8000:
736 mfe_reg->reg_mfe_s_marb_imi_cache_size = 1;
737 break;
738 case 0x4000:
739 mfe_reg->reg_mfe_s_marb_imi_cache_size = 2;
740 break;
741 case 0x2000:
742 mfe_reg->reg_mfe_s_marb_imi_cache_size = 3;
743 break;
744 default:
745 mfe_reg->reg_mfe_s_marb_imi_cache_size = 0;
746 MS_ASSERT(0);
747 }
748 }
749
750 #endif
751
752 #if defined(MFE_DBF_PACKED_MODE)
753 mfe_reg->reg_mfe_s_gn_bwr_mode |= 0x2;
754 #endif
755
756 mfe_reg->reg_mfe_g_frame_type = pConfig->vopPredType==I_VOP?0:(pConfig->vopPredType==P_VOP?1:2);
757
758 mfe_reg->reg_mfe_g_ref_no = pInfo->RefCount==2 ? 1 : 0;
759 /*
760 if(pInfo->PicInterlace==FIELD_CODING){
761 if(pInfo->structure==BOTTOM_FIELD){
762 mfe_reg->reg_mfe_g_ref_no = 0;
763 }
764 }
765 */
766 // ME setting
767 mfe_reg->reg_mfe_s_ime_mesr_max_addr = (pInfo->SEARCH_RANGE_Y==16 ? 95 : /*83*/85);//0x5f;
768 mfe_reg->reg_mfe_s_ime_mesr_min_addr =(pInfo->SEARCH_RANGE_Y==16 ? 0 : /*16*/10);//0;
769
770 #if defined(MFE_SUPPORT_720P)
771 // If force encoding frame size bigger than 720p on 720p/30fps chip,
772 // reduce ime search range to improve encoding speed.
773 if (pConfig->nBufWidth * pConfig->nBufHeight > 1280 * 736)
774 {
775 mfe_reg->reg_mfe_s_ime_mvx_min = 0x10;
776 mfe_reg->reg_mfe_s_ime_mvx_max = 0x2e;
777 }
778 else
779 #endif
780 {
781 mfe_reg->reg_mfe_s_ime_mvx_min = -(pInfo->iSearchRangeForward) + 32; // Min X is -pVopMd->iSearchRangeForward
782 mfe_reg->reg_mfe_s_ime_mvx_max = (pInfo->iSearchRangeForward-2) + 32; // Max X is pVopMd->iSearchRangeForward-1
783 }
784
785 mfe_reg->reg_mfe_s_ime_mvy_min = -pInfo->SEARCH_RANGE_Y + 16; // Min Y
786 mfe_reg->reg_mfe_s_ime_mvy_max = (pInfo->SEARCH_RANGE_Y==16 ? 15 : 8) + 16; // Max Y
787 mfe_reg->reg_mfe_s_ime_sr16 = (mfe_reg->reg_mfe_s_ime_mvx_min>=16 ? 1 : 0);
788 mfe_reg->reg_mfe_s_ime_umv_disable = pInfo->no_umv;
789
790 mfe_reg->reg_mfe_s_ime_ime_wait_fme = 1;
791 #ifdef FME_PIPELINE_OPEN
792 mfe_reg->reg_mfe_s_fme_pipeline_on = mfe_reg->reg_mfe_s_ime_ime_wait_fme ? 1 : 0;
793 #else
794 mfe_reg->reg_mfe_s_fme_pipeline_on = 0x0;
795 #endif
796
797 #ifdef CHECK_P8x8_BOUND_RECT
798 mfe_reg->reg_mfe_s_ime_boundrect_en = (pInfo->ProfileIDC==66 && pInfo->LevelIDC<=30) ? 1 : 0;
799 #endif
800 mfe_reg->reg_mfe_s_ime_h264_p8x8_ctrl_en = pInfo->nMaxP8x8Count<(mfe_reg->reg_mfe_g_pic_width>>4)*(mfe_reg->reg_mfe_g_pic_height>>4) ? 1 : 0;
801 if (mfe_reg->reg_mfe_s_ime_h264_p8x8_ctrl_en)
802 mfe_reg->reg_mfe_s_ime_h264_p8x8_max = pInfo->nMaxP8x8Count>>4;
803 mfe_reg->reg_mfe_s_mesr_adapt = pInfo->IME_ADAPTIVE_WINDOW?1:0;
804 mfe_reg->reg_mfe_s_me_ref_en_mode = pInfo->RefCount==2 ? 0x3 : (pInfo->RefCount==1 ? 0x1 : 0);
805
806 mfe_reg->reg_mfe_s_fme_quarter_disable = (pInfo->fme_precision!=2);
807 mfe_reg->reg_mfe_s_fme_half_disable = (pInfo->fme_precision==0);
808 //mfe_reg->reg_mfe_s_fme_one_mode = 1;
809 mfe_reg->reg_mfe_s_fme_pmv_enable = (/*(PSKIP_PREFERRED==3) &&*/ pInfo->InterSearch[0][0]);
810 mfe_reg->reg_mfe_s_fme_mode_no = pInfo->nMaxFmeMode-1;
811
812 mfe_reg->reg_mfe_s_fme_mode0_refno = 1;
813 mfe_reg->reg_mfe_s_fme_mode1_refno = 1;
814 mfe_reg->reg_mfe_s_fme_mode2_refno = 1;
815 /*
816 if(pInfo->PicInterlace==FIELD_CODING){
817 if(pInfo->structure==BOTTOM_FIELD){
818 mfe_reg->reg_mfe_s_fme_mode0_refno = 0;
819 mfe_reg->reg_mfe_s_fme_mode1_refno = 0;
820 mfe_reg->reg_mfe_s_fme_mode2_refno = 0;
821 }
822 }
823 */
824 // Intra update
825 mfe_reg->reg_mfe_s_txip_irfsh_en = 0;
826
827 if(mfe_reg->reg_mfe_s_txip_irfsh_en)
828 {
829 MS_S32 i;
830 MS_S32 count, prv_intra;
831 MS_S32 start[2], end[2];
832 IntraUpdateContext* ctx = &pConfig->m_IUContext;
833
834 count = 0;
835 prv_intra = 0;
836 for (i=0; i<ctx->nTotalMb; i++) {
837 if (ctx->pHwMbMap[i].intra) {
838 if (prv_intra==0) {
839 count++;
840 if (count>2) {
841 MS_ASSERT(0);
842 }
843 start[count-1] = end[count-1] = i;
844 }
845 else
846 end[count-1] = i;
847 }
848 prv_intra = ctx->pHwMbMap[i].intra;
849 }
850 if (count>0) {
851 mfe_reg->reg_mfe_s_txip_irfsh_en |= 1;
852 mfe_reg->reg_mfe_s_txip_irfsh_mb_s0 = start[0];
853 mfe_reg->reg_mfe_s_txip_irfsh_mb_e0 = end[0];
854 }
855 if (count>1) {
856 mfe_reg->reg_mfe_s_txip_irfsh_en |= 2;
857 mfe_reg->reg_mfe_s_txip_irfsh_mb_s1 = start[1];
858 mfe_reg->reg_mfe_s_txip_irfsh_mb_e1 = end[1];
859 }
860 }
861
862 mfe_reg->reg_mfe_s_mdc_h264_nal_ref_idc = pInfo->nal_ref_idc;
863 mfe_reg->reg_mfe_s_mdc_h264_nal_unit_type = pInfo->idr_flag ? 1 : 0;
864 mfe_reg->reg_mfe_s_mdc_h264_fnum_bits = pInfo->log2_max_frame_num_minus4+4-5;
865 mfe_reg->reg_mfe_s_mdc_h264_dbf_control = pInfo->bDeblockCtrlPresent;
866 mfe_reg->reg_mfe_s_mdc_h264_fnum_value = pInfo->frame_num;//img->frame_num;
867 mfe_reg->reg_mfe_s_mdc_h264_idr_pic_id = (pInfo->number/*img->number*/ % 2);
868 mfe_reg->reg_mfe_s_mdc_h264_disable_dbf_idc = pInfo->nDeblockIDC;//img->LFDisableIdc==1?1:2;
869 mfe_reg->reg_mfe_s_mdc_h264_alpha = pInfo->nDeblockAlpha;//img->LFAlphaC0Offset/2;
870 mfe_reg->reg_mfe_s_mdc_h264_beta = pInfo->nDeblockBeta;//img->LFBetaOffset/2;
871 mfe_reg->reg_mfe_s_mdc_h264_ridx_aor_flag = ((pInfo->num_ref_idx_l0_active != (pInfo->num_ref_idx_l0_active_minus1 +1)) ? 1 : 0);
872
873 mfe_reg->reg_mfe_s_quan_idx_last = 63;
874 if (mfe_reg->reg_mfe_s_quan_idx_last<63)
875 mfe_reg->reg_mfe_s_quan_idx_swlast = 1;
876 else
877 mfe_reg->reg_mfe_s_quan_idx_swlast = 0;
878
879 // MBR
880 mfe_reg->reg_mfe_g_mbr_en = rcCtx->m_rcGranularity==MBLEVELRC ? 1 : 0;
881 mfe_reg->reg_mfe_s_mbr_pqp_dlimit = LEFT_QP_DIFF_LIMIT;
882 mfe_reg->reg_mfe_s_mbr_uqp_dlimit = TOP_QP_DIFF_LIMIT;
883
884 // er_en
885 if (rcCtx->m_nVPMbRow>0 && rcCtx->m_nVPSize<=0)
886 mfe_reg->reg_mfe_g_er_mode = 0;
887 else if (rcCtx->m_nVPMbRow<=0 && rcCtx->m_nVPSize>0)
888 mfe_reg->reg_mfe_g_er_mode = 1;
889 else if (rcCtx->m_nVPMbRow>0 && rcCtx->m_nVPSize>0)
890 mfe_reg->reg_mfe_g_er_mode = 2;
891 else
892 mfe_reg->reg_mfe_g_er_mode = 3;
893 if (rcCtx->m_nVPMbRow==0 || rcCtx->m_nVPMbRow==1)
894 mfe_reg->reg_mfe_g_er_mby = 0;
895 else if (rcCtx->m_nVPMbRow==2)
896 mfe_reg->reg_mfe_g_er_mby = 1;
897 else if (rcCtx->m_nVPMbRow==4)
898 mfe_reg->reg_mfe_g_er_mby = 2;
899 else if (rcCtx->m_nVPMbRow==8)
900 mfe_reg->reg_mfe_g_er_mby = 3;
901 else if (rcCtx->m_nVPMbRow>0) {
902 MS_ASSERT(0);
903 }
904 if (mfe_reg->reg_mfe_g_er_mode==1 || mfe_reg->reg_mfe_g_er_mode==2)
905 mfe_reg->reg_mfe_g_er_bs_th = rcCtx->m_nVPSize;
906 mfe_reg->reg_mfe_g_qscale = pInfo->intQP;
907 mfe_reg->reg_mfe_s_mbr_frame_qstep = rcCtx->m_nFrameQStep;
908 mfe_reg->reg_mfe_s_mbr_tmb_bits = rcCtx->m_nTargetMbBits;
909 // QP/QStep: Min, max
910 mfe_reg->reg_mfe_s_mbr_qp_min = rcCtx->m_nMinQP;
911 mfe_reg->reg_mfe_s_mbr_qp_max = rcCtx->m_nMaxQP;
912 MS_ASSERT(rcCtx->m_nMinQStep<(2<<7));
913 mfe_reg->reg_mfe_s_mbr_qstep_min = rcCtx->m_nMinQStep;
914 mfe_reg->reg_mfe_s_mbr_qstep_max = rcCtx->m_nMaxQStep;
915
916 mfe_reg->reg_mfe_g_rec_en = 1;
917
918 // IEAP
919 mfe_reg->reg_mfe_s_ieap_last_mode = pInfo->ieap_last_mode;
920 mfe_reg->reg_mfe_s_ieap_constraint_intra = pInfo->ieap_constraint_intra;
921 mfe_reg->reg_mfe_s_ieap_ccest_en = pInfo->ieap_ccest_en;
922 mfe_reg->reg_mfe_s_ieap_ccest_thr = pInfo->ieap_ccest_thr;
923 mfe_reg->reg_mfe_s_ieap_drop_i16 = pInfo->ieap_drop_i16;
924 #if defined(_MFE_MUJI_) || defined(_MFE_MONET_) || defined(_MFE_MESSI_) || defined(_MFE_MANHATTAN_) || defined(_MFE_MASERATI_) || defined(_MFE_MAXIM_) || defined(_MFE_KANO_) || defined(_MFE_K6_)
925 mfe_reg->reg_mfe_s_ieap_early_termination = 1;
926 #endif
927 // Field coding
928 switch (pInfo->h264_mcc_offset[0]) {
929 case 0:
930 mfe_reg->reg_mfe_s_mvdctl_ref0_offset = 0;
931 break;
932 case 2:
933 mfe_reg->reg_mfe_s_mvdctl_ref0_offset = 1;
934 break;
935 case -2:
936 mfe_reg->reg_mfe_s_mvdctl_ref0_offset = 2;
937 break;
938 }
939 switch (pInfo->h264_mcc_offset[1]) {
940 case 0:
941 mfe_reg->reg_mfe_s_mvdctl_ref1_offset = 0;
942 break;
943 case 2:
944 mfe_reg->reg_mfe_s_mvdctl_ref1_offset = 1;
945 break;
946 case -2:
947 mfe_reg->reg_mfe_s_mvdctl_ref1_offset = 2;
948 break;
949 }
950
951 #if defined(MFE_MIU_WRITE_PROTECTION)
952 {
953 MS_U32 gn_buf_size = (pConfig->nBufWidth / 16) * 128;
954 mfe_reg->reg_mfe_s_marb_lbound_3_low = MEM_BOUND_LO(pBufInfo->m_nGNAddr.miuAddress);
955 mfe_reg->reg_mfe_s_marb_lbound_3_high = MEM_BOUND_HI(pBufInfo->m_nGNAddr.miuAddress);
956 mfe_reg->reg_mfe_s_marb_ubound_3_low = MEM_BOUND_LO(pBufInfo->m_nGNAddr.miuAddress + gn_buf_size);
957 mfe_reg->reg_mfe_s_marb_ubound_3_high = MEM_BOUND_HI(pBufInfo->m_nGNAddr.miuAddress + gn_buf_size);
958
959 // write ports 2 and 3 share the same buffer
960 mfe_reg->reg_mfe_s_marb_lbound_2_low = mfe_reg->reg_mfe_s_marb_lbound_3_low;
961 mfe_reg->reg_mfe_s_marb_lbound_2_high = mfe_reg->reg_mfe_s_marb_lbound_3_high;
962 mfe_reg->reg_mfe_s_marb_ubound_2_low = mfe_reg->reg_mfe_s_marb_ubound_3_low;
963 mfe_reg->reg_mfe_s_marb_ubound_2_high = mfe_reg->reg_mfe_s_marb_ubound_3_high;
964
965 // bsp obuf
966 mfe_reg->reg_mfe_s_marb_lbound_0_low = MEM_BOUND_LO(pBufInfo->m_nOutBufAddr[pConfig->nOBufIndex].miuAddress);
967 mfe_reg->reg_mfe_s_marb_lbound_0_high = MEM_BOUND_HI(pBufInfo->m_nOutBufAddr[pConfig->nOBufIndex].miuAddress);
968 mfe_reg->reg_mfe_s_marb_ubound_0_low = MEM_BOUND_LO(pBufInfo->m_nOutBufAddr[pConfig->nOBufIndex].miuAddress + pBufInfo->m_OutBufferSize);
969 mfe_reg->reg_mfe_s_marb_ubound_0_high = MEM_BOUND_HI(pBufInfo->m_nOutBufAddr[pConfig->nOBufIndex].miuAddress + pBufInfo->m_OutBufferSize);
970
971 // recon frames (between gn buf and bsp obuf)
972 mfe_reg->reg_mfe_s_marb_lbound_1_low = mfe_reg->reg_mfe_s_marb_ubound_3_low;
973 mfe_reg->reg_mfe_s_marb_lbound_1_high = mfe_reg->reg_mfe_s_marb_ubound_3_high;
974 mfe_reg->reg_mfe_s_marb_ubound_1_low = mfe_reg->reg_mfe_s_marb_lbound_0_low;
975 mfe_reg->reg_mfe_s_marb_ubound_1_high = mfe_reg->reg_mfe_s_marb_lbound_0_high;
976
977 mfe_reg->reg_mfe_s_marb_miu_bound_en_0 = 1;
978 mfe_reg->reg_mfe_s_marb_miu_bound_en_1 = 1;
979 mfe_reg->reg_mfe_s_marb_miu_bound_en_2 = 1;
980 mfe_reg->reg_mfe_s_marb_miu_bound_en_3 = 1;
981 }
982 #endif
983
984 #ifdef HW_ECO_STARTCODE_PREVENTION
985 mfe_reg->reg_eco_bsp_rdy_fix = 1;
986 #if defined(_MFE_EDISON_)
987 //agate U02 cannot set this.
988 mfe_reg->reg_eco_bsp_multi_slice_fix = 1;
989 #endif
990 #endif
991 #if defined(_MFE_MUJI_) || defined(_MFE_MONET_) || defined(_MFE_MESSI_) || defined(_MFE_MANHATTAN_) || defined(_MFE_MASERATI_) || defined(_MFE_MAXIM_) || defined(_MFE_KANO_) || defined(_MFE_K6_)
992 mfe_reg->reg_eco_bsp_stuffing = 1;
993 #endif
994 //////////////////////////////////////////////////////////////////////////
995 // swcfg1 output
996 nTarWriteCount = 0;
997 nRegWriteCount = 0;
998 nTarFDCCount = 0;
999 nRegFDCCount = 0;
1000 if (nFrmNum==0) {
1001 nTarWriteCount = 2;
1002 // Switch to sw mode
1003 mfe_reg->reg_mfe_g_tbc_mode = 0;
1004 WriteRegMFE(0x3, mfe_reg->reg03, (MS_S8*)("[%d] reg03"), nRegWriteCount++, (MS_S8*)("tbc_mode=0"));
1005 // Switch to hw mode
1006 mfe_reg->reg_mfe_g_tbc_mode = 1;
1007 WriteRegMFE(0x3, mfe_reg->reg03, (MS_S8*)("[%d] reg03"), nRegWriteCount++, (MS_S8*)("tbc_mode=1"));
1008 MS_ASSERT(nRegWriteCount==nTarWriteCount);
1009 }
1010
1011 nRegWriteCount = 0;
1012 nTarFDCCount = PutFDC(mfe_reg, pContext, 1);
1013 nTarWriteCount = 54+(nTarFDCCount*3);
1014
1015 nTarWriteCount++; // reg to set fdc round
1016 nTarWriteCount++; // reset 0/1: MPEG4 enable/disable p skip mode
1017
1018 #ifdef CLOCK_GATING
1019 nTarWriteCount++;
1020 #endif
1021 #ifdef MFE_SUPPORT_TLB
1022 nTarWriteCount++; // mfe_reg1.reg36
1023 #endif
1024 #ifdef MFE_YUV_LOADER
1025 nTarWriteCount += 2; // mfe_reg1.reg56, mfe_reg1.reg0b
1026 #endif
1027 #ifdef MFE_DBF_PACKED_MODE
1028 nTarWriteCount++; // mfe_reg.reg4f
1029 #endif
1030 #if defined(MFE_MIU_WRITE_PROTECTION)
1031 nTarWriteCount += 16; // mfe_reg.reg58 ~ mfe_reg.reg67
1032 #endif
1033
1034 nTarFDCCount *= 3;
1035 nTarFDCCount++; // reg to set fdc round
1036
1037 // SW reset
1038 mfe_reg->reg_mfe_g_soft_rstz = 0;
1039 WriteRegMFE(0x0, mfe_reg->reg00, (MS_S8*)("[%d] reg00"), nRegWriteCount++, (MS_S8*)("SW reset 0"));
1040 mfe_reg->reg_mfe_g_soft_rstz = 1;
1041 WriteRegMFE(0x0, mfe_reg->reg00, (MS_S8*)("[%d] reg00"), nRegWriteCount++, (MS_S8*)("SW reset 1"));
1042 WriteRegMFE(0x1, mfe_reg->reg01, (MS_S8*)("[%d] reg01"), nRegWriteCount++, (MS_S8*)("picture width"));
1043 WriteRegMFE(0x2, mfe_reg->reg02, (MS_S8*)("[%d] reg02"), nRegWriteCount++, (MS_S8*)("picture height"));
1044 WriteRegMFE(0x3, mfe_reg->reg03, (MS_S8*)("[%d] reg03"), nRegWriteCount++, (MS_S8*)("value"));
1045 WriteRegMFE(0x4, mfe_reg->reg04, (MS_S8*)("[%d] reg04"), nRegWriteCount++, (MS_S8*)("er_bs mode threshold"));
1046 WriteRegMFE(0x5, mfe_reg->reg05, (MS_S8*)("[%d] reg05"), nRegWriteCount++, (MS_S8*)("inter prediction preference"));
1047
1048 WriteRegMFE(0x20, mfe_reg->reg20, (MS_S8*)("[%d] reg20"), nRegWriteCount++, (MS_S8*)("ME partition setting"));
1049 WriteRegMFE(0x21, mfe_reg->reg21, (MS_S8*)("[%d] reg21"), nRegWriteCount++, (MS_S8*)("value"));
1050 WriteRegMFE(0x22, mfe_reg->reg22, (MS_S8*)("[%d] reg22"), nRegWriteCount++, (MS_S8*)("me search range max depth"));
1051 WriteRegMFE(0x23, mfe_reg->reg23, (MS_S8*)("[%d] reg23"), nRegWriteCount++, (MS_S8*)("me mvx"));
1052 WriteRegMFE(0x24, mfe_reg->reg24, (MS_S8*)("[%d] reg24"), nRegWriteCount++, (MS_S8*)("me mvy"));
1053 WriteRegMFE(0x25, mfe_reg->reg25, (MS_S8*)("[%d] reg25"), nRegWriteCount++, (MS_S8*)("FME"));
1054
1055 #ifdef CLOCK_GATING
1056 WriteRegMFE(0x16, mfe_reg->reg16, (MS_S8*)("[%d] reg16"), nRegWriteCount++, (MS_S8*)("Clock gating"));
1057 #endif
1058
1059 // Input buffers
1060 //
1061 if(pConfig->g_nUseYUV422 == 0) {
1062 WriteRegMFE(0x06, mfe_reg->reg06, (MS_S8*)("[%d] reg06"), nRegWriteCount++, (MS_S8*)("current luma base address"));
1063 WriteRegMFE(0x07, mfe_reg->reg07, (MS_S8*)("[%d] reg07"), nRegWriteCount++, (MS_S8*)("current luma base address high"));
1064 WriteRegMFE(0x08, mfe_reg->reg08, (MS_S8*)("[%d] reg08"), nRegWriteCount++, (MS_S8*)("current chroma base address"));
1065 WriteRegMFE(0x09, mfe_reg->reg09, (MS_S8*)("[%d] reg09"), nRegWriteCount++, (MS_S8*)("current chroma base address high"));
1066 }
1067 WriteRegMFE(0x0a, mfe_reg->reg0a, (MS_S8*)("[%d] reg0a"), nRegWriteCount++, (MS_S8*)("reference luma base address0"));
1068 WriteRegMFE(0x0b, mfe_reg->reg0b, (MS_S8*)("[%d] reg0b"), nRegWriteCount++, (MS_S8*)("reference luma base address0 high"));
1069 WriteRegMFE(0x0c, mfe_reg->reg0c, (MS_S8*)("[%d] reg0c"), nRegWriteCount++, (MS_S8*)("reference luma base address1"));
1070 WriteRegMFE(0x0d, mfe_reg->reg0d, (MS_S8*)("[%d] reg0d"), nRegWriteCount++, (MS_S8*)("reference luma base address1 high"));
1071 WriteRegMFE(0x0e, mfe_reg->reg0e, (MS_S8*)("[%d] reg0e"), nRegWriteCount++, (MS_S8*)("reference chroma base address0"));
1072 WriteRegMFE(0x0f, mfe_reg->reg0f, (MS_S8*)("[%d] reg0f"), nRegWriteCount++, (MS_S8*)("reference chroma base address0 high"));
1073 WriteRegMFE(0x10, mfe_reg->reg10, (MS_S8*)("[%d] reg10"), nRegWriteCount++, (MS_S8*)("reference chroma base address1"));
1074 WriteRegMFE(0x11, mfe_reg->reg11, (MS_S8*)("[%d] reg11"), nRegWriteCount++, (MS_S8*)("reference chroma base address1 high"));
1075 WriteRegMFE(0x12, mfe_reg->reg12, (MS_S8*)("[%d] reg12"), nRegWriteCount++, (MS_S8*)("reconstructed luma base address:"));
1076 WriteRegMFE(0x13, mfe_reg->reg13, (MS_S8*)("[%d] reg13"), nRegWriteCount++, (MS_S8*)("reconstructed luma base address high"));
1077 WriteRegMFE(0x14, mfe_reg->reg14, (MS_S8*)("[%d] reg14"), nRegWriteCount++, (MS_S8*)("reconstructed chroma base address:"));
1078 WriteRegMFE(0x15, mfe_reg->reg15, (MS_S8*)("[%d] reg15"), nRegWriteCount++, (MS_S8*)("reconstructed chroma base address: high"));
1079
1080 #if defined(_MFE_T8_)&&!defined(_MFE_AGATE_)
1081 // Output buffer
1082 WriteRegMFE(0x3c, mfe_reg->reg3c, (MS_S8*)("[%d] reg3c"), nRegWriteCount++, (MS_S8*)("bsp obuf start address: "));
1083 WriteRegMFE(0x3d, mfe_reg->reg3d, (MS_S8*)("[%d] reg3d"), nRegWriteCount++, (MS_S8*)("bsp obuf start address high"));
1084 WriteRegMFE(0x3e, mfe_reg->reg3e, (MS_S8*)("[%d] reg3e"), nRegWriteCount++, (MS_S8*)("bsp obuf end address: "));
1085 WriteRegMFE(0x3f, mfe_reg->reg3f, (MS_S8*)("[%d] reg3f"), nRegWriteCount++, (MS_S8*)("bsp obuf end address high"));
1086 mfe_reg->reg_mfe_s_bspobuf_set_adr = 1;
1087 #endif
1088 //
1089 mfe_reg->reg_mfe_s_bspobuf_fifo_th = 1;
1090 mfe_reg->reg_mfe_s_mvobuf_set_adr = 0;
1091 mfe_reg->reg_mfe_s_mvobuf_fifo_th = 0;
1092
1093 #if defined(_MFE_MUJI_) || defined(_MFE_MONET_) || defined(_MFE_MESSI_) || defined(_MFE_MANHATTAN_) || defined(_MFE_MASERATI_) || defined(_MFE_MAXIM_) || defined(_MFE_KANO_) || defined(_MFE_K6_)
1094 if(!pConfig->SecurityMode)
1095 #endif
1096 {
1097 #if defined(_MFE_T8_)&&!defined(_MFE_AGATE_)
1098 WriteRegMFE(0x3b, mfe_reg->reg3b, (MS_S8*)("[%d] reg3b"), nRegWriteCount++, (MS_S8*)("set bsp obuf"));
1099 mfe_reg->reg_mfe_s_bspobuf_set_adr = 0; // HW is write-one-clear
1100 #elif defined(_MFE_M1_)||defined(_MFE_AGATE_)
1101 // Enable set-obuf
1102 mfe_reg->reg_mfe_s_bspobuf_update_adr = 1;
1103 WriteRegMFE(0x3f, mfe_reg->reg3f, (MS_S8*)("[%d] reg3f"), nRegWriteCount++, (MS_S8*)("reg_mfe_s_bspobuf_update_adr"));
1104 mfe_reg->reg_mfe_s_bspobuf_update_adr = 0; // write-one-clear
1105 #if defined(WIN32)
1106 mfe_reg->enable_obufadr_update = 0;
1107 UDMA_RIURead16(REG_BANK_MFE+0x6a, (MS_U16*)&mfe_reg->reg6a);
1108 while (mfe_reg->enable_obufadr_update!=1) {
1109 UDMA_RIURead16(REG_BANK_MFE+0x6a, (MS_U16*)&mfe_reg->reg6a);
1110 printf("Wait for enable_obufadr_update=1!\n"));
1111 }
1112 #endif
1113 #if defined(USE_HW_DBL_OBUF)
1114 nRegWriteCount += SetObufAddr((MS_U32)pBufInfo->m_nOutBufAddr, pBufInfo->m_OutBufferSize, 0, 0);
1115 nRegWriteCount += SetObufAddr((MS_U32)pBufInfo->m_nOutBufAddr+pBufInfo->m_OutBufferSize, pBufInfo->m_OutBufferSize, 1, 1);
1116 #else
1117 /*
1118 #define CEILING_ALIGN(value, align) (((MEF_U32)(value)+((align)-1UL)) & ~((align)-1UL))
1119 #define IN_SIZE (CEILING_ALIGN(720UL,32UL)*1280UL+CEILING_ALIGN(720UL,64UL)*1280UL/2UL+0x100UL)
1120
1121 pBufInfo->m_nOutBufAddr[pConfig->nOBufIndex].miuAddress = 0x000ABEA000 + IN_SIZE;
1122 pBufInfo->m_OutBufferSize = 1024*1024;
1123 */
1124 nRegWriteCount += SetObufAddr(mfe_reg, (MS_U32)pBufInfo->m_nOutBufAddr[pConfig->nOBufIndex].miuAddress, pBufInfo->m_OutBufferSize, 0, 1);
1125 #endif
1126 #endif
1127 }
1128 // GN
1129 WriteRegMFE(0x4c, mfe_reg->reg4c, (MS_S8*)("[%d] reg4c"), nRegWriteCount++, (MS_S8*)("reg_mfe_s_gn_sadr_low"));
1130 WriteRegMFE(0x4d, mfe_reg->reg4d, (MS_S8*)("[%d] reg4d"), nRegWriteCount++, (MS_S8*)("reg_mfe_s_gn_sadr_high"));
1131
1132 // MBR
1133 WriteRegMFE(0x26, mfe_reg->reg26, (MS_S8*)("[%d] reg26"), nRegWriteCount++, (MS_S8*)("MBR: mbbits"));
1134 WriteRegMFE(0x27, mfe_reg->reg27, (MS_S8*)("[%d] reg27"), nRegWriteCount++, (MS_S8*)("MBR: frame qstep"));
1135 WriteRegMFE(0x29, mfe_reg->reg29, (MS_S8*)("[%d] reg29"), nRegWriteCount++, (MS_S8*)("264 qp-offset"));
1136 WriteRegMFE(0x2a, mfe_reg->reg2a, (MS_S8*)("[%d] reg2a"), nRegWriteCount++, (MS_S8*)("QP min/max"));
1137 WriteRegMFE(0x6e, mfe_reg->reg6e, (MS_S8*)("[%d] reg6e"), nRegWriteCount++, (MS_S8*)("QStep min"));
1138 WriteRegMFE(0x6f, mfe_reg->reg6f, (MS_S8*)("[%d] reg6f"), nRegWriteCount++, (MS_S8*)("QStep max"));
1139
1140 // MDC
1141 WriteRegMFE(0x39, mfe_reg->reg39, (MS_S8*)("[%d] reg39"), nRegWriteCount++, (MS_S8*)("value"));
1142
1143 // Intra Update
1144 WriteRegMFE(0x2f, mfe_reg->reg2f, (MS_S8*)("[%d] reg2f"), nRegWriteCount++, (MS_S8*)("value"));
1145 WriteRegMFE(0x30, mfe_reg->reg30, (MS_S8*)("[%d] reg30"), nRegWriteCount++, (MS_S8*)("value"));
1146 WriteRegMFE(0x31, mfe_reg->reg31, (MS_S8*)("[%d] reg31"), nRegWriteCount++, (MS_S8*)("value"));
1147 WriteRegMFE(0x32, mfe_reg->reg32, (MS_S8*)("[%d] reg32"), nRegWriteCount++, (MS_S8*)("value"));
1148
1149 // DBF
1150 WriteRegMFE(0x3a, mfe_reg->reg3a, (MS_S8*)("[%d] reg3a"), nRegWriteCount++, (MS_S8*)("value"));
1151
1152 mfe_reg->reg_mfe_g_crc_mode = 0xC;
1153 mfe_reg->reg_mfe_g_debug_tcycle_chk_en = 0x1;
1154 //#ifdef TEST_CRC_MODE
1155 mfe_reg->reg_mfe_g_debug_tcycle_chk_sel = 0x0;
1156 //#endif
1157
1158 mfe_reg->reg_mfe_g_debug_en = 0; // TEST
1159 WriteRegMFE(0x73, mfe_reg->reg73, (MS_S8*)("[%d] reg73"), nRegWriteCount++, (MS_S8*)("crc mode"));
1160
1161 //mfe_reg->reg_mfe_s_txip_idle_cnt = 160;
1162 //WriteRegMFE(0x33, mfe_reg->reg33, (MS_S8*)("[%d] reg33"), nRegWriteCount++, (MS_S8*)("txip_idle_cnt"));
1163 #if defined(_MFE_MUJI_) || defined(_MFE_MONET_) || defined(_MFE_MESSI_) || defined(_MFE_MANHATTAN_) || defined(_MFE_MASERATI_) || defined(_MFE_MAXIM_) || defined(_MFE_KANO_) || defined(_MFE_K6_)
1164 mfe_reg->reg_mfe_g_ieap_sram_4x2_swap = 1;
1165 #endif
1166 WriteRegMFE(0x2c, mfe_reg->reg2c, (MS_S8*)("[%d] reg2c"), nRegWriteCount++, (MS_S8*)("Last zigzag"));
1167
1168 // IEAP
1169 WriteRegMFE(0x2b, mfe_reg->reg2b, (MS_S8*)("[%d] reg2b"), nRegWriteCount++, (MS_S8*)("ieap"));
1170
1171 // Cross-format wrong reg setting prevention
1172 mfe_reg->reg_mfe_g_viu_soft_rstz = 1;
1173 WriteRegMFE(0x18, mfe_reg->reg18, (MS_S8*)("[%d] reg18"), nRegWriteCount++, (MS_S8*)("JPE encode mode"));
1174 WriteRegMFE(0x1b, mfe_reg->reg1b, (MS_S8*)("[%d] reg1b"), nRegWriteCount++, (MS_S8*)("MPEG4 FieldDCT"));
1175 MS_ASSERT(mfe_reg->reg19==0);
1176 WriteRegMFE(0x19,0, (MS_S8*)("[%d] reg19"), nRegWriteCount++, (MS_S8*)("0/1: MPEG4 enable/disable p skip mode"));
1177 #if defined(_MFE_MUJI_) || defined(_MFE_MONET_) || defined(_MFE_MESSI_) || defined(_MFE_MANHATTAN_) || defined(_MFE_MASERATI_) || defined(_MFE_MAXIM_) || defined(_MFE_KANO_) || defined(_MFE_K6_)
1178 WriteRegMFE_BANK1(0x52, mfe_reg1->reg52, (MS_S8*)("[%d] reg52"), nRegWriteCount++, (MS_S8*)("YUV422 and handshake mode"));
1179
1180 if(pConfig->g_nUseYUV422 != 0) {
1181 WriteRegMFE_BANK1(0x12, mfe_reg1->reg12, (MS_S8*)("[%d] reg12"), nRegWriteCount++, (MS_S8*)("enc curr_y addr"));
1182 WriteRegMFE_BANK1(0x13, mfe_reg1->reg13, (MS_S8*)("[%d] reg13"), nRegWriteCount++, (MS_S8*)("enc curr_y addr"));
1183 }
1184 #endif
1185
1186 #if defined(MFE_YUV_LOADER)
1187 WriteRegMFE_BANK1(0x0b, mfe_reg1->reg0b, (MS_S8*)("[%d] reg0b"), nRegWriteCount++, (MS_S8*)("YUV422 pitch"));
1188 WriteRegMFE_BANK1(0x56, mfe_reg1->reg56, (MS_S8*)("[%d] reg56"), nRegWriteCount++, (MS_S8*)("YUV Loader"));
1189 #endif
1190
1191 #ifdef _MFE_T8_
1192 if (mfe_reg->reg_mfe_g_enc_mode !=REG_ENC_MODE_MPG4) { // MPEG-4
1193 WriteRegMFE(0x37, mfe_reg->reg37=0, (MS_S8*)("[%d] reg37"), nRegWriteCount, (MS_S8*)("MPEG4 MDC"));
1194 WriteRegMFE(0x38, mfe_reg->reg38=0, (MS_S8*)("[%d] reg38"), nRegWriteCount, (MS_S8*)("MPEG4: vop_time_increment"));
1195 // B-direct
1196 WriteRegMFE(0x1a, mfe_reg->reg1a=0, (MS_S8*)("[%d] reg1a"), nRegWriteCount, (MS_S8*)("MPEG4 BDirect"));
1197 }
1198 #endif
1199 #if defined(_MFE_M1_)||defined(_MFE_AGATE_)
1200 // Prefetch & Low bandwidth mode
1201 WriteRegMFE(0x68,mfe_reg->reg68, (MS_S8*)("[%d] reg68"), nRegWriteCount++, (MS_S8*)("Prefetch & Low bandwidth mode"));
1202 // Prefetch
1203 WriteRegMFE(0x6d,mfe_reg->reg6d, (MS_S8*)("[%d] reg6d"), nRegWriteCount++, (MS_S8*)("Prefetch MB idle count"));
1204 //Low BandWidth
1205 WriteRegMFE(0x6b, mfe_reg->reg6b, (MS_S8*)("[%d] reg6b"), nRegWriteCount++, (MS_S8*)("Low Bandwidth: IMI addr low"));
1206 WriteRegMFE(0x6c, mfe_reg->reg6c, (MS_S8*)("[%d] reg6c"), nRegWriteCount++, (MS_S8*)("Low Bandwidth: IMI addr high"));
1207
1208 #if defined(MFE_DBF_PACKED_MODE)
1209 WriteRegMFE(0x4f, mfe_reg->reg4f, (MS_S8*)("[%d] reg4f"), nRegWriteCount++, (MS_S8*)("DBF packed mode"));
1210 #endif
1211
1212 // Reset any StopAndGo or StopAndDrop setting.
1213 mfe_reg->reg_mfe_s_txip_sng_mb = 0;
1214 WriteRegMFE(0x2d, mfe_reg->reg2d, (MS_S8*)("[%d] reg2d"), nRegWriteCount++, (MS_S8*)("reg_mfe_s_txip_sng_mb=0"));
1215
1216 #endif
1217 //hw bug, disable it.
1218 mfe_reg->reg_mfe_s_mcc_prldr_mode = 0;
1219 WriteRegMFE(0x7f, mfe_reg->reg7f, (MS_S8*)("[%d] reg7f"), nRegWriteCount++, (MS_S8*)("reg_mfe_s_mcc_prldr_mode=0"));
1220 mfe_reg->reg_mfe_s_marb_rp0_promote = 0x0;
1221 mfe_reg->reg_mfe_s_marb_rp1_promote = 0x0;
1222 mfe_reg->reg_mfe_s_marb_rp2_promote = 0x0;
1223 mfe_reg->reg_mfe_s_marb_rp3_promote = 0x0;
1224 mfe_reg->reg_mfe_s_marb_mrpriority_thd = 0xf;
1225 mfe_reg->reg_mfe_s_marb_mwpriority_thd = 0xf;
1226 mfe_reg->reg_mfe_s_marb_rp4_occupy = 0x0;
1227 mfe_reg->reg_mfe_s_marb_rp4_promote = 0x0;
1228 WriteRegMFE(0x51, mfe_reg->reg51, (MS_S8*)("[%d] reg51"), nRegWriteCount++, (MS_S8*)("marb_rp_promote"));
1229 WriteRegMFE(0x55, mfe_reg->reg55, (MS_S8*)("[%d] reg55"), nRegWriteCount++, (MS_S8*)("marb_rp4_promote"));
1230
1231 //enable eco item
1232 WriteRegMFE(0x7d, mfe_reg->reg7d, (MS_S8*)("[%d] reg7d"), nRegWriteCount++, (MS_S8*)("reg_mfe_s_txip_eco0=1"));
1233
1234 #if defined(TEST_MB_STOPANDGO) || defined(TEST_MB_STOPANDDROP)
1235 if (nFrmNum==STOP_FRAME)
1236 TestStopAtMb();
1237 #endif
1238 #ifdef MFE_MIU_PROFILE
1239 mfe_reg1->reg_mfe_s_rhist_en = 1;
1240 WriteRegMFE_BANK1(0x45, mfe_reg1->reg45, (MS_S8*)("[%d] reg45"), nRegWriteCount++, (MS_S8*)("Read histogram enable"));
1241 mfe_reg1->reg_mfe_s_whist_en = 1;
1242 WriteRegMFE_BANK1(0x40, mfe_reg1->reg40, (MS_S8*)("[%d] reg40"), nRegWriteCount++, (MS_S8*)("Write histogram enable"));
1243 #endif
1244
1245 #ifdef MFE_SUPPORT_TLB
1246 mfe_reg1->reg_mfe_tlb = pConfig->bEnableTLB ? 1 : 0;
1247 WriteRegMFE_BANK1(0x36, mfe_reg1->reg36, (MS_S8*)("[%d] reg36"), nRegWriteCount++, (MS_S8*)("Enable TLB"));
1248 #endif
1249
1250 #if defined(MFE_MIU_WRITE_PROTECTION)
1251 WriteRegMFE(0x58, mfe_reg->reg58, (MS_S8*)("[%d] reg58"), nRegWriteCount++, (MS_S8*)("MIU upper bound 0"));
1252 WriteRegMFE(0x59, mfe_reg->reg59, (MS_S8*)("[%d] reg59"), nRegWriteCount++, (MS_S8*)("MIU upper bound 0"));
1253 WriteRegMFE(0x5a, mfe_reg->reg5a, (MS_S8*)("[%d] reg5a"), nRegWriteCount++, (MS_S8*)("MIU lower bound 0"));
1254 WriteRegMFE(0x5b, mfe_reg->reg5b, (MS_S8*)("[%d] reg5b"), nRegWriteCount++, (MS_S8*)("MIU lower bound 0"));
1255 WriteRegMFE(0x5c, mfe_reg->reg5c, (MS_S8*)("[%d] reg5c"), nRegWriteCount++, (MS_S8*)("MIU upper bound 1"));
1256 WriteRegMFE(0x5d, mfe_reg->reg5d, (MS_S8*)("[%d] reg5d"), nRegWriteCount++, (MS_S8*)("MIU upper bound 1"));
1257 WriteRegMFE(0x5e, mfe_reg->reg5e, (MS_S8*)("[%d] reg5e"), nRegWriteCount++, (MS_S8*)("MIU lower bound 1"));
1258 WriteRegMFE(0x5f, mfe_reg->reg5f, (MS_S8*)("[%d] reg5f"), nRegWriteCount++, (MS_S8*)("MIU lower bound 1"));
1259 WriteRegMFE(0x60, mfe_reg->reg60, (MS_S8*)("[%d] reg60"), nRegWriteCount++, (MS_S8*)("MIU upper bound 2"));
1260 WriteRegMFE(0x61, mfe_reg->reg61, (MS_S8*)("[%d] reg61"), nRegWriteCount++, (MS_S8*)("MIU upper bound 2"));
1261 WriteRegMFE(0x62, mfe_reg->reg62, (MS_S8*)("[%d] reg62"), nRegWriteCount++, (MS_S8*)("MIU lower bound 2"));
1262 WriteRegMFE(0x63, mfe_reg->reg63, (MS_S8*)("[%d] reg63"), nRegWriteCount++, (MS_S8*)("MIU lower bound 2"));
1263 WriteRegMFE(0x64, mfe_reg->reg64, (MS_S8*)("[%d] reg64"), nRegWriteCount++, (MS_S8*)("MIU upper bound 3"));
1264 WriteRegMFE(0x65, mfe_reg->reg65, (MS_S8*)("[%d] reg65"), nRegWriteCount++, (MS_S8*)("MIU upper bound 3"));
1265 WriteRegMFE(0x66, mfe_reg->reg66, (MS_S8*)("[%d] reg66"), nRegWriteCount++, (MS_S8*)("MIU lower bound 3"));
1266 WriteRegMFE(0x67, mfe_reg->reg67, (MS_S8*)("[%d] reg67"), nRegWriteCount++, (MS_S8*)("MIU lower bound 3"));
1267 #endif
1268
1269 //DumpAllReg();
1270 // Enable HW
1271 mfe_reg->reg_mfe_g_frame_start_sw = 1;
1272 WriteRegMFE(0x00, mfe_reg->reg00, (MS_S8*)("[%d] reg00"), nRegWriteCount++, (MS_S8*)("frame start"));
1273 mfe_reg->reg_mfe_g_frame_start_sw = 0; // HW is write-one-clear
1274
1275
1276 nRegFDCCount = PutFDC(mfe_reg, pContext, 0);
1277 nRegWriteCount += nRegFDCCount;
1278
1279 #if defined(TEST_STOPANDGO) || defined(TEST_STOPANDDROP)
1280 if (nFrmNum==STOP_FRAME)
1281 TestStop();
1282 #endif
1283
1284 if(nRegFDCCount != nTarFDCCount) {
1285 ms_dprintk(DRV_L3, "nRegFDCCount = %d, nTarFDCCount = %d\n", (int)nRegFDCCount, (int)nTarFDCCount);
1286 }
1287 if(nRegWriteCount != nTarWriteCount) {
1288 ms_dprintk(DRV_L3, "nRegWriteCount = %d, nTarWriteCount = %d\n", (int)nRegWriteCount, (int)nTarWriteCount);
1289 }
1290 // Only for debug
1291 //MS_ASSERT(nRegFDCCount==nTarFDCCount);
1292 //MS_ASSERT(nRegWriteCount==nTarWriteCount);
1293 }
1294
1295
1296