1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
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76 //******************************************************************************
77 //<MStar Software>
78 #define _PANEL_C_
79 #include "mdrv_mfc_platform.h"
80 #include "mdrv_mfc.h"
81 #include "mdrv_mfc_fb.h"
82
83 #if(CODESIZE_SEL == CODESIZE_ALL)
84
85 extern code U8 tInitializeColorMatrix[];
86 extern U8 tInitializeColorMatrix_count;
87
88 extern code MST_MFC_RegUnitType_t tInitializeTcon23b[];
89 extern code MST_MFC_RegUnitType_t tInitializeScTop2[];
90 extern code U8 tOverDrive[];
91 #if 0
92 //_RSDS
93 code MST_MFC_RegUnitType_t tInitializeTcon22a[]=
94 {
95 {0x22A0, 0xb2},
96 {0x22A2, 0xd4},
97 {0x22A6, 0x05},
98 {0x22A8, 0x05},
99 {0x22AA, 0x02},
100 {0x22AC, 0x11},
101 {0x22AE, 0x5a},
102
103 {_END_OF_TBL_, _END_OF_TBL_},
104 };
105
106 code MST_MFC_RegUnitType_t tInitializeTcon23a[]=
107 {
108 {0x2302, 0x7b},
109 {0x2304, 0x30},
110 {0x2306, 0x06},
111 {0x2308, 0x80},
112 {0x230A, 0x0c},
113 {0x230E, 0x50},
114
115 {0x2310, PANEL_WIDTH},
116 {0x2311, PANEL_WIDTH>>8},
117 {0x2314, PANEL_HEIGHT},
118 {0x2315, PANEL_HEIGHT>>8},
119 {0x2318, PANEL_HTOTAL},
120 {0x2319, PANEL_HTOTAL>>8},
121 {0x231C, PANEL_VTOTAL},
122 {0x231D, PANEL_VTOTAL>>8},
123 {0x231E, 0x80},
124
125 {0x2320, TP_START},
126 {0x2321, TP_START>>8},
127 {0x2322, TP_WIDTH},
128 {0x2323, TP_WIDTH>>8},
129 {0x2324, 0x30},
130 {0x2326, STV_START},
131 {0x2327, STV_START>>8},
132
133 {0x232A, CPV_START},
134 {0x232B, CPV_START>>8},
135 {0x232E, CPV_WIDTH},
136 {0x232F, CPV_WIDTH>>8},
137
138 {0x2332, OE_START},
139 {0x2333, OE_START>>8},
140 {0x2334, OE_WIDTH},
141 {0x2335, OE_WIDTH>>8},
142 {0x2336, 0x00},
143 {0x2338, POL_START},
144 {0x2339, POL_START>>8},
145 #if (PANEL_CHANNEL==_SINGLE)
146 {0x233C, PANEL_WIDTH},
147 {0x233D, PANEL_WIDTH>>8},
148 #elif (PANEL_CHANNEL==_DUAL)
149 {0x233C, PANEL_WIDTH>>1},
150 {0x233D, PANEL_WIDTH>>9},
151 #else
152 {0x233C, PANEL_WIDTH>>2},
153 {0x233D, PANEL_WIDTH>>10},
154 #endif
155 {0x233E, 0xf0},
156
157 {0x2340, 0x00}, //
158 {0x2341, 0x00}, //
159 {0x2342, 0xe2}, //
160 {0x2343, 0x02}, //
161 {0x2344, 0x82}, //
162 {0x2345, 0x01}, //
163 {0x2348, 0xd4}, //
164 {0x2349, 0x00}, //
165 {0x234A, 0x20}, //
166 {0x234B, 0x02}, //
167 {0x234C, 0x21}, //
168 {0x234E, 0x80}, //
169
170 {0x2360, 0x1a},
171 {0x2361, 0x02},
172 {0x2362, 0x1a},
173 {0x2363, 0x02},
174 {0x2364, 0xc7},
175 {0x2365, 0x00},
176 {0x2368, 0x00},
177 {0x2369, 0x00},
178 {0x236A, 0xff},
179 {0x236B, 0x02},
180 {0x236C, 0x31},
181 {0x236E, 0x05},
182
183 {0x2382, 0xe2}, //
184 {0x2383, 0x02}, //
185 {0x2384, 0x82}, //
186 {0x2385, 0x01}, //
187 {0x2388, 0xd4}, //
188 {0x2389, 0x00}, //
189 {0x238A, 0x22}, //
190 {0x238B, 0x02}, //
191 {0x238C, 0x00}, //
192 {0x238D, 0xff}, //
193 {0x238E, 0x05}, //
194 {0x238F, 0x80}, //
195
196 {0x2392, 0xd4}, //
197 {0x2393, 0x00}, //
198 {0x2394, 0xd4}, //
199 {0x2395, 0x00}, //
200 {0x2396, 0x08}, //
201 {0x2398, 0xd4}, //
202 {0x2399, 0x00}, //
203
204 {0x23A0, 0x80}, //
205 {0x23A2, 0x24}, //
206 {0x23A3, 0x02}, //
207 {0x23A4, 0x26}, //
208 {0x23A5, 0x02}, //
209 {0x23A6, 0x28}, //
210 {0x23A7, 0x02}, //
211
212 {0x23E2, 0x00},
213 {0x23E3, 0x00},
214
215 {_END_OF_TBL_, _END_OF_TBL_},
216 };
217 #endif
218
219 //_MINI_LVDS
220 code MST_MFC_RegUnitType_t tInitializeTcon22b_Comm[]=
221 {
222 {0x22A0, 0x01}, //DEOUT delay
223 {0x22A1, 0x00},
224 {0x22A2, 0x00}, //DEOUT_AHEAD delay
225 {0x22A3, 0x11},
226 {_END_OF_TBL_, _END_OF_TBL_},
227 };
228
229 code MST_MFC_RegUnitType_t tInitializeTcon23b_Comm[]=
230 {
231 //common
232 //{0x2301, 0x00},
233 {0x2302, 0x7c}, // {8'h0, skew_reg, ivmd_on, bist_hw_set, swap_fs, fsmode, dskew} = { - 01111, 3'h4};
234 {0x2303, 0x00},
235 {0x2304, 0x50}, // {8'h0, f2line, fcol, f1a2line, age_8bit, 4'h0} = {- 0001 - }
236 {0x2305, 0x00},
237 {0x230A, 0x2d},
238 /*{0x2310, 0xc0}, // {5'h0, hres} = {- 11'h556 }
239 {0x2311, 0x03},
240 {0x2314, 0x38}, // {5'h0, vres } = {- 11'h300 }
241 {0x2315, 0x04},
242 {0x2318, 0x98}, // {4'h0, htot} = {- 12'h698 }
243 {0x2319, 0x08},*/
244 {0x231A, 0x20}, // {10'h0, cout_type, inmod_pad_sel, 4'h0} = {- 00 -}
245 {0x231B, 0x00},
246 ///{0x231C, 0x65}, // {5'h0, vtot } = {- 12'h326 }
247 ///{0x231D, 0x04},
248 {0x231E, 0xc0}, // {8'h0, tp_drv, sth_drv, 1'b0, pol_newtype, 4'h0} = {- 11 - 0 -};
249 {0x231F, 0x00},
250 ///////Tcon setting by panel start/////////
251 {0x23E0, 0xa6}, //2370
252 {0x23E1, 0x03},
253 {0x23E4, 0x00}, //[15]en_minilvds [14:13]bit_flag [12:9]mini_channel_max
254 {0x23E5, 0xac},
255 {0x23E8, 0x20},//2374
256 {0x23E9, 0x5b},
257 {0x23F4, 0x00},
258 {0x23F5, 0x40}, //GOE Mask
259 {0x23F6, 0x08},
260 {0x23F7, 0x00},
261 {_END_OF_TBL_, _END_OF_TBL_},
262 };
263
264 code MST_MFC_RegUnitType_t tInitializeTcon23b_42[]=
265 {
266 {0x233C, 0xe0}, // {5'h0, bank1_len[10:0]}
267 {0x233D, 0x01},
268 {0x2326, 0xd0}, //2313(GSP)
269 {0x2327, 0x01},
270 {0x2320, 0xdd},//2310(SOE)
271 {0x2321, 0x03},
272 {0x2322, 0x46},//2311
273 {0x2323, 0x00},
274 {0x2332, 0x14},//2319(GOE)
275 {0x2333, 0x03},
276 {0x2334, 0xD2},//231A
277 {0x2335, 0x00},
278 {0x232A, 0xa0},//2315(GSC)
279 {0x232B, 0x03},
280 {0x232E, 0x26},//2317
281 {0x232F, 0x02},
282 {0x2338, 0xC4},//231c(POL)
283 {0x2339, 0x03},
284 {0x23EC, 0x9F},//2376(FLK)
285 {0x23ED, 0x02},
286 {_END_OF_TBL_, _END_OF_TBL_},
287 };
288
289 code MST_MFC_RegUnitType_t tInitializeTcon23b_47[]=
290 {
291 {0x233C, 0xe0}, // {5'h0, bank1_len[10:0]}
292 {0x233D, 0x01},
293 {0x2326, 0xd0},//2313
294 {0x2327, 0x01},
295 {0x2320, 0xd9},//2310
296 {0x2321, 0x03},
297 {0x2322, 0x4f},//2311
298 {0x2323, 0x00},
299 {0x2332, 0x21},//2319
300 {0x2333, 0x03},
301 {0x2334, 0x04},//231A
302 {0x2335, 0x01},
303 {0x232A, 0xa6},//2315
304 {0x232B, 0x03},
305 {0x232E, 0x26}, //2317 //0x73
306 {0x232F, 0x02},
307 {0x2338, 0xC4},//231c
308 {0x2339, 0x03},
309 {0x23EC, 0x85},//2376
310 {0x23ED, 0x02},
311 {_END_OF_TBL_, _END_OF_TBL_},
312 };
313
314 code MST_MFC_RegUnitType_t tInitializeTcon23b_55[]=
315 {
316 {0x233C, 0xe0}, // {5'h0, bank1_len[10:0]}
317 {0x233D, 0x01},
318 {0x2326, 0xd0},//2313
319 {0x2327, 0x01},
320 {0x2320, 0xFF},//2310
321 {0x2321, 0x03},
322 {0x2322, 0x46},//2311
323 {0x2323, 0x00},
324 {0x2332, 0xA6},//2319
325 {0x2333, 0x03},
326 {0x2334, 0x52},//231A
327 {0x2335, 0x00},
328 {0x232A, 0xd9},//2315
329 {0x232B, 0x03},
330 {0x232E, 0x73}, //2317 //0x73
331 {0x232F, 0x02},
332 {0x2338, 0xC4},//231c
333 {0x2339, 0x03},
334 {0x23EC, 0xFF},//2376
335 {0x23ED, 0x01},
336 {_END_OF_TBL_, _END_OF_TBL_},
337 };
338
339 //_MINI_LVDS_GIP
340 code MST_MFC_RegUnitType_t tInitializeTcon22c[]=
341 {
342 {0x22A0, 0x01}, //DEOUT delay
343 {0x22A1, 0x00},
344 {0x22A2, 0x00}, //DEOUT_AHEAD delay
345 {0x22A3, 0x11},
346 {_END_OF_TBL_, _END_OF_TBL_},
347 };
348
349 code MST_MFC_RegUnitType_t tInitializeTcon23c[]=
350 {
351 //common
352 //{0x2301, 0x00},
353 {0x2302, 0x7c}, // {8'h0, skew_reg, ivmd_on, bist_hw_set, swap_fs, fsmode, dskew} = { - 01111, 3'h4};
354 {0x2303, 0x00},
355 {0x2304, 0x50}, // {8'h0, f2line, fcol, f1a2line, age_8bit, 4'h0} = {- 0001 - }
356 {0x2305, 0x00},
357 {0x230A, 0x2d},
358 {0x2310, 0xc0}, // {5'h0, hres} = {- 11'h556 }
359 {0x2311, 0x03},
360 {0x2314, 0x38}, // {5'h0, vres } = {- 11'h300 }
361 {0x2315, 0x04},
362 {0x2318, 0x98}, // {4'h0, htot} = {- 12'h698 }
363 {0x2319, 0x08},
364 {0x231A, 0x20}, // {10'h0, cout_type, inmod_pad_sel, 4'h0} = {- 00 -}
365 {0x231B, 0x00},
366 {0x231C, 0x65}, // {5'h0, vtot } = {- 12'h326 }
367 {0x231D, 0x04},
368 {0x231E, 0xc0}, // {8'h0, tp_drv, sth_drv, 1'b0, pol_newtype, 4'h0} = {- 11 - 0 -};
369 {0x231F, 0x00},
370 {0x2320, 0xdd},//0xd9, // {4'h0, tpst } = {- 12'h2b5 }
371 {0x2321, 0x03},
372 {0x2322, 0x46},//0x44, // {8'h0, tppw} = {- 8'h63 }
373 {0x2323, 0x00},
374 {0x2326, 0xd0}, // {4'h0, stvst} = {- 12'h1c0 }
375 {0x2327, 0x01},
376 {0x232A, 0xa9}, // {4'h0, cpvst} = {- 12'h2e2 }
377 {0x232B, 0x03},
378 {0x232E, 0x73}, // {4'h0, cpvpw} = {- 12'h1a5 }
379 {0x232F, 0x02},
380 {0x2332, 0x52}, // {4'h0, oest} = {- 12'h28b }
381 {0x2333, 0x03},
382 {0x2334, 0xd2}, // {6'h0, oepw} = {- 10'h95 }
383 {0x2335, 0x00},
384 {0x2338, 0xC4},//0x00, // {4'h0, poltg} = {- 12'h256} ;
385 {0x2339, 0x03},//0x04,
386 {0x233C, 0xe0}, // {5'h0, bank1_len[10:0]} = {- 11'h2ab}
387 {0x233D, 0x01},
388 {0x23E0, 0xa6},
389 {0x23E1, 0x03},
390 {0x23E4, 0x00}, //[15]en_minilvds [14:13]bit_flag [12:9]mini_channel_max
391 {0x23E5, 0xac},
392 {0x23E8, 0x20}, //HEMAN
393 {0x23E9, 0x5B},
394 {0x23EC, 0xff},
395 {0x23ED, 0x01},
396 {0x23F5, 0x40},
397 {0x23F6, 0x08},
398 {0x23F7, 0x00},
399 //gip
400 //gpo0 //GCLK1
401 {0x234E, 0x20},//
402 {0x234F, 0x00},
403 {0x2348, 0x13},//[15]frame_tog_md,[14]line_tog_md,[13]first_2h_mode,[12]wave_polarity,[11:0]vst
404 //{0x2349, 0x40},
405 {0x234A, 0x4b}, //[11:0]vend
406 {0x234B, 0x04},
407 {0x2340, 0x4b},//[15:12]n_frame_tog_l4[11:0]hst2
408 {0x2341, 0x04},
409 {0x2342, 0x4b},//[15:12]n_frame_tog_h4[11:0]hst1
410 {0x2343, 0x04},
411 {0x2344, 0x1f}, //[15:12]n_line_tog_l4[11:0]hpw1
412 {0x2345, 0x23},
413 {0x2346, 0x1f}, //[15:12]n_line_tog_h4[11:0]hpw2
414 {0x2347, 0x03},
415 {0x23A8, 0x4B},//hst3
416 {0x23A9, 0x04},
417 {0x23AA, 0x1f}, //hpw3
418 {0x23AB, 0x03},
419 //gpo1 //GCLK2
420 {0x235E, 0x20},//
421 {0x235F, 0x00},
422 {0x2358, 0x14},//[15]frame_tog_md,[14]line_tog_md,[13]first_2h_mode,[12]wave_polarity,[11:0]vst
423 {0x2359, 0x40},
424 {0x235A, 0x4c}, //[11:0]vend
425 {0x235B, 0x04},
426 {0x2350, 0x4B},//[15:12]n_frame_tog_l4[11:0]hst2
427 {0x2351, 0x04},
428 {0x2352, 0x4B},//[15:12]n_frame_tog_h4[11:0]hst1
429 {0x2353, 0x04},
430 {0x2354, 0x1f}, //[15:12]n_line_tog_l4[11:0]hpw1
431 {0x2355, 0x23},
432 {0x2356, 0x1f}, //[15:12]n_line_tog_h4[11:0]hpw2
433 {0x2357, 0x03},
434 {0x23AC, 0x4B},//hst3
435 {0x23AD, 0x04},
436 {0x23AE, 0x1f}, //hpw3
437 {0x23AF, 0x03},
438 //gpo2 //GCLK3
439 {0x236E, 0x20},//
440 {0x236F, 0x00},
441 {0x2368, 0x15},//[15]frame_tog_md,[14]line_tog_md,[13]first_2h_mode,[12]wave_polarity,[11:0]vst
442 {0x2369, 0x40},
443 {0x236A, 0x4d}, //[11:0]vend
444 {0x236B, 0x04},
445 {0x2360, 0x4b},//[15:12]n_frame_tog_l4[11:0]hst2
446 {0x2361, 0x04},
447 {0x2362, 0x4b},//[15:12]n_frame_tog_h4[11:0]hst1
448 {0x2363, 0x04},
449 {0x2364, 0x1f}, //[15:12]n_line_tog_l4[11:0]hpw1
450 {0x2365, 0x23},
451 {0x2366, 0x1f}, //[15:12]n_line_tog_h4[11:0]hpw2
452 {0x2367, 0x03},
453 {0x23B0, 0x4b},//hst3
454 {0x23B1, 0x04},
455 {0x23B2, 0x1f}, //hpw3
456 {0x23B3, 0x03},
457 //gpo3 //GCLK4
458 {0x237E, 0x20},//
459 {0x237F, 0x00},
460 //{0x2378, 0x10},//[15]frame_tog_md,[14]line_tog_md,[13]first_2h_mode,[12]wave_polarity,[11:0]vst
461 {0x2379, 0x40},
462 {0x237A, 0x4e}, //[11:0]vend
463 {0x237B, 0x04},
464 {0x2370, 0x4b},//[15:12]n_frame_tog_l4[11:0]hst2
465 {0x2371, 0x04},
466 {0x2372, 0x4b},//[15:12]n_frame_tog_h4[11:0]hst1
467 {0x2373, 0x04},
468 {0x2374, 0x1f}, //[15:12]n_line_tog_l4[11:0]hpw1
469 {0x2375, 0x23},
470 {0x2376, 0x1f}, //[15:12]n_line_tog_h4[11:0]hpw2
471 {0x2377, 0x03},
472 {0x23B4, 0x4b},//hst3
473 {0x23B5, 0x04},
474 {0x23B6, 0x1f}, //hpw3
475 {0x23B7, 0x03},
476 //gpo4 //GCLK5
477 {0x238C, 0x55},// Output Tristate of 4 ,5 ,6 ,7
478 {0x238D, 0x00},
479 {0x238E, 0x00},//
480 {0x238F, 0x00},
481 //{0x2388, 0x11},//[15]frame_tog_md,[14]line_tog_md,[13]first_2h_mode,[12]wave_polarity,[11:0]vst
482 {0x2389, 0x40},
483 {0x238A, 0x49}, //[11:0]vend
484 {0x238B, 0x04},
485 {0x2380, 0x4b},//[15:12]n_frame_tog_l4[11:0]hst2
486 {0x2381, 0x04},
487 {0x2382, 0x4b},//[15:12]n_frame_tog_h4[11:0]hst1
488 {0x2383, 0x04},
489 {0x2384, 0x1f}, //[15:12]n_line_tog_l4[11:0]hpw1
490 {0x2385, 0x23},
491 {0x2386, 0x1f}, //[15:12]n_line_tog_h4[11:0]hpw2
492 {0x2387, 0x03},
493 {0x23B8, 0x4b},//hst3
494 {0x23B9, 0x04},
495 {0x23BA, 0x1f}, //hpw3
496 {0x23BB, 0x03},
497 //gpo5 //GCLK6
498 //{0x2392, 0x12},//[15]frame_tog_md,[14]line_tog_md,[13]first_2h_mode,[12]wave_polarity,[11:0]vst
499 {0x2393, 0x40},
500 {0x23A2, 0x4a}, //[11:0]vend
501 {0x23A3, 0x04},
502 {0x23BC, 0x4b},//[15:12]n_frame_tog_l4[11:0]hst1
503 {0x23BD, 0x04},
504 {0x23BE, 0x1f}, //[15:12]n_frame_tog_h4[11:0]hst2
505 {0x23BF, 0x03},
506 {0x23D4, 0x4b},//[15:12]n_line_tog_l4[11:0]hpw1
507 {0x23D5, 0x24},
508 {0x23D6, 0x1f}, //[15:12]n_line_tog_h4[11:0]hpw2
509 {0x23D7, 0x03},
510 {0x23D8, 0x4b},//hst3
511 {0x23D9, 0x04},
512 {0x23DA, 0x1f}, //hpw3
513 {0x23DB, 0x03},
514 //gpo6 //VST
515 //{0x2394, 0x0F},//[14]line_tog_md,[12]wave_polarity,[11:0]vst
516 {0x2395, 0x40},
517 //{0x23A4, 0x10},//[11:0]vend
518 //{0x23A5, 0x40},
519 {0x23DC, 0x23},//[15:12]n_line_tog_l4[11:0]hpw1
520 {0x23DD, 0x10},
521 {0x23DE, 0x39},//[15:12]n_line_tog_h4[11:0]hst1
522 {0x23DF, 0x03},
523 //gpo5b //VDD_EVEN
524 {0x23C8, 0x10},
525 {0x23C9, 0x00},
526 {0x23C4, 0x00}, //[15]frame_tog_md,[12]wave_polarity,[11:0]vst
527 {0x23C5, 0x80},
528 {0x23C6, 0x00},
529 {0x23C7, 0x00},
530 //0x23a5 0x0000 ; //[11:0]vend
531 {0x23C0, 0x80},//[15:12]n_frame_tog_l4[11:0]hpw1
532 {0x23C1, 0x80},
533 {0x23C2, 0x20}, //[15:12]n_frame_tog_h4[11:0]hst1
534 {0x23C3, 0xD0},
535 //gpo6b //VDD_ODD
536 {0x23D2, 0x10},
537 {0x23D3, 0x00},
538 {0x23CE, 0x00}, //[15]frame_tog_md,[12]wave_polarity,[11:0]vst
539 {0x23CF, 0x90},
540 {0x23D0, 0x00},
541 {0x23D1, 0x00},
542 //0x23a5 0x0000 ; //[11:0]vend
543 {0x23CA, 0x20},//[15:12]n_frame_tog_l4[11:0]hpw1
544 {0x23CB, 0x80},
545 {0x23CC, 0x80},//[15:12]n_frame_tog_h4[11:0]hst1
546 {0x23CD, 0xD0},
547 {0x2312, 0xC0}, //En
548 {0x2300, 0xF8},
549 {0x2338, 0xC4}, //poltg
550 {0x2339, 0x03},
551 {0x2320, 0xdd}, //tpst
552 {0x2321, 0x03},
553 {0x2322, 0x78},//tppw
554 //Gip setting //don't change process////George recommnat //j081031
555 {0x23C8, 0x00},
556 {0x23D2, 0x00},
557 {0x23F4, 0x00},
558 {_END_OF_TBL_, _END_OF_TBL_},
559 };
560
561
msInitializeColorMatrix(void)562 void msInitializeColorMatrix(void)
563 {
564 U8 i;
565
566 MDrv_MFC_WriteBit(0x20C0, gmfcSysInfo.u8PanelCSC, _BIT0); // [0]:CSC [1]:dither [2]:round
567 MDrv_MFC_WriteByte(0x3074, 0x00); // disable dither 6bit enable
568 MDrv_MFC_WriteByte(0x3075, 0x2d);
569 for (i=0; i<tInitializeColorMatrix_count/*sizeof(tInitializeColorMatrix)*/; i++) // 0x3002 ~ 0x301d
570 {
571 if((0x3002+i)==0x3017)
572 MDrv_MFC_WriteByteMask(0x3002+i, tInitializeColorMatrix[i], 0x7F);
573 else
574 MDrv_MFC_WriteByte(0x3002+i, tInitializeColorMatrix[i]);
575 }
576
577 //printf("\r\nmsInitializeColorMatrix()");
578 }
579
msInitializeTcon(void)580 void msInitializeTcon(void)
581 {
582 //if(gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP)
583 // MDrv_MFC_WriteByte(0x1E0F, 0x10); //HEMAN
584
585 //MDrv_MFC_WriteBit(0x2330, 1, _BIT4);//GOE polarity swap-----I-Chang 0829
586 //MDrv_MFC_WriteByte(0x23F0, 0xC0);//reg_ctrl_low_sel and reg_de_delay-----I-Chang 0909
587 MDrv_MFC_WriteBit(0x23F0, 1, _BIT3);//reg_ctrl_low_sel-----I-Chang 0909
588 MDrv_MFC_WriteBit(0x23F0, 1, _BIT2);//reg_de_delay-----I-Chang 0909
589 MDrv_MFC_WriteBit(0x23F0, 0, _BIT1);//reg_de_delay-----I-Chang 0909
590 MDrv_MFC_WriteBit(0x23F0, 0, _BIT0);//reg_de_delay-----I-Chang 0909
591 MDrv_MFC_WriteBit(0x2313, 1, _BIT7);//reg_tp_md_sel-----I-Chang 0909
592 MDrv_MFC_WriteBit(0x230F, 1, _BIT3);//Request by Bryan, control load-----I-Chang 0901
593
594 if(gmfcSysInfo.u8PanelType != _MINI_LVDS_GIP && gmfcSysInfo.u8PanelType != _MINI_LVDS_GIP_V5)
595 MDrv_MFC_WriteBit(0x238C, 0, _BIT0); //Output Enable FLK //j081031
596
597 MDrv_MFC_WriteByte(0x2398, 0x00);
598 MDrv_MFC_WriteByte(0x2399, 0x00);
599 MDrv_MFC_WriteByte(0x23A6, 0xFF);
600 MDrv_MFC_WriteByte(0x23A7, 0x00);
601 MDrv_MFC_WriteByte(0x23E0, 0xFF);
602 MDrv_MFC_WriteByte(0x23E1, 0x00);
603 MDrv_MFC_WriteByte(0x23EC, 0xFF);
604 MDrv_MFC_WriteByte(0x23ED, 0x00);
605 //msWriteBit(0x2330, 0, _BIT4);//GOE polarity swap-----I-Chang 0829
606 MDrv_MFC_WriteBit(0x2052, 0, _BIT0);//Only for visit; PC mode on-----I-Chang 0829
607 //printf("\r\nmsInitializeTcon()");
608 MDrv_MFC_WriteBit(0x2300, gmfcSysInfo.u8PanelBlankCPVC, _BIT6);
609 MDrv_MFC_WriteBit(0x2300, gmfcSysInfo.u8PanelBlankOEC, _BIT5);
610 MDrv_MFC_WriteBit(0x2300, gmfcSysInfo.u8PanelBlankTPC, _BIT4);
611 MDrv_MFC_WriteBit(0x2300, gmfcSysInfo.u8PanelBlankSTHC, _BIT3);
612
613 /* if(gmfcSysInfo.u8PanelType==_RSDS)
614 {
615 MDrv_MFC_WriteRegsTbl(0x2200, tInitializeTcon22a); // initialize all of bank
616 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23a); // initialize all of bank
617 }
618 else */if(gmfcSysInfo.u8PanelType==_MINI_LVDS)
619 {
620 MDrv_MFC_WriteRegsTbl(0x2200, tInitializeTcon22b_Comm); // initialize all of bank
621 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_Comm); // initialize all of bank
622
623 MDrv_MFC_Write2Bytes(0x2310, gmfcSysInfo.u16Width/2);
624 MDrv_MFC_Write2Bytes(0x2314, gmfcSysInfo.u16Height);
625 MDrv_MFC_Write2Bytes(0x2318, gmfcSysInfo.u16HTotal);
626 MDrv_MFC_Write2Bytes(0x231C, gmfcSysInfo.u16VTotal);
627
628
629 #if(CODEBASE_SEL == CODEBASE_51)
630 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b); //each panel
631 #elif(PANEL_TYPE_SEL == PNL_LCEAll)
632 if(MDrv_MFC_ReadByte(0x1E48) == 1)
633 {
634 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_42);
635 }
636 else if(MDrv_MFC_ReadByte(0x1E48) == 2)
637 {
638 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_47);
639 }
640 #else//55" need to refine the code
641 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_55);
642 #endif
643 }
644 else if(gmfcSysInfo.u8PanelType==_MINI_LVDS_GIP ||gmfcSysInfo.u8PanelType==_MINI_LVDS_GIP_V5)
645 {
646 MDrv_MFC_WriteRegsTbl(0x2200, tInitializeTcon22c); // initialize all of bank
647 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23c); // initialize all of bank
648
649 if(gmfcSysInfo.u8PanelType==_MINI_LVDS_GIP)//V4
650 {
651 MDrv_MFC_WriteByte(0x2349, 0x60);
652 MDrv_MFC_WriteByte(0x2378, 0x16);
653 MDrv_MFC_WriteByte(0x2388, 0x17);
654 MDrv_MFC_WriteByte(0x2392, 0x18);
655 MDrv_MFC_WriteByte(0x2394, 0x14);
656 MDrv_MFC_WriteByte(0x23A4, 0x15);
657 MDrv_MFC_WriteByte(0x23A5, 0x00);
658 }
659 else//V5
660 {
661 MDrv_MFC_WriteByte(0x2349, 0x40);
662 MDrv_MFC_WriteByte(0x2378, 0x10);
663 MDrv_MFC_WriteByte(0x2388, 0x11);
664 MDrv_MFC_WriteByte(0x2392, 0x12);
665 MDrv_MFC_WriteByte(0x2394, 0x0F);
666 MDrv_MFC_WriteByte(0x23A4, 0x10);
667 MDrv_MFC_WriteByte(0x23A5, 0x40);
668
669 // Fitch T cont V5 setting
670 // 20090810
671 MDrv_MFC_WriteBit(0x3240, 1, _BIT7);
672 // 20090812
673 //MDrv_MFC_WriteByte(0x3253, 0xC0);
674 //MDrv_MFC_WriteByte(0x3252, 0xC0);
675 MDrv_MFC_WriteByte(0x3276, 0xFC);
676 MDrv_MFC_WriteByte(0x1E3F, 0x60);
677 MDrv_MFC_WriteByte(0x1E40, 0xFC);
678 MDrv_MFC_WriteByte(0x2540, 0x05);
679 // 20090813
680 MDrv_MFC_WriteByte(0x23DC, 0x00);
681 MDrv_MFC_WriteByte(0x23DD, 0x00);
682 MDrv_MFC_WriteByte(0x23DE, 0x7E);
683 MDrv_MFC_WriteByte(0x23DF, 0x03);
684 MDrv_MFC_WriteByte(0x23C0, 0x01);
685 MDrv_MFC_WriteByte(0x23C1, 0x80);
686 MDrv_MFC_WriteByte(0x23C2, 0xE4);
687 MDrv_MFC_WriteByte(0x23C3, 0xD0);
688 MDrv_MFC_WriteByte(0x23CA, 0x64);
689 MDrv_MFC_WriteByte(0x23CB, 0x80);
690
691 MDrv_MFC_WriteByte(0x3250, (0x4C|MOD_POWER_ON_AFTER_INIT));
692 MDrv_MFC_WriteByte(0x324E, 0x0F);
693 MDrv_MFC_WriteByte(0x324F, 0x31);
694
695 MDrv_MFC_WriteByte(0x2505, 0x0D);
696 MDrv_MFC_WriteByte(0x2504, 0x3F);
697 MDrv_MFC_WriteByte(0x2507, 0x86);
698 MDrv_MFC_WriteByte(0x2506, 0x2F);
699 MDrv_MFC_WriteByte(0x2509, 0x04);
700 MDrv_MFC_WriteByte(0x2508, 0x00);
701 MDrv_MFC_WriteByte(0x250B, 0x0D);
702 MDrv_MFC_WriteByte(0x250A, 0x3F);
703 MDrv_MFC_WriteByte(0x250D, 0x49);
704 MDrv_MFC_WriteByte(0x250C, 0x7E);
705 MDrv_MFC_WriteByte(0x250F, 0x04);
706 MDrv_MFC_WriteByte(0x250E, 0x00);
707 MDrv_MFC_WriteByte(0x2541, 0x00);
708 MDrv_MFC_WriteByte(0x2540, 0x0F);
709 MDrv_MFC_WriteByte(0x2543, 0x00);
710 MDrv_MFC_WriteByte(0x2542, 0x0D);
711 MDrv_MFC_WriteByte(0x2555, 0x86);
712 MDrv_MFC_WriteByte(0x2554, 0x9F);
713 MDrv_MFC_WriteByte(0x2557, 0x00);
714 MDrv_MFC_WriteByte(0x2556, 0x01);
715 }
716
717 //*****HEMAN*******//
718 //Gip setting //don't change process////Bryan recommnat //j081031
719 MDrv_MFC_WriteByte(0x3270, 0x90);
720 mfcSleepMs(20);
721 MDrv_MFC_WriteByte(0x238C, 0x51);
722 mfcSleepMs(25);
723 MDrv_MFC_WriteByte(0x238C, 0x00);
724 //MDrv_MFC_WriteByte(0x3230, 0x00);
725 //MDrv_MFC_WriteByte(0x3231, 0x00);
726 //MDrv_MFC_WriteByte(0x3232, 0x00);
727 //MDrv_MFC_WriteByte(0x3233, 0x00);
728 MDrv_MFC_WriteByte(0x234E, 0x00);
729 MDrv_MFC_WriteByte(0x235E, 0x00);
730 MDrv_MFC_WriteByte(0x236E, 0x00);
731 MDrv_MFC_WriteByte(0x237E, 0x00);
732 //MDrv_MFC_WriteByte(0x238C, 0x15);
733 //MDrv_MFC_WriteByte(0x238C, 0x05);
734
735 //MDrv_MFC_WriteByte(0x1E0E, 0x00);
736 //MDrv_MFC_WriteByte(0x1E0F, 0x00);
737 }
738 if(S7M==0) MDrv_MFC_WriteByte(0x2301, 0x00); //not ttl
739
740 MDrv_MFC_WriteByte(0x23F9, 0x20);
741 MDrv_MFC_WriteBit(0x1E0F, 0, _BIT4);
742 }
743
744 #if (OD_MODE_SEL != OD_MODE_OFF)
MDrv_MFC_InitializeOD(U8 * pODTbl)745 void MDrv_MFC_InitializeOD(U8* pODTbl)
746 {
747
748 U8 ucVal;
749 U32 wCount;
750 U8 ucTARGET;
751
752 // od_top clock enable
753 MDrv_MFC_WriteByte(0x2802, 0x0e); // sram io enable
754 MDrv_MFC_WriteByte(0x2803, 0x00); // sram io enable
755
756 // Uncompressed mode
757 ucTARGET=*(pODTbl+9);// 10th
758 for (wCount=0; wCount<272; wCount++)
759 {
760 MDrv_MFC_WriteByte(0x2806, (wCount == 9)?ucTARGET:(ucTARGET ^ *(pODTbl+wCount)));
761 MDrv_MFC_Write2Bytes(0x2804, wCount|0x8000);
762 while(_bit7_(MDrv_MFC_ReadByte(0x2805)));
763
764 //MDrv_MFC_Write2Bytes(0x2804, wCount|0x4000);
765 //printf(" ,-[%x]", MDrv_MFC_ReadByte(0x2808));
766 // while(_bit6_(MDrv_MFC_ReadByte(0x2805)));
767 }
768
769 ucTARGET=*(pODTbl+272+19);// 20th
770 for (wCount=0; wCount<272; wCount++)
771 {
772 MDrv_MFC_WriteByte(0x280C, (wCount == 19)?ucTARGET:(ucTARGET ^ *(pODTbl+272+wCount)));
773 MDrv_MFC_Write2Bytes(0x280A, wCount|0x8000);
774 while(_bit7_(MDrv_MFC_ReadByte(0x280B)));
775 }
776
777 ucTARGET=*(pODTbl+272*2+29);// 30th
778 for (wCount=0; wCount<256; wCount++)
779 {
780 MDrv_MFC_WriteByte(0x2812, (wCount == 29)?ucTARGET:(ucTARGET ^ *(pODTbl+272*2+wCount)));
781 MDrv_MFC_Write2Bytes(0x2810, wCount|0x8000);
782 while(_bit7_(MDrv_MFC_ReadByte(0x2811)));
783 }
784
785 ucTARGET=*(pODTbl+272*2+256+39);// 40th
786 for (wCount=0; wCount<256; wCount++)
787 {
788 MDrv_MFC_WriteByte(0x2818, (wCount == 39)?ucTARGET:(ucTARGET ^ *(pODTbl+272*2+256+wCount)));
789 MDrv_MFC_Write2Bytes(0x2816, wCount|0x8000);
790 while(_bit7_(MDrv_MFC_ReadByte(0x2817)));
791 }
792
793 MDrv_MFC_WriteByte(0x2802, 0x00); // sram io disable
794 MDrv_MFC_WriteByte(0x2803, 0x00); // sram io disable
795 MDrv_MFC_WriteByte(0x2823, 0x5f); //[3:0] od_user_weight, [7:4] b_weight
796 MDrv_MFC_WriteByte(0x2824, 0x0c); // [7:0] od active threshold
797 // [7:0] Even request base address low byte
798 MDrv_MFC_WriteByte(0x282A, (U8)(gmfcMiuBaseAddr.u32OdBaseEven>>4));
799 // [7:0] Even request base address med byte
800 MDrv_MFC_WriteByte(0x282B, (U8)((gmfcMiuBaseAddr.u32OdBaseEven>>4)>>8));
801 // [7:0] Even request base address high byte
802 MDrv_MFC_WriteByte(0x282C, (U8)((gmfcMiuBaseAddr.u32OdBaseEven>>4)>>16));
803
804 // [7:0] request limit address low byte
805 MDrv_MFC_WriteByte(0x282E, (U8)(gmfcMiuBaseAddr.u32OdLimitEven>>4));
806 // [7:0] request limit address med byte
807 MDrv_MFC_WriteByte(0x282F, (U8)((gmfcMiuBaseAddr.u32OdLimitEven>>4)>>8));
808 // [7:0] request limit address high byte
809 MDrv_MFC_WriteByte(0x2830, (U8)((gmfcMiuBaseAddr.u32OdLimitEven>>4)>>16));
810
811 // [7:0] reg_od_wadr_max_limit low byte
812 MDrv_MFC_WriteByte(0x2872, (U8)(gmfcMiuBaseAddr.u32OdSizehalf>>4));
813 // [7:0] reg_od_wadr_max_limit med byte
814 MDrv_MFC_WriteByte(0x2873, (U8)((gmfcMiuBaseAddr.u32OdSizehalf>>4)>>8));
815 // [7:0] reg_od_wadr_max_limit high byte
816 MDrv_MFC_WriteByte(0x2874, (U8)((gmfcMiuBaseAddr.u32OdSizehalf>>4)>>16));
817
818 // [7:0] reg_od_radr_max_limit low byte
819 MDrv_MFC_WriteByte(0x2876, (U8)(gmfcMiuBaseAddr.u32OdSizehalf>>4));
820 // [7:0] reg_od_radr_max_limit med byte
821 MDrv_MFC_WriteByte(0x2877, (U8)((gmfcMiuBaseAddr.u32OdSizehalf>>4)>>8));
822 // [7:0] reg_od_radr_max_limit high byte
823 MDrv_MFC_WriteByte(0x2878, (U8)((gmfcMiuBaseAddr.u32OdSizehalf>>4)>>16));
824
825 // [7:0] Odd request base address low byte
826 MDrv_MFC_WriteByte(0x288E, (U8)(gmfcMiuBaseAddr.u32OdBaseOdd>>4));
827 // [7:0] Odd request base address med byte
828 MDrv_MFC_WriteByte(0x288F, (U8)((gmfcMiuBaseAddr.u32OdBaseOdd>>4)>>8));
829 // [7:0] Odd request base address high byte
830 MDrv_MFC_WriteByte(0x2890, (U8)((gmfcMiuBaseAddr.u32OdBaseOdd>>4)>>16));
831
832 // [7:0] request limit address low byte
833 MDrv_MFC_WriteByte(0x2891, (U8)(gmfcMiuBaseAddr.u32OdLimitOdd>>4));
834 // [7:0] request limit address med byte
835 MDrv_MFC_WriteByte(0x2892, (U8)((gmfcMiuBaseAddr.u32OdLimitOdd>>4)>>8));
836 // [7:0] request limit address high byte
837 MDrv_MFC_WriteByte(0x2893, (U8)((gmfcMiuBaseAddr.u32OdLimitOdd>>4)>>16));
838
839 MDrv_MFC_WriteByte(0x2832, 0x30); // [7:0] reg_od_r_thrd
840 MDrv_MFC_WriteByte(0x2833, 0x7e); // [7:0] reg_od_wff_ack_thrd
841 MDrv_MFC_WriteByte(0x2834, 0x20); // [7:0] reg_od_r_thrd2
842 MDrv_MFC_WriteByte(0x2835, 0x50); // [7:0] reg_od_r_hpri
843 MDrv_MFC_WriteByte(0x2836, 0x30); // [7:0] reg_od_w_thrd
844 MDrv_MFC_WriteByte(0x2837, 0x04); // [7:0] reg_od_wlast_fire_thrd
845 MDrv_MFC_WriteByte(0x2838, 0x20); // [7:0] reg_od_w_thrd2
846 MDrv_MFC_WriteByte(0x2839, 0x50); // [7:0] reg_od_w_hpri
847 MDrv_MFC_WriteByte(0x2841, 0x00); // od request space stop cnt
848 MDrv_MFC_WriteByte(0x285C, 0x80); // [7:0] reg_patchTh0
849 MDrv_MFC_WriteByte(0x285D, 0x00); // [5:0] reg_patchTh1 : bias offset
850 // [6] reg_patchTh1 : patch enable
851 MDrv_MFC_WriteByte(0x285E, 0x88); // [3:0] reg_patchTh2
852 // [7:4] reg_patchTh3
853 MDrv_MFC_WriteByte(0x2866, 0x10); // [7:0] reg_min3x3Length
854 MDrv_MFC_WriteByte(0x2867, 0x40); // [7:0] reg_max3x3Length
855
856 // [7:0] reg_od_mem_adr_limit low byte
857 MDrv_MFC_WriteByte(0x2859, (U8)(gmfcMiuBaseAddr.u32OdSize>>4));
858 // [7:0] reg_od_mem_adr_limit med byte
859 MDrv_MFC_WriteByte(0x285A, (U8)((gmfcMiuBaseAddr.u32OdSize>>4)>>8));
860 // [7:0] reg_od_mem_adr_limit high byte
861 MDrv_MFC_WriteByte(0x285B, (U8)((gmfcMiuBaseAddr.u32OdSize>>4)>>16));
862
863 // lsb request base address low byte
864 MDrv_MFC_WriteByte(0x289E, (U8)(gmfcMiuBaseAddr.u32OdLsbBase>>4));
865 // lsb request base address med byte
866 MDrv_MFC_WriteByte(0x289F, (U8)((gmfcMiuBaseAddr.u32OdLsbBase>>4)>>8));
867 // lsb request base address high byte
868 MDrv_MFC_WriteByte(0x28A0, (U8)((gmfcMiuBaseAddr.u32OdLsbBase>>4)>>16));
869
870 // lsb request limit address low byte
871 MDrv_MFC_WriteByte(0x28A1, (U8)(gmfcMiuBaseAddr.u32OdLsbLimit>>4));
872 // lsb request limit address med byte
873 MDrv_MFC_WriteByte(0x28A2, (U8)((gmfcMiuBaseAddr.u32OdLsbLimit>>4)>>8));
874 // lsb request limit address high byte
875 MDrv_MFC_WriteByte(0x28A3, (U8)((gmfcMiuBaseAddr.u32OdLsbLimit>>4)>>16));
876
877 MDrv_MFC_WriteByte(0x28A4, 0x20); // [7:0] reg_od_r_thrd_lsb
878 MDrv_MFC_WriteByte(0x28A5, 0x30); // [7:0] reg_od_r_thrd2_lsb
879 MDrv_MFC_WriteByte(0x28A6, 0x50); // [7:0] reg_od_r_hpri_lsb
880 MDrv_MFC_WriteByte(0x28A7, 0x50); // [7:0] reg_od_w_hpri_lsb
881 MDrv_MFC_WriteByte(0x28A8, 0x20); // [7:0] reg_od_w_thrd_lsb
882 MDrv_MFC_WriteByte(0x28A9, 0x30); // [7:0] reg_od_w_thrd2_lsb
883 MDrv_MFC_WriteByte(0x28AB, 0x14); // [3:0] reg_vsync_start_delay
884 // [5:4] reg_vsync_width_delay // [7:6] reg_vfend_delay
885 if (gmfcMiuBaseAddr.u8OdMode==OD_MODE_666_COMPRESS)
886 MDrv_MFC_WriteByte(0x289B, 0x25);
887 else if (gmfcMiuBaseAddr.u8OdMode==OD_MODE_555_COMPRESS)
888 MDrv_MFC_WriteByte(0x289B, 0x15);
889 else
890 MDrv_MFC_WriteByte(0x289B, 0x05);
891
892 // [0] reg_last_data_ctrl_en
893 // [1] reg_od1_last_dummy_pix_sel
894 // [2] reg_od1_last_rdy_sel
895 // [6:4] reg_od_compress_mode
896 // [7] reg_od_lsb_wlast_force_req_disable
897
898 #if 0
899 MDrv_MFC_WriteByte(0x2824, 0x0c); // od active threshold
900 MDrv_MFC_WriteByte(0x2825, 0x00); // od active threshold
901 MDrv_MFC_WriteByte(0x2841, 0x00); // od request space stop cnt
902 MDrv_MFC_WriteByte(0x28AB, 0x14); // od self generate vsync
903 MDrv_MFC_WriteByte(0x286C, 0x07); // [7:6] reg_od_status_sel
904 // [5] reg_od_read_over_disable
905 // [4] reg_od_read_over_sel
906 // [3] reg_od_status_rst
907 // [2] reg_od_rq_over_under_mask_en
908 // [1] reg_od_next_frame_en
909 // [0] reg_od_active_sel
910
911 MDrv_MFC_WriteByte(0x286D, 0x82);
912 // [7] reg_od1_write_data_over_sel, compress bypaa mode need to set 0
913 // [6:4] reg_od1_overflow_thrd, compress mode check line buffer overflow threshold sel
914 // [3:0] reg_od1_underflow_thrd, compress mode check line buffer underflow threshold
915
916 MDrv_MFC_WriteByte(0x284B, 0x80);
917 // [7] reg_od1_read_data_under_sel
918 // [6] reg_od1_linebuf_bypass_en
919
920 MDrv_MFC_WriteByte(0x2885, 0x80); // [7:4] reg_od1_read_under_act_thrd
921 MDrv_MFC_WriteByte(0x285F, 0xff); // [7:0] reg_od1_rbuf_thrd
922 #endif
923 ucVal = OD_MODE_SEL;
924 ucVal &= 0x0F;
925 MDrv_MFC_WriteByte(0x2820, 0x20|ucVal);
926 // [0] od_en
927 // [3:1] od_mode , 000{444}, 001{565}, 010{y-8}, 011{333}, 100{666}, 101{compress}, 110{555}, 111{888}
928 // [4] reserved
929 // [5] reg_od_user_weight_sel
930 // [6] od_h_range_en
931 // [7] od_v_range_en
932
933 //printf("MDrv_MFC_InitializeOD()\n");
934 }
935 #endif
936
MDrv_MFC_InitializePanel(void)937 void MDrv_MFC_InitializePanel(void)
938 {
939 msInitializeColorMatrix();
940
941 if (gmfcSysInfo.u8PanelType == _MINI_LVDS || gmfcSysInfo.u8PanelType == _RSDS || gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP || gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP_V5)
942 msInitializeTcon();
943
944 #if (OD_MODE_SEL != OD_MODE_OFF)
945 if (gmfcMiuBaseAddr.u8OdMode != OD_MODE_OFF)
946 {
947 #if (PANEL_TYPE_SEL == PNL_LCEAll)
948 if( MDrv_MFC_ReadByte(0x1E48)>0 && MDrv_MFC_ReadByte(0x1E48)<=3 )
949 {
950 if(MDrv_MFC_ReadByte(0x1E48) == 1)//42"
951 MDrv_MFC_InitializeOD(tOD42);
952 else if(MDrv_MFC_ReadByte(0x1E48) == 2)//47"
953 MDrv_MFC_InitializeOD(tOD47);
954 else if(MDrv_MFC_ReadByte(0x1E48) == 3)//GIP 37"
955 MDrv_MFC_InitializeOD(tOD37);
956 }
957 #else
958 //MDrv_MFC_InitializeOD(tOverDrive); // calvin
959 MDrv_MFC_InitializeOD(tOD42);
960 #endif
961 }
962 #endif
963 //if(gmfcSysInfo.u8MirrorMode)
964 //MDrv_MFC_Write2Bytes(0x2F2C, (gmfcSysInfo.u16Height-50)&0x07FF); // for flip memc issue
965 }
966
MDrv_MFC_InitializeScTop2_Bypanel(void)967 void MDrv_MFC_InitializeScTop2_Bypanel(void)
968 {
969 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop2);
970 }
971
972 #if(CODEBASE_SEL == CODEBASE_LINUX)
MDrv_MFC_InitializeBypass(void)973 void MDrv_MFC_InitializeBypass(void)
974 {
975 U8 i;
976 //for bypass use
977 //IP CSC off: 20C0[0] = 0
978 MDrv_MFC_WriteBit(0x20C0, 0, _BIT0); // [0]:CSC [1]:dither [2]:round
979
980 //IP 121 horizontal and vertical disable: 2052[1:0] = 0
981 MDrv_MFC_WriteByteMask(0x2052, 0, _BIT0|_BIT1);
982
983 //MFC off: 290E[3:0] = 0.
984 MDrv_MFC_WriteByteMask(0x290E, 0x00, 0x0F);
985
986 //Color matrixes disable: 3002[3] = 0, 3003~3015 set to 0.
987 MDrv_MFC_WriteBit(0x3002, 0, _BIT3);
988 for (i=0; i<0x13; i++) // 0x3003 ~ 0x3015
989 MDrv_MFC_WriteByte(0x3003+i, 0);
990
991 //Brightness disable: 3016[1] = 0, 3018~301B set to 0.
992 MDrv_MFC_WriteBit(0x3016, 0, _BIT1);
993 for (i=0; i<0x4; i++) // 0x3018 ~ 0x301B
994 MDrv_MFC_WriteByte(0x3018+i, 0);
995 }
996 #endif
997
998 #endif
999